TPS40060 TPS40061 8 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER FEATURES • • • • • • • • • • • DESCRIPTION Operating Input Voltage 10 V to 55 V Input Voltage Feed-Forward Compensation < 1% Internal 0.7-V Reference Programmable Fixed-Frequency, Up to 1-MHz Voltage Mode Controller Internal Gate Drive Outputs for High-Side P-Channel and Synchronous N-Channel MOSFETs 16-Pin PowerPAD™ Package (θJC = 2°C/W) Thermal Shutdown Externally Synchronizable Programmable High-Side Sense Short Circuit Protection Programmable Closed-Loop Soft-Start TPS40060 Source Only/TPS40061 Source/Sink The TPS40060 and TPS40061 are high-voltage, wide input (10 V to 55 V) synchronous, step-down converters. This family of devices offers design flexibility with a variety of user programmable functions, including; soft-start, UVLO, operating frequency, voltage feed-forward, high-side current limit, and loop compensation. These devices are also synchronizable to an external supply. The TPS40060 and TPS40061 incorporate MOSFET gate drivers for external P-channel high-side and N-channel synchronous rectifier (SR) MOSFETs. Gate drive logic incorporates anti-cross conduction circuitry to prevent simultaneous high-side and synchronous rectifier conduction. APPLICATIONS • • • • Networking Equipment Telecom Equipment Base Stations Servers SIMPLIFIED APPLICATION DIAGRAM VIN 1 TPS40060PWP KFF ILIM 16 2 RT VIN 15 3 BP5 HDRV 14 4 SYNC BPN10 13 5 SGND SW 12 6 SS/SD BP10 11 7 VFB LDRV 10 8 COMP PGND 9 + VOUT UDG-02157 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2004, Texas Instruments Incorporated TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA LOAD CURRENT PACKAGE (1) PART NUMBER SOURCE (2) Plastic HTSSOP (PWP) TPS40060PWP SOURCE/SIN (2) Plastic HTSSOP (PWP) TPS40061PWP –40°C to 85°C (1) (2) The PWP package is alsoavailable taped and reeled. Add an R suffix to the device type (i.e.,TPS40060PWPR). See the application section of the data sheet for PowerPADdrawing and layout information. See ApplicationInformation section. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPS40060 TPS40061 VIN 60 V VFB, SS/SD, SYNC VIN Input voltage range –0.3 V to 6 V –0.3 V to 60 V or VIN+5 V (whichever is less) SW SW. transient < 50 ns –2.5 V –0.3 V to 6 V VOUT Output voltage range COMP, RT, KFF, SS IIN Input current KFF 5 mA IOUT Output current RT 200 µA TJ Operating junction temperature range –40°C to 125°C Tstg Storage temperature –55°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) 260°C Stresses beyond thoselisted under "absolute maximum ratings" may cause permanent damage to thedevice. These are stress ratings only, and functional operation of the deviceat these or any other conditions beyond those indicated under "recommendedoperating conditions" is not implied. Exposure to absolute-maximum-ratedconditions for extended periods may affect devicereliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VIN Input voltage TA Operating free-air temperature PWP PACKAGE (1)(2) (TOP VIEW) KFF RT BP5 SYNC SGND SS/SD VFB COMP 2 1 2 3 4 5 6 7 8 THERMAL PAD 16 15 14 13 12 11 10 9 ILIM VIN HDRV BPN10 SW BP10 LDRV PGND (1) For more information on the PWP package, refer to TI Technical Brief (SLMA002). (2) PowerPAD™ heat slug must be connected to SGND (Pin 5), or electrically isolated from all other pins. UNIT 10 55 V –40 85 °C TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VIN = 24 Vdc, RT = 165 kΩ, IKFF = 113 µA, fSW = 300 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input voltage range, VIN 10 55 V 1.5 2.5 mA 4.5 5.0 5.5 V 270 300 330 kHz OPERATING CURRENT IDD Quiescent current Output drivers not switching 5-V REFERENCE VBP5 Input voltage OSCILLATOR/RAMP GENERATOR (1) fOSC Frequency VRAMP PWM ramp voltage (2) VIH High-level input voltage, SYNC VIL Low-level input voltage, SYNC ISYNC Input current, SYNC Pulse width, SYNC VRT 2 2 Pulse amplitude = 5 V 2.32 Maximum duty cycle VFB = 0 V, 100 kHz ≤ fSW≤ 1 MHz Minumum duty cycle VFB ≥ 0.75 V Feed-forward voltage IKFF Feed-forward current operating range (3) 5 10 2.50 2.68 50 RT voltage VKFF V 0.8 µA ns 85% V 98% 0% 3.35 3.50 20 3.65 V 1100 µA SS/SD (SOFT START) ISS Soft-start source current 1.8 2.3 2.9 µA VSS Soft-start clamp voltage 3.1 3.7 4.0 V tDSCH Discharge time CSS = 220 pF 1.8 2.2 2.8 tSS Soft-start time CSS = 220 pF, 0 V ≤ VSS ≤ 1.6 V 120 155 190 90 120 145 mV 160 210 260 mV 9.0 9.7 10.7 V TA = 25°C 0.698 0.700 0.704 0°C ≤ TA ≤ 85°C 0.690 0.700 0.707 0.715 µs SS/SD (SHUTDOWN) VSD Shutdown threshold voltage VEN Device action threshold voltage 10-V REFERENCE VBP10 Input voltage ERROR AMPLIFIER VFB Feedback regulation voltage 0.690 0.700 GBW Gain bandwidth 3 5 MHz AVOL Open loop gain 60 80 dB IOH High-level output source current VCOMP = 2.0 V, VFB = 0 V 1.5 4.0 IOL Low-level output sink current VCOMP = 2.0 V, VFB = 1 V 2.5 4.0 IBIAS Input bias current VFB = 0.7 V 100 300 VOH High-level output voltage IOH = 0.5 mA, VFB = 0 V 3.25 3.45 3.60 VOL Low-level output voltage IOL = 0.5 mA, VFB = 1 V 0.050 0.215 0.350 (1) (2) (3) V mA nA V KFF current(IKFF) increases with SYNC frequency(fSYNC) and decreases with maximum dutycycle (DMAX). Ensured by design. Notproduction tested. Ensured by design. Notproduction tested. 3 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VIN = 24 Vdc, RT = 165 kΩ, IKFF = 113 µA, fSW = 300 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 8.3 10.0 11.5 µA VILIM = 23.7 V, VSW = (VILIM– 0.5 V) 330 500 VILIM = 23.7 V, VSW = (VILIM– 2 V) 275 375 CURRENT LIMIT ISINK Current limit sink current tDELAY Propagation delay to output tON Switch leading-edge blanking pulse time (4) tOFF Off time during a fault VOS Overcurrent comparator offset voltage ns 100 7 -200 cycles -60 50 96 mV OUTPUT DRIVER tHFALL High-side driver fall time (4) CHDRV = 2200 pF, (VIN– VBPN10) 48 tHRISE High-side driver rise time (4) CHDRV = 2200 pF, (VIN– VBPN10) 36 72 tLFALL Low-side driver fall time (4) CLDRV = 2200 pF, BP10 24 48 tLRISE Low-side driver rise time (4) CLDRV = 2200 pF, BP10 48 96 1.0 VOH High-level ouput voltage, HDRV IHDRV = 0.1 A , (VIN– VHDRV) VOL Low-level ouput voltage, HDRV IHDRV = 0.1 A , (VHDRV– VBPN10) VOH High-level ouput voltage, LDRV ILDRV = 0.1 A, (VBP10– VLDRV) Low-level ouput voltage, LDRV ILDRV = 0.1 A VOL ns 1.4 0.75 V 1.0 1.5 100 150 ns –7.5 –8.5 –9.5 V –6 0 6 mV 1 µA 0.5 Minimum controllable pulse width BPN10 REGULATOR VBPN1 0 Output voltage Outputs off RECTIFIER ZERO CURRENT COMPARATOR (TPS40060 ONLY) VSW Switch voltage LDRV output OFF SW NODE ILEAK Leakage current (4) THERMAL SHUTDOWN Shutdown temperature (4) TSD 165 Hysteresis (4) °C 25 UNDERVOLTAGE LOCKOUT VUVLO Undervoltage lockout threshold voltage, BP10 RKFF = 10 kΩ 6.25 Undervoltage lockout hysteresis VKFF (4) 4 KFF programmable threshold voltage Ensured by design. Notproduction tested. 6.5 7.5 0.4 RKFF = 82.5 kΩ 9 10 V 11 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION BP5 3 O 5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used with an external DC load of 1 mA or less. BP10 11 O 10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF ceramic capacitor. This pin may be used with an external DC load of 1 mA or less. BPN10 13 O Negative 8-V reference with respect to VIN. This voltage is used to provide gate drive for the high side P-channel MOSFET. This pin should be bypassed to VIN with a 0.1-µF capacitor COMP 8 I Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to improve large signal transient response. HDRV 14 O Floating gate drive for the high-side P-channel MOSFET. This pin switches from VIN (MOSFET off) to BPN10 (MOSFET on). ILIM 16 I Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VIN. The voltage on this pin is compared to the voltage drop (VIN -SW) across the high side MOSFET during conduction. KFF 1 I A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into this pin is internally divided and used to control the slope of the PWM ramp. LDRV 10 I Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET off). PGND 9 RT 2 SGND 5 Signal ground reference for the device. SS/SD 6 I Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS pin is used as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is approximately 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V. The controller is considered shut down when VSS/SD is 125 mV or less. All internal circuitry is inactive. The internal circuitry is enabled when VSS/SD is 210 mV or greater. When VSS/SD is less than approximately 0.85 V, the outputs cease switching and the output voltage (VOUT) decays while the internal circuitry remains active. SW 12 I This pin is connected to the switched node of the converter and used for overcurrent sensing. This pin is used for zero current sensing in the TPS40060. SYNC 4 I Synchronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency. VFB 7 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage, 0.7 V. VIN 15 I Supply voltage for the device. Power ground reference for the device. There should be a low-impedance connection from this point to the source of the power MOSFET. I A resistor is connected from this pin to ground to set the internal oscillator ramp charging current and switching frequency. 5 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 SIMPLIFIED BLOCK DIAGRAM ILIM 16 VIN 15 11 BP10 13 BPN10 14 HDRV 12 SW BP10 + CLK RT 2 SYNC 4 Clock Oscillator CLK 7 10−V Regulator 7 VIN 7 1V5REF 7 HDRV 7 Ramp Generator KFF Reference Voltages 1 07VREF 7 1V5REF 7 3V5REF 7 BP5 HDRV 7 7 CL 3−bit up/down Fault Counter P-Channel Driver 7 7 7 7 BPN10 Restart Fault BP5 COMP 3 BP5 7 7 Fault 8 VFB 7 7 07VREF 7 + CL + + SS/SD 7 BP10 0.85 V 7 07VREF 6 + Q R Q N-Channel Driver 7 7 SW CLK 7 Zero Current Detector (TPS40060 Only) Restart 5 SGND 6 S S Q R Q 10 LDRV 9 PGND UDG−02160 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION The TPS40060/61 family of parts allows the user to optimize the PWM controller to the specific application. The TPS40061 is the controller of choice for synchronous buck designs which will include most applications. It has two quadrant operation and will source or sink output current. This provides the best transient response. The TPS40060 operates in one quadrant and sources output current only, allowing for paralleling of converters and ensures that one converter does not sink current from another converter. This controller also emulates a standard buck converter at light loads where the inductor current goes discontinuous. At continuous output inductor currents the controller operates as a synchronous buck converter to optimize efficiency. SW NODE RESISTOR The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output current which flows during this dead time. This negative voltage could affect the operation of the controller, especially at low input voltages. Therefore, a 10-Ω resistor must be placed between the lower MOSFET drain and pin 12 (SW) of the controller as shown in Figure 13 as RSW. SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR) The TPS40060 and TPS40061 have independent clock oscillator and ramp generator circuits. The clock oscillator serves as the master clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the clock oscillator is set by a single resistor (RT) to ground. The clock frequency is related to RT, in kΩ by Equation 1 and the relationship is charted in Figure 2. RT + ǒ f SW 1 17.82 10 *6 Ǔ * 23 kW (1) PROGRAMMING THE RAMP GENERATOR CIRCUIT The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1). VIN VIN SW SW RAMP VPEAK COMP COMP RAMP VVALLEY tON1 t d + ON T T1 tON2 T2 tON1 > tON2 and d1 > d2 UDG-02131 Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle 7 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The PWM ramp time is programmed via a single resistor (RKFF) pulled up to VIN. RKFF is related to RT, and the minimum input voltage, VIN(min) through the following: R KFF + ǒVIN (min) * 3.5Ǔ ǒ65.27 RT ) 1502Ǔ (W) (2) where: • • VIN is the desired start-up (UVLO) input voltage RT is the timing resistor in kΩ See the section on UVLO operation for further description. The curve showing the feedforward impedance required for a given switching frequency, fSW, at various input voltages is shown in Figure 3. For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and regulates the output voltages. For more information on large duty cycle operation, refer to Application Note (SLUA310). FEED-FORWARD IMPEDANCE vs SWITCHING FREQUENCY TIMING RESISTANCE vs SWITCHING FREQUENCY 600 800 700 RKFF - Feed-Forward Impedance - kΩ RT - Timing Resistance - kΩ 500 400 300 200 100 0 0 200 400 600 800 fSW - Switching Frequency - kHz Figure 2. 1000 VIN = 25 V 600 500 400 VIN = 15 V 300 200 VIN = 9 V 100 0 200 400 600 800 1000 fSW - Switching Frequency - kHz Figure 3. UVLO OPERATION The TPS40060 and TPS40061 use both fixed and variable (user programmable) UVLO protection. The fixed UVLO monitors the BP10 and BP5 bypass voltages. The UVLO circuit holds the soft-start low until the BP5 and BP10 voltage rails have exceeded their thresholds and the input voltage has exceed the user programmable undervoltage threshold. The TPS40060 and TPS40061 use the feed-forward pin, KFF, as a user programmable low-line UVLO detection. This variable low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage condition existis if the device receives a clock pulse before the ramp has reached 90% of its full amplitude. The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor can be referenced to the oscillator frequency as descibed in Equation 3: 8 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) R KFF + ǒVIN (min) * 3.5Ǔ ǒ65.27 RT ) 1502Ǔ (W) (3) where: • • VIN is the desired start-up (UVLO) input voltage RT is the timing resistor in kΩ The variable UVLO function utilizes a 3-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter the clock cycle a powergood signal is asserted, a soft-start initiated, and the upper and lower MOSFETs are turned off. Once the soft-start is initiated, the UVLO cicruit must see a total count of seven cycles in which the ramp duration is longer than the clock cycle before an undervoltage condition is declared (See Figure 4). UVLO Threshold VIN Clock PWM RAMP 1 2 3 4 5 6 7 PowerGood 1 2 1 2 3 4 5 6 7 UDG-02132 Figure 4. Undervoltage Lockout Operation UNDERVOLTAGE LOCKOUT vs HYSTERESIS 3.0 VUVLO - Output Voltage - V 2.5 2.0 1.5 1.0 0.5 0 10 15 20 25 30 35 40 45 50 45 VUVLO - Undervoltage Lockout Threshold - V Figure 5. 9 TPS40060 TPS40061 SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 www.ti.com APPLICATION INFORMATION (continued) The impedance of the input voltage can cause the input voltage, at the TPS4006x, to sag when the converter starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents nuisance shutdowns at the UVLO point. With RT chosen to select the operating frequency and RKFF chosen to select the start-up voltage, the amount of hysteresis voltage is shown in Figure 5. PROGRAMMING SOFT START TPS4006x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is programmed by charging an external capacitor (CSS) via an internally generated current source. The voltage on CSS minus 0.85 V, is fed into a separate non-inverting input to the error amplifier (in addition to FB and 0.7-V VREF). The loop is closed on the lower of the (CSS– 0.85 V) voltage or the internal reference voltage ( 0.7-V VREF). Once the (CSS– 0.85 V) voltage rises above the internal reference voltage, regulation is based on the internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than the L-CO time constant as described in Equation 4. t START w 2p ǸL CO (seconds) (4) There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the higher the input current required during start-up. This relationship is describe in more detail in the section titled, Programming the Current Limit which follows. The soft-start capacitance, CSS, is described in Equation 5. For applications in which the VIN supply ramps up slowly, (typically between 50 ms and 100 ms) it may be necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO tripping. The soft-start time should be longer than the time that the VINsupply transitions between 6 V and 7 V. 2.3 mA C SS + t START (Farads) 0.7 V (5) 10 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) PROGRAMMING CURRENT LIMIT This device uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the MOSFET when the gate is driven low. The MOSFET voltage is compared to the voltage dropped across a resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated. The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 6 for typical overcurrent protection waveforms. The minimum current limit setpoint (ILIM) depends on tSTART, CO, VO, and the load current at turn-on (IL). I LIM + ƪǒ CO t SS ƫ V OǓ ) I L (A) (6) The current limit programming resistor (RILIM) is calculated using Equation 7. Care must be taken in choosing the values used fro VOS and ISINK in the equation. In order to ensure the output current at the overcurrent level, the minimum value of ISINK and the maximum value of VOS must be used. I OC RDS(on)[max] V R ILIM + ) OS (W) I SINK I SINK (7) where: • • • ISINK is the current into the ILIM pin and is nominally 8.3 µA, minimum IOC is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current VOS is the overcurrent comparator offset and is 50 mV maximum BP5, BPN10 AND BPN10 INTERNAL VOLTAGE REGULATOR Start-up characteristics of the BP5, BP10 and BPN10 regulators are shown in Figure 6. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the BPN10 and BP10 regulation characteristics is also based on the load presented by switching the external MOSFETs. 11 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) INTERNAL REGULATOR OUTPUT VOLTAGE vs INPUT VOLTAGE 12 BP10 VBPx - Output Voltage - V 10 8 BP5 6 BPN10 4 2 0 2 4 6 8 10 12 VIN - Input Voltage - V Figure 6. HDRV CLOCK tBLANKING VILIM VVIN-VSW SS 7 CURRENT LIMIT TRIPS (HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP) 7 SOFT-START CYCLES UDG-02136 Figure 7. Typical Current Limit Protection Waveforms CALCULATING THE BPN10 AN BP10V BYPASS CAPACITOR The BPN10 capacitance provides a local, low impedance source for the high-side driver. The BPN10 capacitor should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BPN10 capacitance is described in Equation 8. 12 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) C BPN10 + Qg DV (F) (8) The 10-V reference pin, BP10V needs to provide energy for the synchronous MOSFET gate drive via the BP10V capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in Equation 9. Q gSR C BP10V + (F) DV (9) SYNCHRONIZING TO AN EXTERNAL SUPPLY The TPS4006x can be synchronized to an external clock through the SYNC pin. The SW node rises on the falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4006x to freely run at the frequency programmed by RT. Internally, the SYNC pin has a pull-down current between 5 µA and 10 µA. In order to synchronize the device to an external clock signal, the SYNC pin has to be overdriven from the external clock circuit. Normal logic gates or an external MOSFET with a pull-up resistor of 10 kΩ is adequate. Internally there is a delay of between approximately 50 ns and 100 ns from the time the SYNC pin is pulled low and the HDRV signal goes high to turn on the upper MOSFET. Additionally, there is some delay as the MOSFET gate charges to turn on the upper MOSFET, typically between 20 ns and 50 ns. The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a 'dummy' value for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the design. R T(dummy) + ǒ f SYNC 1 17.82 10 *6 Ǔ * 23 kW Use the value of RT(dummy) to calculate the value for RKFF. R KFF + ǒVIN(min) * 3.5 VǓ ǒ65.27 (10) Ǔ RT(dummy) ) 1502 kW (11) where: • RT is in kΩ This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency. SELECTING THE INDUCTOR VALUE The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good compromise is to select the inductance value such that the converter doesn't enter discontinuous mode until the load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in Equation 12. L+ ǒV IN * V OǓ VIN DI VO f SW (H) (12) where: • • VO is the output voltage ∆I is the peak-to-peak inductor current 13 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) CALCULATING THE OUTPUT CAPACITANCE The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any output voltage deviation requirement during a load transient. The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output ripple is described in Equation 13. DV + DI ƪ ESR ) ǒ 1 CO 8 Ǔƫ f SW ǒVP*PǓ (13) The output ripple voltage is typically between 90% and 95% due to the ESR component. The output capacitance requirement typically increases in the presence of a load transient requirement. During a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess inductor energy (heavy-to-light load step) while maintaining the output voltage within acceptable limits. The amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the inductor. Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in Equation 14 and Equation 15. E L + 1 L I 2 (J) 2 (14) where: I2 + ƪǒI Ǔ OH 2 * ǒI OLǓ ƫ ǒ(Amperes)2Ǔ 2 (15) where: IOH is the output current under heavy load conditions IOL is the output current under light load conditions • • Energy in the capacitor is given by the following equation: E C + 1 C V2 (J) 2 (16) where: 2 V 2 + ǒVfǓ * ǒV iǓ 2 ǒVolts2Ǔ (17) where: Vf is the final peak capacitor voltage Vi is the initial capacitor voltage • • By substituting Equation 14 into Equation 13, substituting Equation 16 into Equation 15, setting Equation 13 equal to Equation 15 and solving for CO yields the following equation. L CO + ƪǒI Ǔ * ǒI Ǔ ƫ ƪǒV Ǔ * ǒV Ǔ ƫ 2 2 OH OL 2 f 2 i (F) (18) Loop Compensation Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS40060 and TPS40061 use voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be included. The modulator gain is described in Figure 7, with VIN being the minimum input voltage required to cause the ramp excursion to cover the entire switching period. 14 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) A MOD + VIN VS or A MOD(db) + 20 log ǒ Ǔ V IN VS (19) Duty dycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the maximum ramp voltage, VS. Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage to output voltage modulator gain in terms of the input voltage and ramp voltage, V V VO V D + O + C or + IN V IN VS VC VS (20) Calculate the Poles and Zeros For a buck converter using voltage mode control there is a double pole due to the output L-CO. The double pole is located at the frequency calculated in Equation 21. 1 f LC + (Hz) Ǹ 2p L CO (21) There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located at the frequency calculated in Equation 22. 1 fZ + (Hz) 2p ESR CO (22) Calculate the value of RBIASto set the output voltage, VOUT. R BIAS + 0.7 R1 W VOUT * 0.7 (23) The maximum crossover frequency (0 dB loop gain) is calculated in Equation 24. f f C + SW (Hertz) 4 (24) Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this frequency, the control to output gain has a –2 slope (-40 dB/decade), while the Type III topology has a +1 slope (20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 9 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated. A Type III topology, shown in Figure 10, has two zero-pole pairs in addition to a pole at the origin. The gain and phase boost of a Type III topology is shown in Figure 11. The two zeros are used to compensate the L-CO double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled gain roll-off. In many cases the second pole can be eliminated and the amplifier's gain roll-off used to roll-off the overall gain at higher frequencies. 15 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) PWM MODULATOR RELATIONSHIPS MODULATOR GAIN vs SWITCHING FREQUENCY ESR Zero, + 1 VS Modulator Gain - dB AMOD = VIN / VS VC Resultant, - 1 D = VC / VS LC Filter, - 2 100 1k 10 k fSW - Switching Frequency - Hz Figure 8. Figure 9. C2 (optional) C1 R3 −1 +1 0 dB R2 −1 GAIN −90° C3 VFB R1 180° 7 VOUT 8 + RBIAS VREF COMP PHASE −270° UDG−02189 Figure 10. Type III Compensation of Configuration Figure 11. Type III Compensation Gain and Phase The poles and zeros for a type III network are described in Equation 25. 1 1 f Z1 + (Hz) f Z2 + (Hz) 2p R2 C1 2p R1 C3 f P1 + 100 k 2p 1 R2 C2 (Hz) f P2 + 2p (25) 1 R3 C3 (Hz) The value of R1 is somewhat arbitraty, but influences other component values. A value between 50kΩ and 100kΩ usually yields reasonable values. The unity gain frequency is described in Equation 26. 1 (Hertz) fC + 2p R1 C2 G where G is the reciprocal of the modulator gain at fC. 16 (26) TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) The modulator gain as a function of frequency at fC, is described in Equation 27. AMOD(f) + AMOD ǒ Ǔ f LC fC 2 and G+ 1 AMOD(f) (27) Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too small. The error amplifier has a finite output source and sink current which must be considered when sizing R2. Too small a value does not allow the output to swing over its full range. VC (max) R2 (MIN) + (W) + 3.45 V + 1.725 kW 2.0 mA I SOURCE (min) (28) dv/dt INDUCED TURN-ON MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on the MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the gate-to-source voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through currents. Therefore the SR MOSFET should be chosen so that the CGD capacitance is smaller than the CGS capacitance. A 2-Ω to 5-Ω resistor in the upper MOSFET gate lead shapes the turn-on and dv/dt of the SW node and helps reduce the induced turn-on. HIGH-SIDE MOSFET POWER DISSIPATION The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The high-side MOSFET conduction losses are defined by Equation 29. P COND + ǒI RMSǓ 2 R DS(on) ǒ1 ) TCR ƪT J * 25 CƫǓ O (W) (29) where: • TCR is the temperature coefficient of the MOSFET RDS(on) The TCR varies depending on MOSFET technology and manufacturer but is typically ranges between 0.0035 ppm/°C and 0.010 ppm/°C. The IRMS current for the high side MOSFET is described in Equation 30. Ǹd ǒAmperes Ǔ I +I RMS O RMS (30) The switching losses for the high-side MOSFET are descibed in Equation 31. P SW(fsw) + ǒVIN I OUT t SWǓ f SW (Watts) (31) where: • • • IO is the DC output current tSW is the switching rise time, typically < 20 ns fSW is the switching frequency Typical switching waveforms are shown in Figure 12. 17 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) ID2 IO ID1 d } ∆I 1-d BODY DIODE CONDUCTION BODY DIODE CONDUCTION SW 0 SYNCHRONOUS RECTIFIER ON ANTI-CROSS CONDUCTION HIGH SIDE ON UDG-02179 Figure 12. Inductor Current and SW Node Waveforms The maximum allowable power dissipation in the MOSFET is determined by the following equation. PT + ǒTJ * TAǓ q JA (W) (32) where: P T + PCOND ) PSW(fsw) (W) (33) and ΘJA is the package thermal impedance. SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on) conduction losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can be found using Equation 29 and the RMS current through the synchronous rectifier MOSFET is described in Equation 34. Ǹ1 * d ǒA Ǔ I +I RMS O RMS (34) The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross conduction delay time. The body diode conduction losses are described by Equation 35. P DC + 2 I O V F t DELAY f SW (W) (35) where: • • VF is the body diode forward voltage tDELAY is the delay time just before the SW node rises The 2-multiplier is used because the body-diode conducts twice during each cycle (once on the rising edge and once on the falling edge) The reverse recovery losses are due to the time it takes for the body diode to recovery from a forward bias to a reverse blocking state. The reverse recovery losses are described in Equation 36. P RR + 0.5 Q RR V IN f SW (W) (36) where: • QRR is the reverse recovery charge of the body diode The total synchronous rectifier MOSFET power dissipation is described in Equation 37. 18 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) P SR + PDC ) PRR ) PCOND (W) (37) TPS40060/TPS40061 POWER DISSIPATION The power dissipation in the TPS40060 and TPS40061 is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power (neglecting external gate resistance, refer to [2] can be calculated from Equation 38. P D + Q g VDR f SW (W) (38) And the total power dissipation in the device, assuming MOSFETs with similar gate charges for both the high-side and synchronous rectifier is described in Equation 39. 2 PD PT + ) IQ V IN (W) V DR ǒ or Ǔ P T + ƪǒ2 (39) f SWǓ ) I Qƫ Qg V IN (W) (40) where: • IQ is the quiescent operating current (neglecting drivers) The maximum power capability of the device's PowerPad package is dependent on the layout as well as air flow. The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air flow. ΘJA = 36.51°C/W The maximum allowable package power dissipation is related to ambient temperature by Equation 36. Substituting Equation 32 into Equation 40 and solving for fSW yields the maximum operating frequency for the TPS40060 and TPS40061. The result is: ǒƪ f SW + ǒT J*T AǓ ƫ ǒq JA V DDǓ ǒ2 Q gǓ * IQ Ǔ (Hz) (41) 19 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 LAYOUT CONSIDERATIONS THE PowerPAD™ PACKAGE The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP (PWP) package the dimensions of the circuit board pad are 5 mm x 3.4 mm. The dimensions of the package pad are shown in Figure 13. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally Enhanced Package[2] for more information on the PowerPAD package. X: Minimum PowerPAD = 1,86 mm Y: Minimum PowerPAD = 1,75 mm Thermal Pad 4,50 mm 6,60 mm 4,30 mm 6,20 mm X 1 Y 10 Figure 13. PowerPAD Dimensions MOSFET PACKAGING MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θJA) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on proper layout and thermal management. The θJAspecified in the MOSFET data sheet refers to a given copper area and thickness. In most cases, a thermal impedance of 40°C/W requires one square inch of 2-ounce copper on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. Please refer to the selected MOSFET's data sheet for more information regarding proper mounting. GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS The device provides separate signal ground (SGND) and power ground (PGND) pins. It is important that circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor. Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The SGND plane should only make a single point connection to the PGND plane. Component placement should ensure that bypass capacitors (BP10, BP5, and BPN10) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high dv/dt nodes such as HDRV, LDRV, BPN10, and the switch node (SW). 20 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 DESIGN EXAMPLE • • • • • • • Input voltage: 18 VDC to 55 VDC Output voltage: 3.3 V ±2% Output current: 5 A (maximum, steady-state), 7 A (surge, 10-ms duration, 10% duty cycle maximum) Output ripple: 33 mVP-P at 5 A Output load response: 0.3 V => 10% to 90% step load change Operating temperature: –40°C to 85°C fSW = 130 kHz 1. Calculate maximum and minimum duty cycles d MIN + V O(min) VIN(max) + 0.0588 d MAX + V O(max) V IN(min) ++ 0.187 (42) 2. Select switching frequency The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater than 330 ns (see Electrical Characteristics table). Therefore V O(min) t + ON or V IN(max) T SW ȡǒ ȣ Ǔ V IN(max) ȧ ȧ 1 +f SW +ȧ T SW T ON ȧ ȧ ȧ Ȣ Ȥ (43) VO(min) Using 400 ns to provide margin, f SW + 0.0588 + 147 kHz 400 ns (44) (45) Since the oscillator can vary by 10%, decrease fSW, by 10% fSW = 0.9 × 147 kHz = 130 kHz and therefore choose a frequency of 130 kHz. 3. Select∆ I In this case ∆I is chosen so that the converter enters discontinuous mode at 20% of nominal load. DI + I O 2 0.2 + 5 2 0.2 + 2.0 A (46) 4. Calculate the power losses Power losses in the high-side MOSFET (Si9407AGY) at 55-VIN where switching losses dominate can be calculated from Equation 46 through Equation 49. Ǹd + 5 Ǹ0.0588 + 1.2 A I +I RMS O substituting Equation 30 into Equation 29 yields P COND + 1.22 0.12 (1 ) 0.007 (150 * 25)) + 0.324 W (47) (48) and from Equation 31, the switching losses can be determined. 21 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 DESIGN EXAMPLE (continued) P SW(fsw) + ǒVIN IO t SWǓ f SW + 55 V 5A 20 ns 130 kHz + 0.715 W (49) The MOSFET junction temperature can be found by substituting Equation 33 into Equation 32 T J + ǒPCOND ) PSWǓ q JA ) T A + (0.324 ) 0.715) 40 ) 85 + 127 C O (50) 5. Calculate synchronous rectifier losses The synchronous rectifier MOSFET has two (2) loss components, conduction, and diode reverse recovery losses. The conduction losses are due to IRMS losses as well as body diode conduction losses during the dead time associated with the anti-cross conduction delay. The IRMS current through the synchronous rectifier from Equation 51 Ǹ1 * d + 5 Ǹ1 * 0.0588 + 4.85 A I +I RMS O (51) RMS The synchronous MOSFET conduction loss from Equation 29 is: P COND + I RMS 2 R DS(on) + 4.85 2 0.011 (1 ) 0.007(150 * 25)) + 0.10 W The body diode conduction loss from Equation 35 is: P DC + 2 I O V FD t DELAY f SW + 2 5.0 A 0.8 V The body diode reverse recovery loss from Equation 36 is: P RR + 0.5 Q RR V IN f SW + 0.5 30 nC 55 V 100 ns 130 kHz + 0.104 W 130 kHz + 0.107 W (52) (53) (54) The total power dissipated in the synchronous rectifier MOSFET from Equation 37 is: P SR + PRR ) PCOND ) PDC + 0.107 ) 0.1 ) 0.104 + 0.311 W (55) The junction temperature of the synchronous rectifier at 85°C is: T J + PSR q JA ) T A + (0.311) 40 ) 85 + 97 oC (56) In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode conduction and reverse recovery periods. 6. Calculate the Inductor Value The inductor value is calculated from Equation 11 (48 * 3.3) 3.3 L+ + 11.8 mH 48 2.0 130 kHz (57) A standard inductor value of 10-µH is chosen. A Coev DXM1306-10RO or Panasonic ETQPF102HFA could be used. 7. Setting the switching frequency The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be derived from following Equation 58, with fSW in kHz. RT + ǒ f SW Ǔ 1 * 23 kW + 408 kW, 17.82 E * 06 use 412 kW (58) 8. Programming the Ramp Generator Circuit The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also controls the input UVLO voltage. For an undervoltage level of 14.4V (20% below the 18 VIN(min), RKFF is calculated in Equation 59. 22 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 DESIGN EXAMPLE (continued) R KFF + ǒVIN(min) * 3.5Ǔǒ65.27 R T ) 1502Ǔ W + 133.7 kW, use 133 kW (59) 9. Calculating the Output Capacitance (CO) In this example. the output capacitance is determined by the load response requirement of ∆V = 0.3 V for a 1 A to 5 A step load. CO can be calculated using Equation 18. 10 mH ǒ5 2 * 1 2Ǔ CO + + 127 mF ǒ3.3 2 * 3.0 2Ǔ (60) Using Equation 13 calculate the ESR required to meet the output ripple requirements. ǒ 33 mV + 2.0 ESR ) 8 1 127 mF 130 kHz Ǔ (61) ESR = 12.7 mΩ In order to get the required ESR, the capacitance needs to be greater than the 127-µF calculated. For example, a single Panasonic SP capacitor, 180-µF with ESR of 12 mΩ can be used. Re-calculating the ESR required with the new value of 180-µF is shown in Equation 62. ǒ 33 mV + 2.0 ESR ) 8 1 180 mF 130 kHz Ǔ (62) ESR = 13.8 mΩ 10. Calculate the Soft-Start Capacitor (CSS) This design requires a soft-start time (tSTART) of 1 ms. CSS is calculated in Equation 63. 2.3 mA C SS + 1 ms + 3.28 nF + 3300 pF 0.7 V (63) 11. Calculate the Current Limit Resistor (RILIM) The current limit set point depends on tSTART, VO, CO and ILOAD at start up as shown in Equation 7. 180 mF 3.3 I LIM u ) 7.0 + 7.6 A 1m (64) Set ILIM for 10.0 A minimum, then from Equation 7 V (50 mV) R ILIM + 10 0.14 ) OS W + 10 0.14 ) W + 175 kW + 174 kW I SINK I SINK 8.3 mA 8.3 mA (65) 12. Calculate Loop Compensation Values Calculate the DC modulator gain (AMOD) from Equation 19. A MOD + 10 + 5 2 A MOD(dB) + 20 log (5.0) + 14 dB Calculate the output poles and zeros from Equation 21 and Equation 22 of the L-C filter. 1 f LC + + 3.7 kHz 2p Ǹ10 mH 180 mF (66) (67) (68) and fZ + 2p 1 0.012 180 mF + 74 kHz (69) Select the close-loop 0 dB crossover frequency, fC. For this example fC = 10 kHz. 23 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 DESIGN EXAMPLE (continued) Select the double zero location for the Type III compensation network at the output filter double pole at 3.7 kHz. Select the double pole location for the Type III compensation network at the output capacitor ESR zero at 73.7 kHz. The amplifier gain at the crossover frequency of 10 kHz is determined by the reciprocal of the modulator gain AMOD at the crossover frequency from Equation 27. A MOD(f) + AMOD ǒ Ǔ f LC fC 2 +5 kHzǓ ǒ3.7 10 kHz 2 + 0.68 And also from Equation 27. 1 G+ + 1 + 1.46 0.68 A MOD(f) (70) (71) Choose R1 = 100 kΩ The poles and zeros for a Type III network are described in Equation 25 and Equation 26. 1 1 f Z2 + N C3 + + 430 pF, choose 470 pF 2p R1 C3 2p 100 kW 3.7 kHz 1 1 f P2 + N R3 + + 4.62 kW, choose 4.64 kW 2p R3 C3 2p 470 pF 73.3 kHz 1 1 fC + N C2 + + 109 pF, choose 100 pF 2p R1 C2 G 2p 100 kW 3.29 1.46 kHz 1 1 f P1 + N R2 + + 21.7 kW, choose 21.5 kW 2p R2 C2 2p 100 pF 73.3 kHz 1 1 f Z1 + N C1 + + 2000 pF, choose 1800 pF 2p R2 C1 2p 21.5 kW 3.7 kHz Calculate the value of RBIAS from Equation 23 with R1 = 100 kΩ. R BIAS + 0.7 V R1 + 0.7 V 100kW + 26.9 kW, choose 26.7 kW VO * 0.7 V 3.3 V * 0.7 V (72) (73) (74) (75) (76) (77) CALCULATING THE BPN10 AND BP10V BYPASS CAPACITANCE The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount of droop allowed on the bypass capacitor. The BPN10 capacitance, allowing for a 0.5-V droop on the BPN10 pin from Equation 8 is shown in Equation 78. Qg C BPN10 + + 30 nC + 60 nF 0.5 DV (78) and the BP10V capacitance from Equation 9 is shown in Equation 79. Q gSR C BP10V + + 57 nC + 114 nF 0.5 DV (79) For this application, a 0.1-µF capacitor was used for the BPN10V and a 1.0-µF was used for the BP10V bypass ccapacitor. Figure 14 shows component selection for the 18-V through 55-V to 3.3-V at 5-A dc-to-dc converter specified in the design example. GATE DRIVE CONFIGURATION Due to the possibility of dv/dt induced turn-on from the fast MOSFET switching times, high VDS voltage and low gate threshold voltage of the Si4470, the design includes a 2-Ω in the gate lead of the upper MOSFET. The resistor can be used to shape the low-to-high transition of the SWitch node and reduce the tendancy of dv/dt-induced turn on. 24 TPS40060 TPS40061 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 DESIGN EXAMPLE (continued) RKFF 133 kΩ RILIM 174 kΩ TPS40060PWP + 1 KFF ILIM 16 2 RT VIN 15 3 BP5 RT 412 kΩ VIN 2Ω HDRV 14 Si9470 0.1 µF − 4 CSS 3300 pF BPN10 13 5 SGND SW 12 6 SS/SD BP10 11 7 C1 1800 pF 8 R2 21.5 kΩ SYNC C2 100 pF COMP PGND RSW 10 Ω 30BQ060 10 µH 1.0 µF + Si4470 LDRV 10 VFB 0.1 µF PGND 9 R3 4.64 kΩ R1 100kΩ CO 180 µF VOUT C3 470 pF − RBIAS 26.7 kΩ UDG−02161 Figure 14. Design Example, 48 V to 3.3 V at 5 A dc-to-dc Converter REFERENCES 1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic 2. 2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief: TI Literature No. SLMA002 25 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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