TI TPS40055PWP

8
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
FEATURES
D Operating Input Voltage 8 V to 40 V
D Input Voltage Feed-Forward Compensation
D < 1 % Internal 0.7-V Reference
D Programmable Fixed-Frequency Up to 1 MHz
DESCRIPTION
The TPS4005x is a family of high-voltage, wide
input (8 V to 40 V), synchronous, step-down
converters. The TPS4005x family offers design
flexibility with a variety of user programmable
functions, including soft-start, UVLO, operating
frequency, voltage feed- forward, high-side
current limit, and loop compensation.
Voltage Mode Controller
D Internal Gate Drive Outputs for High-Side and
D
D
D
D
D
D
D
D
Synchronous N-Channel MOSFETs
16-Pin PowerPADt Package (θJC = 2°C/W)
Thermal Shutdown
Externally Synchronizable
Programmable High-Side Current Limit
Programmable Closed-Loop Soft-Start
TPS40054 Source Only
TPS40055 Source/Sink
TPS40057 Source/Sink With VOUT Prebias
The TPS4005x are also synchronizable to an
external supply. They incorporate MOSFET gate
drivers for external N-channel high-side and
synchronous rectifier (SR) MOSFETs. Gate drive
logic incorporates anti-cross conduction circuitry
to prevent simultaneous high-side and
synchronous rectifier conduction.
The TPS4005x uses voltage feed-forward control
techniques to provide good line regulation over
the wide (4:1) input voltage range, and fast
response to input line transients with near
constant gain with input variation which eases
loop compensation. The externally programmable
current limit provides pulse-by-pulse current limit,
as well as hiccup mode operation utilizing an
internal fault counter for longer duration
overloads.
APPLICATIONS
D Power Modules
D Networking/Telecom
D Industrial
D Servers
SIMPLIFIED APPLICATION DIAGRAM
TPS4005xPWP
VIN
1
KFF
ILIM
16
2
RT
VIN
15
3
BP5
BOOST
14
4
SYNC
HDRV
13
5
SGND
SW
12
6
SS/SD
BP10
11
7
VFB
LDRV
10
8
COMP
PGND
9
+
VOUT
−
UDG−03179
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Copyright  2004, Texas Instruments Incorporated
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1
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
APPLICATION
PACKAGE
PART NUMBER
SOURCE(2)
Plastic HTSSOP
(PWP)(NO TAG)
TPS40054PWP
SOURCE/SINK(2)
Plastic HTSSOP
(PWP)(NO TAG)
TPS40055PWP
SOURCE/SINK(2) with prebias
Plastic HTSSOP
(PWP)(NO TAG)
TPS40057PWP
−40°C to 85°C
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40054PWPR). See the application section
of the data sheet for PowerPAD drawing and layout information.
(2) See Application Information section, pg. 7
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(3)
TPS40054
TPS40055
TPS40057
VIN
Input voltage range, VIN
UNIT
45
VFB, SS, SYNC
−0.3 to 6
SW
−0.3 to 45
SW, transient < 50 ns
V
−2.5
KFF, with IIN(max) = −5 mA
−0.3 to 11
Output voltage range, VOUT
COMP, RT, SS
−0.3 to 6
Input current, IIN
KFF
5
mA
Output current, IOUT
RT
200
µA
Operating junction temperature range, TJ
−40 to 125
Storage temperature, Tstg
−55 to 150
°C
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
(3) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage, VI
8
Operating free-air temperature, TA
2
−40
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NOM
MAX
UNIT
40
V
85
°C
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
PWP PACKAGE(4)(5)
(TOP VIEW)
KFF
RT
BP5
SYNC
SGND
SS/SD
VFB
COMP
1
2
3
4
5
6
7
8
THERMAL
PAD
16
15
14
13
12
11
10
9
ILIM
VIN
BOOST
HDRV
SW
BP10
LDRV
PGND
(4) For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002.
(5) PowerPADt heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.
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3
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
ELECTRICAL CHARACTERISTICS
TA = −40°C to 85°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range, VIN
OPERATING CURRENT
IDD
Quiescent current
8
Output drivers not switching,
VFB ≥ 0.75 V
40
V
1.5
3.0
mA
BP5
VBP5
Output voltage
OSCILLATOR/RAMP GENERATOR(2)
IOUT ≤ 1 mA
4.7
5.0
5.2
V
fOSC
Accuracy
VRAMP PWM ramp voltage(1)
8 V ≤ VIN ≤ 40 V
470
520
570
kHz
VIH
VIL
High-level input voltage, SYNC
ISYNC
Input current, SYNC
VPEAK−VVAL
2.0
2
5
Low-level input voltage, SYNC
Pulse width, SYNC
VRT
Maximum duty cycle
Minumum duty cycle
VKFF
IKFF
0.8
V
5
10
µA
2.50
2.58
50
RT voltage
2.38
VFB = 0 V, fSW ≤ 500 kHz
VFB = 0 V, 500 kHz ≤ fSW ≤ 1 MHz (1)
VFB ≥ 0.75 V
Feed-forward voltage
ns
85%
V
94%
80%
0%
3.35
Feed-forward current operating range(1)
V
3.48
20
3.65
V
1100
µA
2.95
µA
SOFT START
ISS
VSS
Soft-start source current
1.65
tDSCH
tSS
Discharge time
CSS = 220 pF
Soft-start time
CSS = 220 pF,
Soft-start clamp voltage
2.35
3.7
0 V ≤ VSS ≤ 1.6 V
V
1.6
2.2
2.8
115
150
215
9.0
9.6
10.3
µss
BP10
VBP10 Ouput voltage
ERROR AMPLIFIER
VFB
Feedback input voltage
IOUT ≤ 1 mA
8 V ≤ VIN ≤ 40 V,
8 V ≤ VIN ≤ 40 V,
TA = 25°C
0°C ≤ TA ≤ 85°C
0.698
0.700
0.704
0.693
0.700
0.707
8 V ≤ VIN ≤ 40 V,
−40°C ≤ TA ≤ 85°C
0.693
0.700
0.715
V
V
GBW
Gain bandwidth(1)
3.0
5.0
MHz
AVOL
IOH
Open loop gain
60
80
dB
High-level output source current
2.0
4.0
IOL
VOH
Low-level output sink current
2.0
4.0
3.2
3.5
VOL
IBIAS
Low-level output voltage
ISOURCE = 500 µA
ISINK = 500 µA
Input bias current
VFB = 0.7 V
(1)
(2)
4
High-level output voltage
Ensured by design. Not production tested.
IKFF increases with SYNC frequency, IKFF decreases with maximum duty cycle
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mA
0.20
0.35
100
200
V
nA
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
ELECTRICAL CHARACTERISTICS
TA = −40°C to 85°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
8.5
10.0
11.5
µA
CURRENT LIMIT
ISINK
Current limit sink current
Propagation delay to output
tON
tOFF
VOS
VILIM = 23.7 V, VSW = (VILIM − 0.5 V)
VILIM = 23.7 V, VSW = (VILIM − 2 V)
Switch leading-edge blanking pulse time(1)
300
200
Off time during a fault
Offset voltage SW vs. ILIM
ns
100
7
−90
−70
cycles
TA = 25°C
VILIM = 23.6 V,
−50
0°C ≤ TA ≤ 85°C
−120
−38
VILIM = 23.6 V,
−40°C ≤ TA ≤ 85°C
−120
−20
mV
OUTPUT DRIVER
tLRISE
tLFALL
Low-side driver rise time
tHRISE
tHFALL
High-side driver rise time
Low-side driver fall time
High-side driver fall time
CLOAD = 2200 pF
CLOAD = 2200 pF, (HDRV − SW)
VOH
High-level ouput voltage, HDRV
IHDRV = −0.1 A (HDRV − SW)
VOL
Low-level ouput voltage, HDRV
IHDRV = 0.1 A (HDRV − SW)
VOH
High-level ouput voltage, LDRV
ILDRV = −0.1 A
VOL
Low-level ouput voltage, LDRV
ILDRV = 0.1 A
BOOST
−1.5 V
48
96
24
48
48
96
36
72
ns
BOOST
−1.0 V
0.75
BP10
−1.4 V
V
BP10
− 1.0 V
0.5
Minimum controllable pulse width
100
150
ns
90
125
160
190
210
245
VBOOST Output voltage
VIN = 24.0 V
RECTIFIER ZERO CURRENT COMPARATOR (TPS40054 ONLY)
31.2
32.2
33.5
VSW
Switch voltage
SW NODE
−10
−5
0
mV
25
µA
SS/SD SHUTDOWN
VSD
VEN
Shutdown threshold voltage
Outputs off
Device active threshold voltage
mV
BOOST REGULATOR
LDRV output OFF
ILEAK
Leakage current(1)
THERMAL SHUTDOWN
Shutdown temperature(1)
Hysteresis(1)
TSD
165
V
°C
20
UVLO
VUVLO
VDD
KFF programmable threshold voltage
VDD
UVLO, hysteresis
(1)
(2)
RKFF = 28.7 kΩ
UVLO, fixed
6.95
7.50
7.95
7.2
7.5
7.9
V
0.46
Ensured by design. Not production tested.
IKFF increases with SYNC frequency, IKFF decreases with maximum duty cycle
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5
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BOOST
14
O
Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input
voltage. A 0.1-µF ceramic capacitor should be connected from this pin to the drain of the lower MOSFET.
BP5
3
O
5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used
with an external DC load of 1 mA or less.
BP10
11
O
10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF
ceramic capacitor. This pin may be used with an external DC load of 1 mA or less.
COMP
8
O
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the
VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to
improve large signal transient response.
HDRV
13
O
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
(MOSFET off).
ILIM
16
I
Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a
voltage drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared
to the voltage drop (VIN −SW) across the high side MOSFET during conduction.
KFF
1
I
A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into
this pin is internally divided and used to control the slope of the PWM ramp.
LDRV
10
O
Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground
(MOSFET off).
PGND
9
−
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s)
of the lower MOSFET(s).
RT
2
I
A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
SGND
5
−
Signal ground reference for the device.
SS/SD
6
I
Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The
capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS pin is used
as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is
approximately 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V.
The controller is considered shut down when VSS/SD is 125 mV or less. All internal circuitry is inactive. The
internal circuitry is enabled when VSS/SD is 210 mV or greater. When VSS/SD is less than approximately 0.85 V,
the outputs cease switching and the output voltage (VOUT) decays while the internal circuitry remains active.
SW
12
I
This pin is connected to the switched node of the converter and used for overcurrent sensing. The TPS40054
and TPS40057 versions use this pin for zero current sensing as well.
SYNC
4
I
Syncronization input for the device. This pin can be used to synchronize the oscillator to an external master
frequency. If synchronization is not used, connect this pin to SGND.
VFB
7
I
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference
voltage, 0.7 V.
VIN
15
I
Supply voltage for the device.
6
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
SIMPLIFIED BLOCK DIAGRAM
ILIM
16
10V Regulator
BP10
VIN 15
−
CLK
RT
+
CLK Oscillator
2
11 BP10
14
1V5REF
7
BOOST
7 CLK
SYNC 4
07VREF7
Ramp Generator
1V5REF 7
Reference
Voltages 3V5REF7
BP5 7
KFF 1
7 CL
3−bit up/down
Fault Counter
N−channel
Driver
13 HDRV
7
7
Restart Fault
BP5 3
12 SW
BP5 7
7 BP10
7 Fault
7 07VREF
VFB 7
7
+
+
Soft Start
SS/SD 6
0V7REF
R Q
n−channel
Driver
10 LDRV
+
7 07VREF
tstart
7
S Q
CL
7
CLK
7 SW
S Q
9
Restart
PGND
R Q
COMP 8
Zero Current Detector
(TPS40054 Only)
5
UDG−0212
8
SGND
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
The TPS40054/55/57 family of parts allows the user to optimize the PWM controller to the specific application.
The TPS40055 is the controller of choice for synchronous buck designs which will include most applications.
It has two quadrant operation and will source or sink output current. This provides the best transient response.
The TPS40054 operates in one quadrant and sources output current only, allowing for paralleling of converters
and ensures that one converter does not sink current from another converter. This controller also emulates a
standard buck converter at light loads where the inductor current goes discontinuous. At continuous output
inductor currents the controller operates as a synchronous buck converter to optimize efficiency.
The TPS40057 operates in one quadrant as a standard buck converter during start up. After the output has
reached the regulation point, the controller operates in two quadrant mode and is put in a synchronous buck
configuration. This is useful for applications that have the output voltage ’pre-biased’ at some voltage before
the controller is enabled. When the TPS40057 controller is enabled it does not sink current during start up which
would pull current from the pre-biased voltage supply.
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
The TPS4005x has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the
master clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the clock oscillator is set by
a single resistor (RT) to ground. The clock frequency is related to RT, in kΩ by equation (1) and the relationship
is charted in Figure 2.
RT +
8
ǒ
f SW
1
17.82
10 *6
Ǔ
* 17
kW
(1)
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
PROGRAMMING THE RAMP GENERATOR CIRCUIT
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator
provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a
constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line
variations since the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1).
VIN
VIN
SW
SW
RAMP
VPEAK
COMP
COMP
RAMP
VVALLEY
tON1
t
d + ON
T
T1
tON2
T2
tON1 > tON2 and d1 >
d2
UDG−02131
Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle
The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The
PWM ramp time is programmed via a single resistor (RKFF) pulled up to VIN. RKFF is related to RT, and the
minimum input voltage, VIN(min) through the following:
ǒ
R KFF + V IN (min) * 3.5
Ǔ ǒ58.14
R T ) 1340Ǔ W
(2)
where:
D VIN(min) is the ensured minimum start-up voltage. The actual start-up voltage is nominally about 10% lower
at 25°C.
D RT is the timing resistance in kΩ
The curve showing the RKFF required for a given switching frequency, fSW, is shown in Figure 3.
For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle
prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and
regulates the output voltage. For more information on large duty cycle operation, refer to Application Note
(SLUA310).
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9
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
FEED-FORWARD IMPEDANCE
vs
SWITCHING FREQUENCY
SWITCHING FREQUENCY
vs
TIMING RESISTANCE
700
RKFF − Feed-Forward Impedance − kΩ
600
RT − Timing Resistance − kΩ
500
400
300
200
100
0
100
600
500
400
VIN = 9 V
300
VIN = 15 V
VIN = 25 V
200
100
200
300
400
500
600
700
800
900 1000
0
100
fSW − Switching Frequency − kHz
200
300 400
500
600
700
800
900 1000
fSW − Switching Frequency − kHz
Figure 3
Figure 2
UVLO OPERATION
The TPS4005x uses variable (user programmable) UVLO protection. The UVLO circuit holds the soft-start low
until the input voltage has exceeded the user programmable undervoltage threshold.
The TPS4005x uses the feed-forward pin, KFF, as a user programmable low-line UVLO detection. This variable
low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage
condition exists if the TPS4005x receives a clock pulse before the ramp has reached 90% of its full amplitude.
The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The
KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor
can be referenced to the oscillator frequency as descibed in equation (3):
ǒ
R KFF + V IN (min) * 3.5
Ǔ ǒ58.14
R T ) 1340Ǔ W
(3)
where:.
D VIN is the desired start-up (UVLO) input voltage
D RT is the timing resistance in kΩ
The variable UVLO function uses a three−bit full adder to prevent spurious shut-downs or turn-ons due to spikes
or fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter than
the clock cycle a powergood signal is asserted and a soft-start initiated, and the upper and lower MOSFETS
are turned off.
10
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
Once the soft-start is initiated, the UVLO cicruit must see a total count of seven cycles in which the ramp duration
is longer than the clock cycle before an undervoltage condition is declared. (See Figure 4).
UVLO Threshold
VIN
Clock
PWM RAMP
1 2 3 4 5 6 7
1 2
1 2 3 4 5 6 7
PowerGood
UDG−02132
Figure 4. Undervoltage Lockout Operation
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at
the nominal start up voltage.
The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter
starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents
nuisance shutdowns at the UVLO point. With RT chosen to select the operating frequency and RKFF chosen
to select the start−up voltage, the approximate amount of hysteresis voltage is shown in Figure 5.
UNDERVOLTAGE LOCKOUT THRESHOLD
vs
HYSTERESIS
1.2
VUVLO − Hysteresis − V
1.0
0.8
0.6
0.4
0.2
0
10
15
20
25
30
35
40
VUVLO − Undevoltage Lockout Threshold − V
Figure 5.
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11
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
BP5 AND BP10 INTERNAL VOLTAGE REGULATORS
Start-up characteristics of the BP5 and BP10 regulators over different temperature ranges are shown in
Figures 6 and 7. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the
BP10 regulation characteristics is also based on the load presented by switching the external MOSFETs.
INPUT VOLTAGE
vs
BP5 VOLTAGE
6
10
5
8
VBP10 − BP10 Voltage − V
VBP5 − BP5 Voltage − V
INPUT VOLTAGE
vs
BP10 VOLTAGE
110°C
4
−55°C
3
25°C
2
6
110°C
4
25°C
−55°C
2
1
0
2
4
6
8
VIN− Input Voltage − V
10
12
Figure 6.
2
4
6
8
VIN− Input Voltage − V
10
12
Figure 7.
SELECTING THE INDUCTOR VALUE
The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current
at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but
is physically larger for the same load current. Too small an inductance results in larger ripple currents and a
greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good
compromise is to select the inductance value such that the converter doesn’t enter discontinuous mode until
the load approximated somewhere between 10% and 30% of the rated output. The inductance value is
described in equation (4).
L+
ǒVIN * VOǓ
V IN
DI
VO
f SW
(Henries)
(4)
where:.
D VO is the output voltage
D ∆I is the peak-to-peak inductor current
12
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
CALCULATING THE OUTPUT CAPACITANCE
The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any
output voltage deviation requirement during a load transient.
The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output
ripple is described in equation (5).
DV + DI
ƪ
ESR )
ǒ
8
1
CO
f SW
Ǔƫ
V P*P
(5)
The output ripple voltage is typically between 90% and 95% due to the ESR component.
The output capacitance requirement typically increases in the presence of a load transient requirement. During
a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess
inductor energy (heavy to light load step) while maintaining the output voltage within acceptable limits. The
amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the
inductor.
Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the
inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in
equation (6).
EL + 1
2
I 2 (Joules)
L
(6)
where:
I2 +
ƪ ǒI
OH
Ǔ
2
* ǒI OLǓ
ƫ
2
ǒ(Amperes)2Ǔ
(7)
D IOH is the output current under heavy load conditions
D IOL is the output current under light load conditions
Some applications may require an additional circuit to prevent false restarts at the UVLO voltage level. This
applies to applications which have high impedance on the input voltage line or which have excessive ringing
on the VIN line. The input voltage impedance can cause the input voltage to sag enough at start-up to cause
a UVLO shutdown and subsequent restart. Excessive ringing can also affect the voltage seen by the device and
cause a UVLO shutdown and restart. A simple external circuit provides a selectable amount of hysteresis to
prevent the nuisance UVLO shutdown.
Assuming a hysteresis current of 10% IKFF, and the peak detector charges to 8 V and VIN(min) = 10 V, the value
of RA is calculated by equation (8) using a RKFF = 71.5 kΩ.
RA +
R KFF
0.1
(8 * 3.5)
ǒVIN(min) * 3.5Ǔ
+ 495 kW ^ 499 kW
(8)
CA is chosen to maintain the peak voltage between switching cycles. To keep the capacitor charge from
drooping 0.1-V, or from 8 V to 7.9 V.
CA +
ǒR A
(8 * 3.5)
7.9
f SWǓ
(9)
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13
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
The value of CA imay calculate to less than 10 pF, but some standard value up to 470 pF works adequately. The
diode can be a small signal switching diode or Schottky rated for more then 20 V. Figure 5 illustrates a typical
implementation using a small switching diode.
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at
the nominal start up voltage.
+
VIN
RA
499 kW
−
RKFF
71.5 kW
CA
470 pF
TPS40050PWP
TPS40051PWP
1 KFF
ILIM 16
2 RT
VIN 15
3 BP5
BOOST 14
4 SYNC
HDRV 13
5 SGND
SW 12
6 SS
BP10 11
7 VFB
LDRV 10
8 COMP
PGND 9
PWP
DA
1N914, 1N4150
Type Signal Diode
UDG−03034
Figure 8. Hysteresis for Programmable UVLO
Energy in the capacitor is described in equation (10).
EC + 1
2
V 2 (Joules)
C
(10)
where:
V2 +
ƪ ǒV Ǔ * ǒ V Ǔ ƫ
2
2
f
ǒVolts2Ǔ
i
(11)
where:
D Vf is the final peak capacitor voltage
D Vi is the initial capacitor voltage
Substituting equation (7) into equation (6), then substituting equation (11) into equation (10), then setting
equation (10) equal to equation (6), and then solving for CO yields the capacitance described in equation (12).
L
CO +
ƪ ǒI Ǔ * ǒ I Ǔ ƫ
ƪ ǒV Ǔ * ǒV Ǔ ƫ
2
OL
2
f
14
2
OH
(Farads)
2
i
(12)
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
PROGRAMMING SOFT START
TPS4005x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start
is programmed by charging an external capacitor (CSS) via an internally generated current source. The voltage
on CSS minus 0.85 V is fed into a separate non-inverting input to the error amplifier (in addition to FB and
0.7-V VREF). The loop is closed on the lower of the (CSS − 0.85 V) voltage or the internal reference voltage
(0.7-V VREF). Once the (CSS − 0.85 V) voltage rises above the internal reference voltage, regulation is based
on the internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be
greater than the L-CO time constant as described in equation (13).
t START w 2p
ǸL
C O (seconds)
(13)
There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART,
the higher the input current required during start-up. This relationship is describe in more detail in the section
titled, Programming the Current Limit which follows. The soft-start capacitance, CSS, is described in
equation (14).
For applications in which the VIN supply ramps up slowly, (typically between 50 ms and 100 ms) it may be
necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO
tripping. The soft-start time should be longer than the time that the VIN supply transitions between 6 V and 7 V.
C SS +
2.3 mA
0.7 V
t START (Farads)
(14)
PROGRAMMING CURRENT LIMIT
The TPS4005x uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection
scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the
MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across
the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.
The MOSFET remains off until the next switching cycle is initiated.
The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and
decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is
issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this
period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the
PWM is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the
counter counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 6 for typical
overcurrent protection waveforms.
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15
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
The minimum current limit setpoint (ILIM) depends on tSTART, CO, VO, and the load current at turn-on (IL).
I LIM +
ƪ
ǒC O
V OǓ
t START
ƫ
) I L (Amperes)
(15)
HDRV
CLOCK
tBLANKING
VILIM
VVIN−VSW
SS
7 CURRENT LIMIT TRIPS
(HDRV CYCLE TERMINATED BY CURRENT LIMIT
TRIP)
7 SOFT-START CYCLES
UDG−02136
Figure 9. Typical Current Limit Protection Waveforms
The current limit programming resistor (RILIM) is calculated using equation (16).
R ILIM +
I OC
R DS(on)[max]
1.12
I SINK
)
V OS
I SINK
(W)
(16)
where:
D ISINK is the current into the ILIM pin and is nominally 10 µA,
D IOC is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current
D VOS is the overcurrent comparator offset and
is nominally −75 mV
SYNCHRONIZING TO AN EXTERNAL SUPPLY
The TPS4005x can be synchronized to an external clock through the SYNC pin. Synchronization occurs on the
falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher
than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock
generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4005x to freely run at the
frequency programmed by RT.
16
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM
ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically
this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching
frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a ’dummy’
value for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT
in the design.
R T(dummy) +
ǒ
1
17.82
f SYNC
10 *6
Ǔ
* 17
kW
(17)
Use the value of RT(dummy) to calculate the value for RKFF.
ǒ
Ǔ ǒ58.14
R KFF + V IN(min) * 3.5 V
Ǔ
R T(dummy) ) 1340 W
(18)
This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency.
D RT(dummy) is in kΩ
LOOP COMPENSATION
Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x
uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be
included. The modulator gain is described in Figure 9, with VIN being the minimum input voltage required to
cause the ramp excursion to cover the entire switching period as described in equation (19).
A MOD +
V IN
VS
A MOD(dB) + 20
or
log
ǒ Ǔ
V IN
VS
(19)
Duty dycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the
maximum ramp voltage, VS. Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage
to output voltage modulator gain in terms of the input voltage and ramp voltage,
D+
V
VO
+ C
V IN
VS
or
VO
V
+ IN
VC
VS
(20)
Calculate the Poles and Zeros
For a buck converter using voltage mode control there is a double pole due to the output L-CO. The double pole
is located at the frequency calculated in equation (21).
f LC +
2p
1
ǸL
(Hertz)
CO
(21)
There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located
at the frequency calculated in equation (22).
fZ +
2p
1
ESR
CO
(Hertz)
(22)
Calculate the value of RBIAS to set the output voltage, VOUT.
R BIAS + 0.7 R1 W
V OUT * 0.7
(23)
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17
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
The maximum crossover frequency (0 dB loop gain) is calculated in equation (24).
fC +
f SW
(Hertz)
4
(24)
Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this
frequency, the control to output gain has a –2 slope (−40 dB/decade), while the Type III topology has a +1 slope
(20 dB/decade), resulting in an overall closed loop –1 slope (−20 dB/decade). Figure 10 shows the modulator
gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.
PWM MODULATOR RELATIONSHIPS
MODULATOR GAIN
vs
SWITCHING FREQUENCY
ESR Zero, + 1
Modulator Gain − dB
AMOD = VIN / VS
VS
VC
Resultant, − 1
D = VC / VS
LC Filter, − 2
100
1k
10 k
fSW − Switching Frequency − Hz
100 k
Figure 11
Figure 10
A Type III topology, shown in Figure 11, has two zero-pole pairs in addition to a pole at the origin. The gain and
phase boost of a Type III topology is shown in Figure 12. The two zeros are used to compensate the L-CO double
pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled
gain roll-off. In many cases the second pole can be eliminated and the amplifier’s gain roll-off used to roll-off
the overall gain at higher frequencies.
18
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
C2
(optional)
−1
C1
R3
R2
+1
0 dB
C3
−1
VFB
R1
−90°
7
8
VOUT
GAIN
COMP
+
RBIAS
180°
PHASE
−270°
VREF
UDG−02189
Figure 12. Type III Compensation Configuration
Figure 13. Type III Compensation Gain and
Phase
The poles and zeros for a Type III network are described in equations (25).
f Z1 +
2p
1
R2
C1
f P1 +
2p
1
R2
C2
(Hertz)
f Z2 +
2p
1
R1
C3
(Hertz)
f P2 +
2p
1
R3
C3
(Hertz)
(25)
(Hertz)
The value of R1 is somewhat arbitraty, but influences other component values. A value between 50kΩ and
100kΩ usually yields reasonable values.
The unity gain frequency is described in equation (26)
fC +
1
2p
R1
C2
G
(Hertz)
(26)
where G is the reciprocal of the modulator gain at fC.
The modulator gain as a function of frequency at fC, is described in equation (27).
AMOD(f) + AMOD
ǒ Ǔ
f LC
fC
2
and
G+
1
AMOD(f)
(27)
Minimum Load Resistance
Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too
small. The error amplifier has a finite output source and sink current which must be considered when sizing R2.
Too small a value does not allow the output to swing over its full range.
R2 (MIN) +
V C (max)
I SOURCE (min)
+ 3.5 V + 1750 W
2 mA
www.ti.com
(28)
19
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
CALCULATING THE BOOST AN BP10 BYPASS CAPACITOR
The BOOST capacitance provides a local, low impedance source for the high-side driver. The BOOST capacitor
should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate
charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BOOST capacitance
is described in equation (29).
C BOOST +
Qg
(Farads)
DV
(29)
The 10-V reference pin, BP10V provides energy for both the synchronous MOSFET and the high-side MOSFET
via the BOOST capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in equation
(30).
C BP10 +
ǒQgHS ) QgSRǓ
DV
(Farads)
(30)
dv/dt INDUCED TURN-ON
MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused
by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on
the MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the
gate-to-source voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large
shoot-through currents. Therefore, the SR MOSFET should be chosen so that the CGD capacitance is smaller
than the CGS capacitance.
HIGH SIDE MOSFET POWER DISSIPATION
The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The
conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The
high-side MOSFET conduction losses are defined by equation (31).
P COND + ǒI RMSǓ
2
R DS(on)
ǒ1 ) TCR ƪTJ * 25 CƫǓ
O
(Watts)
(31)
where:
D TCR is the temperature coefficient of the MOSFET RDS(on)
The TCR varies depending on MOSFET technology and manufacturer, but typically ranges between
.0035 ppm/_C and .010 ppm/_C.
The IRMS current for the high side MOSFET is described in equation (32).
I RMS + I OUT
20
Ǹd
ǒARMSǓ
(32)
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
The switching losses for the high-side MOSFET are descibed in equation (33).
P SW(fsw) + ǒV IN
t SWǓ
I OUT
f SW (Watts)
(33)
where:
D IO is the DC output current
D tSW is the switching rise time, typically < 20 ns
D fSW is the switching frequency
Typical switching waveforms are shown in Figure 13.
ID2
IO
ID1
d
}
∆I
1−d
BODY DIODE
CONDUCTION
BODY DIODE
CONDUCTION
SW
0
ANTI−CROSS
CONDUCTION
SYNCHRONOUS
RECTIFIER ON
HIGH SIDE ON
UDG−02139
Figure 14. Inductor Current and SW Node Waveforms
The maximum allowable power dissipation in the MOSFET is determined by equation (34).
PT +
ǒT J * T AǓ
q JA
(Watts)
(34)
where:
P T + P COND ) P SW(fsw) (Watts)
(35)
and θJA is the package thermal impedance.
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21
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION
The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on)
conduction losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can
be found using equation (29) and the RMS current through the synchronous rectifier MOSFET is described in
equation (36).
I RMS + I O
Ǹ1 * d
ǒAmperesRMSǓ
(36)
The body-diode conduction losses are due to forward conduction of the body diode during the anti−cross
conduction delay time. The body diode conduction losses are described by equation (37).
P DC + 2
IO
VF
t DELAY
f SW (Watts)
(37)
where:
D VF is the body diode forward voltage
D tDELAY is the delay time just before the SW node rises
The 2-multiplier is used because the body diode conducts twice during each cycle (once on the rising edge and
once on the falling edge). The reverse recovery losses are due to the time it takes for the body diode to recovery
from a forward bias to a reverse blocking state. The reverse recovery losses are described in equation (38).
P RR + 0.5
Q RR
V IN
f SW (Watts)
(38)
where:
D QRR is the reverse recovery charge of the body diode
The QRR is not always described in a MOSFET’s data sheet, but may be obtained from the MOSFET vendor.
The total synchronous rectifier MOSFET power dissipation is described in equation (39).
P SR + P DC ) P RR ) P COND (Watts)
22
(39)
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
TPS4005X POWER DISSIPATION
The power dissipation in the TPS4005x is largely dependent on the MOSFET driver currents and the input
voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power
(neglecting external gate resistance, refer to [2] can be calculated from equation (40).
PD + Qg
V DR
f SW (Wattsńdriver)
(40)
And the total power dissipation in the TPS4005x, assuming the same MOSFET is selected for both the high-side
and synchronous rectifier is described in equation (41).
PT +
ǒ
2
PD
) IQ
V DR
Ǔ
V IN (Watts)
(41)
or
P T + ǒ2
f SW ) I QǓ
Qg
V IN (Watts)
(42)
where:
D IQ is the quiescent operating current (neglecting drivers)
The maximum power capability of the device’s PowerPad package is dependent on the layout as well as air flow.
The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no
air flow.
q JA + 36.515 CńW
O
(43)
The maximum allowable package power dissipation is related to ambient temperature by equation (44).
PT +
TJ * TA
(Watts)
q JA
(44)
Substituting equation (37) into equation (35) and solving for fSW yields the maximum operating frequency for
the TPS4005x. The result is described in equation (45).
ǒƪ
ǒT J*T AǓ
ǒq JA V DDǓ
f SW +
ǒ2
ƫ
Q gǓ
* IQ
Ǔ
(Hz)
(45)
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23
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
LAYOUT CONSIDERATIONS
THE POWERPADt PACKAGE
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For
maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the
package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP
(PWP) package dimensions of the circuit board pad area are 5 mm x 3.4 mm [2]. The dimensions of the package
pad are shown in Figure 14.
Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper
is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with
a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally
Enhanced Package[2] and the mechanical illustration at the end of this document for more information on the
PowerPAD package.
5,10 mm
4,90 mm
Thermal Pad
4,50 mm 6,60 mm
4,30 mm 6,20 mm
2,46 mm
1,86 mm
1
8
2,31 mm
1,75 mm
Figure 15. PowerPAD Dimensions
MOSFET PACKAGING
MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions.
In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance
(θJA) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends
on proper layout and thermal management. The θJA specified in the MOSFET data sheet refers to a given
copper area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch
of 2-ounce copper on a G−10/FR−4 board. Lower thermal impedances can be achieved at the expense of board
area. Please refer to the selected MOSFET’s data sheet for more information regarding proper mounting.
24
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SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
LAYOUT CONSIDERATIONS
GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS
The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that
circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if
possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling
capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor.
Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The
SGND plane should only make a single point connection to the PGND plane.
Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible
to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located
near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).
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25
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
DESIGN EXAMPLE
D
D
D
D
D
D
D
Input Voltage: 10 Vdc to 24 Vdc
Output voltage: 3.3 V ±2% (3.234 ≤ VO ≤ 3.366)
Output current: 8 A (maximum, steady state), 10 A (surge, 10 ms duration, 10% duty cycle maximum)
Output ripple: 33 mVP-P at 8 A
Output load response: 0.3 V => 10% to 90% step load change, from 1 A to 7 A
Operating temperature: −40°C to 85°C
fSW=300 kHz
1. Calculate maximum and minimum duty cycles
d MIN +
V O(min)
+ 3.324 + 0.135
24
V IN(max)
d MAX +
V O(max)
V IN(min)
+ 3.366 + 0.337
10
(46)
2. Select switching frequency
The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit
comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater
than 300 ns (see Electrical Characteristics table). Therefore
V O(min)
V IN(max)
+
t ON
T SW
or
(47)
ȡǒ VO(min) Ǔȣ
ȧ VIN(max) ȧ
1 +f
+
ȧ TON ȧ
SW
T SW
ȧ
ȧ
Ȣ
Ȥ
(48)
Using 400 ns to provide margin,
f SW + 0.135 + 337 kHz
400 ns
(49)
Since the oscillator can vary by 10%, decrease fSW, by 10%
f SW + 0.9
337 kHz + 303 kHz
and therefore choose a frequency of 300 kHz.
3. Select ∆I
In this case ∆I is chosen so that the converter enters discontinuous mode at 20% of nominal load.
DI + I O
26
2
0.2 + 8
2
0.2 + 3.2 A
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(50)
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
DESIGN EXAMPLE
4. Calculate the power losses
Power losses in the high-side MOSFET (Si7860DP) at 24-VIN where switching losses dominate can be
calculated from equation (51).
I RMS + I O
Ǹd + 8
Ǹ0.135 + 2.93 A
(51)
substituting (34) into (33) yields
P COND + 2.93 2
(1 ) 0.007
0.008
(150 * 25)) + 0.129 W
(52)
and from equation (33), the switching losses can be determined.
P SW(fsw) + ǒV IN
t SWǓ
IO
f SW + 24 V
8A
20 ns
300 kHz + 1.152 W
(53)
The MOSFET junction temperature can be found by substituting equation (35) into equation (34)
T J + ǒP COND ) P SWǓ
q JA ) T A + (0.129 ) 1.152)
40 ) 85 + 136 C
O
(54)
5. Calculate synchronous rectifier losses
The synchronous rectifier MOSFET has two (2) loss components, conduction, and diode reverse recovery
losses. The conduction losses are due to IRMS losses as well as body diode conduction losses during the dead
time associated with the anti-cross conduction delay.
The IRMS current through the synchronous rectifier from (38)
I RMS + I O
Ǹ1 * d + 8
Ǹ1 * 0.135 + 7.44 A
RMS
(55)
The synchronous MOSFET conduction loss from (33) is:
P COND + I RMS
2
R DS(on) + 7.44 2
(1 ) 0.007(150 * 25)) + 0.83 W
0.008
(56)
The body diode conduction loss from (39) is:
P DC + 2
IO
V FD
t DELAY
f SW + 2
8.0 A
0.8 V
100 ns
300 kHz + 0.384 W
(57)
The body diode reverse recovery loss from (40) is:
P RR + 0.5
Q RR
V IN
f SW + 0.5
30 nC
24 V
300 kHz + 0.108 W
(58)
The total power dissipated in the synchronous rectifier MOSFET from (41) is:
P SR + P RR ) P COND ) P DC + 0.108 ) 0.83 ) 0.384 + 1.322 W
(59)
The junction temperature of the synchronous rectifier at 85°C is:
T J + P SR
q JA ) T A + (1.322)
40 ) 85 + 139 oC
(60)
In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the
overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode
conduction and reverse recovery periods.
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27
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
DESIGN EXAMPLE
6. Calculate the inductor value
The inductor value is calculated from equation (4).
L+
(24 * 3.3 V) 3.3 V
+ 2.96 mH
24 V 3.2 A 300 kHz
(61)
A 2.9-µH Coev DXM1306−2R9 or 2.6-µH Panasonic ETQ−P6F2R9LFA can be used.
7. Setting the switching frequency
The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be found from
equation (1), with fSW in kHz.
RT +
ǒ
f SW
1
17.82
10 *6
Ǔ
* 17
kW + 170 kW N use 169 kW
(62)
8. Programming the ramp generator circuit
The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also
controls the input UVLO voltage. For an undervoltage level of 10 V, RKFF can be calculated from (2)
ǒ
Ǔ
R KFF + V IN(min) * 3.5 ǒ58.14
R T ) 1340Ǔ kW + 72.5 kW N use 71.5 kW
(63)
9. Calculating the output capacitance (CO)
In this example the output capacitance is determined by the load response requirement of ∆V = 0.3 V for a 1 A
to 8 A step load. CO can be calculated using (14)
CO +
ǒ(8 A)2 * (1 A)2Ǔ
+ 97 mF
ǒ(3.3)2 * (3.0)2Ǔ
2.9 m
(64)
Using (7) we can calculate the ESR required to meet the output ripple requirements.
ǒ
33 mV + 3.2 A ESR )
8
73 mF
Ǔ
1
300 kHz
ESR + 10.3 mW * 3.33 mW + 6.97 mW
(65)
(66)
For this design example two (2) Panasonic SP EEFUEOJ1B1R capacitors, (6.3 V, 180 µF, 12 mΩ) are used.
10. Calculate the soft-start capacitor (CSS)
This design requires a soft−start time (tSTART) of 1 ms. CSS can be calculated on (16)
C SS +
28
2.3 mA
0.7 V
1 ms + 3.29 nF + 3300 pF
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(67)
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
DESIGN EXAMPLE
11. Calculate the current limit resistor (RILIM)
The current limit set point depends on tSTART, VO,CO and ILOAD at start-up as shown in equation (15). For this
design,
I LIM u
360 mF 3.3 V
) 8.0 A + 9.2 A
1 ms
(68)
For this design, set ILIM for 11.0 ADC minimum. From equation (16), with IOC equal to the DC output surge current
plus one-half the ripple current of 3.2 A and RDS(on) is increased 30% (1.3 * 0.008) to allow for MOSFET heating.
R ILIM + 12.6 A
1.12
0.0104W ) (* 0.075) + 11.7 kW * 7.5 kW + 4.2 kW ^ 4.22 kW
10 mA
10 mA
(69)
12. Calculate loop compensation values
Calculate the DC modulator gain (AMOD) from equation (19)
A MOD + 10 + 5.0
2
A MOD(dB) + 20
log (5) + 14 dB
(70)
Calculate the output filter L-CO poles and CO ESR zeros from (23) and (25)
f LC +
1
2p ǸL
CO
1
+
2p Ǹ2.9 mH
360 mF
+ 4.93 kHz
(71)
and
fZ +
2p
1
ESR
CO
+
2p
1
0.006
360 mF
+ 73.7 kHz
(72)
Select the close-loop 0 dB crossover frequency, fC. For this example fC = 20 kHz.
Select the double zero location for the Type III compensation network at the output filter double pole at 4.93kHz.
Select the double pole location for the Type III compensation network at the output capacitor ESR zero at
73.7 kHz.
The amplifier gain at the crossover frequency of 20 kHz is determined by the reciprocal of the modulator gain
AMOD at the crossover frequency from equation (27).
A MOD(f) + A MOD
ǒ Ǔ
f LC
fC
2
+5
kHzǓ
ǒ4.93
20 kHz
2
+ 0.304
(73)
And also from equation (27).
G+
1
+ 1 + 3.29
0.304
A MOD(f)
(74)
Choose R1 = 100 kΩ
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29
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
DESIGN EXAMPLE
The poles and zeros for a type III network are described in equations (25) and (26).
f Z2 +
2p
1
R1
C3
f P2 +
2p
1
R3
C3
fC +
2p
R1
C2
f P1 +
2p
1
R2
C2
f Z1 +
2p
1
R2
C1
N C3 +
2p
1
100 kW
4.93 kHz
+ 323 pF, choose 330 pF
N R3 +
2p
1
330 pF
73.3 kHz
+ 6.55 kW, choose 6.49 kW
1
G
N C2 +
1
2p
100 kW
N R2 +
2p
1
22 pF
N C1 +
2p
1
97.6 kW
3.29
73.3 kHz
20 kHz
+ 24.2 pF, choose 22 pF
+ 98.2 kW, choose 97.6 kW
4.93 kHz
+ 331 pF, choose 330 pF
(75)
(76)
(77)
(78)
(79)
Calculate the value of RBIAS from equation (23) with R1 = 100 kΩ.
R BIAS + 0.7 V R1 + 0.7 V 100kW + 26.9 kW, choose 26.7 kW
V O * 0.7 V
3.3 V * 0.7 V
(80)
CALCULATING THE BOOST AND BP10V BYPASS CAPACITANCE
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass cap. The BOOST capacitance for the Si7860DP, allowing for a 0.5 voltage droop
on the BOOST pin from equation (29) is:
C BOOST +
Qg
+ 18 nC + 36 nF
0.5 V
DV
(81)
and the BP10V capacitance from (32) is
C BP(10 V) +
Q gHS ) Q gSR
DV
+
2
Qg
+ 36 nC + 72 nF
0.5 V
DV
(82)
For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1.0-µF capacitor is used
for the BP10V bypass.
DESIGN EXAMPLE SUMMARY
Figure 15 shows component selection for the 10-V to 24-V to 3.3-V at 8 A dc-to-dc converter specified in the
design example. For an 8-V input application, it may be necessary to add a Schottky diode from BP10 to BOOST
to get sufficient gate drive for the upper MOSFET. As seen in Figure 7, the BP10 output is about 6 V with the
input at 8 V so the upper MOSFET gate drive may be less than 5 V.
A schottky diode is shown connected across the synchronous rectifier MOSFET as an optional device that may
be required if the layout causes excessive negative SW node voltage, greater than or equal to 2 V.
30
www.ti.com
SLUS593B − DECEMBER 2003 − REVISED APRIL 2004
DESIGN EXAMPLE
+
RKFF
71.5 kΩ
VIN
330 µF
4.22 kΩ
330 µF
TPS4005xPWP
−
1N4150 499 kΩ
RT
169 kΩ
470 pF
100 pF
1 KFF
ILIM 16
2 RT
VIN 15
0.1 µF
3 BP5
1.0 µF
BOOST 14
22 µF
50 V
22 µF
50 V
1.0 kΩ
Optional
Hysteresis for
UVLO
4 SYNC
1.0 µF
CSS
3300 pF
5 SGND
6 SS
C1
330 pF
7 VFB
R2
97.6 kΩ
C2
22 pF
HDRV 13
Si7860
2.9 µH
+
SW 12
R3
6.49 kΩ
BP10 11
LDRV 10
Si7860
1.0 µF
8 COMP PGND 9
PWP
*optional
R1
100 kΩ 180 µF
VOUT
180 µF
C3
330 pF
−
RBIAS
26.7 kΩ
UDG−03180
Figure 16. 24-V to 3.3-V at 8-A DC-to-DC Converter Design Example
REFERENCES
1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas
Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM−1400 Topic 2.
2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief
(SLMA002)
www.ti.com
31
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