GP2015 GPS Receiver RF Front End Sept. 2007 The GP2015 is a small format RF Front-end for Global Positioning System (GPS) receivers. Equivalent in performance to the GP2010 but in a TQFP package, this product is suited for size-critical applications as the RF area can be reduced by a factor of two to three using miniature surface mount passive components The GP2015 is designed to operate from either 3 or 5 Volt supplies. Ordering Information GP2015/1G/FP1N GP2015/IG/FP1Q GP2015/1G/FP2Q GP2015/1G/FP2N 36 35 34 33 32 31 30 29 28 27 26 25 The device has been designed to operate with the GP2021 12-channel GPS Correlator and GP4020 GPS Baseband Processor, both available from Zarlink Semiconductor. Features • Ultra miniature TQFP package • Low Voltage Operation (3V - 5V) 37 38 39 24 23 22 40 41 42 21 20 19 GP2015 43 44 18 17 45 46 47 48 16 15 14 13 1 • Low Power - 200mW typ. (3V supply) Pin • C/A Code Compatible • On-chip PLL Including Complete VCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 • Triple Conversion Receiver • 48-Lead Surface Mount Quad Flat-Pack Package • Sign and Magnitude Digital Outputs • Compatible with GP2021 and GP4020 Correlators Applications • C/A Code Global Positioning by Satellite Receivers • Time Standards • Navigation • Surveying Related Products and Publications Description Data Reference GP2021 Twelve-Channel Correlator DS4057 GP4020 GPS Baseband Processor DS5134 App. Note GPS ORION 12 Channel GPS Receiver Reference Design AN4808 App Note. GP2000 GPS Receiver Hardware Design AN4855 App. Brief GP2010/GP2015: Using Murata SAFJA35M4WC0Z00 SAW Filter AB5202 Trays, Bake & Drypack Tape & Reel, Bake & Drypack Tape & Reel, Bake & Drypack Trays, Bake & Drypack *Pb Free Matte Tin The input to the device is the L1 (1575.42MHz) CoarseAcquisition (C/A) code Global Positioning signal from an antenna (via a low-noise pre-amplifier). The output is 2-bit quantised for subsequent signal processing in the digital domain. The GP2015 contains an on-chip synthesiser, mixers, AGC and a quantiser which provides Sign and Magnitude digital outputs. A minimum of external components is required to make a complete GPS front-end. Part 48 Pin LQFP 48 Pin LQFP 48 Pin LQFP* 48 Pin LQFP* Name IF Output PLL Filter 1 PLL Filter 2 VEE (OSC) VCC (OSC) VEE (OSC) VEE (REG) PRef PReset VEE (IO) CLK N/C N/C MAG SIGN OPCIKOPCIK+ VDD (IO) PDN TEST LD VEE (DIG) AGC AGC + 2 3 4 5 6 7 8 Name Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 FP48 9 10 11 12 N/C VCC (DIG) REF 2 REF 1 VCC (RF) VEE (RF) VEE (RF) RF Input VEE (RF) VEE (RF) VCC (RF) N/C O/P 1O/P 1+ VCC (2) I/P 2I/P 2+ VEE (IF) VEE (IF) O/P 2O/P 2+ VCC (3) I/P 3I/P 3+ Figure 1 - Pin connections - top view 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2007, Zarlink Semiconductor Inc. All Rights Reserved. GP2015 ABSOLUTE MAXIMUM RATINGS (Non-simultaneous) IF STRIP The input signal to the GP2015 is the GPS L1 signal received via an antenna and a suitable LNA. The L1 input is a spread spectrum signal at 1575.42MHz with 1.023Mbps BPSK modulation. The signal level at the antenna is about -130dBm, spread over a 2.046MHz bandwidth, so the wanted signal is actually buried in noise. The high RF input compression point of the GP2015 means that with subsequent IF filtering it is possible to reject large out of band jamming signals, in particular 900MHz as used by mobile telephones.The on-chip PLL generates the first local-oscillator frequency at 1400MHz. The output of the front-end mixer (Stage 1) at 175.42 MHz can then be filtered before being applied to the second stage. The double-balanced stage 1 mixer outputs are open-collectors, and require external dc bias to VCC. The second stage contains further gain and a mixer with a local oscillator signal at 140 MHz giving a second IF at 35.42 MHz. The second stage mixer is also double-balanced with open-collector outputs requiring external dc bias to VCC. The signal from stage 2 is passed through an external filter with a 1dB bandwidth of 1.9MHz. The performance of this filter is critical to system performance and it is recommended that a SAW filter is used (part number SAFJA35M4WC0Z00 , available from Murata). The output of the filter then feeds the main IF amplifier. This includes 2 AGC amplifiers and a third mixer with a local oscillator signal at 31.111 MHz giving a final IF at 4.309 MHz. There is an onchip filter after the third mixer which provides filtering centred on 4.309 MHz. The IF output, which has 1kΩ output impedance, is provided for test purposes. All of the signals within the IF amplifier are differential including the filter inputs Max. Supply Voltage 7V Max. RF Input +15dBm Max. voltage on any pin VCC/VDD + 0.5V except LD (pin 21) and PReset (pin 9), which are 5.5V Min. voltage on any pin VEE - 0.5V Storage Temperature -65°C to +150°C Operation Junction Temperature -40°C to +150°C 10MHz Reference Input 1.5V pk -pk ESD PROTECTION The GP2015 device is static sensitive. The most sensitive pins withstand a 750V test by the human body model. Therefore, ESD handling precautions are essential to avoid degradation of performance or permanent damage to this device. PRODUCT DESCRIPTION The GP2015 receives the 1575.42MHz signal transmitted by GPS satellites and converts it to a 4.309MHz IF, using triple down-conversion. The 4.309MHz IF is sampled to produce a 2-bit digital output. If the GP2015 is used in conjunction with the GP2021 correlator, then the GP2021 provides a sampling clock of 5.714MHz. This converts the IF to a 1.405MHz 2-bit digital output at TTL levels. The GP2015 can operate from a single supply from +3V (nominal) to +5V (nominal). A block diagram of the circuit is shown in figure 2. 35.42MHz FILTER (44,45) (40,41) FRONT END MIXER (32) RF Input 175.42MHz FILTER (37,38) L1 (1575.42MHz) 2nd STAGE MIXER 1.400GHz VCO AGC CAPACITOR (47,48) (23) AGC 140MHz ÷5 PLL REF I/P 10MHz (REF 2) (21) (27) ÷5 ÷2 +Vr PLL LOOP FILTER ÷7 ÷9 -Vr +1.21V PHASE DETECTOR PLL REFERENCE OSCILLATOR _ + POWER-ON RESET 1.400GHz PHASELOCKED LOOP POWER CONTROL (16,17) 40MHz CLOCK O/P (FOR CORRELATOR CHIP) (OPCIK +/-) (20) (TEST) (8) POWER-ON REFERENCE I/P (PREF) (19) POWER DOWN I/P (PDn) (9) POWER-ON RESET O/P (PRESET) Figure 2 - Block diagram of GP2015 2 SIGN O/P LATCH (15) MAG O/P LATCH (14) A -> D CONVERTER (28) REF 1 I/P (FOR USE WITH CRYSTAL REF ONLY) IF Output (4.309MHz) 31.11MHz ÷4 PLL LOCK LOGIC O/P (LD) (1) 4.3MHz FILTER AGC CONTROL (2) (3) 3rd STAGE MIXER AGC VOLTAGE REGULATOR EXTERNAL LOOP FILTER (24) (11) SIGN TTL O/P MAG TTL O/P SAMPLE CLOCK I/P (CLK) (5.71MHz TTL) GP2015 and outputs, except the IF output (pin 1), to reduce any common mode interference. The IF output is fed to a 2-bit quantiser which provides sign and magnitude (MSB and LSB) outputs. The magnitude data controls the AGC loop, such that on average the magnitude bit is set (high) 30% of the time. The AGC time constant is set by an external capacitor. The sign and magnitude data, SIGN (pin 15) and MAG (pin 14), are latched by the rising edge of the sample clock, CLK (pin 11), which is normally derived from the correlator; the GP2021 provides a 5.714MHz (=40/7) clock, giving a sampled IF centred on 1.405MHz. The Digital Interface circuits use a separate power-supply, VDD (IO), which would normally be shared with the correlator to minimise crosstalk between the analog and digital sections of the device. ON-CHIP PHASE-LOCKED LOOP SYNTHESISER All of the local oscillator signals are derived from an on chip phase locked loop synthesiser. This includes a 1400MHz VCO complete with on-chip tank circuit, dividers and phase detector, with external loop filter components. A 10.000MHz reference frequency is required for the PLL. This can be achieved by attaching an external 10.000MHz crystal to the on-chip PLL reference oscillator (see figure 5). However in most applications the user will need an external source, such as a TCXO, to provide greater frequency stability (see figure 6). An external reference should be ac coupled to REF2 (pin 27); REF 1 (pin 28) should be left open circuit. The three local oscillator signals 1400MHz, 140.0MHz and 31.11MHz are derived from the 1400MHz synthesiser output. The synthesiser also provides a 40 MHz balanced differential output clock (pins 16 & 17) which can be used to clock the GP2021 correlator. The clock is a low level differential signal which helps minimise interference with the analog areas of the circuit. A PLL lock-detect output, LD (pin 21), is also provided, which is logic high when the PLL is phaselocked to the 10.000MHz reference signal. The VCO power-supply incorporates an on-chip regulator to improve the noise-immunity of the PLL. This feature is only available when operating with a 5 volt (nominal) supply which is regulated to 3.3 volts internally. This internal regulated supply is referenced to VCC(OSC) (pin 5). Figure 7 shows the required connections for both 3 volt and 5 volt operation. A further feature of the circuit is the TEST input (pin 20). When this input is held high the PLL is unlocked with the VCO at its maximum frequency. POWER-DOWN CAPABILITY A power down function is provided on the GP2015, to limit power consumption. This powers down the majority of the circuit except the “power-on reset” function (see below). If the power down feature is not required, the Powerdown input, PDn (pin 19), should be connected to 0V dc (=Vee/Ground). POWER-ON RESET FUNCTION The GP2015 includes a voltage detector which operates from the digital interface supply. This circuit is used to produce a TTL logic low output while the GPS receiver power supply is switching on, and produces a logic high output when the power supply voltage has achieved a nominal value. This output can be used to disable the GP2021 correlator while the power supply is switching on. An internal bandgap reference of approximately +1.21V is compared with the voltage on a sense pin, PRef (pin 8); when the voltage on this pin exceeds the reference, a TTL logic high level appears at the Power-on Reset output, PReset (pin 9). Thus, if the sense input voltage is derived from an external resistive divider from the Digital Interface supply, V DD(IO) (pin 16), such that the sense voltage at nominal VCC is VS, then the supply threshold, Vcc(thresh), at which the PReset output goes to logic high is:VS = V CC (nom) x 1.21 VCC (thresh) For a V CC (nom) of 5.0V, VCC (thresh) may be set to approx. 4.0V, giving VS of 1.5V. For a V CC (nom) of 3.0V, VCC (thresh) may be set to approx. 2.4V, giving VS of 1.5V. ADDITIONAL INFORMATION All the digital inputs and outputs can use a separate power supply to help prevent digital switching transitions interacting with the analog sections of the device, and as an additional precaution, the digital inputs and outputs are on the opposite side of the device to the critical analog pins. 3 GP2015 ELECTRICAL CHARACTERISTICS The Electrical Characteristics are guaranteed over the following range of operating conditions (see Fig. 3 for test circuit): Industrial (I) grade: TAMB = -40°C to +85°C Supply voltage: VCC and VDD = +2.7V to +5.5V Test conditions (unless otherwise stated): Supply voltages: VCC = +2.7V and +5.5V, VDD = +2.7V and +5.5V Test temperature: Industrial (I) grade product: +25°C Value Characteristic Min. SUPPLY CURRENT Normal mode - Analog interface - Digital interface Power down mode - Analog interface - Digital interface Power Supply Differential Power down Response time IF STRIP Front End/Mixer 1 Conversion Gain (G1) Noise Figure Input Compression (1dB) Input Impedance -22 Differential Output Impedance RF Input Image Rejection Stage 2/Mixer 2 Conversion Gain (G2) Input Compression (1dB) Differential Input Impedance Differential Output Impedance Stage 3 High Gain (In terms of total strip) High Gain (G3) Gain Control Range Differential Input Impedance IF Output amplitude IF Output impedance 4.3MHz Filter Response Flatness 4.3 ± 1MHz Rejection @ 0.5MHz @ 50MHz 2 BIT QUANTISER Sign Duty Cycle Mag Duty Cycle AGC Time Constant ON-CHIP PLL SYNTHESISER Phase Noise ± 1kHz ± 10kHz ± 100kHz ± 1MHz ± 5MHZ ± 50MHz PLL Spurs 4 22 5 55 9 3 3 77 14.5 6 5 100 mA mA mA mA mV µs Pins 5, 26, 29, 35, 39, 46 Pin 18 Pins 5, 26, 29, 35, 39, 46 Pin 18 Between any VCC/VDD pins (Note 7) (Note 7) 25 dB RO = 600Ω (Note 2) FIN = 1575.42MHz ZS = 50Ω (Note 7) 18 9 -16 17 3.4 700 dB dBm Ω nH Ω 7 dB 27 14 700 500 33 106-G1-G2 60 75 60 1 85 1 40 20 120 +1.0 -1.5 45 Conditions Max. 3 11 Units Typ. 14 70 50 30 2 60 40 Pin 32 (Notes 1 and 7) (Notes 1 and 7) Pins 37 & 38 (Note 8) FIN = 1224.58MHz (Note 7) dB mV rms Ω Ω FIN = 175.42MHz dB dB dB kΩ mV rms kΩ (Note 6) FIN = 35.42MHz (Note 3) Pins 47 & 48 (Note 8) CW input (Note 3) Pin 1(Note 8) dB dB dB % % ms Pins 40 & 41 (Note 8) Pins 44 & 45 (Note 8) (Note 7 and 9) (Note 10) CAGC = 100nF 15kHz Loop Bandwidth -68 -75 -88 -110 -120 -120 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -50 dBc (Note 7) (Note 7) GP2015 Value Characteristic VCO Maximum Lock Frequency VCO Minimum Lock Frequency VCO regulator output voltage VCO Gain Phase Detector Gain 10MHz Reference Input 10MHz Reference Input Impedance Min. Typ. Max. 1414 3 50 0.1 PLL Lockup Time PLL Loop Gain 3.3 150 5.3 0.6 5 1386 3.5 240 1.2 6 150 DIGITAL INTERFACES Sample Clock, Power Down, Test Inputs. VIH VIL Input Current High IIH Input Current Low IIL Sign/Mag Outputs VOH VOL MHz MHz V MHz/V V/rad (Note 4) V pk-pk kΩ Pin 27 (Note 11) ms dB VDD 0.5 10 2 0 -300 0.5 20 Sample Clock to Sign/Mag Delay VDD -1.25 (Note 7) From Power up (Note 7) (Note 7) 43 LD (PLL Lock)/PReset Outputs Low Level (VOL) High Level (VOH) 0.2 VDD VDD-1 V V µA µA VIH = VDD VIL = VEE V V Pins 15, 14 IO = -0.5mA IO = 0.5mA ns CL = 15pF, RL = 15kΩ (Note 7) V VDD-1 VDD -0.8 V VOH-0.1 mV p-p 220 Duty Cycle Power-on Reset comparator input Power Reset Reference Level Power Reset Reference Input Current Conditions Pins 11, 19, 20 VDD-1 40MHz Clock Output High Level (VOH) Low Level (VOL) Output (differential) Units % Pins 16 & 17 (Note 5) CL = 15pF (GND) (Note 7) CL = 5pF (Diff) (Note 7) (Note 7) 0.5 V V Pins 21 and 9 IO = 0.5mA IO = -10µA 1.35 10 V µA Pin 8 1.1 -10 Notes on Electrical Characteristics:- All RF measurements are made with appropriate matching to the input or output impedances, such as balun transformers, and levels refer to matched 50ohm ports (see figure 3 for test circuit) 1. 2. 3. 4. 5. 6. RF input impedance (series) without input matching components connected - expressed as Real impedance with reactive inductor value. Measured at 1575.42MHz. Input matched to 50ohm, output loaded wlth 600ohm differential Maximum Stage 3 input signal amplitude for correct AGC operation = 20mV rms. VCO regulator voltage measured with respect to Vcc (OSC) - pin 5. The OPCLK outputs are differential and are referenced to V DD. Minimum gain requirement expressions -7dBm where: -7dBm -174dBm/Hz 19dB -21dB 63dB 7. 8. 9. 10. 11. < -174dBm/Hz + 19dB + G1 + G2 + G3 - 21dB + 63dB = = = = = typical IF Output level with AGC active (equivalent to 100mV rms) background noise level at RF input sum of LNA gain and noise figure total loss in 175MHz and 35MHz filters summation of noise over a 2MHz bandwidth Rearranging the above expression gives G1 + G2 + G3 > 106dB. This parameter is not production tested. This impedance is toleranced at +/-30% and is not production tested. Roll off occurs in on-chip capacitive coupling IF Output to input of ADC circuit. Not measurable at IF Output. CW input on pins 47 & 48 of 35.42MHz at 7mV rms. This input impedance applies to the typical input level. The impedance is level dependent and is not tested or guaranteed. 5 GP2015 PIN DESCRIPTIONS All VEE and VCC /VDD pins must be connected to ensure correct operation 6 Pin No. Signal Name Input/Output Description 1 IFOutput Output IF Test output. Connected to output of Stage 3 prior to the A to D converter. A series 1kΩ resistor is incorporated for buffering purposes. 2 PLL Filter 1 Output PLL Filter 1. Connected to the bias network within the on-chip VCO. An external PLL loop filter network should be connected between this pin and PLL Filt 2 (see below). 3 PLL Filter 2 Output PLL Filter 2. Connected to the varactor diodes within the on-chip VCO. An external PLL loop filter network should be connected between this pin and PLL Filt 1 (see above). 4,6 VEE (OSC) Input Negative supply to the on-chip VCO. (See Note 1) 5 VCC (OSC) Input Positive supply to the on-chip VCO. 7 VEE (REG) Input Negative supply to the VCO regulator. This must be connected to GND. 8 PRef Input Power-on Reset Reference input. An on-chip comparator produces a logic HI when the PRef input voltage exceeds +1.21V. (Nom) (See Page 3) 9 PReset Output Power-on Reset Output. A TTL compatible output controlled by the Power-on reset comparator (See above). This output remains active even when the chip is powered down. (See pin 19 - PDn). 10 VEE (IO) Input Negative supply to the Digital Interface. (See Note 2) 11 CLK Input Sample Clock input from the correlator chip. A TTL compatible input (which operates at 5.714MHz if used with GP2021 correlator device) used to clock the MAG & SIGN output latches, on the rising edge of the CLK signal. 12, 13 N/C 14 MAG Output Magnitude bit data output. A TTL compatible signal, representing the magnitude of the mixed down IF signal. Derived from the on-chip 2-bit A to D converter, synchronised to the CLK input clock signal. 15 SIGN Output Sign bit data output. A TTL compatible signal, representing the polarity of the mixed down IF signal. Derived from the on-chip 2-bit A to D converter, synchronised to the CLK input clock signal. 16 OPClk- Output 40MHz Clock output - inverse phase. One side of a balanced differential output clock, with opposite polarity to Pin 17 - OPClk+. Used to drive a master-clock signal within the correlator chip. 17 OPClk+ Output 40MHz Clock output - true phase. Other side of a balanced differential output clock set, with opposite polarity to Pin 16 - OPClk-. Used to drive a masterclock signal within the correlator chip. Not connected. (See Note 4) GP2015 Pin No. Signal Name Input/Output Description 18 VDD (IO) Input Positive supply to the Digital Interface. (See Note 2) 19 PDn Input Power-Down control input. A TTL compatible input, which when set to logic high, will disable ALL of the GP2015 functions, except the power-on reset block. Useful to reduce the total power consumption of the GP2015. If this feature is not required, the pin should be connected to 0V (VEE/GND). 20 TEST Input Test control input - Disable PLL. A TTL compatible input, which when set to logic high, will disable the on-chip PLL, by disconnecting the divided-down VCO signal to the phase-detector. The VCO will free run at its upper range of frequency operation. If this feature is not required, the pin should be connected to 0V (VEE/GND). 21 LD Output PLL Lock Detect output. A TTL compatible output, which indicates if the PLL is phaselocked to the PLL reference oscillator. Will become logic high only when phase-lock is achieved. 22 VEE (DIG) Input Negative supply to the PLL and A to D converter. 23 AGC- Output AGC Capacitor output - inverse phase. One side of a balanced output from the AGC block within IF Stage 3, to which an external capacitor is connected to set the AGC time-constant. 24 AGC+ Output AGC Capacitor output - true phase. One side of a balanced output from the AGC block within IF Stage 3, to which an external capacitor is connected to set the AGC time-constant. 25 N/C 26 VCC (DIG) Input Positive supply to the PLL and A to D converter. 27 REF 2 Input 10.000MHz PLL Reference signal input . Input to which an externally generated 10.000MHz PLL reference signal should be ac coupled, if an external PLL reference frequency source (e.g TCXO) is used (see fig. 6). If no external reference is used, this pin forms part of the onchip PLL reference oscillator, in conjunction with an external 10.000MHz crystal (see fig. 5). 28 REF 1 Input PLL reference oscillator auxillary connection. Used in conjunction with Pin 27 (REF 2) to allow a 10.000MHz external crystal to provide the PLL reference signal if no external PLL reference frequency source (e.g TCXO) is used. This pin should NOT be connected if an external TCXO is being used (see fig. 5). 29, 35 VCC (RF) Input Positive supply to the RF input and Stage 1 IF mixer. Both pins are connected internally, but must both be connected to VCC externally, to keep series inductance to a minimum. 30, 31, 33, 34 VEE (RF) Input Negative supply to the RF input and Stage 1 IF mixer. The pins are all connected internally, but must ALL be connected to 0V (VEE/GND) externally, to keep series inductance to a minimum. Not connected. (See Note 4) 7 GP2015 Pin No. 8 Signal Name Input/Output Description Input RF input. The GPS RF input signal @ 1575.42MHz from an external antenna with LNA and filter is connected to this pin via an input-matching network (see fig.4). 32 RF Input 36 N/C 37 O/P 1- Output Stage 1 mixer output @ 175.42MHz - inverse phase. One of a balanced output from first stage IF mixer, to which one input of an external balanced 175MHz bandpass filter is connected. External dc biasing is required via an inductor connected to V CC(RF) - the value of which is dependent on the filter used. 38 O/P 1+ Output Stage 1 mixer output @ 175.42MHz - true phase. Second of a balanced output from first stage IF mixer, to which the second input of an external balanced 175MHz bandpass filter is connected. External dc biasing is required via an inductor connected to VCC(RF) - the value of which is dependent on the filter used. 39 VCC (2) Input Positive supply to the Stage 2 IF mixer. 40 I/P 2- Input Stage 2 mixer input @ 175.42MHz - inverse phase. One of a balanced input to the second stage IF mixer, to which one of the balanced signal outputs from the external 175MHz bandpass filter is connected. 41 I/P 2+ Input Stage 2 mixer input @ 175.42MHz - true phase. Second of a balanced input to the second stage IF mixer, to which the second of the balanced signal outputs from the external 175MHz bandpass filter is connected. 42, 43 VEE (IF) Input Negative supply to the Stage 2 IF mixer, and Stage 3 IF block. 44 O/P 2- Output Stage 2 mixer output @ 35.42MHz - inverse phase. One of a balanced output from second stage IF mixer, to which one input of an external balanced 35.42MHz bandpass filter is connected. External dc biasing is required via an Inductor connected to V CC. (See Note 3) 45 O/P 2+ Output Stage 2 mixer output @ 35.42MHz - true phase. Second of a balanced output from second stage IF mixer, to which the second input of an external balanced 35.42MHz bandpass filter is connected. External dc biasing is required via an Inductor connected to V CC. (See Note 3) 46 VCC (3) Input Positive supply to the Stage 3 IF mixer. 47 I/P 3- Input Stage 3 mixer input @ 35.42MHz - inverse phase. One of a balanced input to the third stage IF mixer, to which one of the balanced signal outputs from the external 35.42MHz bandpass filter is connected. (See Note 3) 48 I/P 3+ Input Stage 3 mixer input @ 35.42MHz - true phase. Second of a balanced input to the third stage IF mixer, to which the second of the balanced signal outputs from the external 35.42MHz bandpass filter is connected. (See Note 3) Not connected. (See Note 4) GP2015 Notes on Pin Descriptions 1). Both pins 4 & 6 (VEE (OSC)) are connected internally. If the VCO regulator is used (VCC = +5.00V nominal) then both pins 4 & 6 must be left floating, with either pin de-coupled to VCC (OSC) with a 100nF capacitor. In this configuration, the dc output level of the regulator can be monitored from VEE (OSC), with respect to VCC (OSC) - NOT 0V (VEE/GND). For operation at VCC <+4.0V, the VCO regulator cannot be used, and both VEE (OSC) pins must be shorted to VEE (REG) (Pin 7) - see Fig. 7. 2). The Digital Interface supply is independent from all the other supply pins, allowing supply separation to reduce the likelihood of undesirable digital signals interfering with the IF strip. (Note the maximum allowable Power Supply Differential in the Electrical Characteristics - page 4). 3). The 35.42MHz Bandpass filter should have a bandwidth of approx 2.0MHz. 4). These pins are not connected within the package, and may therefore be used in power/ground routing if desired. To avoid crosstalk, their use in signal routing is not recommended. CONTROL SIGNALS L Normal Operation Normal Operation Power Down TEST H Powered Down Test Stage 3 Input 35 MHz Stage 2 Output 35 MHz Stage 2 Input 175 MHz Stage 1 Output 175 MHz M1 - 4 = Matching Networks, incorporating Balun transformers M1 M1 M2 M2 M3 M3 M4 M4 IF Output 37 RF INPUT Cs 32 38 40 41 Stage 1 44 45 47 48 CLK 1 Stage Stage 22 Stage 33 11 ADC Cp 15 14 2 Power Down PLL SYNTHESISER PLL LOOP C1 FILTER 3 16 17 21 27 20 19 Power Detect 9 AGCControl Control AGC 8 23 24 SIGN MAG C1 = 470nF C2 = 10nF R1 = 270Ω Cagc = 100nF Cs = 12pF Cp = 2.7pF R1 C2 OPClk LD REF 2 TEST PDn PRESET PREF Cagc Figure 3 - GP2015 test circuit OPERATING NOTES A typical application circuit is shown in figure 4 with the GP2015 front-end interfaced to the GP2021 12-channel correlator integrated circuit. The RF input has an unmatched input impedance (see page 4). The RF input matching components Cs and Cp should be mounted as close to the RF input as possible: also the Vee(RF) tracks must be kept as short as possible. A SAW filter may be used as a 175.42MHz filter, but this can be replaced by a simpler coupled-tuned LC filter if there is no critical out-of-band jamming immunity requirement. The DC bias to mixer 1 is provided via inductors L1 and L2, which may form part of the 175.42MHz filter. The output of mixer 2 requires an external dc bias, achieved with inductors L3 and L4, which also serve to tune out the input capacitance of the 35.42MHz SAW filter. The output of the SAW filter is tuned with inductor L5. Capacitor (Cagc) determines the AGC time-constant. The PLL loop filter components are selected to give a PLL loop bandwidth of approximately 10kHz. The IF Output is normally used for test-purposes only, but is available to the user if required. Typically a low noise preamplifier (gain >+15dB) is used between the antenna and the RF input (pin 32), and may be located remotely, with the antenna. QUALITY AND RELIABILITY At Zarlink Semiconductor, quality and reliability are built into products by rigorous control of all processing operations, and by minimising random, uncontrolled effects in all manufacturing operations. Process management involves full documentation of procedures, recording of batchby-batch data, and the use of traceability procedures. A common information management system is used to monitor the manufacturing on Zarlink Semiconductor CMOS and Bipolar processes. All products benefit from the use of an integrated monitoring system throughout all manufacturing operations, leading to high quality standards for all technologies. Further information is contained in the Quality Brochure, available from Zarlink Semiconductor's Sales Offices. 9 GP2015 Vcc VALUES FOR L1,L2,L3,L4 & L5 ARE DEPENDENT ON FILTERS USED L1 L2 RF INPUT MATCHING Cs = 12pF Cp = 2.7pF L4 175MHz FILTER Cs RF INPUT L3 37 38 32 SAW FILTER 40 41 Vcc L5 44 45 Creg = 0.1uF (Vcc = +5.0V only) 47 48 4, 6 Cp 33, 34, 30,31 23 REF2 10MHz I/P 27 GP2015 FRONT-END 48 PIN C1 2 Cagc =0.1uF PLL LOOP FILTER R1 24 17 16 11 15 14 21 9 8 20 3 C2 C1 = 0.47uF R1 = 270Ω C2 = 10nF Vcc R4 R5 R6 R2 POWER-ON REF R3 70 71 73 76 77 66 2 CLK_T CLK_I SAMP CLK SIGN 0 MAG 0 PLL LOCK POWER_GOOD R4, R5 = 470Ω R6 = 1.5kΩ POWER-ON REF LADDER R3 =2.7k R2 = 2.7k (Vcc = +3.0V) = 6.8k (Vcc = +5.0V) GP2021 CORRELATOR 80 PIN Figure 4 - GP2015 typical application Ref 2 (27) GP2015 33pF 10.000MHz CRYSTAL (28) Ref 1 22pF Figure 5 - Crystal Reference connections 10 GP2015 47nF Ref 2 (27) RA 10.000MHz TCXO GP2015 RB (28) Ref 1 NC RA & RB SET TO REDUCE TCXO O/P TO 0.5V P-P. Figure 6 - TCXO Reference connections 3V 5V V CCOSC V CCOSC (5) 100nF (5) (4) (4) V EEOSC GP2015 V EEOSC GP2015 (6) (6) (7) (7) V EEREG V EEREG 0V 0V No VCO Regulator needed Using VCO regulator with Vcc > +4.0V Figure 7 - VCO power-supply connections 11 GP2015 TYPICAL CHARACTERISTICS OF THE GP2015 GPS RECEIVER RF FRONT-END The GP2015 has been characterised to guarantee reliable operation over the Industrial Temperature range (-40°C -> +85°C ambient). This was achieved by setting the device case temperature to extremes of +110°C and -50°C. The following charts show the typical variation of key parameters across the extended case temperature range. NOTE:- ALL Measurements at Vcc = +2.65V made with VCO voltage-regulator DISABLED. 70 65 CURRENT (mA) 60 55 Vcc = +2.65V Vcc = +3.8V 50 Vcc = +5.55V 45 40 35 30 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 8 - Supply Current - Analog interface - normal mode 4.5 4 3.5 CURRENT (mA) 3 Vcc = +2.65V 2.5 Vcc = +3.8V 2 Vcc = +5.55V 1.5 1 0.5 0 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 9 - Supply Current - Analog interface - power-down mode 12 GP2015 12 10 CURRENT (mA) 8 Vcc = +2.65V Vcc = +3.8V 6 Vcc = +5.55V 4 2 0 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 10 - Supply Current - Digital interface - normal mode 4.5 4 3.5 CURRENT (mA) 3 Vcc = +2.65V 2.5 Vcc = +3.8V 2 Vcc = +5.55V 1.5 1 0.5 0 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 11 - Supply Current - Digital interface - power-down mode 13 GP2015 12 10 NOISE FIGURE (dB) 8 Vcc = +2.65V 6 Vcc = +3.8V Vcc = +5.55V 4 2 0 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 12 - Noise figure of IF chain in a typical application circuit 151 150.5 150 LOOP GAIN (dB) 149.5 149 Vcc = +2.65V Vcc = +3.8V 148.5 Vcc = +5.55V 148 147.5 147 146.5 -60 -40 -20 0 20 40 60 80 100 CASE TEMP(°C) Figure 13 - On-chip Phase-locked-loop Synthesiser Loop gain 14 120 GP2015 6 PHASE-DETECTOR GAIN (V/radian) 5.5 5 Vcc = +2.65V Vcc = +3.8V 4.5 Vcc = +5.55V 4 3.5 3 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 14 - On-chip Phase-locked-loop Synthesiser Phase-detector gain 1600 1500 NOTE:- 1400MHz is the nominal VCO frequency VCO FREQUENCY (MHz) 1400 LOW - 2.65V HIGH - 2.65V LOW - 3.8V 1300 HIGH - 3.8V LOW - 5.55V HIGH - 5.55V 1200 1100 1000 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 15 - On-chip Phase-locked-loop Synthesiser - LOW and HIGH limits of VCO frequency for PLL to be locked (Note that this a typical characteristic and cannot be guaranteed) 15 GP2015 -65 PHASE NOISE (dBc/Hz) -70 -75 10kHz OFFSET 100kHz OFFSET -80 NOTE: Vcc = +5.55V for each offset -85 -90 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP (°C) Figure 16 - On-chip Phase-locked-loop Synthesiser - Phase-noise of VCO producing 1400MHz CW signal at 10kHz offset (15kHz PLL loop bandwidth) -110 PHASE NOISE (dBc/Hz) -112 -114 -116 1MHz OFFSET 5MHz OFFSET -118 -120 NOTE: Vcc = +5.55V for each offset -122 -124 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP (°C) Figure 17 - On-chip Phase-locked-loop Synthesiser - Phase-noise of VCO producing 1400MHz CW signal at 100kHz offset (15kHz PLL loop bandwidth) 16 GP2015 19.5 19 GAIN (dB) 18.5 Vcc = +2.65V 18 Vcc = +3.8V Vcc = +5.55V 17.5 17 16.5 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP (°C) Figure 18 - Frontend/Mixer 1 Small-signal Conversion Gain - RF I/P frequency at 1575.42MHz -12 -13 INPUT LEVEL (dBm) -14 -15 Vcc = +2.65V -16 Vcc = +3.8V Vcc = +5.55V -17 -18 -19 -20 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP (°C) Figure 19 - Frontend/Mixer 1 Input level for 1dB Conversion Gain-compression - RF I/P frequency at 1575.42MHz 17 GP2015 8.5 8 RF I/P IMAGE REJECTION (dB) 7.5 7 Vcc = +2.65V Vcc = +3.8V Vcc = +5.55V 6.5 6 5.5 5 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 20 - Frontend/Mixer 1 Image rejection - RF I/P frequency at 1224.58MHz 28 27.5 27 GAIN (dB) 26.5 Vcc = +2.65V 26 Vcc = +3.8V Vcc = +5.55V 25.5 25 24.5 24 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 21 - Stage 2/Mixer 2 Small-signal Conversion Gain - Stage 2 I/P frequency at 175.42MHz 18 GP2015 20 18 INPUT LEVEL (mV RMS) 16 Vcc = +2.65V Vcc = +3.8V 14 Vcc = +5.55V 12 10 8 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP (°C) Figure 22 - Stage 2/Mixer 2 Input level for 1dB Conversion Gain-compression - Stage 2 I/P frequency at 175.42MHz 80 79 GAIN (dB) 78 Vcc = +2.65V 77 Vcc = +3.8V Vcc = +5.55V 76 75 74 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 23 - Stage 3 MAXIMUM Small-signal Conversion Gain - Stage 3 I/P frequency at 35.42MHz 19 GP2015 1.255 1.25 PREF VOLTAGE (V) 1.245 1.24 Vcc = +2.65V 1.235 Vcc = +3.8V Vcc = +5.55V 1.23 1.225 1.22 1.215 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP (°C) Figure 24 - Power-on Reset Threshold level 32 31.5 31 DUTY CYCLE (%) 30.5 Vcc = +2.65V Vcc = +3.8V 30 Vcc = +5.55V 29.5 29 28.5 28 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 25 - Duty-cycle of MAG digital output (pin 14), sampled at 5.71MHz in a typical application circuit RF I/P signal = 1575.42MHz CW, -85dBm - equivalent to 26dB excess noise from a typical GPS antenna 20 GP2015 50.5 50.45 50.4 DUTY CYCLE (%) 50.35 50.3 Vcc = +2.65V Vcc = +3.8V 50.25 Vcc = +5.55V 50.2 50.15 50.1 50.05 50 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 26 - Duty-cycle of SIGN digital output (pin 15), sampled at 5.71MHz in a typical application circuit - RF I/P signal = 1575.42MHz CW, -85dBm - equivalent to 26dB excess noise from a typical GPS antenna 90 88 86 AMPLITUDE (mV RMS) 84 82 Vcc = +2.65V Vcc = +3.8V 80 Vcc = +5.55V 78 76 74 72 70 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMP(°C) Figure 27 - Amplitude of IFOUT (pin 1) at 4.3MHz (±1.0MHz) in a typical application circuit - RF I/P signal = 1575.42MHz CW, -85dBm - equivalent to 26dB excess noise from a typical GPS antenna 21 GP2015 IMPEDANCE AT 1575.42MHz j1 j3 j0.5 0.3 0 1 1 +110°C 49.2 + j13.3 ohms 2 +25°C 50.9 + j9.2 ohms 3 -50°C 52.1 + j4.9 ohms ∞ 3 3 2 1 MATCHING COMPONENTS 12pF 50 OHM LINE FROM Network Analyser RF INPUT (32) 2.7pF -j3 -j0.5 GP2015 VEE (30, 31, 33, 34) -j1 Figure 28 - Typical Matched RF I/P Impedance between 1000MHz and 2000MHz RF I/P level @ -40dBm 22 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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