Preliminary PT9120 GPS Receiver RF Front End IC DESCRIPTION The PT9120 is a single chip Global Positioning System (GPS) receiver front-end IC requiring few external components and offering extremely low power consumption. The PT9120 employs a super-heterodyne receiver topology which down-converts the 1575.42MHz L1-band GPS signal to a 1st IF. The 1st IF is then filtered by an off-chip L-C filter and subsequently sub-sampled by the 2-bit A/D converter to provide both sign and magnitude quantized CMOS level outputs to base band inputs. FEATURES • • • • • • GPS L1-band (C/A code) receiver Integrated LNA and antenna detector Fully-monolithic VCO Support for several reference frequencies 2-bit ADC output (sign and magnitude) Extremely low current consumption (7mA at AVDD=DVDD=2.5V) • Multiple power-down modes • Available in 28 pins or 24 pins, QFN package APPLICATION • GPS systems BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT9120 APPLICATION CIRCUIT 24 PINS, QFN 28 PINS, QFN PRE1.3 2 PT9120 ORDER INFORMATION Valid Part Number PT9120-24QF Package Type 24 Pins, QFN Top Code PT9120 PIN CONFIGURATION 28 PINS, QFN 24 PINS, QFN PRE1.3 3 PT9120 PIN DESCRIPTION Pin Name I/O SGN MAG O O AOK O CP DVSS DVDD I/O G P XEN I XO XI VB PLL AON LNI ISNS PVDD LNO AVDD AVSS RFIN VBG IF1P IF1N IF2P IF2N MODE AGC P1 P0 O I O O O I I O O P G I O O O I I I I/O I I PRE1.3 Description Quantized 2nd IF “sign” bit Quantized 2nd IF “magnitude” bit Active antenna status output (AOK = HIGH = active antenna OK; AOK=LOW=active antenna either open or shorted) Reference clock input/output Ground (digital circuitry) Supply voltage (digital circuitry) Crystal oscillator enable pin (XEN=HIGH=enabled; XEN=LOW=disabled) Crystal oscillator output Crystal oscillator input Regulator (1.9V) output Charge pump output Antenna switch-controlled supply voltage to active antenna LNA input Antenna detector current sense input Supply voltage (active antenna) LNA output Supply voltage (analog circuitry) Ground (analog circuitry) Mixer input Band gap reference (1.23V) output Differential mixer IF output/differential first-stage IF amplifier input Differential first-stage IF amplifier output/differential IF AGC input Reference frequency mode select input AGC capacitor connection. Sets the AGC time constant. Power-down control pins (see PT9120 operating modes) Pin No. 28-pin 24-pin 1 1 2 2 3 - 4 5 6 3 4 5 7 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 - 4 PT9120 FUNCTION DESCRIPTION The PT9120 low power GPS receiver IC employs a double-conversion, super-heterodyne receiver topology to achieve excellent performance. A complete GPS L1-band receiver front-end may be constructed using the PT9120 IC together with an active antenna, RF and IF filters, and a reference crystal. The PT9120 consists of an RF LNA; an RF mixer; complete frequency synthesizer including a VCO, phase/frequency detector (PFD), charge pump, input and reference dividers, and a reference crystal oscillator; IF AGC amplifier; and a 2-bit A/D converter with CMOS-level outputs. The PT9120 includes an on-chip voltage regulator and an integrated antenna detector and switch capable of supplying power to an active antenna as well as providing current limiting protection when an antenna open or short has been detected. The on-chip voltage regulator provides a stable 1.9V output at the VB pin. In addition, the PT9120 implements four distinct operating modes including two low power modes and one complete power-down mode. The application circuit includes the PT9120 IC and provides an option for either a patch antenna or active antenna, a single connector to a power supply, power-down control inputs, and digital data outputs. Among the various external parts are an external LNA, filter and oscillator components (TCXO), de-coupling resistors and capacitors for the analog and digital power supplies, and the SAW filter between the discrete LNA output and the PT9120 RF input. ANTENNA DETECTOR/SWITCH The PT9120 integrates an antenna detector and switch to supply power to and control an optional active antenna. The supply voltage for an active antenna is applied to the PT9120’s PVDD pin. The actual voltage supply connection to the antenna is available on the AON pin. An external resistor between PVDD and ISNS is used to set the “antenna short” and “antenna open” current thresholds. The actual antenna current is derived from the measured voltage drop across the external sense resistor. The minimum and maximum voltage drop thresholds are internally set to 36mV and 300mV, respectively. For a 56Ω external sense resistor, these voltage drops correspond to minimum (“antenna open”) and maximum (“antenna short”) current thresholds Imin = 36mV/56Ω = 640µA and Imax = 300mV/56Ω = 5.35mA. Once the PT9120 is set to the fully active mode, internal antenna detector circuitry determines whether an active antenna is properly connected by monitoring the current consumed by the antenna. As long as the monitored current falls within the range delineated by Imin and Imax, the AOK pin is set to logic HIGH, and an internal switch within the PT9120 is closed to allow voltage to be supplied to the antenna from the AON pin. Otherwise, the AOK pin is set to logic LOW, and additionally, if the voltage drop across the sense resistor is > 300mV, the output current thru the AON pin is limited to a value around 10% above Imax. If desired, the antenna switch may be bypassed by connecting the active antenna directly to the ISNS pin. Furthermore, the antenna detector may be bypassed by shorting PVDD to ISNS (AOK will always be set to logic LOW). In both these cases, the short circuit current-limiting protection circuit is disabled. If no active antenna is used, PVDD must be connected to ground, while AON and ISNS may be connected to ground or left open. In this case, the AOK pin will always be set to logic HIGH when the PT9120 is in fully active mode, and will be set to logic LOW in all other modes. EXTERNAL LNA As shown in the application circuit, an off-chip cascade LNA (15dB gain and 1.5dB NF) may be used to amplify the 1575.42MHz L1 GPS RF input signal prior to sending it to the RF input of the PT9120. The input and output impedances for the LNA are nominally 50Ω at 1575.42MHz. PRE1.3 5 PT9120 RF LNA Impedance matching at the PT9120’s integrated LNA’s input and output is required. At the LNA input, an optimum noise match is required for best sensitivity performance. At the LNA output, a match to the 50Ω impedance of the SAW filter is required. Typical matching topologies and component values are shown in Typical PT9120 RF application circuit schematic. Note that the layout of the application PCB may affect these component values. RF MIXER The RF mixer down-converts the GPS signal band to a 1st IF near 20MHz (depending upon the chosen crystal reference frequency as specified in Supported frequency plans). The RFIN input of the mixer is on-chip matched to 50Ω and is internally biased near ground potential (AVSS) and should not receive any external dc biasing. IF FILTER AND AGC The PT9120 also requires 2 external IF filters at the mixer output for channel selection and to reject image frequency noise at the input of the sub-sampling 2-bit A/D converter. These filters should have a bandwidth of at least 2MHz, centered at the 1st IF corresponding to the frequency plan chosen (see Supported frequency plans), and should also provide a low impedance path to ground at the local oscillator frequency. A typical GPS receiver application may include the 4th order L-C band-pass filter connected between the IF1P/IF1N and IF2P/IF2N pins as shown in the application circuit of Typical PT9120 RF application circuit schematic. With the component values shown, the filter is centered at 20.46MHz and has a bandwidth of roughly 4MHz to accommodate component tolerances of ±5%. On the PCB, the IF filter components should be placed far away from digital signals. The IF- amplifier provides roughly 70dB of gain and includes 60dB of AGC range, which is sufficient to accommodate a wide range of input signals without saturation. The AGC is calculated from MAG bit and sets the gain of the 1st IF amplifier to achieve a logic HIGH duty cycle of 33% on the MAG bit output. The time constant of the AGC loop is calculated from MAG bit set using a capacitor connected to the AGC pin. DIGITAL INTERFACE The reference clock input/output pin (CP) and the 2-bit AD converter’s digital output pins (SGN and MAG) are CMOS-level compatible with a low-to-high logic swing from DVSS to DVDD. The SGN and MAG outputs represent the sign and the magnitude bits, respectively, of the digitized (2-bit) 2nd IF signal. The 4 possible levels for both SGN and MAG are coded as shown in Coded SGN and MAG output signal. SGN MAG Value LOW HIGH +3 LOW LOW +1 HIGH LOW -1 HIGH HIGH -3 The SGN and MAG output bits change on the falling edge of CP and should be read in by the baseband processor on the rising edge of CP as illustrated in SGN and MAG output timing diagram. PRE1.3 6 PT9120 For the PT9120, the CP pin may be used as either clock input or output. With the on-chip reference crystal oscillator enabled, the CP pin becomes an output and delivers a CMOS-level signal with a nominal duty cycle of 50% at the same frequency as the reference crystal oscillator. By disabling the on-chip crystal oscillator (setting XEN to logic LOW), the CP pin becomes an input which accepts an external CMOS-level (DVSS to DVDD) clock signal with a duty cycle between 40% and 60%. The RF application circuit shown in Typical PT9120 RF application circuit schematic has been successfully interfaced with the PTC GPS base-band processor. Since the base-band processor requires a 2-bit IF input, the PT9120’s SGN and MAG digital outputs are both fed to the base-band processor. Note that the SGN and MAG output pins are only capable of driving a small load, e.g. a typical digital input (2 to 4pF), and hence, they will drive neither a clock distribution tree nor a common 15pF oscilloscope probe. Overall performance degradation of the PT9120 caused by increased switching noise leading to excessive power line interference may result from high capacitive loading. This interference may be reduced by inserting series damping resistors (220 to 470Ω) at the interface between the PT9120’s SGN and MAG outputs and the base-band processor inputs. As a rule of thumb, PCB traces connected to the PT9120’s digital output pins should be kept short and routed away from the external IF filter components. CRYSTAL OSCILLATOR The reference frequency for the PLL and the clock signal for the 2-bit A/D converter may be generated by either the on-chip crystal oscillator, or supplied externally. An external reference clock signal (such as the low amplitude signal from a typical TCXO as shown in the application circuit in Typical PT9120 RF application circuit schematic) should only be ac-coupled to the XO pin when the on-chip crystal oscillator is enabled (XEN is set to DVDD) since the on-chip oscillator device will serve as a buffer for the external signal. The external reference clock signal should have a minimum voltage swing of 400mVP-P. The on-chip crystal oscillator uses a Pierce topology and requires external crystal resonator and shunt load capacitances. The crystal oscillator is enabled by setting XEN to DVDD and disabled by setting XEN to logic LOW. The XEN pin should never be left floating. For interfacing to the PTC base-band processor, the crystal oscillator should be set to 16.368MHz. SUPPORTED FREQUENCY PLANS The PT9120 supports separate frequency plans for eight different reference frequencies. The selection of the reference frequency is determined by logic input level at the MODE pin (which should be hardwired to either AVDD or AVSS) and also the logic levels at the internal IC metal layer M1 and M2 pads. Supported frequency plans shows the relationship among the reference frequencies, MODE/M1/M2 logic levels, 1st and 2nd IF and LO frequencies, and N-divider divide ratios. Reference LO Frequency N-divider M1 M2 Mode 1st IF (MHz) 2nd IF (MHz) Frequency (MHz) (MHz) Divide Ratio 16.369 20.37 3.996 1555.05 1520 Low 16.368 20.46 4.092 1554.96 1520 Low Low 16.367 20.55 4.188 1554.86 1520 High 13.000 (GSM) 16.58 3.58 1592 1592 Low 19.800(CDMA) 24.42 4.62 1599.84 1616 High Low 19.200(CDMA) 23.25 4.051 1552.17 1536 High 19.680 (CDMA) 15.55 4.127 1590.97 1536 Low 14.400(PDC) 18.18 3.78 1593.6 1328 High High High 12.600(PDC) 21.87 3.328 1597.29 1648 Low 16.367 20.55 4.188 1554.86 1520 Low High High 15.360(WCDMA) 18.94 3.58 1556.48 1520 PRE1.3 7 PT9120 POWER-DOWN CONTROL The PT9120 provides four distinct operating modes: (1) fully active, (2) stand-by, (3) doze, and (4) sleep. CMOS-level compatible input control pins, P1 and P0, set the operating state of the chip. The relationship between the P1 and P0 inputs and the PT9120’s operating state is given in PT9120 operating modes Gray coding has been used for the P1 and P0 inputs in order to minimize glitches while switching from one operating mode to the other. When switching from doze to fully active mode, stand-by should be selected first. P1 P0 Operating Mode High Low Fully active High High Stand-by Low High Doze Low Low Sleep POWER SUPPLY CONNECTIONS The PT9120 minimally requires two power supply voltage connections, AVDD and DVDD. Both AVDD and DVDD must be well filtered, particularly the analog power supply voltage connection, AVDD. An R-C or L-C filter on the DVDD line may be used for improved noise suppression. The AVDD and DVDD supply lines must also be well de-coupled. A 100nF ceramic capacitor mounted very close to the chip package is recommended on both AVDD and DVDD. A 2.2µF(or higher) tantalum capacitor may be required on AVDD, especially if AVDD is not regulated. In order to avoid switching noise interference from the digital portion of the chip, it is recommended that a star grounding topology, where AVSS and DVSS are connected at only one point very close to the chip package, be used. PRE1.3 8 PT9120 ABSOLUTE MAXIMUM RATINGS (AVSS=DVSS=VSS=0V) Parameter Supply voltage Symbol VCC Rating VSS-0.3 to VSS +4.0 Unit V Soldering temperature TSLD 255 °C Soldering time range tSLD 10 Sec. Operating temperature Topr -40 to 85 °C Storage temperature Tstg -55 to 125 °C RECOMMEND OPERATING CONDITIONS (AVSS=DVSS=VSS= 0V) Parameter Analog supply voltage range Digital supply voltage range Operating temperature PRE1.3 Symbol AVDD DVDD TA Min. 2.2 1.6 -40 Rating Typ. 2.5 2.5 25 Max. 3.6 AVDD + 0.2 85 Unit V V °C 9 PT9120 ELECTRICAL CHARACTERISTICS (Unless otherwise noted, AVDD=DVDD=2.5V, AVSS=DVSS=0V, TA=25℃) Parameter Symbol Conditions DC AVDD (analog) AVDD DVDD (digital) DVDD PVDD (antenna) PVDD AVDD fully active current IAVDD DVDD fully active current ITVDD Sleep current (AVDD and DVDD) ISLEEP AVDD + DVDD Antenna Detector and Switch Low trip voltage ANTVL High trip voltage ANTVH Maximum switch current IPDD PVDD = 2.2V LNA Gain GLNA power gain, noise matched Noise figure (NOTE) NFLNA power gain, noise matched RF Mixer Conversion gain GMIX voltage gain, no load SSB noise figure NFMIX IF Strip 1st IF filter voltage gain GIFFLT Unloaded ADC SGN duty cycle DSGN ADC MAG duty cycle DMAG Frequency Synthesizer (Local Oscillator) VCO frequency range VCO gain GVCO 100KHz offset, 50KHz loop SSB phase noise NFVCO bandwidth setting Digital Interface Input logic HIGH level VIH DVDD=2.5V Input logic LOW level VIL DVDD=2.5V Output logic HIGH level VOH DVDD=2.5V Output logic LOW level VOL DVDD=2.5V Output rise time TRISE Cload=15pF Output fall time TFALL Cload=15pF Min. Typ. Max. Unit 2.2 1.6 2.2 -- 2.5 6.4 800 - 3.6 AVDD + 0.2 3.6 7.0 1000 1 V V V mA µA µA 36 300 - 400 - mV mV mA 15 18 1.5 20 2.0 dB - 16 8 17 9 18 10 dB dB 10 15 50 33 - dB % % 1.35 400 550 1.9 - -65 -70 - GHz MHz/V dBc/H z 20 12 2 0 2.25 - 0 - 2.7 0.5 2.5 0.25 10 10 V V V V ns ns Note: Depend on PCB layout and matching components. PRE1.3 10 PT9120 PACKAGE INFORMATION 24 PINS, QFN (BODY SIZE 4MM X 4MM, LEAD PICH 0.5MM) Symbol A A1 A2 A3 b D E e D2 E2 L Min. 0.80 0 0 0.22 2.10 2.10 0.35 Dimensions Nom. 0.85 0.035 0.65 0.203 REF. 0.25 4.00 BSC. 4.00 BSC. 0.50 BSC. 2.20 2.20 0.40 Max. 0.90 0.05 0.67 0.30 2.30 2.30 0.45 Notes 1. Refer to JEDED MO-220 2. Unit : mm PRE1.3 11 PT9120 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw PRE1.3 12