KESRX01 Data Sheet

KESRX01
290 - 460MHz ASK Receiver
Data Sheet
March 2006
DF2
IF1
VCC
4
2
3
MIXIP
5
6
RFOP
7
VEERF
8
24
23
XTAL2
XTAL1
22
DF2
21
20
DF1
DF0
19
LF
18
NC
NC
17
9
VCO2
DSN
DATAOP
10
16
15
11
14
VCO1
PD
PEAK
12
13
VEE1
QP24
QPA24
Fig. 1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
All voltages relative to V EE (0V)
Junction temperature, Tj
Storage temperature, Tstg
Supply voltage, V CC max
Voltage on any pin, Vshort
Tape& Reel
Tubes
Tape& Reel
Tubes
DF1
1
RFIN
FEATURES
■ Very low supply current (2.30mA typical)
■ Low external part count
■ –105dBm sensitivity (typical 315MHz)
■ Integrated VCO and IF Filters.
ORDERING INFORMATION
KESRX01G/IG/QP1T 24 Pin QSOP
KESRX01G/IG/QP1S 24 Pin QSOP
KESRX01G/IG/QP2Q 24 Pin QSOP*
KESRX01G/IG/QP2P 24 Pin QSOP*
*Pb Free Matte Tin
IFDC1
IFDC2
IF2
KESRX01
The KESRX01 is a single chip ASK (Amplitude Shift Key)
Receiver IC. It is designed to operate in a variety of low power
radio applications including keyless entry, general domestic
and industrial remote control, RF tagging and local paging
systems.
This single conversion super–heterodyne receiver offers
an exceptionally high level of integration and performance.
The unique architecture enables data rates up to 50Kbits/sec
to be supported. All low power radio regulations, including
ETSI–ETS 300 220, and FCC, part 15, can easily be met.
Local oscillator generation is performed by an on–chip PLL
which uses an external crystal reference oscillator (4.5 to
7.2MHz). All popular radio frequencies (315MHz, 433.92MHz,
etc) can then be supported by simply choosing the appropriate
crystal frequency.
Particular emphasis has been placed on low current
consumption, with pulsed ON/OFF operation allowing <1mA
average current consumption to be achieved. The on–chip
VCO and IF significantly minimise the external components
needed thus reducing any re–radiation effects.
DF0
IF DC1 IF DC2
PEAK DETECTOR
IF 2
IF 1
MIXIP RFOP
IF FILTER
600KHz
LOG
AMP
PEAK
–55 to +150°C
–55 to +150°C
V CC –0.5 to +8.0 V
–0.5 to +8.0V
DATA FILTER
DATOP
+
DATA SLICER
MIXER
–
RFIN
RSSI O/P
DSN
DIV 64
VCC
LNA
PHASE FREQUENCY
DETECTOR
VEE1
PD
VCO
XTAL
OSCILLATOR
XTAL 1 XTAL 2
LF
VCO 1 VCO 2
Fig. 2. Block diagram
1
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Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1998-2006, Zarlink Semiconductor Inc. All Rights Reserved.
VEERF
KESRX01
ELECTRICAL CHARACTERISTICS D.C.
Tamb = -40 to + 85°C, VCC = 4.75V to 7.0V. These characteristics are guaranteed by either production test or design. They
apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Characteristic
Symbol
Value
Min
Units
Conditions
Supply current
ICC1
Typ
2.30
Max
3.00
mA
Vcc = 5V, all
Supply current
ICC2
1.90
2.60
mA
VCC = 5V, all
(PLL powered down)
Power down pin input logic high
Vih
VCC-0.5
VCC+0.5
V
Power down pin input logic low
Vil
VEE-0.5
VEE+0.5
V
Peak detector source current
Ipk
Peak detector leakage
IIK
Data output Logic High
Voh
Data output Logic Low
Vol
µA
500
250
nA
0.7VCC
0.3VCC
V
IIoad = 10µA
V
lload = 10µA
Electrostatic discharge (ESD) protection (human body model) 2KV minimum, all pins.
NOTES: Care must be taken not to power up the device with pins 7 and 8 shorted by a solder bridge, as operation with pin 7 grounded can damage
the device and result in low sensitivity.
ELECTRICAL CHARACTERISTICS A.C.
Tamb = -40 to + 85°C, VCC = 4.75V to 7.0V. These characteristics are guaranteed by either production test or design. they
apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Characteristic
Symbol
Value
Min
Sensitivity See Note 1
Typ
-103
Signal handling See Note 2
Units
Conditions
Max
-100
-23.5
dBm
RS = 50Ω, 434MHz, 2KB/s
dBm
RS = 50Ω, 434MHz, 2KB/s
LNA input impedance
VCC = 5V; 25°C ambient; 434MHz
Parallel combination R11/C11
2.65//2.2
3.61//2.2
KΩ//pF
Mixer input impedance
Also see note 5
VCC = 5V; 25°C ambient; 434MHz
Parallel combination R11/C11
1.15//1.1
Crystal oscillator input
1.21//1.62
KΩ//pF
-0.77
-1.8
-2.1
KΩ
Also see note 5
C5 = C4 = 18pF
450
550
750
KHz
All
impedance
Integrated IF filter -3dB low
IF3dB
pass cut off frequency
Spurious reverse isolation to
100
µV (rms)
65
dB
RS = 500Ω
RFIN See Note 3
Adjacent channel rejection
ACR
10MHz offset from receiver VCO
See Note 4
Notes:
1. Sensitivity is defined as the minimum average signal level measured at the input necessary to achieve a bit error ratio of
10-2 where the input signal is a return to zero pulse (RZ) with an average duty cycle of 50%. The RF input is assumed to
be matched into 50Ω.
Measured in test circuit Fig. 6 with data filter bandwidth of 5KHz as shown and for a 2Kbit/s, 50% duty cycle signal.
2. Signal handling is defined as the maximum input signal capable of being succcessfully de-modulated. It is assumed the
input is ASK modulated with an extinction ratio of a least 40dB. The combination of this specification together with the
sensitivity specification gives a minimum signal handling range of 76dB. The RF input is assumed to be matched into 50Ω.
Measured in test circuit Fig. 6. with data filter bandwidth of 5KHz as shown.
3. -67dBm in 50Ω measured with the RF input matching network.
4. Adjacent channel rejection is defined for an interfering tone (ACR) dB above threshold and 10MHz offset from the carrier giving a 3dB
reduction in sensitivity i.e. the interfering tone is 4.74mV (rms) @ Fc ± 10MHz and to achieve the specified sensitivity the wanted signal
will have to be increased to 2.2µV (rms)
5. Please refer to Smith charts Fig.8 through to 10 covering frequency range 250-500MHz.
2
KESRX01
PIN LISTING
Pin
Symbol
1
2
IFDC1
IFDC2
3
4
IF1
IF2
5
6
VCC
MIXIP
Positive power supply
RF mixer input (tank)
7
8
RFOP
VEERF
RF amplifier output (tank)
RF amplifier ground
9
10
RFIN
DSN
11
DATAOP
12
PEAK
Description
IF amplifier – decouple point
IF amplifer – decouple point
Mixer output
IF amplifer input
RF input (antenna)
Bit slicer comparator
negative input
Bit slicer comparator output
Pin
13
Symbol
VEE
Description
Negative power supply (0V)
14
15
PD
VCO1
PLL power down
VCO maintaining amplifer
16
17
VCO2
NC
VCO maintaining amplifier
Not connected, unless to GND
18
19
NC
LF
Not connected,unless to GND
PLL loop filter O/P output
20
21
DF0
DF1
Data filter – external connection
Data filter – external connection
22
23
DF2
XTAL1
Data filter – external connection
Crystal oscillator
24
XTAL2
Crystal oscillator
Peak detector output
FUNCTION
Phase locked loop
A divide by 64 prescaler is present in the PLL feedback
loop. The local oscillator frequency is then Fo=64xF ref . A
system operating at 433.92MHz (RFIN) with a 270KHz IF
frequency would require a reference of 6.77578MHz
(assuming mixer low side injection). Alternative choice of
crystal and tank components permit operation at specific
frequencies in the range 290 – 460MHz.
This phase detector has a triangle characteristic for an
input phase error in the range -2π < θ<+2π and has the benefit
of being a true frequency detector (as well as a phase
detector) and hence will always achieve lock for any initial
VCO frequency.
The charge pump provides an output current in the range
±30µA and hence gives a phase detector gain of 4.8µA/rad.
The PLL loop characteristics such as lock-up time, capture
range, loop bandwidth and VCO reference sideband
suppression are controlled by the external loop filter.
For the intended application a 2nd order loop should be
sufficient as shown in the test circuit Fig. 6.
Phase detector
VCO
The phase detector used is a phase frequency detector
(PFD) with a current (charge pump) output.
A balanced configuration is used with the LC tank
connected externally across VCO1 and VCO2 Fig. 3.
The phase locked loop generates the local oscillator by
frequency multiplication of a crystal referenced oscillator.
Dividers
DP
DPb
VCO1
VCO2
Fig. 3 Input circuit of VCO and divider chain
3
KESRX01
External SAW resonator
Down converting mixer
For reduced power the PLL based oscillator can be
replaced by a SAW based oscillator. If pin PD is tied low (VEE)
the crystal oscillator, dividers and phase detector/charge
pump are powered down. The VCO can then be used as a
maintaining amplifier for an external SAW based oscillator.
The normal mode of operation is with PD set high (VCC) or
alternatively left unconnected. Note: the power down facility
is intended to be hard wired (either to VCC or VEE) and hence
the PD pin is not specified for operation with normal CMOS or
TTL logic levels.
The RF input is a.c. coupled into a doubly balanced mixer
configuration. Its input impedance is given in Fig.8.
PD
V CC /NC
MODE
PLL Enable
V EE
PLL Disable
IF filtering
The IF filter has a (nominal) bandpass response from
25KHz to 550KHz. The single high pass section is provided by
the combination of the external a.c. coupling capacitor
between IF1 and IF2 and an on chip resistor (nominal value
12kΩ). The low pass section is entirely on chip and to meet the
selectivity requirements (adjacent channel rejection) this filter
has 4 low pass poles with a Butterworth response.
IF amplifiers and demodulator
The majority of the receiver gain is provided in the form of
an IF limiting strip. These amplifiers are all d.c. coupled and
hence differential d.c. feedback is required. This is decoupled
externally at pins IFDC1 and IFDC2. The IF amplifier stages
also combine to provide a Received Signal Strength Indicator
(RSSI) function. Since the modulation is ASK and the RSSI
output has
a linear output for a logarithmic change on its input then the
RSSI output is the demodulated data. The only uncertainty is
the d.c. level.
Reference crystal oscillator
A crystal stabilised oscillator provides a reference clock for
the PLL. The oscillator is configured for parallel resonant
operation in the fundamental mode (typical operating
frequency of 4–7MHz). The crystal is connected between pins
XTAL1, XTAL2 with external components as shown in Fig. 6.
Note that this is a single transistor Colpitts oscillator where the
external load capacitors must be taken into account in
specifying the crystal. See Application Note AN207.
Data filter
Prior to the data slicer the demodulated data passes through
a low pass filter. This filter is a 2nd order Sallen–Key section
using an on chip voltage follower. External capacitors set the
cutoff frequency and filter Q. The value of the on chipresistors
is 100KΩ (nominal). See Fig. 4.
The cut-off frequency of the data filter,ƒo, should be set to
reduce high frequency noise into the data slicer without
distorting the wanted signal. Normally this would be at least
three times the data frequency.
RF amplifier
The RF amplifier consists of a low noise transistor in a
common emitter configuration. A separate emitter connection
is provided (VEERF) to reduce sensitivity to any common
impedance in this path. The amplifier is current source biased
so the signal (RFIN) should be a.c. coupled. The collector is
open circuit so that the gain can be set with an external tuned
load, Fig. 6. Its input impedance is given in Fig. 9 and output
impedance in Fig. 10.
C1
CUT OFF FREQUENCY = fo
R
R
DF0
DF1
100K
DF2
C2
ωo = 2 . π . fo . y
C1 = 2.Q
R . ωo
C2 =
BESSEL
Q = 0.577
Y = 1.732
BUTTERWORTH
Q = 0.71
Y = 1.0
Fig. 4 Choosing data filter components
Example
To implement a Bessel response filter with a 10KHz 3dB cutoff
C1 = 106pF
C2 = 80pF
4
1
2 . Q . R ωo.
KESRX01
Bit slicer and Peak Detector
To provide maximum flexibility an independent data
comparator is provided. External circuitry must be provided to
obtain the bit slicer threshold level. Two basic approaches are
supported.
2. For coding schemes with d.c. content (e.g. low duty cycle
pulse width modulation) an active peak detector is included.
The output at pin PEAK represents the peak level at the data
filter output (as shown in Fig.5). An external RC time constant
at this pin determines the maximum attack and decay times of
the peak detector. Typical values for the leakage and diode
current source capability are shown in the specifications. The
comparator has relatively low drive capability (push/pull
current source output of 20µA) and hence DATOP should not
be excessively loaded. On chip positive feedback around the
comparator provides a nominal hysteresis level of 20mV.
1. For coding schemes with no d.c. content (e.g. Manchester
coding or 33% / 66% pulse width encoding) this can be based
on the integrated d.c. level (using a series R and C). See
Application Note AN207.
INTERNAL CIRCUIT
–
+
–
+
PEAK
PEAK LEVEL OUTPUT
Fig. 5 Peak detector output
Sensitivity
In digital radio systems, sensitivity is often defined as the
lowest signal level at the receiver input that will achieve a
specified Bit Error Ratio (BER) at the output. The sensitivity of
the KESRX01 receiver, when used in the 434MHz application
shown in Fig. 6, is typically –103dBm average power (ASK
modulated with 2kHz, 50% duty cycle square wave) to achieve
a 0.01 BER. The input was matched for a 50Ω signal source.
At 315MHz, –105dBm average power is typically achievable.
Consult the Applications Notes refered to at the end of this
Datasheet for detailed PCB design issues to secure
perfomance.
The local oscillator frequency is set at 433.65MHz with a
required accuracy of at least ± 100kHz (see section below) i.e
433.55MHz to 433.75MHz.
This guarantees that the IF (70KHz to 470KHz) falls within
the acceptance bandwidth of the IF filter.
The frequency of operation for such products in Europe is
433.05MHz to 434.79MHz. The choice of such a low IF
frequency ensures that any image falls within the regulatory
band. This in turn ensures that the receiver cannot be blocked
by the image response of an unwanted signal outside of this
band.
Choice of IF frequency and IF bandwidth
Frequency Accuracy
The IF frequency is selected to be nominally 270KHz with
the low frequency cut-off at 25KHz and the high frequency
cut-off at 550KHz (nominal). For worst case tolerances the
transmitter frequency may be 433.92MHz ± 100KHz. i.e from
433.82MHz to 434.02MHz (see transmitter design
specification application notes)
The stability of the local oscillator is equal to that of the
crystal reference oscillator. Therefore to obtain a final output
accuracy of ± 100KHz at 433MHz would require a crystal with
a tolerance specification of ± 230ppm. This tolerance should
encompass all causes e.g. initial accuracy, temperature
stability and ageing. Choose a tighter tolerance crystal for
increased frequency accuracy.
5
KESRX01
C17
C18
XTAL1
-15 V
RLY7
KESRX01
IF O/P SELECT
IF O/P
2
IFDC1 XTAL2 24
IFDC2 XTAL1 23
3
DF2
22
1
IC1
C8
+15 V
R65
C9
L2
Vcc 1
SELECT ATTENUATOR
RLY 2
RF Input 0 dB
20 dB
C14
Vcc 1
C16
C50
IF2
4
IF1
DF1
21
5
Vcc
DF0
20
6
Mix IP
LF 19
RF OP Vee 2 18
7
8
C2
L1
Vee RF
VARAC
RF IN VCO2
9
C4
DF2 O/P
RSSI O/P Select
RSSI O/P
C19
C20
PLL SELECT
RLY9
NC
C13
NC
16
15
10 DSN
C1
17
C5
VCO1
11 Data O/P PD 14
12 Peak Vee 1 11
L4
C11
13
R8
VCO OVERDRIVE
VAR R9
R60
VCO EXTERNAL
C12
R55
R14
C24
Data O/P
Power Down
Fig. 6 KESRX01 Test circuit at 434MHz (peak detector slice mode)
Component
Function
Value
Units
C1
Input Matching circuit
4.7
pF
C2
Input Matching circuit
1
pF
C4, C5
XTAL feedback capacitors
100
pF
C8
DC decoupling capacitor
470
pF
C9
IF filter high pass
220
pF
C11, C13
VCO decouple
33
pF
C12
PLL loop filter
560
pF
C14
VCC decoupling capacitor
1
µF
C16
RF amplifier load
56
pF
C17, C18
IF amplifier decouple
100
nF
C19
Data filter
150
pF
C20
Data filter
220
pF
C24
Data slicer time constant
1
µF
C50
VCC decoupling capacitor
100
pF
R8
Varactor bias
47
KΩ
R9
PLL loop filter
18
KΩ
R14
Data slicer threshold circuit
1
MΩ
R55
Data slicer threshold circuit
4.3
KΩ
R60
Varactor bias
47
KΩ
R65
IC1 bias
1
MΩ
L1
RF amplifier input matching
47
nH
L2
RF amplifier/Mixer matching network
27
nH
L4
VCOtank circuit
39
nH
VAR
VCO tank circuit varactor
SMV-1104-35
4 to 11pF
XTAL
Reference frequency
6.775
MHz
Table 1. Component values for test circuit
6
KESRX01
If required, the reference signal to the PLL can be driven
externally from a stable signal source as shown in Fig. 7.
Typically a 200mVp clock signal is ac coupled to produce
differential output on OP and OPb. (C=10nF, Rs (source) <
5kΩ)
C
OP
CLK
Rs
OPb
XTAL2
XTAL1
Fig. 7 Direct drive of crystal oscillator
Applications
For detailed applications support material consult the following Application Notes.
AN207
AN4561
KESRX01 Demonstrator Receiver - A practical Application
KESTX01/02 Demonstrator Transmitter
0.5
0
0.2
2.0
1
5
MIXER INPUT
IMPEDANCE
250 TO 500MHz
-0.5
-2.0
Fig. 8 KESRX01 mixer input impedance at -40, 27 and + 85 degrees
7
KESRX01
0.5
0.
0.2
2.0
1.
5.
RF INPUT
IMPEDANCE
250 TO 500MHz
-0.5
-2.0
Fig. 9 KESRX01 LNA input impedance at -40, 27 and +85 degrees
0.5
0.
0.2
2.0
1
5
RF OUTPUT
250 TO 500MHz
-0.5
-2.0
Fig. 10 KESSRX01 LNA output impedance at -40, 27 and +85 degrees
8
KESRX01
RF INPUT IMPEDANCE
Min
Freq
Typ
Max
Mag
Phase
Mag
Phase
Mag
Phase
303
0.935
-22.49
0.963
-23.16
0.975
-23.35
315
403
0.935
0.935
-23.43
-30.17
0.962
0.959
-24.09
-30.74
0.999
0.999
-24.26
-30.80
418
434
0.934
0.934
-31.29
-32.47
0.958
0.957
-31.85
-33.02
0.969
0.968
-31.89
-33.04
MHz
RF OUTPUT IMPEDANCE
Min
Freq
Typ
Max
Mag
Phase
Mag
Phase
Mag
Phase
303
315
0.999
0.999
-14.62
-15.2
0.999
0.999
-14.32
-14.88
0.999
0.999
-13.92
-14.47
403
418
0.999
0.999
-19.37
-20.08
0.999
0.999
-18.97
-19.67
0.999
0.999
-19.36
-19.37
434
0.999
-20.83
0.999
-20.40
0.999
-19.84
MHz
MIXER INPUT IMPEDANCE
Min
Freq
Typ
Max
Mag
Phase
Mag
Phase
Mag
Phase
303
315
0.927
0.926
-14.64
-15.16
0.938
0.935
-14.42
-14.95
0.949
0.949
-14.11
-14.63
403
418
0.925
0.925
-19.03
-19.98
0.937
0.937
-18.82
-19.47
0.948
0.948
-18.49
-19.11
434
0.925
-20.39
0.937
-20.17
0.948
-19.84
MHz
9
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