MT93L16 AEC for Analog Hands-Free Communication Data Sheet Zarlink has introduced a new generation family of AEC (ZL38002 and ZL38004). Zarlink recommends these products for new designs. October 2006 Ordering Information MT93L16AQ 36 Pin QSOP MT93L16AF 48 Pin TQFP MT93L16AQ1 36 Pin QSOP* *Pb Free Matte Tin Features • Contains two echo cancellers: 112 ms acoustic echo canceller + 16 ms line echo canceller • Works with low cost voice codec. ITU-T G.711 or signed mag µ/A-Law, or linear 2’s comp • Each port may operate in different format • Advanced NLP design - full duplex speech with no switched loss on audio paths • Fast re-convergence time: tracks changing echo environment quickly • Adaptation algorithm converges even during Double-Talk • Designed for exceptional performance in high background noise environments • Provides protection against narrow-band signal divergence • Howling prevention stops uncontrolled oscillation in high loop gain conditions • Offset nulling of all PCM channels + Offset Null Linear ACOUSTIC ECHO PATH • ST-BUS, GCI, or variable-rate SSI PCM interfaces • User gain control provided for speaker path (-24 dB to +21 dB in 3 dB steps) • • AGC on speaker path Handles up to 0 dB acoustic echo return loss and 0 dB line ERL Transparent data transfer and mute options 20 MHz master clock operation Low power mode during PCM Bypass Bootloadable for future factory software upgrades 2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs • • • • • + - S2 Program RAM S3 S1 Program ROM CONTROL Linear/ µ/A-Law Sout Micro Interface DATA2 DATA1 UNIT Adaptive Filter R3 R1 AGC User Gain Controller NBSD SCLK R2 -24 -> +21 dB Linear/ µ/A-Law Howling Adaptive Filter Double Talk Detector CS - ADV NLP + Offset Null + µ/A-Law/ Linear Limiter VDD VSS RESET FORMAT ENA1 ENA2 PORT 1 PORT 2 Serial micro-controller interface Limiter MD2 Rout • ADV NLP MD1 NBSD -40C to +85°C Line ECho Path Sin µ/A-Law/ Tubes Tubes Tubes LAW F0i BCLK/C4i MCLK Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved. Rin MT93L16 Data Sheet Applications • Full duplex speaker-phone for digital telephone • Echo cancellation for video conferencing • Hands-free in automobile environment • Full duplex speaker-phone for PC MT93L16 ZL38001 ZL38002 ZL38003 Description AEC for analog handsfree communication AEC for analog hands- AEC with noise reduction for digital free communication hands-free communication AEC with noise reduction & codecs for digital hands-free communication Application Analog Desktop phone Analog Intercom Analog Desktop phone Hands-free Car Kits Hands-free Car Kits Analog Intercom Digital Desktop Phone Home Security Digital Desktop Phone Home Security Intercom & Pedestals Intercom & Pedestals Features AEC 1 channel 1 channel 1 channel 1 channel LEC 1 channel 1 channel Custom Load Custom Load Gains User Gain User Gain/18 dB Gain on Sout User Gain + System tuning gains User Gain + System tuning gains Noise Reduction N N Y Y Integrated Codecs N N N dual channel Table 1 - Acoustic Echo Cancellation Family 2 Zarlink Semiconductor Inc. MT93L16 QSOP 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC VSS VDD2 VSS2 NC IC IC BCLK/C4i NC F0i Rout NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 IC IC IC MCLK2 NC VSS VDD2 VSS2 IC IC BCLK/C4i F0i Rout Sout VDD NC DATA1 DATA2 36 NC MCLK2 IC IC IC NC ENA1 NC MD1 ENA2 MD2 Rin 32 34 30 28 26 38 24 22 40 20 42 TQFP 18 44 16 46 14 48 2 4 6 8 10 12 Sout VDD NC DATA1 NC DATA2 NC CS SCLK NC NC RESETB NC Sin IC NC MCLK IC IC IC LAW NC FORMAT NC ENA1 MD1 ENA2 MD2 Rin Sin IC MCLK IC IC IC LAW FORMAT RESET NC NC SCLK CS Data Sheet Figure 2 - Pin Connection Pin Description QSOP Pin # TQFP Pin # Name Description 1 43 ENA1 SSI Enable Strobe / ST-BUS & GCI Mode for Rin/Sout (Input). This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present for frame synchronization. This is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for on Rin/Sout pins. Strobe period is 125 microseconds. For ST-BUS or GCI, this pin, in conjunction with the MD1 pin, selects the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). 2 45 MD1 ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI operation, this pin, in conjunction with the ENA1 pin, will select the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode. 3 46 ENA2 SSI Enable Strobe / ST-BUS & GCI Mode for Sin/Rout (Input).This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer on Sin/Rout pins. Strobe period is 125 microseconds. For ST-BUS/GCI, this pin, in conjunction with the MD2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). 4 47 MD2 ST-BUS & GCI Mode for Sin/Rout (Input).When in ST-BUS or GCI operation, this pin in conjunction with the ENA2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode. 5 48 Rin Receive PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data may be in either companded or 2’s complement linear format. This is the Receive Input channel from the line (or network) side. Data bits are clocked in following SSI, GCI or ST-BUS timing requirements. 3 Zarlink Semiconductor Inc. MT93L16 Data Sheet Pin Description (continued) QSOP Pin # TQFP Pin # Name Description 6 2 Sin Send PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data may be in either companded or 2’s complement linear format. This is the Send Input channel (from the microphone). Data bits are clocked in following SSI, GCI or ST-BUS timing requirements. 7 3 IC Internal Connection (Input): Must be tied to Vss. 8 5 MCLK 9,10,11 6, 7, 8 IC 12 9 LAW 13 11 14 13 RESET Reset / Power-down (Input). An active low resets the device and puts the MT93L16 into a low-power stand-by mode. 17 16 SCLK Serial Port Synchronous Clock (Input). Data clock for the serial microport interface. 18 17 CS 19 19 DATA2 Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd. 20 21 DATA1 Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1 pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for transmitting and receiving data. 22 23 VDD Positive Power Supply (Input). Nominally 3.3 volts. 23 24 Sout Send PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream. Data may be in either companded or 2’s complement linear PCM format. This is the Send Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked out following SSI, ST-BUS, or GCI timing requirements. 24 26 Rout Receive PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream. Data may be in either companded or 2’s complement linear PCM format. This is the Receive out signal after line echo cancellation non-linear processing, AGC, and gain control. Data bits are clocked out following SSI, STBUS, or GCI timing requirements. 25 27 F0i 26 29 Master Clock (Input): Nominal 20 MHz Master Clock input (may be asynchronous relative to 8 KHz frame signal.) Tie together with MCLK2 (pin 33). Internal Connection (Input): Must be tied to Vss. A/µ Law Select (Input). When low, selects µ−Law companded PCM. When high, selects A-Law companded PCM. This control is for both serial pcm ports. FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM code. This control is for both serial pcm ports. Serial Port Chip Select (Input). Enables serial microport interface data transfers. Active low. Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low (or active-high) frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss. BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit clock. This clock must be synchronous with ENA1, and ENA2 enable strobes. In ST-BUS or GCI operation, C4i pin must be connected to the 4.096 MHz (C4) system clock. 4 Zarlink Semiconductor Inc. MT93L16 Data Sheet Pin Description (continued) QSOP Pin # TQFP Pin # Name 27, 28 30,31 IC 29 33 VSS2 Digital Ground (Input): Nominally 0 volts. 30 34 VDD2 Positive Power Supply (Input): Nominally 3.3 volts (tie together with VDD, pin 22). 31 35 VSS 33 38 MCLK2 Description Internal Connection (Input). Tie to Vss. Digital Ground (Input): Nominally 0 volts (tie together with VSS2, pin 29). Master Clock (Input): Nominal 20 MHz master clock (tie together with MCLK, pin 8). 15,16,2 1, 4, 10, 1,32 12, 14, 15, 18, 20, 22, 25, 28, 32, 36, 37, 42, 44 NC No Connect (Output). This pin should be left unconnected. 34, 35, 36 IC Internal Connection (Input). Tie to Vss. 30,40,41 Notes: 1. All inputs have CMOS compatible, 5 V-tolerant logic levels. 2. All outputs have CMOS logic levels. Rout, Sout, and DATA1 are 5 V-tolerant when tristated (to withstand other 5 V drivers on a shared bus). Glossary Double-Talk Near-end Single-Talk Far-end Single-Talk ADV NLP Howling Narrowband NBSD Noise-Gating Offset Nulling Reverberation time Simultaneous signals present on Rin and Sin. Signals only present at Sin input. Signals only present at Rin input. Advanced Non-Linear-Processor Oscillation caused by feedback from acoustic and line echo paths Any mono or dual sinusoidal signals Narrow Band Signal Detector Audible switching of background noise Removal of DC component The time duration before an echo level decays to -60 dBm 5 Zarlink Semiconductor Inc. MT93L16 Data Sheet Changes Summary The following table captures the changes from the July 2004 issue. Page 3 and 4 Item Pin Description Table Change Corrected TQFP pinout table. Pin names and descriptions for pins 16-35, 38-41 and 43 were incorrect. Functional Description The MT93L16 device contains two echo cancellers, as well as the many control functions necessary to operate the echo cancellers. One canceller is for acoustic speaker to microphone echo, and one for line echo cancellation. The MT93L16 provides clear signal transmission in both audio path directions to ensure reliable voice communication, even with low level signals. The MT93L16 does not use variable attenuators during double-talk or single-talk periods of speech, as do many other acoustic echo cancellers for speaker-phones. Instead, the MT93L16 provides high performance full-duplex operation similar to network echo cancellers, so that users experience clear speech and un-interrupted background signals during the conversation. This prevents subjective sound quality problems associated with “noise gating” or “noise contrasting”. The MT93L16 uses an advanced adaptive filter algorithm that is double-talk stable, which means that convergence takes place even while both parties are talking1. This algorithm allows continual tracking of changes in the echo path, regardless of double-talk, as long as a reference signal is available for the echo canceller. The echo tail cancellation capability of the acoustic echo canceller has been sized appropriately (112 ms) to cancel echo in an average sized office with a reverberation time of less than 112 ms. The 16 ms line echo canceller is sufficient to ensure a high ERLE for most line circuits. In addition to the echo cancellers, the following functions are supported: • Control of adaptive filter convergence speed during periods of double-talk, far end single-talk, and near-end echo path changes. • Control of Non-Linear Processor thresholds for suppression of residual non-linear echo. • Howling detector to identify when instability is starting to occur, and to take action to prevent oscillation. • Narrow-Band Detector for preventing adaptive filter divergence caused by narrow-band signals • Offset Nulling filters for removal of DC components in PCM channels. • Limiters that introduce controlled saturation levels. • Serial controller interface compatible with Motorola, National and Intel microcontrollers. • PCM encoder/decoder compatible with µ/A-Law ITU-T G.711, µ/A-Law Sign-Mag or linear 2’s complement coding. • Automatic gain control on the receive speaker path. Adaptation Speed Control The adaptation speed of the acoustic echo canceller is designed to optimize the convergence speed versus divergence caused by interfering near-end signals. Adaptation speed algorithm takes into account many different factors such as relative double-talk condition, far end signal power, echo path change and noise levels to achieve fast convergence. 1. Patented. 6 Zarlink Semiconductor Inc. MT93L16 Data Sheet Advanced Non-Linear Processor (ADV-NLP)1 After echo cancellation, there is likely to be residual echo which needs to be removed so that it will not be audible. The MT93L16 uses an NLP to remove low level residual echo signals which are not comprised of background noise. The operation of the NLP depends upon a dynamic activation threshold, as well as a double-talk detector which disables the NLP during double-talk periods. The MT93L16 keeps the perceived noise level constant, without the need for any variable attenuators or gain switching that causes audible “noise gating”. The noise level is constant and identical to the original background noise even when the NLP is activated. For each audio path, the NLP can be disabled by setting the NLP- bit to 1 in the LEC or AEC control registers. Narrow Band Signal Detector (NBSD)2 Single or multi-frequency tones (e.g., DTMF, or signalling tones) present in the reference input of an echo canceller for a prolonged period of time may cause the adaptive filter to diverge. The Narrow Band Signal Detector (NBSD) is designed to prevent this divergence by detecting single or multi-tones of arbitrary frequency, phase, and amplitude. When narrow band signals are detected, the filter adaptation process is stopped but the echo canceller continues to cancel echo. The NBSD can be disabled by setting the NB- bit to 1 in the MC control registers. Howling Detector (HWLD)3 The Howling detector is part of an Anti-Howling control, designed to prevent oscillation as a result of positive feedback in the audio paths. The HWLD can be disabled by setting the AH- bit to 1 in the (MC) control register. Offset Null Filter To ensure robust performance of the adaptive filters at all times, any DC offset that may be present on either the Rin signal or the Sin signal, is removed by highpass filters. These filters have a corner frequency placed at 40 Hz. The offset null filters can be disabled by setting the HPF- bit to 1 in the LEC or AEC control registers. Limiters To prevent clipping in the echo paths, two limiters with variable thresholds are provided at the outputs. The Rout limiter threshold is in Rout Limiter Register 1 and 2. The Sout limiter threshold is in Sout Limiter Register. Both output limiters are always enabled. User Gain The user gain function provides the ability for users to adjust the audio gain in the receive path (speaker path). This gain is adjustable from -24 dB to +21 dB in 3 dB steps. It is important to use ONLY this user gain function to adjust the speaker volume. The user gain function in the MT93L16 is optimally placed between the two echo cancellers such that no reconvergence is necessary after gain changes. The gain can be accessed through Receive Gain Control Register. 1. Patented. 2. Patented. 3. Patented. 7 Zarlink Semiconductor Inc. MT93L16 Data Sheet AGC The AGC function is provided to limit the volume in the speaker path. The gain of the speaker path is automatically reduced during the following conditions: • When clipping of the receive signal occurs. • When initial convergence of the acoustic echo canceller detects unusually large echo return. • When howling is detected. The AGC can be disabled by setting the AGC- bit to 1 in MC control register. Mute Function A pcm mute function is provided for independent control of the Receive and Send audio paths. Setting the MUTE_R or MUTE_S bit in the MC register, causes quiet code to be transmitted on the Rout or Sout paths respectively. Quiet code is defined according to the following table: LINEAR SIGN/ 16 bits MAGNITUDE µ-Law 2’s A-Law complement +Zero (quiet code) 0000h 80h CCITT (G.711) µ-Law A-Law FFh D5h Table 2 - Quiet PCM Code Assignment Bypass Control A PCM bypass function is provided to allow transparent transmission of pcm data through the MT93L16. When the bypass function is active, pcm data passes transparently from Rin to Rout and from Sin to Sout, with bit-wise integrity preserved. When the Bypass function is selected, most internal functions are powered down to provide low power consumption. The BYPASS control bit is located in the main control MC register. Adaptation Enable/Disable Adaptation control bits are located in the AEC and LEC control registers. When the ADAPT- bit is set to 1, the adaptive filter is frozen at the current state. In this state, the device continues to cancel echo with the current echo model. When the ADAPT- bit is set to 0, the adaptive filter is continually updated. This allows the echo canceller to adapt and track changes in the echo path. This is the normal operating state. MT93L16 Throughput Delay In all modes, voice channels always have 2 frames of delay. In ST-BUS/GCI operation, the D and C channels have a delay of one frame. Power Down / Reset Holding the RESET pin at logic low will keep the MT93L16 device in a power-down state. In this state all internal clocks are halted, and the DATA1, Sout and Rout pins are tristated. 8 Zarlink Semiconductor Inc. MT93L16 Data Sheet The user should hold the RESET pin low for at least 200 msec following power-up. This will insure that the device powers up in a proper state. Following any return of RESET to logic high, the user must wait for 8 complete 8 KHz frames prior to writing to the device registers. During this time, the initialization routines will execute and set the MT93L16 to default operation (program execution from ROM using default register values). PCM Data I/O The PCM data transfer for the MT93L16 is provided through two PCM ports. One port consists of Rin and Sout pins while the second port consists of Sin and Rout pins. The data are transferred through these ports according to either ST-BUS, GCI, or SSI conventions, and the device automatically detects the correct convention. The device determines the convention by monitoring the signal applied to the F0i pin. When a valid ST-BUS (active low) frame pulse is applied to the F0i pin, the MT93L16 will assume ST-BUS operation. When a valid GCI (active high) frame pulse is applied to the F0i pin, the device will assume GCI operation. If F0i is tied continuously to Vss, the device will assume SSI operation. Figures 11 to 13 show timing diagrams of these 3 PCM-interface operation conventions. ST-BUS and GCI Operation The ST-BUS PCM interface conforms to Zarlink’s ST-BUS standard, with an active-low frame pulse. Input data is clocked in by the rising edge of the bit clock (C4i) three-quarters of the way into the bitcell, and output data bit boundaries (Rout, Sout) occur every second falling edge of the bit clock (see Figure 11.) The GCI PCM interface corresponds to the GCI standard commonly used in Europe, with an active-high frame pulse. Input data is clocked in by the falling edge of the bit clock (C4i) three-quarters of the way into the bitcell, and output data bit boundaries (Rout, Sout) occur every second rising edge of the bit clock (see Figure 12.) Either of these interfaces (STBUS or GCI) can be used to transport 8 bit companded PCM data (using one timeslot) or 16 bit 2’s complement linear PCM data (using two timeslots). The MD1/ENA1 pins select the timeslot on the Rin/Sout port while the MD2/ENA2 pin selects the timeslot on the Sin/Rout port, as in Table 3. Figures 3 to 6 illustrate the timeslot allocation for each of these four modes. PORT1 Rin/Sout ST-BUS/GCI Mode Selection Enable Pins MD1 ENA1 0 0 0 PORT2 Sin/Rout Enable Pins MD2 ENA2 Mode 1. 8 bit companded PCM I/O on timeslot 0 0 0 1 Mode 2. 8 bit companded PCM I/O on timeslot 2. 0 1 1 0 Mode 3. 8 bit companded PCM I/O on timeslot 2. Includes D & C channel bypass in timeslots 0 & 1. 1 0 1 1 Mode 4. 16 bit 2’s complement linear PCM I/O on timeslots 0 & 1. 1 1 Table 3 - ST-BUS & GCI Mode Select 9 Zarlink Semiconductor Inc. MT93L16 Data Sheet C4i start of frame (stbus & GCI) F0i (ST-BUS) 0 1 2 3 4 B F0i (GCI) PORT1 Rin 7 6 5 4 3 2 1 0 EC 7 6 5 4 3 2 1 0 Sout PORT2 7 6 5 4 3 2 1 0 Sin EC 7 6 5 4 3 2 1 0 Rout outputs = High impedance inputs = don’t care In ST-BUS/GCI Mode 1, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 0. Note that the user can configure PORT1 and PORT2 into different modes. Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1) C4i start of frame (stbus & GCI) F0i (ST-BUS) 0 1 2 3 4 B F0i (GCI) PORT1 Rin 7 6 5 4 3 2 1 0 EC 7 6 5 4 3 2 1 0 Sout PORT2 7 6 5 4 3 2 1 0 Sin EC 7 6 5 4 3 2 1 0 Rout outputs = High impedance inputs = don’t care In ST-BUS/GCI Mode 2, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 2. Note that the user can configure PORT1 and PORT2 into different modes. Figure 4 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 2 (Mode 2) 10 Zarlink Semiconductor Inc. MT93L16 Data Sheet C4i start of frame (stbus & GCI) F0i (ST-BUS) 0 D 1 2 C B 3 4 F0i (GCI) PORT1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Rin EC 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Sout PORT2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Sin EC 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Rout outputs = High impedance inputs = don’t care indicates that an input channel is bypassed to an output channel ST-BUS/GCI Mode 3 supports connection to 2B+D devices where timeslots 0 and 1 transport D and C channels and echo canceller (EC) I/O channels are assigned to ST-BUS timeslot 2 (B). Both PORT1 and PORT2 must be configured in Mode 3. Figure 5 - ST-BUS and GCI 8-Bit Companded PCM I/O with D and C Channels (Mode 3) C4i start of frame (stbus & GCI) F0i (stbus) F0i (GCI) Rin S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 PORT1 Sout Sin EC S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 PORT2 Rout EC S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 outputs = High impedance inputs = don’t care ST-BUS/GCI Mode 4 allows 16 bit 2’s complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and PORT2 need not necessarily both be in mode 4. Figure 6 - ST-BUS and GCI 16-Bit 2’s Complement Linear PCM I/O (Mode 4) 11 Zarlink Semiconductor Inc. MT93L16 Data Sheet SSI Operation The SSI PCM interface consists of data input pins (Rin, Sin), data output pins (Sout, Rout), a variable rate bit clock (BCLK), and two enable pins (ENA1, ENA2) to provide strobes for data transfers. The active high enable may be either 8 or 16 BCLK cycles in duration. Automatic detection of the data type (8 bit companded or 16 bit 2’s complement linear) is accomplished internally. The data type cannot change dynamically from one frame to the next. In SSI operation, the frame boundary is determined by the rising edge of the ENA1 enable strobe (see Figure 7). The other enable strobe (ENA2) is used for parsing input/output data and it must pulse within 125 microseconds of the rising edge of ENA1. In SSI operation, the enable strobes may be a mixed combination of 8 or 16 BCLK cycles allowing the flexibility to mix 2’s complement linear data on one port (e.g., Rin/Sout) with companded data on the other port (e.g., Sin/Rout). Enable Strobe Pin Designated PCM I/O Port ENA1 Line Side Echo Path (PORT 1) ENA2 Acoustic Side Echo Path (PORT 2) Table 4 - SSI Enable Strobe Pins PCM Law and Format Control (LAW, FORMAT) The PCM companding/coding law used by the MT93L16 is controlled through the LAW and FORMAT pins. ITU-T G.711 companding curves for µ-Law and A-Law are selected by the LAW pin. PCM coding ITU-T G.711 and SignMagnitude are selected by the FORMAT pin. See Table 5. 12 Zarlink Semiconductor Inc. MT93L16 Data Sheet BCLK start of frame (SSI) PORT1 ENA1 8 or 16 bits Rin EC Sout 8 or 16 bits PORT2 ENA2 8 or 16 bits Sin EC 8 or 16 bits Rout outputs = High impedance inputs = don’t care Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate with 16-bit enable strobes. Figure 7 - SSI Operation Sign-Magnitude ITU-T (G.711) FORMAT=0 FORMAT=1 PCM Code µ/A-LAW µ-LAW A-LAW LAW = 0 or 1 LAW = 0 LAW =1 + Full Scale 1111 1111 1000 0000 1010 1010 + Zero 1000 0000 1111 1111 1101 0101 - Zero 0000 0000 0111 1111 0101 0101 - Full Scale 0111 1111 0000 0000 0010 1010 Table 5 - Companded PCM 13 Zarlink Semiconductor Inc. MT93L16 Data Sheet Linear PCM The 16-bit 2’s complement PCM linear coding permits a dynamic range beyond that which is specified in ITU-T G.711 for companded PCM. The echo-cancellation algorithm will accept 16 bits 2’s complement linear code which gives a maximum signal level of +15 dBm0. Bit Clock (BCLK/C4i) The BCLK/C4i pin is used to clock the PCM data for GCI and ST-BUS (C4i) interfaces, as well as for the SSI (BCLK) interface. In SSI operation, the bit rate is determined by the BCLK frequency. This input must contain either eight or sixteen clock cycles within the valid enable strobe window. BCLK may be any rate between 128 KHz to 4.096 MHz and can be discontinuous outside of the enable strobe windows defined by ENA1, ENA2 pins. Incoming PCM data (Rin, Sin) are sampled on the falling edge of BCLK while outgoing PCM data (Sout, Rout) are clocked out on the rising edge of BCLK. See Figure 13. In ST-BUS and GCI operation, connect the system C4 (4.096 MHz) clock to the C4i pin. Master Clock (MCLK) A nominal 20 MHz, continuously-running master clock (MCLK) is required. MCLK may be asynchronous with the 8 KHz frame. Microport The serial microport provides access to all MT93L16 internal read and write registers, plus write-only access to the bootloadable program RAM (see next section for bootload description.) This microport is compatible with Intel MCS-51 (mode 0), Motorola SPI (CPOL=0, CPHA=0), and National Semiconductor Microwire specifications. The microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a synchronous data clock pin (SCLK). The MT93L16 automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National requirements. The microport dynamically senses the state of the SCLK pin each time CS pin becomes active (i.e. high to low transition). If SCLK pin is high during CS activation, then Intel mode 0 timing is assumed. In this case DATA1 pin is defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during CS activation, then Motorola/National timing is assumed and DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. The MT93L16 supports Motorola half-duplex processor mode (CPOL=0 and CPHA=0). This means that during a write to the MT93L16, by the Motorola processor, output data from the DATA1 pin must be ignored. This also means that input data on the DATA2 pin is ignored by the MT93L16 during a valid read by the Motorola processor. All data transfers through the microport are two bytes long. This requires the transmission of a Command/Address byte followed by the data byte to be written to or read from the addressed register. CS must remain low for the duration of this two-byte transfer. As shown in Figures 8 and 9, the falling edge of CS indicates to the MT93L16 that a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the MT93L16 and the microcontroller. At the end of the two-byte transfer, CS is brought high again to terminate the session. The rising edge of CS will tri-state the DATA1 pin. The DATA1 pin will remain tri-stated as long as CS is high. Intel processors utilize Least Significant Bit (LSB) first transmission while Motorola/National processors use Most Significant Bit (MSB) first transmission. The MT93L16 microport automatically accommodates these two schemes for normal data bytes. However, to ensure timely decoding of the R/W and address information, the Command/Address byte is defined differently for Intel and Motorola/National operations. Refer to the relative timing 14 Zarlink Semiconductor Inc. MT93L16 Data Sheet diagrams of Figure 8 and Figure 9. Receive data bits are sampled on the rising edge of SCLK while transmit data is clocked out on the falling edge of SCLK. Detailed microport timing is shown in Figure 14 and Figure 15. Bootload Process and Execution from RAM A bootloadable program RAM (BRAM) is available on the MT93L16 to support factory-issued software upgrades to the built-in algorithm. To make use of this bootload feature, users must include 4096 X 8 bits of memory in their microcontroller system (i.e., external to the MT93L16), from which the MT93L16 can be bootloaded. Registers and program data are loaded into the MT93L16 in the same fashion via the serial microport. Both employ the same command / address / data byte specification described in the previous section on serial microport. Either intel or motorola mode may be transparently used for bootloading. There are also two registers relevant to bootloading (BRC=control and SIG=signature, see Register Summary). The effect of these register values on device operation is summarized in Table 6. FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM) R/W Address Data W 3fh (= 1 1 1 1 1 1 b) Writes "data" to BRC reg. - Bootload frozen; BRAM contents are NOT affected. C3C2C1C0 W other than 3fh Writes "data" to next byte in BRAM (bootloading.) X 1 0 0 R 1x xxxxb Reads back "data" = BRC reg value. - Bootload frozen; BRAM contents are NOT affected. R 0x xxxxb Reads back "data" = SIG reg value. - Bootload frozen; BRAM contents are NOT affected. BRC Register Bits NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs) BRC Register Bits C3C2C1C0 R/W Address Data W any (= a5 a4 a3 a2 a1 a0 b) Writes "data" to corresponding DREG. R any (= a5 a4 a3 a2 a1 a0 b) Reads back "data" = corresponding DREG value. X 0 0 0 PROGRAM EXECUTION MODES C3C2C1C0 0 0 0 0 Execute program in ROM, bootload mode disabled. - BRAM address counter reset to initial (ready) state. - SIG reg reseeded to initial (ready) state C3C2C1C0 Execute program in ROM, while bootloading the RAM. - BRAM address counter increments on microport writes (except to 3fh) - SIG reg recalculates signature on microport writes (except to 3fh) C3C2C1C0 1 0 0 0 Execute program in RAM, bootload mode disabled. - BRAM address counter reset to initial (ready) state. - SIG reg reseeded to initial (ready) state C3C2C1C0 - NOT RECOMMENDED (Execute program in RAM, while bootloading the RAM) 0 1 0 0 1 1 0 0 Table 6 - Bootload RAM Control (BRC) Register States Note: bits C1 C0 are reserved, and must be set to zero. 15 Zarlink Semiconductor Inc. MT93L16 Data Sheet Bootload mode is entered and exited by writing to the bootload bit in the Bootload RAM Control (BRC) register at address 3fh (see Register Summary). During bootload mode, any serial microport "write" (R/W command bit =0) to an address other than that of the BRC register will contribute to filling the program BRAM. Call these transactions "BRAM-fill" writes. Although a command/address byte must still precede each data byte (as described for the serial microport), the values of the address fields for these "BRAM-fill" writes are ignored (except for the value 3fh, which designates the BRC register.) Instead, addresses are internally generated by the MT93L16 for each "BRAM-fill" write. Address generation for "BRAM-fill" writes resumes where it left off following any read transaction while bootload mode is enabled. The first 4096 such "BRAM-fill" writes while bootload is enabled will load the memory, but further ones after that are ignored. Following the write of the first 4096 bytes, the program BRAM will be filled. Before bootload mode is disabled, it is recommended that users then read back the value from the signature register (SIG) and compare it to the one supplied by the factory along with the code. Equality verifies that the correct data has been loaded. The signature calculation uses an 8-bit MISR which only incorporates input from "BRAM-fill" writes. Resetting the bootload bit (C2) in the BRC register to 0 (see Register Summary) exits bootload mode, resetting the signature (SIG) register and internal address generator for the next bootload. A hardware reset (RESET=0) similarly returns the MT93L16 to the ready state for the start of a bootload. Once the program has been loaded, to begin execution from RAM, bootload mode must be disabled (BOOT bit, C2=0) and execution from RAM enabled (RAM_ROMb bit, C3=1) by setting the appropriate bits in the BRC register. During the bootload process, however, ROM program execution (RAM_ROMb bit, C3=0) should be selected. See Table 6 for the effect of the BRC register settings on Microport accesses and on program execution. Following program loading and enabling of execution from RAM, it is recommended that users set the software reset bit in the Main Control (MC) register, to ensure that the device updates the default register values to those of the new program in RAM. Note: it is important to use a software reset rather than a hardware (RESET=0) reset, as the latter will return the device to its default settings (which includes execution from program ROM instead of RAM.) To verify which code revision is currently running, users can access the Firmware Revision Code (FRC) register (see Register Summary). This register reflects the identity code (revision number) of the last program to run register initialization (which follows a software or hardware reset.) COMMAND/ADDRESS e DATA 1 R/W A0 A1 A2 A3 A4 A5 DATA INPUT/OUTPUT D0 D1 D2 D3 D4 D5 D6 D7 X a SCLK b CS d c a b This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT93L16. The MT93L16: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK c The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high. d A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. e The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 6 bits - Addressing Data 1 bit - Unused Figure 8 - Serial Microport Timing for Intel Mode 0 16 Zarlink Semiconductor Inc. MT93L16 COMMAND/ADDRESS e DATA 2 Receive R/W A5 A4 A3 A2 A1 A0 Data Sheet DATA INPUT X D7 D6 D5 D4 D3 D2 D1 D0 DATA OUTPUT DATA 1 Transmit D7 D6 D5 D4 D3 D2 D1 D0 High Impedance a SCLK b CS d c a This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT93L16. b The MT93L16: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK c The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high. d A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. e The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 6 bits - Addressing Data 1 bit - Unused Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire 17 Zarlink Semiconductor Inc. MT93L16 Data Sheet Absolute Maximum Ratings* Parameter Symbol Min. Max. Units VDD-VSS -0.5 5.0 V 1 Supply Voltage 2 Input Voltage Vi VSS-0.3 5.5 V 3 Output Voltage Swing Vo VSS-0.3 5.5 V 4 Continuous Current on any digital pin Ii/o ±20 mA 5 Storage Temperature TST 150 °C 6 Package Power Dissipation PD 90 (typ) mW -65 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. . Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated Characteristics Sym. Min. Typ. Max. Units VDD 2.7 3.3 3.6 V 1 Supply Voltage 2 Input High Voltage 1.4 VDD V 3 Input Low Voltage VSS 0.4 V 4 Operating Temperature -40 +85 °C TA Test Conditions Echo Return Limits Characteristics Min. Typ. Max. Units Test Conditions 1 Acoustic Echo Return 0 dB Measured from Rout -> Sin 2 Line Echo Return 0 dB Measured from Sout -> Rin DC Electrical Characteristics*- Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym. Min. Typ‡. Max. Units 70 µA RESET = 0 mA RESET = 1, clocks active Standby Supply Current: ICC 3 Operating Supply Current: IDD 20 2 Input HIGH voltage VIH 3 Input LOW voltage VIL 4 Input leakage current IIH/IIL 5 High level output voltage VOH 6 Low level output voltage VOL 7 High impedance leakage IOZ 1 8 Output capacitance Co 10 1 0.7VDD Conditions/Notes V 0.1 0.3VDD V 10 µA VIN=VSS to VDD V IOH=2.5 mA 0.4VDD V IOL=5.0 mA 10 µA VIN=VSS to VDD 0.8VDD pF 8 pF 9 Input capacitance Ci ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. *DC Electrical Characteristics are over recommended temperature and supply voltage. 18 Zarlink Semiconductor Inc. MT93L16 Data Sheet AC Electrical Characteristics† - Serial Data Interfaces - Voltages are with respect to ground (VSS) unless otherwise stated Characteristics Sym. Min. Typ. Max. Units 20.5 MHz Test Notes 1 MCLK Frequency fCLK 19.15 2 BCLK/C4i Clock High tBCH, tC4H 90 ns 3 BCLK/C4i Clock Low tBLL, tC4L 90 ns 4 BCLK/C4i Period tBCP 240 5 SSI Enable Strobe to Data Delay (first bit) tSD 80 ns CL=150 pF 6 SSI Data Output Delay (excluding first bit) tDD 80 ns CL=150 pF 7 SSI Output Active to High Impedance tAHZ 80 ns CL=150 pF 8 SSI Enable Strobe Signal Setup tSSS 10 tBCP -15 ns 9 SSI Enable Strobe Signal Hold tSSH 15 tBCP -10 ns 10 SSI Data Input Setup tDIS 10 ns 11 SSI Data Input Hold tDIH 15 ns 12 ST-BUS/GCI F0i Setup tF0iS 20 150 ns 13 ST-BUS/GCI F0i Hold tF0iH 20 150 ns 14 ST-BUS/GCI Data Output delay tDSD 80 ns CL=150 pF 15 ST-BUS/GCI Output Active to High Impedance tASHZ 80 ns CL=150 pF 16 ST-BUS/GCI Data Input Hold time tDSH 20 ns 17 ST-BUS/GCI Data Input Setup time tDSS 20 ns † Timing is over recommended temperature and power supply voltages. 19 Zarlink Semiconductor Inc. 7900 ns MT93L16 Data Sheet AC Electrical Characteristics† - Microport Timing Characteristics Sym. Min. Typ. Max. Units 1 Input Data Setup tIDS 30 ns 2 Input Data Hold tIDH 30 ns 3 Output Data Delay tODD 100 ns 4 Serial Clock Period tSCP 500 ns 5 SCLK Pulse Width High tSCH 250 ns 6 SCLK Pulse Width Low tSCL 250 ns 7 CS Setup-Intel tCSSI 200 ns 8 CS Setup-Motorola tCSSM 100 ns 9 CS Hold tCSH 100 ns 10 CS to Output High Impedance tOHZ 100 ns Test Notes CL=150 pF CL=150 pF † Timing is over recommended temperature range and recommended power supply voltages. Characteristic Symbol CMOS Level Units CMOS reference level VCT 0.5*VDD V Input HIGH level VH 0.9*VDD V Input LOW level VL 0.1*VDD V Rise/Fall HIGH measurement point VHM 0.7*VDD V Rise/Fall LOW measurement point VLM 0.3*VDD V Table 7 - Reference Level Definition for Timing Measurements T=1/fCLK MCLK (I) VH VCT VL Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions) Figure 10 - Master Clock - MCLK 20 Zarlink Semiconductor Inc. MT93L16 Bit 7 Data Sheet Bit 6 Sout/Rout (O) VCT tDSD C4i (I) tASHZ tC4H VH VCT input sampled VL tF0iS tF0iH F0i (I) VH tC4L VCT VL start of frame Rin/Sin (I) tDSS tDSH VH VCT VL Bit 6 Bit 7 Figure 11 - GCI Data Port Timing ) Bit 7 Bit 6 Sout/Rout (O) VCT tDSD VH VL tF0iS tF0iH F0i (I) tASHZ VH VCT input sampled C4i (I) tC4H tC4L VCT VL start of frame Rin/Sin (I) tDSS tDSH VH VL VCT Bit 7 Bit 6 Figure 12 - ST-BUS Data Port Timing 21 Zarlink Semiconductor Inc. MT93L16 Bit 7 Bit 6 Data Sheet Bit 5 VCT Sout/Rout (O) tSD VH VCT VL tSSS ENA1 (I) or ENA2 (I) tAHZ tBCH input sampled BCLK (I) tDD tBCP VH tBCL tSSH VCT VL tDIS tDIH start of frame VH Rin/Sin (1) VCT VL Notes: O. CMOS output Bit 7 Bit 6 Bit 5 I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions) Figure 13 - SI Data Port Timing DATA OUTPUT DATA INPUT DATA1 (I,O) VCT tIDS tIDH SCLK (I) tSCH tODD tOHZ VH VCT VL tCSSI CS (I) tSCL tSCP VH tCSH VCT VL Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions) Figure 14 - INTEL Serial Microport Timing 22 Zarlink Semiconductor Inc. MT93L16 DATA2 (I) (Input) VH VCT VL tIDS tIDH SCLK (I) Data Sheet tSCH tSCP VH VCT VL tCSSM CS (I) tSCL tCSH VH VCT VL tODD DATA1 (O) (Output) tOHZ VCT Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions) Figure 15 - Motorola Serial Microport Timing 23 Zarlink Semiconductor Inc. MT93L16 Data Sheet Register Summary Address: 00h R/W Power Up Reset 00h RESET AHAGCNB- Main Control Register (MC) 7 MSB LIMIT 6 MUTE_R 5 MUTE_S 4 BYPASS 3 NB- 2 AGC- 1 AH- 0 RESET LSB When high, the power initialization routine is executed presetting all registers to default values. This bit automatically clears itself to’0’ when reset is complete. When high, the Howling detector is disabled and when low the Howling detector is enabled. When high, AGC is disabled and when low AGC is enabled. When high, Narrowband signal detectors in Rin and Sin paths are disabled and when low the signal detectors are enabled BYPASS When high, the Send and Receive paths are transparently by-passed from input to output and when low the Send and Receive paths are not bypassed MUTE_S When high, the Sin path is muted to quite code (after the NLP) and when low the Sin path is not muted MUTE_R When high, the Rin path is muted to quite code (after the NLP) and when low the Rin path is not muted LIMIT When high, the 2-bit shift mode is enabled in conjunction with bit 7 of LEC register and when low 2-bit shift mode is disabled Address: 21h R/W Power Up Reset 00h ECBY ADAPT- Acoustic Echo Canceller Control Register (AEC) 7 MSB P- 6 ASC- 5 NLP- 4 INJ- 3 HPF- 2 HCLR 1 ADAPT- 0 ECBY When high, the Echo estimate from the filter is not subtracted from the input (Sin), when low the estimate is subtracted When high, the Echo canceller adaptation is disabled and when low the adaptation is enabled HCLR When high, Adaptive filter coefficients are cleared and when low the filter coefficients are not cleared HPF- When high, Offset nulling filter is bypassed in the Sin/Sout path and when low the Offset nulling filter in not bypassed INJ- When high, the Noise filtering process is disabled in the NLP and when low the Noise filtering process is enabled NLP- When high, the Non Linear Processor is disabled in the Sin/Sout path and when low the NLP is enabled ASC- When high, the Internal Adaptation speed control is disabled and when low the Adaptation speed is enabled P- When high, the Exponential weighting function for the adaptive filter is disabled and when low the weighting function is enabled Address: 01h R/W Power Up Reset 00h ECBY ADAPT- LSB Line Echo Canceller Control Register (LEC) MSB 7 SHFT 6 ASC- 5 NLP- 4 INJ- 3 HPF- 2 HCLR 1 ADAPT- 0 ECBY LSB When high, the Echo estimate from the filter is not substracted from the input (Rin), when low the estimate is substracted When high, the Echo canceller adaptation is disabled and when low the adaptation is enabled HCLR When high, Adaptive filter coefficients are cleared and when low the filter coefficients are not cleared HPF- When high, Offset nulling filter is bypassed in the Rin/Rout path and when low the Offset nulling filter in not bypassed INJ- When high, the Noise filtering process is disabled in the NLP and when low the Noise filtering process is enabled NLP- When high, the Non Linear Processor is disabled in the Rin/Rout path and when low the NLP is enabled ASC- When high, the Internal Adaptation speed control is disabled and when low the Adaptation speed is enabled SHFT when high the 16-bit linear mode, inputs Sin, Rin, are shift right by 2 and outputs Sout, Rout are shift left by 2. This bit is ignored when 16-bit linear mode is not selected in both ports. This bit is also ignored if bit 7 of MC register is set to zero 24 Zarlink Semiconductor Inc. MT93L16 Acoustic Echo Canceller Status Register (ASR) (* Do not write to this register) Address: 22h Read Power Up Reset 00h NBS Data Sheet 7 6 ACMUND 5 HWLNG - MSB 4 3 - NLPDC 2 LOGICAL OR of the status bit NBS + NBR from LSR Register DT When high the Double Talk is detected and when low, the Double talk is not detected HWLNG ACMUND - RESERVED. When high, Howling is occurring in the loop and when low, no Howling is detected When high, No active signal in the Rin/Rout path RESERVED. Line Echo Canceller Status Register (LSR) (* Do not write to this register) Power Up Reset 00h 6 - 5 - 4 - 3 - NLPC 2 1 DT NB 0 NBR LSB When high, a narrowband signal has been detected in the Receive (Rin) path. When low no narrowband signal is not detected in the Rin path NB This bit indicates a LOGICAL-OR of Status bits NBR + NBS (from ASR Register) DT When high, double-talk is detected and when low double-talk is not detected NLPC LSB When high, the NLP is activated and when low the NLP is not activated Address: 02h Read NBR 0 NBS NB When high, the Narrowband signal has been detected in the Sin/Sout path and when low, the Narrowband signal has not been detected in the Sin/Sout path NB NLPDC 1 DT When high, NLP is activated and when low NLP is not activated - RESERVED. . -- Receive Gain Control Register (RGC) Address: 20h R/W Power Up Reset 6Dh 7 MSB - 6 - 5 - 4 - 3 G3 2 G2 1 0 G1 GO LSB G0 G1 G2 User Gain Control on the Rin/Rout path (Tolerance of gains: +/- 0.15 dB). The hexadecimal number represents G3 to G0 value in the table below. G3 - RESERVED - Gain Values for Receive Gain Control Register Bit G3 to G0 (RGC) 0h -24 dB 4h -12 dB 8h 0 dB Ch +12 dB 1h -21 dB 5h -9 dB 9h + 3 dB Dh + 15 dB 2h -18 dB 6h -6 dB Ah + 6 dB Eh + 18 dB 3h -15 dB 7h -3 dB Bh +9 dB Fh + 21 dB 25 Zarlink Semiconductor Inc. MT93L16 Receive (Rin) Peak Detect Register 1 Address: 16h Read Power Up Reset 00h Data Sheet MSB 7 RIPD 7 6 RIPD6 5 RIPD5 4 RIPD4 3 RIPD3 2 (RIPD1) RIPD2 1 RIPD1 0 RIPD0 LSB RIPD0 RIPD1 RIPD2 RIPD3 These peak detector registers allow the user to monitor the receive in signal (Rin) peak level at reference point R1 (see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1. RIPD4 RIPD5 RIPD6 RIPD7 Receive (Rin) Peak Detect Register 2 Address: 17h Read Power Up Reset 00h MSB 7 RIPD 15 6 RIPD14 5 RIPD13 4 RIPD12 3 RIPD11 2 (RIPD2) RIPD10 1 RIPD9 0 RIPD8 LSB RIPD8 RIPD9 RIPD10 RIPD11 See Above Description RIPD12 RIPD13 RIPD14 RIPD15 Receive (Rin) ERROR Peak Detect Register 1 Address: 18h Read Power Up Reset 00h MSB 7 REPD 7 6 REPD6 5 REPD 5 4 REPD 4 3 REPD 3 2 REPD 2 (REPD1) 1 REPD1 0 REPD 0 LSB REPD0 REPD1 REPD2 REPD3 These peak detector registers allow the user to monitor the error signal peak level at reference point R2 (see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1. REPD4 REPD5 REPD6 REPD7 26 Zarlink Semiconductor Inc. MT93L16 Receive (Rin) ERROR Peak Detect Register 2 Address: 19h Read Power Up Reset 00h Data Sheet MSB 7 REPD 6 REPD14 15 5 REPD13 4 REPD 12 3 REPD11 2 REPD 10 (REPD2) 1 REPD 9 0 REPD8 LSB REPD8 REPD9 See above description REPD10 REPD11 REPD12 REPD13 REPD14 REPD15 Receive (Rout) Peak Detect Register 1 Address: 3Ah Read Power Up Reset 00h MSB 7 ROPD 7 6 ROPD 6 5 ROPD 5 4 ROPD4 3 ROPD3 2 (ROPD1) ROPD2 1 ROPD1 0 ROPD 0 LSB ROPD0 ROPD1 ROPD2 ROPD3 These peak detector registers allow the user to monitor the receive out signal (Rout) peak level at reference point R3 (see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1. ROPD4 ROPD5 ROPD6 ROPD7 Receive (Rout) Peak Detect Register 2 Address: 3Bh Read Power Up Reset 00h MSB 7 ROPD 6 5 ROPD14 ROPD13 15 4 ROPD 3 ROPD 2 ROPD 11 12 10 ROPD8 ROPD9 ROPD10 ROPD11 ROPD12 (ROPD2) See Above description ROPD13 ROPD14 ROPD15 27 Zarlink Semiconductor Inc. 1 ROPD 9 0 ROPD8 LSB MT93L16 Send (Sin) Peak Detect Register 1 Address: 36h Read Power Up Reset 00h Data Sheet MSB 7 SIPD 7 6 SIPD6 5 SIPD5 4 SIPD4 3 SIPD3 2 (SIPD1) SIPD2 1 SIPD1 0 SIPD0 LSB SIPD0 SIPD1 SIPD2 SIPD3 These peak detector registers allow the user to monitor the receive in signal (Sin) peak level at reference point S1 (see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1. SIPD4 SIPD5 SIPD6 SIPD7 Send (Sin) Peak Detect Register 2 Address: 37h Read Power Up Reset 00h MSB 7 SIPD 15 6 SIPD14 5 SIPD13 4 SIPD12 3 SIPD11 2 (SIPD2) SIPD10 1 SIPD9 0 SIPD8 LSB SIPD8 SIPD9 SIPD10 SIPD11 See above description SIPD12 SIPD13 SIPD14 SIPD15 Send ERROR Peak Detect Register 1 Address: 38h Read Power Up Reset 00h MSB 7 SEPD 7 6 SEPD6 5 SEPD5 4 SEPD4 3 SEPD3 2 (SEPD1) SEPD2 1 SEPD1 0 SEPD0 LSB SEPD0 SEPD1 SEPD2 SEPD3 These peak detector registers allow the user to monitor the error signal peak level in the send path at reference point S2 (see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1. SEPD4 SEPD5 SEPD6 SEPD7 28 Zarlink Semiconductor Inc. MT93L16 Send ERROR Peak Detect Register 2 Address: 39h Read Power Up Reset 00h Data Sheet MSB 7 SEPD 6 SEPD14 15 5 SEPD13 4 SEPD 3 SEPD11 12 (SEPD2) 2 SEPD 10 1 SEPD 9 0 SEPD8 LSB SEPD8 SEPD9 SEPD10 SEPD11 SEPD12 See Above description SEPD13 SEPD14 SEPD15 Send (Sout) Peak Detect Register 1 Address: 1Ah Read Power Up Reset 00h MSB 7 SOPD 7 6 SOPD 6 5 SOPD 5 4 SOPD 4 3 SOPD 3 2 (SOPD1) SOPD2 1 SOPD1 0 SOPD 0 LSB SOPD0 SOPD1 SOPD2 SOPD3 These peak detector registers allow the user to monitor the Send out signal (Sout) peak level at reference point S3 (see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1. SOPD4 SOPD5 SOPD6 SOPD7 Send (Sout) Peak Detect Register 2 Address: 1Bh Read Power Up Reset 00h MSB 7 SOPD 6 SOPD14 15 5 SOPD13 4 SOPD 3 SOPD11 12 SOPD8 SOPD9 SOPD10 SOPD11 See Above description SOPD12 SOPD13 SOPD14 SOPD15 29 Zarlink Semiconductor Inc. (SOPD2) 2 SOPD 10 1 SOPD 9 0 SOPD8 LSB MT93L16 Acoustic Echo Canceller Adaptation Speed Register 1 Address: 3Ch R/W Power Up Reset 00h A_AS0 A_AS1 A_AS2 A_AS3 Data Sheet MSB 7 A_AS 7 6 A_AS 6 5 A_AS 5 4 A_AS 4 3 A_AS 3 2 A_AS2 1 (A_AS1) A_AS1 0 A_AS 0 LSB This register allows the user to program control the adaptation speed of the Acoustic Echo Canceller. This register value changes dynamically when the ’ASC-’ bit in the Acoustic Echo Canceller Control Register is low. The ’ASC-’ bit must be 1 when this register is under user control. The valid range is from 0000h to 7FFFh. The high byte is in Register 2 and the low byte is in Register 1. Smaller values correspond to slower adaptation speed. A_AS4 A_AS5 A_AS6 A_AS7 Acoustic Echo Canceller Adaptation Speed Register 2 Address: 3Dh R/W Power Up Reset 10h MSB 7 A_AS 6 A_AS14 15 5 A_AS13 4 A_AS 12 3 A_AS11 2 A_AS 10 (A_AS2) 1 A_AS 9 0 A_AS8 LSB A_AS8 A_AS9 A_AS10 A_AS11 See Above description A_AS12 A_AS13 A_AS14 A_AS15 Line Echo Canceller Adaptation Speed Register 1 Address: 1Ch R/W Power Up Reset 00h L_AS0 L_AS1 L_AS2 L_AS3 MSB 7 L_AS 7 6 L_AS 6 5 L_AS 5 4 L_AS 4 3 L_AS 3 2 L_AS2 (L_AS1) 1 L_AS1 0 L_AS 0 LSB This register allows the user to program control the adaptation speed of the Line Echo Canceller. This register value changes dynamically when the ’ASC-’ bit in the Acoustic Echo Canceller Control Register is low. The ’ASC-’ bit must be 1 when this register is under user control. The valid range is from 0000h to 7FFFh. The high byte is in Register 2 and the low byte is in Register 1. Smaller values correspond to slower adaptation speed. L_AS4 L_AS5 L_AS6 L_AS7 30 Zarlink Semiconductor Inc. MT93L16 Line Echo Canceller Adaptation Speed Register 2 Address: 1Dh Read Power Up Reset 08h Data Sheet MSB 7 L_AS 6 L_AS14 15 5 L_AS13 4 L_AS 12 3 L_AS11 2 L_AS 10 (L_AS2) 1 L_AS 9 0 1 0 L_AS8 LSB L_AS8 L_AS9 L_AS10 L_AS11 See Above description L_AS12 L_AS13 L_AS14 L_AS15 Rout Limiter Register 1 (RL1) Address: 24h R/W Power Up Reset 80h 7 MSB L0 6 - 5 4 - - 3 - 2 - - - LSB - RESERVED L0 This bit is used in conjunction with Rout Limiter Register 2. (See description below.) Rout Limiter Register 2 (RL2) Address: 25h R/W Power Up Reset 3Eh 7 MSB L8 6 L7 5 L6 4 L5 3 L4 2 L3 1 L2 0 L1 LSB L1 L2 L3 L4 L5 L6 In conjunction with bit 7 (L0) of the above (RL1) register, this register (RL2) allows the user to program the output Limiter threshold value in the Rout path. Default value is (1f40)h which is equal to 3.14 dBmo Maximum value is (7FC0)h = 15 dBmo Minimum value is (0040)h = -38 dBmo L7 L8 31 Zarlink Semiconductor Inc. MT93L16 Sout Limiter Register (SL) Address: 26h R/W Power Up Reset 3Dh Data Sheet 7 MSB L4 6 L3 5 L2 4 L1 3 L0 2 - 1 - 0 - 0 - 0 - LSB - RESERVED L0 L1 L2 L3 This register allows the user to program the output Limiter threshold value in the Rout path Default value is (1f40)h which is equal to 3.14 dBmo Maximum value is (7F40)h L4 Firmware Revision Code Register (FRC) Address: 03h Read Power Up Reset 00h 7 MSB FRC2 6 FRC1 5 FRC0 4 - 3 - 2 - 1 - LSB - RESERVED - FRC0 FRC1 Revision code of the firmware program currently being run (default=rom=00). FRC2 Bootload RAM Control Register (BRC) Address: 3fh R / W Power Up Reset 00h 7 MSB - 6 - 5 - 4 - 3 RAM_ROMb 2 BOOT 1 C0 RESERVED. Must be set to zero. C1 RESERVED. Must be set to zero. C2 BOOT bit. When high, puts device in bootload mode. When low, bootload is disabled. C3 RAM_ROMb bit. When high, device executes from RAM. When low, device executes from ROM. - RESERVED - 32 Zarlink Semiconductor Inc. - LSB MT93L16 Bootload RAM Signature Register (SIG) Address: 07h Read Power Up Reset FFh Data Sheet MSB 7 SIG 7 6 SIG 6 5 SIG5 4 SIG 4 3 SIG3 2 SIG 2 1 SIG 1 0 SIG0 SIG7 SIG6 SIG5 SIG4 This register provides the signature of the bootloaded data to verify error-free delivery into the device. Note: this register is only accessible if BOOT bit is high (bootload mode enabled) in the above BRC register. While bootload is disabled, the register value is held constant at its reset seed value of FFh. SIG3 SIG2 SIG1 SIG0 33 Zarlink Semiconductor Inc. LSB Package Code c Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Previous package codes For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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