Le71HR0073
Le78D11/FXS/FXO
Line Module User’s Guide
Rev. A, Ver. 2
October 4, 2007
Document Number: 081213
A
Voice Solution
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
trademarks of Zarlink Semiconductor Inc.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
TABLE OF CONTENTS
CHAPTER 1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Documentation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Design Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 2
QUICK START GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Set-Up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 How the Circuit Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CHAPTER 3
SYSTEM DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Le78D110VC Codec Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Le77S111TC SLIC Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 FXO Interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 4
CIRCUIT DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 FXS Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1.1 Transmission and Loop Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1.2 Surge Suppression of the FXS Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1.3 PWM Switching Power Supply of the FXS Section . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 FXO Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.1 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.2 Lightning and AC fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.3 Line In Use Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.4 FXO Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CHAPTER 5
PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Coefficients and WinSLAC™ 2 .0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 FXS Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 FXO Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 Operation Script (VP Script) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 FXS Transmission Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 FXS Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 FXS Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3 FXS Gain Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.4 FXS Total Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.5 FXS Longitudinal Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 FXO Transmission Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 FXO Return loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 FXO Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 FXO Gain Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4 FXO Total Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5 FXO Longitudinal Balance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.6 FXO Return loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.7 FXO Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 6
PRINTED CIRCUIT BOARD DOCUMENTATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Schematic Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document ID# 081213 Date:
Rev:
A
Version:
Distribution:
Public Document
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6.2
6.3
6.4
6.5
6.6
6.7
Line Module User Guide
Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parts Placement Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Routing and Grounding Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.1 Routing Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.2 Switching Power Supply Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Design Schematics and BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.1 Le71HR0073 Reference Design Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.2 Le71HR0073 Reference Design BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CHAPTER
1
1.1
INTRODUCTION
DOCUMENTATION OVERVIEW
This document describes one of a series of Zarlink line modules. Each module is a complete
standalone solution applicable to a specific target market or application. When used with Zarlink’s
VoicePath software and the VP demo board, a fully functional, multi-channel telecommunications
network can be realized.
The Le71HR0073 Le78D11/FXS/FXO line module provides a complete two-channel voice
implementation. Optimized for voice-over-broadband applications with internal balanced ringing,
the line module features all necessary circuitry between the PCM backplane and the two-wire
interface, including line protection and an on-board independent switching power supply. The FXO
circuit, which use CPC5621 Clare DAA chip and the associated circuit, draws the loop current from
FXS and accepts the caller ID. It also perform ring detection and line-in-use detections.
1.2
DESIGN OBJECTIVES
Zarlink’s Le71HR0073 Le78D11/FXS/FXO line module was designed to meet the following
objectives:
•
Be fully hardware and software compatible with Zarlink’s VoicePath™ demo platform
•
Optimized for 12-V applications
•
Supply up to 30 mA loop current and up to 90 V peak ringing voltage
•
Feature a performance optimized layout
•
Have two-wire port impedance of 600 Ω with option for complex impedance
•
Include over-voltage and over-current line protection
Figure 1–1
Le71HR0073 Le78D11/FXS/FXO Line Module
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1.3
Line Module User Guide
REFERENCED DOCUMENTS
The following documents are referred to in this document and may be helpful.
1. Le78D11 Data Sheet, document ID# 080697
2. Le77S11 Data Sheet, document ID# 081052
3. Le77D11 / Le78D11 Chip Set User’s Guide, document ID# 080716
4. WinSLAC™ Software User’s Guide, document ID# 080779
5. VoicePath™ Demo Board User’s Guide, document ID# 080756
6. Mini-PBX Demo Application User’s Guide, document ID# 080722
7. Le71HR0023 770 Series 90Vpk Ringing Line Module, document ID# 081115
8. Layout Considerations for the Le77D112 and Le9502 Devices, document ID# 081013
9. DS-CPC5620/CPC5621-R03 data sheet at www.clare.com
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CHAPTER
2
2.1
QUICK START GUIDE
SET-UP PROCEDURE
Zarlink reference designs mate to Zarlink VoicePath™ demo boards and utilize Zarlink
VoicePath software. Refer to Figure 2–1.
Figure 2–1 Generic Demonstration Set-Up Diagram
PC terminal
window
serial port
cable
power
supply
FXS/FXO line
module
VP demo board
Le71HP0200
FXS/FXS
line module
FXS
FXS
FXO
FXS
VP demo board
Le71HP0200
RJ11 cable
CO side
PBX side
telephone
telephone
The VoicePath demo board accommodates up to four telephone interfaces. It is supplied with an
external power supply module and accepts an optional high voltage power supply and ringer source
module (for external unbalanced ringing applications). Mini-PBX firmware is contained within the
VoicePath demo board’s EEPROM and interfaces to the PC through the serial port.
Quick start steps:
1. Assemble the components as depicted in Figure 2–1.
2. Initiate any generic terminal software on the PC and configure the COM port.
3. Apply power to the VP demo boards and line modules.
Note:
If the VP demo board’s FLASH is loaded with the correct firmware for the installed line module and
configured for autorun, the terminal program will display the reference design application menu. If it is not,
acquire the appropriate application HEX file from =DUOLQN.
4. Reset the VP demo board by pressing the RESET button then, within 3 seconds, pressing A
on your keyboard.
5. At VP-MON> prompt, type XA <CR> to erase FLASH. Then type W <CR> to write.
6. Select Send File from terminal program’s FILE menu, then select and send the HEX application
file. Once the file is loaded, reset the board (refer to Step 4.). This starts the application.
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Le71HR0073
Line Module User Guide
7. One serial COM port can be shared by first loading the program file into the Le71HR0023 line
module, then connecting to the Le71HR0073 line module to load the second program.
2.2
HOW THE CIRCUIT WORKS
In this arrangement, two VoicePath demo boards acts as the CO and the PBX. The setup requires
that the line module port of the VoicePath demo board be populated with an Le71HR0023 line
module, and the Le71HR0073 board sets on top the second line module. Refer to Chapter 2, on
page 4
Figure 2–2 System Demo Setup Diagram
Serial
Power
Power
Serial
RJ-45
RJ-45
Le78D11
Le71HR0023
Line Module
Zarlink
VoicePath
Demo Board
Le71HP0200
101
(FXS)
Le77D11
Le71HR0073
Line Module
Le78D11
Le77S11
CPC5621
Zarlink
VoicePath
Demo Board
Le71HP0200
RJ-11 Bank
102
(FXS)
RJ-11 Bank
101
(FXS)
102
(FXO)
Lines 101 and 102 are both FXS lines and belong to the Le71HR0023 line module. Line 102 on the
Le71HR0073 board, being an FXO line, cannot receive or place telephone calls. Therefore, the 102
phone number is unavailable, and the caller will hear a fast-busy tone if the number is dialed. Line
101 on the Le71HR0073 board, being FXS, can be mapped to the FXO line and will send and
receive calls via the FXO.
In its default configuration, the Mini-PBX does not map the Le71HR0073 FXS line to the FXO line.
To map these lines together so that calls can be generated from the FXS port and routed through
the FXO port, the user should follow these steps when the serial port is connected to the VPDB of
the Le71HR0073 board:
1. Select Top Menu Option ’F’ - Configure Line Features
2. In Configure Line Features Menu, select option ’U’ - FXO Support Options
At that point the user is provided a menu that will find the FXO line (line 102) and a list of the FXS
lines that the FXO line can be mapped to. The user should enter ’B’ at this menu to select line 102
as the FXO line to affect, then enter ’I’ to select the FXS line 101 to map.
At this point, the FXO line and FXS line on the Le71HR0073 board are logically mapped. This
means that the FXO on Line 102 mimics the hook state of Line 101. Likewise, Line 101 rings
whenever ringing is detected on Line 102. The examples in the remainder of this section assume a
setup like the one shown in Figure 2–2, with Line 102 of the Le71HR0073 board (FXO line)
physically connected to Line 102 of the Le71HR0023 board (FXS line). It is convenient to think of
the Le71HR0073 FXS/FXO reference design board as the PBX and the Le71HR0023 line module
as the Central Office or VoIP.
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The following actions occur when Line 101 on the Le71HR0073 board goes off-hook:
1. The MiniPBX detects off-hook on Line 101 (Le71HR0073).
2. Since Line 101 is mapped to Line 102 on the Le71HR0073 board, Line 102 (FXO) is placed in
the Off-hook state.
3. Since the FXO line is physically connected to Line 102 of the Le71HR0023 board (FXS line),
the MiniPBX running the Le71HR0023 board detects off-hook on Line 102.
4. The MiniPBX places dial tone on Line 102. This dial tone may also be heard on Line 101 of the
Le71HR0073 board since the FXO and FXS (Le71HR0073) voice path is connected.
5. Digits may now be dialed by Line 101 (either DTMF or Pulse) on the Le71HR0073 module and
decoded by Line 102 on the Le71HR0023 board. For example, Line 101 on Le71HR0073 could
place a call to Line 101 on Le71HR0023.
The following actions occur when Line 101 dials Line 102 on the Le71HR0023 board:
1. The MiniPBX places a cadenced ring on Line 102 (Le71HR0023 FXS).
2. The resulting ringing on Line 102 (FXO line) of Le71HR0073 is detected.
3. The MiniPBX places ringing on Line 101 of Le71HR0073 board to match that detected on the
FXO line.
If Line 101 of Le71HR0073 is taken off-hook, then the first three steps described in the previous
sequence occur, and a voice path is connected between Lines 101 of the Le71HR0023 board and
101 of Le71HR0073 board.
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Line Module User Guide
CHAPTER
3
3.1
SYSTEM DESCRIPTION
FEATURES
The Le71HR0073 line module features Zarlink’s Le78D110 Dual Channel Subscriber Line AudioProcessing Circuit, Zarlink’s Le77D112 Dual Channel or Le77S11 Single Channel Subscriber Line
Interface Circuit and a FXO, Clare DAA based circuit.
Figure 3–1
Line Module Block Diagram
+3.3V
+3.3V
Lightning Protection
Dual
Channel
Single
Channel
PTC
PCM
Highway
L
e
7
8
D
1
1
PTC
L
e
7
7
S
1
1
uP
Interface
+12V
Single Channel
Switching Power
Supply
+3.3V
Fuse
FXO circuit
Lightning Protection
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3.1.1
3.1.2
3.1.3
3.1.4
Line Module User Guide
System Features
–
Integrated dual-channel chip set
–
Optimized for voice-over-broadband applications
–
Line test capability (GR-909 compliant for the Le77S11/Le78D11 chip set)
–
Over-voltage and over-current line protection
–
Requires minimal external components
Le78D110VC Codec Features
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Dual-channel device
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Integrated signal generation (ringing, DTMF, metering, Caller ID)
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Integrated tone detection (DTMF, modem, FAX)
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Integrated loop-test and self-test features
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Integrated switching power supply support
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Transmit and receive gain and equalization
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Worldwide AC input impedance scaling
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A-law, µlaw, ADPCM, or linear coding
–
Flexible PCM and µP interfaces
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3.3V CMOS
Le77S111TC SLIC Device Features
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Single channel device
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Integrated boost switching power supply controller
–
3.3 V plus 8 V to 40 V (12 V nominal) supplies
–
Up to 90 Vpk sinusoidal or trapezoidal ringing at 5 REN with DC offset
–
Configurable constant current feed
–
Programmable loop-detect/ring-trip threshold
–
On-hook transmission
–
Low standby power
–
Thermally enhanced package
FXO Interface features
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Optical isolated solid state DAA
–
Loop start signaling
–
CID signal reception function
–
Ring detection
–
Polarity reversal detections
–
FXO line in use detection
–
3 KVrms line isolation
–
Complies with the following requirements: TIA/EIA/IS-968 (FCC part 68), UL1950,
UL60950, EN60950, IEC60950, EN55022B, CISPR22B, EN55024, and TBR21.
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CHAPTER
4
CIRCUIT DESIGN
4.1
FXS FUNCTIONS
4.1.1
Transmission and Loop Feed
Transconductance amplifiers within the Le77S11 SLIC device generate and sense currents on the
subscriber loop. These amplifiers also facilitate the conversion to voltage signals which interface to
the Le78D11 SLAC™ device. Communication between the devices is voltage-driven with gain in
both the receive path and transmit path by gain stages in the Le78D11 codec and resistor RIMT. The
programmability from Le78D11 SLAC device could generate the coefficients to match worldwide
termination impedances without changing the hardware.
Figure 4–1 Analog FXS Interface Component Diagram
VOUT
VIN
VIN
VIMT
1/2
PCM
Highway
L
e
7
8
D
1
1
RIMT
VHP
CHP
CFLT
L
e
7
7
S
1
1
+
VAB
-
RDC
VDC
RDC
Loop feed current is set by programming the appropriate Le78D11 SLAC device register with
knowledge of the value of RDC. Refer to the data sheet for details.
4.1.2
Surge Suppression of the FXS Section
Overvoltage and overcurrent suppression circuits are included on the line module (refer to
Figure 4–2, FXS Line Protection Component Diagram, on page 10.)
Overvoltage protection, via the TISP61089 device, is voltage tracking and senses the regulated
supply voltage generated by the switching regulator circuit. In this way, subscriber loop interface
nodes are held between ground potential and the regulated voltage VREG.
Overcurrent protection is provided by the MZ2L-50R PTC devices which ramp to a high impedance
value once the threshold current of 50 mA has been exceeded. Below this threshold current, the
devices act as nominal 50-Ω resistors.
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Line Module User Guide
Figure 4–2 FXS Line Protection Component Diagram
MZ2L-50R
1/2
L
e
7
7
S
1
1
L
e
7
8
D
1
1
VREG
TISP
61089
MZ2L-50R
4.1.3
PWM Switching Power Supply of the FXS Section
The switching power supply topology for the Le77S11 device operates as a pulse width modulated
buck-boost section. The component values are chosen for nominal 12-V input with up to −100-V
output.
The circuit varies the pulse width of the control signal delivered to the base of the PNP transistor.
The nominal frequency of this signal is 85.3 kHz.
When the transistor is turned on, it applies voltage to an inductor which draws a linearly increasing
current. When it is turned off, the inductor current ramps down, charging the output capacitor
through a rectifier diode. This establishes a large negative voltage across this capacitor which
passes through a low-pass LC filter to smooth out ripple (VREG). Refer to Figure 4–3.
Figure 4–3 FXS PWM Switching Power Supply Component Diagram
VREG
1/2
L
e
7
8
D
1
1
+12V
L
e
7
7
S
1
1
RCS
Chopper Clock
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Zarlink Semiconductor Inc.
Le71HR0073
4.2
FXO FUNCTIONS
4.2.1
Transmission
Line Module User Guide
The FXO is based on Clare LITELINK III Phone line Interface IC (silicon DAA) CPC5621, and acts
like a telephone set or modem. The gains in the transmit and receive paths are set by both on-chip
amplifiers and the codec/filter. There are analog gain blocks and digital gain blocks for both transmit
path and received path. A total of 18 dB can be adjusted in gain and loss via each direction. The
maximum level on the two-wire line is limited by the supply voltage, minimum loop current, and the
front end components chosen in the applications. The AC termination default setting is for 600 Ω.
With Zarlink codec/filter programmability, it is possible to match most worldwide complex
terminations without changing components. The WinSLAC™ program will calculate the filters
automatically after user specified termination network. In order to meet the IV curve requirements
of some countries, additional component adjustments may be necessary. The Le78D11 codec/filter
state controls the FXO interface on/off hook operation. The codec/filter Reverse Polarity state
places the FXO in the On-hook condition. The codec/filter Active state places the FXO interface in
the Off-hook condition. The circuit is incorporated with L00P/911 function to detect the parallel
handset off hook request during the FXO off hook condition.
4.2.2
Lightning and AC fault protection
The circuit includes one fast acting fuse (429.001) from Littlefuse and one Sidactor (T2300SA) from
Teccor. This design complies with ITU K.21 requirements.
4.2.3
Line In Use Detection
The line-in-use detection circuit consists of the following: a high voltage attenuation network, and
CPC5710 Phone Line Monitor (PLM) IC from Clare, attenuation from tip and ring voltage, with
proper gain setting, and an attenuation RC network to convert the line voltage to current with
filtering then feeding into the IMT2 (A to D converter) of the Le78D11 device. By setting an
appropriate threshold for On/Off hook detections, Normal and Polarity Reversal detections, the
codec/filter will report each event after it happens, then take further action according to the system
software programming. Addtionally, the circuit will knowledge the line lost event and distinguish
between pulse dial and ring interruption.
4.2.4
FXO Operation Table
DAA Line State (Le78D11)
OFF-HOOK (C1)
CID (C2)
NOTES
CID Control (Disconnect)
0 (false)
1 (true)
CID is Active Low
On Hook/ Ring Detect (Pol. Rev.)
1 (true)
1 (true)
Off Hook (Active)
1 (true)
0 (false)
OFF_HOOK is Active Low
For detailed information on operating the CPC5621 in various modes, refer to the Clare CPC5620/
CPC5621 data sheet.
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Zarlink Semiconductor Inc.
Le71HR0073
12
Zarlink Semiconductor Inc.
Line Module User Guide
CHAPTER
5
5.1
PERFORMANCE
COEFFICIENTS AND WINSLAC™ 2 .0
Coefficient files were generated from Zarlink’s WinSLAC™ 2.0 software and used to program
filters and to set gains.
5.1.1
FXS Coefficients
The following schematic was used to generate FXS coefficients.
Figure 5–1
WinSLAC™ Software/Le77S11 Device Schematic
X2
Le77S11
X2
6 Le77S11
VIN
6 VIN
TIP
1 VOUT TIP 3
3
1
VIN
VIN
VOUT
VOUT
RIMT
RIMT
100K
100K
RING 2
RING
2
4 VHP
VHP
TIP
TIP
50
50
RFA
RFA
RING
RING
50
50
5
5 CFILT
CFILT LPF
LPF
7 7
CHP
CHP
1.5uF
1.5uF
VOUT
RFB
RFB
CLP
4.7uF
CLP
RSA
RSA
475K
RSB
RSB
475K
475K
475K
0
0
0
0
4.7uF 0
0
Coefficients were generated as follows:
5.1.2
•
600-Ω termination
•
Receive relative level = 0 dBr
•
Transmit relative level = 0 dBr
•
A-Law encoding (or µ-Law)
FXO Coefficients
Coefficient files are provided in the following script. Circuit is optimized for 600-Ω AC termination
only.
Coefficients were generated as follows:
5.1.3
•
600-Ω termination
•
Receive relative level = 0 dBr
•
Transmit relative level = 0 dBr
•
A-Law encoding (or µ-Law)
Operation Script (VP Script)
Refer to the FXO/FXS test operation script on the following page. This script is different than the
Mini-PBX software mentioned in Chapter 2.
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Zarlink Semiconductor Inc.
Le71HR0073
Line Module User Guide
# This script is modified from the original VoSLIC/SLAC line module application
# This script will set up the VPDB for FXO/FXS test operation.
# The following two lines depend on how jumper 4 (JP4)
# is set on the eval board. If it is set to 1,2 then line
# one is used. If it is set to 2,3 then the second line is needed.
#vpdBrd DIO Combined
vpdBrd DIO Separate
# Sets up the VPDB for E1
vpdBrd FrmMode e1
acifBrd CS10
acifBrd MClk 2.048MHz
vpdBrd TMode Master
acifDut HwReset
acifDut DCR1Wrt 93 ;# setup clock
acifDut XR_CsWrt 3F
after 50
foreach ele {01 02} {
acifDut ECWrt $ele
acifDut ChnCnfg8Wrt 80 ;# work around due to A2 change
}
acifDut Calibrate
after 10
foreach ele {01 02} {
acifDut ECWrt $ele
acifDut ChnCnfg8Wrt 00 ;# unset SP_EN bit to prevent noise on the line
}
# multiple channel writes are not valid for A2
# so this loop is used to load the coeffs. into
# one after other.
foreach ele {01} {
acifDut ECWrt $ele;# enable channel X
# FXS section
acifDut ZWrt 7F5C0036FCB3FF0900E30166001B
acifDut RWrt 85BB008EFF12006701A2FE414110
acifDut XWrt 0000FE3C0214FFCEFE99FF4E40D6
acifDut GRCWrt 270F
acifDut GXCWrt FE74
acifDut B1Wrt FFB7FFA0FFE8018913B428E011F4
acifDut B2Wrt FDD88148FFBBFFBBFFBAFFB9FFB9
acifDut ELTWrt 04
acifDut EPGWrt 04
acifDut AdptBCtlWrt 02201C00
acifDut AnGnDISNWrt 02
acifDut ChnCnfg1Wrt 00
acifDut ChnCnfg3Wrt 00 ;# A-law encoding
#acifDut ChnCnfg3Wrt 40 ;# u-law encoding
acifDut LpSuperWrt 2080001813007F14100C7F
# For demo purpose, Rx level set -6dBr, Tx level set 0dbr for FXS
#acifDut SigGenAWrt 000001015B4C2CCD0000;# 20Hz, 70V amp., 0V offset
#acifDut SigGenAWrt FF38FCBC14E62CCD0000 ;#20Hz, 70V amp., 0 offset, trap 1.2
crest
#acifDut SigGenAWrt FF38FCBC14E6299AFC29 ;#20Hz, 65V amp., -6V offset, trap 1.2
crest
acifDut SigGenAWrt 000001015B4C399A0000
;#20Hz, 90V amp., 0 offset, sine
acifDut Activate
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Zarlink Semiconductor Inc.
Le71HR0073
Line Module User Guide
}
foreach ele {02} {
acifDut ECWrt $ele;# enable channel X
# FXO section
acifDut ZWrt 7F5CFFFDFF5BFFB3001F0061002A
acifDut RWrt 83CF000000000000000000004000
acifDut XWrt 0000FD6002500074FBDC01B03F50
acifDut GRCWrt 52B3
acifDut GXCWrt F152
acifDut B1Wrt 001F002A002FFE77F186E611F603
acifDut B2Wrt 01238148002100200027002C0025
acifDut ELTWrt 04
acifDut EPGWrt 04
acifDut AdptBCtlWrt 02201C00
acifDut AnGnDISNWrt 00
acifDut ChnCnfg1Wrt 00
acifDut ChnCnfg3Wrt 00 ;# A-law encoding
#acifDut ChnCnfg3Wrt 40 ;# u-law encoding
acifDut GDMaskWrt 11
;# Enable parallel off hook detect on VS2 interrupt
acifDut SlacStatWrt 30 # standby on hook, pol. rev.is off hook for FXO
#For demo purpose, Rx level set 0dBr, Tx level set -6dbr for FXO
acifDut Activate
acifDut SlacStatWrt 38; #pol.rev.state is on-hook FXO
acifDut ChnCnfg8Wrt C0 ;# set SP_EN bit to enable VS interrupt & extras
acifDut Activate
acifDut ChnCnfg6Wrt 3F ;# set no mask for MHOOK=0 and MGNK=0
}
acifDut ECWrt 02
#
#
#
#
5.2
Once this code has been run the part
is ready for half channel testing. Enable
either channel and put the SLIC into whatever
state is needed.
FXS TRANSMISSION PERFORMANCE
The following graphs illustrate transmission performance using the W&G PCM-4.
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Zarlink Semiconductor Inc.
Le71HR0073
5.2.1
Line Module User Guide
FXS Return Loss
Figure 5–2 Two-Wire Return Loss
Two Wire Return Loss 600 (B11) (Li: −−−, Lo: −−−, Input Level −10, a−law)
50
40
Loss (dB)
30
20
10
4000
3000
2000
1000
0
0
Frequency (Hz)
Figure 5–3 Four-Wire Return Loss
Four Wire Return Loss (A23) D−D 600 (Li: −−−, Lo: −−−, Input Level −10, a−law)
50
40
Loss (dB)
30
20
10
Frequency (Hz)
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Zarlink Semiconductor Inc.
4000
3000
2000
1000
0
0
Le71HR0073
5.2.2
Line Module User Guide
FXS Attenuation Distortion
Figure 5–4 Receive Path Attenuation Distortion
Attenuation Distortion (A11) D−A 600 (Li: −−−, Lo: 0, Input Level −10, a−law)
Level offset at 1KHz: 0.12 (dB)
0.5
0.25
0
−0.25
Level (dB)
−0.5
−0.75
−1
−1.25
−1.5
−1.75
4000
3000
2000
1000
0
−2
Frequency (Hz)
Figure 5–5 Transmit Path Attenuation Distortion
Attenuation Distortion (A11) A−D 600 (Li: 0, Lo: −−−, Input Level −10, a−law)
Level offset at 1KHz: 0.33 (dB)
0.5
0.25
0
−0.25
−0.75
−1
−1.25
−1.5
−1.75
Frequency (Hz)
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Zarlink Semiconductor Inc.
4000
3000
2000
1000
−2
0
Level (dB)
−0.5
Le71HR0073
5.2.3
Line Module User Guide
FXS Gain Tracking
Figure 5–6 Receive Path Gain Tracking
Gain Tracking (A43) D−A 600 (Li: −−−, Lo: 0, a−law)
Overload Comp.: @+3.00 dBm0 = +0.00 dB, @+6.00 dBm0 = −1.73 dB, @+7.00 dBm0 = −2.55 dB,
ICN: PSOPH (A61) −79.96 dBm0, 300Hz...3350Hz (A63) −77.62 dBm0
1.5
1
Gain (dB)
0.5
0
−0.5
−1
−10
0
−10
0
−20
−30
−40
−50
−60
−1.5
Level (dB)
Figure 5–7 Transmit Path Gain Tracking
Gain Tracking (A43) A−D 600 (Li: 0, Lo: −−−, a−law)
Overload Comp.: @+3.00 dBm0 = −0.01 dB, @+6.00 dBm0 = −1.90 dB, @+9.00 dBm0 = −4.48 dB,
ICN: PSOPH (A61) −79.62 dBm0, 300Hz...3350Hz (A63) −76.75 dBm0
1.5
1
0
−0.5
−1
Level (dB)
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Zarlink Semiconductor Inc.
−20
−30
−40
−50
−1.5
−60
Gain (dB)
0.5
Le71HR0073
5.2.4
Line Module User Guide
FXS Total Distortion
Figure 5–8 Receive Path Total Distortion
Total Distortion (A56) D−A 600 (Li: −−−, Lo: 0, a−law)
Harmonic Dis 2nd (A91): +52.22, 3rd (A92): +52.64 (dB)
Intermod. Dis 2nd (A93): +54.62, 3rd (A94): +52.27 (dB)
50
40
Distortion (dB)
30
20
10
0
10
0
10
−10
−20
−30
−40
−50
−60
0
Level (dB)
Figure 5–9 Transmit Path Total Distortion
Total Distortion (A56) A−D 600 (Li: 0, Lo: −−−, a−law)
Harmonic Dis 2nd (A91): +54.19, 3rd (A92): +53.36 (dB)
Intermod. Dis 2nd (A93): +54.81, 3rd (A94): +55.09 (dB)
50
40
Distortion (dB)
30
20
10
Level (dB)
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Zarlink Semiconductor Inc.
−10
−20
−30
−40
−50
−60
0
Le71HR0073
5.2.5
Line Module User Guide
FXS Longitudinal Balance
Figure 5–10 Longitudinal Balance
Longitudinal Balance (B21) 600 (Li: −−−, Lo: −−−, Input Level −10, a−law)
70
60
50
Distortion (dB)
40
30
20
10
Frequency (Hz)
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Zarlink Semiconductor Inc.
4000
3000
2000
1000
0
0
Le71HR0073
5.3
Line Module User Guide
FXO TRANSMISSION PERFORMANCE
The following graphs illustrate transmission performance using the W&G PCM-4.
5.3.1
FXO Return loss
Figure 5–11 Two-Wire Return Loss
Two Wire Return Loss 600 (B11) (Li: −−−, Lo: −−−, Input Level −10, a−law)
50
40
Loss (dB)
30
20
10
3000
4000
3000
4000
2000
1000
0
0
Frequency (Hz)
Figure 5–12 Four-Wire Return Loss
Four Wire Return Loss (A23) D−D 600 (Li: −−−, Lo: −−−, Input Level −10, a−law)
50
40
Loss (dB)
30
20
10
2000
1000
0
0
Frequency (Hz)
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Le71HR0073
5.3.2
Line Module User Guide
FXO Attenuation Distortion
Figure 5–13 Receive Path Attenuation Distortion
Attenuation Distortion (A11) D−A 600 (Li: −−−, Lo: 0, Input Level −10, a−law)
Level offset at 1KHz: −0.1 (dB)
0.5
0.25
0
−0.25
Level (dB)
−0.5
−0.75
−1
−1.25
−1.5
−1.75
4000
3000
2000
1000
0
−2
Frequency (Hz)
Figure 5–14 Transmit Path Attenuation Distortion
Attenuation Distortion (A11) A−D 600 (Li: 0, Lo: −−−, Input Level −10, a−law)
Level offset at 1KHz: 0.5 (dB)
0.5
0.25
0
−0.25
−0.75
−1
−1.25
−1.5
−1.75
Frequency (Hz)
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Zarlink Semiconductor Inc.
4000
3000
2000
1000
−2
0
Level (dB)
−0.5
Le71HR0073
5.3.3
Line Module User Guide
FXO Gain Tracking
Figure 5–15 Receive Path Gain Tracking
Gain Tracking (A43) D−A 600 (Li: −−−, Lo: 0, a−law)
Overload Comp.: @+3.00 dBm0 = −0.01 dB, @+6.00 dBm0 = −1.75 dB, @+7.00 dBm0 = −2.56 dB,
ICN: PSOPH (A61) −78.25 dBm0, 300Hz...3350Hz (A63) −75.76 dBm0
1.5
1
Gain (dB)
0.5
0
−0.5
−1
0
−10
−20
−30
−40
−50
−60
−1.5
Level (dB)
Figure 5–16 Transmit Path Gain Tracking
Gain Tracking (A43) A−D 600 (Li: 0, Lo: −−−, a−law)
Overload Comp.: @+3.00 dBm0 = −0.10 dB, @+6.00 dBm0 = −2.15 dB, @+9.00 dBm0 = −4.86 dB,
ICN: PSOPH (A61) −79.19 dBm0, 300Hz...3350Hz (A63) −76.27 dBm0
1.5
1
0
−0.5
−1
Level (dB)
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Zarlink Semiconductor Inc.
0
−10
−20
−30
−40
−50
−1.5
−60
Gain (dB)
0.5
Le71HR0073
5.3.4
Line Module User Guide
FXO Total Distortion
Figure 5–17 Receive Path Total Distortion
Total Distortion (A56) D−A 600 (Li: −−−, Lo: 0, a−law)
Harmonic Dis 2nd (A91): +52.26, 3rd (A92): +54.36 (dB)
Intermod. Dis 2nd (A93): +54.58, 3rd (A94): +52.06 (dB)
50
40
Distortion (dB)
30
20
10
10
0
−10
−20
−30
−40
−50
−60
0
Level (dB)
Figure 5–18 Transmit Path Total Distortion
Total Distortion (A56) A−D 600 (Li: 0, Lo: −−−, a−law)
Harmonic Dis 2nd (A91): +56.40, 3rd (A92): +51.33 (dB)
Intermod. Dis 2nd (A93): +54.31, 3rd (A94): +53.13 (dB)
50
40
Distortion (dB)
30
20
10
Level (dB)
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Zarlink Semiconductor Inc.
10
0
−10
−20
−30
−40
−50
−60
0
Le71HR0073
5.3.5
Line Module User Guide
FXO Longitudinal Balance
Longitudinal Balance (B21) 600 (Li: −−−, Lo: −−−, Input Level −10, a−law)
70
60
50
Distortion (dB)
40
30
20
10
Frequency (Hz)
25
Zarlink Semiconductor Inc.
3000
2000
1000
0
0
Le71HR0073
5.3.6
Line Module User Guide
FXO Return loss
Figure 5–19 Two-Wire Return Loss
Two Wire Return Loss (A23) A−A ETSI (Li: 1.49, Lo: 1.49, Input Level 0, a−law)
50
40
Loss (dB)
30
20
10
4000
3000
2000
1000
0
0
Frequency (Hz)
Figure 5–20 Four-Wire Return Loss
Four Wire Return Loss (A23) D−D ETSI (Li: −−−, Lo: −−−, Input Level 0, a−law)
50
40
Loss (dB)
30
20
10
Frequency (Hz)
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Zarlink Semiconductor Inc.
4000
3000
2000
1000
0
0
Le71HR0073
5.3.7
Line Module User Guide
FXO Attenuation Distortion
Figure 5–21 Receive Path Attenuation Distortion
Attenuation Distortion (A11) D−A ETSI (Li: −−−, Lo: 1.49, Input Level 0, a−law)
Level offset at 1KHz: +0.52(dB)
0.5
0.25
0
−0.25
Level (dB)
−0.5
−0.75
−1
−1.25
−1.5
−1.75
4000
3000
2000
1000
0
−2
Frequency (Hz)
Figure 5–22 Transmit Path Attenuation Distortion
Attenuation Distortion (A11) A−D ETSI (Li: 1.49, Lo: −−−, Input Level 0, a−law)
Level offset at 1KHz: −0.26 (dB)
0.5
0.25
0
−0.25
−0.75
−1
−1.25
−1.5
−1.75
Frequency (Hz)
27
Zarlink Semiconductor Inc.
4000
3000
2000
1000
−2
0
Level (dB)
−0.5
Le71HR0073
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Zarlink Semiconductor Inc.
Line Module User Guide
CHAPTER
6
6.1
PRINTED CIRCUIT BOARD
DOCUMENTATION
SCHEMATIC UPDATES
The following schematic updates were made from revision A to revision B:
6.2
•
Tip and Ring interface on FXS page renamed between TIP1and RING1 to match the chip A/B
pins.
•
TIP2 has been moved after the F1 and renamed TIP2A to enforce the protection scheme on
line sense circuit input of FXO page.
•
Snoop inputs on IC2 has been changed to match the corresponding polarity on FXO page.
JUMPER OPTIONS
There are no jumpers on the line module.
6.3
ID EEPROM
The Le71HR0073 reference design PCB features a Dallas Semiconductor DS2433 4K bit 1-wire
EEPROM. While not critical to board operation, this memory is integral to proper demo system
operation. The memory is factory loaded with a reference design identification, a serial number, and
max. battery operation range for ringing.
6.4
PARTS PLACEMENT STRATEGY
Parts placement on revision A of the reference design was intended to be logical as well as efficient
to conserve PCB area. However, the rational flow of signals to and from the digital backplane
through the Tip/Ring interface was considered first before minimizing board space. Furthermore,
from a practical perspective, parts placement was dictated by the routing strategy. Parts were often
placed where they would facilitate the preferred routing.
There are two jumpers on the PCB, J5 3.3V and J4 12V, for debugging purposes. They can be cut
to measure the currents. There are eleven test points placed around the PCB for DC voltages,
grounds, and AC interface monitoring between the SLIC, FXO and codec/filter. No ground plane
should be underneath the high voltage circuit around the primary area of the FXO section. The
isolation barrier should keep at least 150mil for 5KV surge. Snoop circuit should keep at least
150mil space to unrelated metal. Refer the schematic for detail requirement. Q1 heat sink should
keep as big as possible, multiple vias used through both top and bottom coppers for better heat
dissipation. Ground flood copper should cover between primary and secondary of the IC2 to reduce
the noise.
There was sufficient room to place the ICs and most of the larger switching power supply
components on the top layer of the PCB. Many smaller discrete components and the surge
suppression circuits are on the bottom layer.
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Zarlink Semiconductor Inc.
Le71HR0073
Line Module User Guide
Figure 6–1 Line Module Parts Placement Diagram
Le77S11
Le78D11
Switching
Power Supply
FXO Circuit
6.5
SIGNAL ROUTING AND GROUNDING STRATEGY
The size of the PCB board was predetermined because the location of the interface connector to
the VP Demo board was already defined. Only four layers were used due to cost considerations.
Since the primary objective was to produce a reference design rather than a production design, no
special grounding features needed to be provided. This flexibility allowed employment of a single
unified ground plane to provide the best noise performance.
Further supporting the single unified ground plane was the fact that the Le77S11 device is housed
in a thermally-enhanced package with an exposed heat slug on the underside. This heat slug
should be soldered to a large internal copper plane to improve heat sinking, and this copper plane
should be electrically tied to ground. This single internal copper ground plane also made sense for
thermal reasons.
With one internal layer assigned to ground, and the top and bottom layers used for signal routing,
the other internal layer was available for power supply routing and any other general signal routing
which could not be easily accommodated on the top or bottom layers.
6.5.1
Routing Priority
From this layering strategy, three levels of routing priority were assigned. The highest priority level
was given to signals involving the switching power supply. This included the analog tip/ring nodes
and the associated surge suppression circuits. Secondary priority was given to analog signals
between the Le78D11 and Le77S11 devices and the FXO circuit, as well as to logic level power
supply traces. Finally, third priority was given to digital interface signals and purely static signals.
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Zarlink Semiconductor Inc.
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Line Module User Guide
Essentially, higher routing priority tends to favor direct traces on a single layer without the use of
vias. Where highest priority could not be accommodated, traces which carry current remained viafree. Vias were employed instead in traces sensing voltage but not carrying any significant level of
current. Where current carrying traces needed vias, large non-inductive vias were used and, where
appropriate, multiple vias (two or more) were used for extra current carrying capability.
6.5.2
Switching Power Supply Routing
Switching power supply routing, the most critical area within the line module’s layout, follows the
layout guidelines discussed in Zarlink application note Layout Considerations for the Le77D112
and Le9502 Devices, document ID# 081013.
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Zarlink Semiconductor Inc.
6.6
6.6.1
A
B
C
D
E
F
G
H
RING1
RING2
J4
MCLK
DXA
FS
IDCS
CS
DCLK
1
8
8
2
4
6
8
10
12
14
16
18
20
2
J3
J2
1
3
5
7
9
11
13
15
17
19
+12V
J1
DS2433
NC
NC
DATA
GND
U3
2
4
6
8
10
12
14
16
18
20
22
24
26
1
2
3
4
2
4
6
8
10
12
14
16
18
20
VPOS
NC
NC
NC
NC
1
3
5
7
9
11
13
15
17
19
21
23
25
8
7
6
5
1
3
5
7
9
11
13
15
17
19
1
J5
PCLK
DRA
DOUT
RS
2
3.3V
TIP1
TIP2
3.3V
C3
0.1uF
C1
0.1uF
7
3.3V
17
29
4
10K
24
10
31
2
22
16
13
18
19
21
20
12
11
14
15
23
C2
0.1uF
R28
Note: DXAPU 10K
3.3V
7
IMT2
VDC2
VB2
VA2
VS2
F2
C12
C22
C32
VIN2
VOUT2
IREF
VREF
CHCLK
IMT1
VDC1
VB1
VA1
VS1
F1
C11
C21
C31
VIN1
VOUT1
Le78D11 TQFP
DGND1
DGND2
AGND1
AGND2
TSCA
MCLK
DCLK
PCLK
FS
DXA
DRA
CS
INT
DIN
DOUT
RS
VCCD
VCCA1
VCCA2
U1
RREF
RDC1
69.8K
RVIN2
100K
VREF
20.0K
3.3V
+
6
7
2
4
44
1
41
38
39
40
43
42
3
8
5
29
10
11
9
13
12
AGND
NC
NC
NC
NC
NC
VCC
AGND
AGND
NC
NC
AGND
FSET
VREF
CHCLK
LPF
IMT
RDC
VHP
CFLT
F
C1
C2
C3
VOUT
VIN
VCC
32
237K
237K
34
32
35
36
37
33
30
31
28
26
27
24
20
22
21
25
CBD1
27nF
TP9 BGND
CNPR1
0.1uF
CHS1
1000pF
TP8 VREG
1
180 Ohm
RBD1
BAV99XCT
DD1
2
3
VPOS
CESR1
0.1uF 200v
NOTE:
3
4
DXAPU 10K is not populated when used with Zarlink
Voice Path Demo Board.
J4, J5 buss-wire jumpers can be cut for
current measurement
U2 can be use for both Le77D11 or Le77S11
Voltage rating on CSW1 and CSW2 must be
greater than VPOS.
Capacitor CESR1 should be located close to
the gate on UT1.
NOTES:
3
NC pin connections on Le77S112 (single channel SLIC)
is made possible for Le77D112 (dual channel SLIC)
use also. Extra traces indicated how to terminated
unused pins.
NOTES:
AGND
AGND
NC
NC
AGND
AGND
NC
NC
VSW
ILS
SD
BGND
NPRFLT
B
A
CHS
23
RSB11
RSB21
VREG
237K
237K
4
CVRG12
0.1uF 200V
RSA11
RSA21
Zarlink Semiconductor Inc.
5
475K
RVS1
Le77S112_eTQFP
U2
LINE_IN_USE_DET
LOOP/911
RING_DET
CID
OFF_HOOK
VIN2
VOUT2
280K
RRAMP
CLPF1
4.7uF
DNP
200pF
eTQFP-44 package (Le77D11) features an
exposed heat slug on the underside which
is thermally tied to a large internal
copper ground plane which acts as a heat
sink.
NOTES:
44
40
42
41
43
5
8
7
6
1
3
38
39
9
33
37
35
36
100K
CIMT1
16
28
34
19
18
17
25
26
27
14
6
32
CHP1
1.5uF
3.3V
15
RIMT1
RVOUT1 CVCC
10K
0.1uF
VREF
5
30
6
REFERENCE DESIGN SCHEMATICS AND BOM
Le71HR0073 Reference Design Schematic
Le71HR0073
ePAD
45
K1
A
A
K1
5
6
7
8
TISP61089BDR
K2
NC
G
K1
UT1
DD3
4148CC-SOT
1
2
3
B
CREG11
1uF 200v
E
2
1
1
1
2
2
+
0.1 5% 1/4W
RLIM1
NOTE:
CSW2
220uF 25v
ES2C
C
QSW1
FZT955/SOT
150 uH
LVREG1
DSW1
LSW1
47uH
50
PTCB1
50
PTCA1
2
CFL11
CSW1
0.1uF 50v
1uF 200v
Date:
Size
C
TP7 VPOS
1uF 200v
CFL12
TIP1
VPOS
RING1
Leming Xu
Thursday, January 29, 2004
Author:
Document Number
Sheet
1
1
of
2
Rev
B
Le71HR0073 1FXS/1FXO Line Module with Le78D11/CPC5621
Note: change on rev. B compare to rev. A:
1. swape between TIP1 and RING1 label to
match the chip A/B name scheme.
Title
1
FXS INTERFACE
On board switcher for Ringing and DC Battery
4
3
2
1
2
A
B
C
D
E
F
G
H
Line Module User Guide
A
B
C
D
E
F
G
H
VOUT2
LOOP/911
VIN2
CID
RING_DET
OFF_HOOK
8
LOOP/911
RRXF
130K
Off-Hook (ACTIVE)
On Hook/Ring Detect (POL. REV.)
RSNP
1.5M
0 (false)
1 (true)
1 (true)
CID (C2)
1 (true)
7
220pF
CSNP+
220pF
RSNP-2
REF
TXF
ZTX
ZNT
TXSL
BRNTS
GAT
NTF
DCS1
DCS2
ZDC
BRPB
RXS
VDDL
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RPB
1.82M
RSNP+1
1.82M
68.1R
60.4K
6
CGAT
100pF
3
RZDC
8.2R
RVDDL
2R
RNTF
RDCS2
1.69M
309K
0.1uF, 100V
CNTS
Please
CDCS
27nF
RNTS
1M
RHTF
143K
RDCS1b
6.49M
RDCS1a
6.49M
RHNT
DNP
RHTX
340K
RNTX
154K
BR+
RZNT
187R
BAT240A
NOTES
TP0
33
4
Zarlink Semiconductor Inc.
5
R29
23.2K
R30 2.55K
Notes: U14 and U15 will replace DB1 for Japan
application.
LINE_IN_USE_DET will cover the
POLARITY and APOH functions
LINE_IN_USE_DET
LINE_IN_USE_DET
3.3V
3.3V
1
2
3
BAT240A
DNP
U14
150
1
2
3
1
1
2
3
4
0.1uF
C63
DNP
8
7
6
5
3
R31 2.55K
5710
VDD
VSS
COUT INCMP
IN+
OUT- OUT+
U5
C62
=> 350V rules, 25mils
Barrier
4
100
8.06Mohm
RLS-2
OV1
SIDACTOR
P3100SC
2
Date:
Size
C
Title
F1
2
429.001 littlefuse 1A
1
RING2
1
Author: Jack Moriarty, Leming Xu
Thursday, January 29, 2004
Sheet
2
Document Number
of
2
Rev
B
Le71HR0073 1FXS/1FXO Line Module with Le78D11/CPC5621
Note: change on rev. B compare to rev. A:
1. move the sensing input from TIP2 to
TIP1A.
2. swape the snoop circuit inputs with
correct polarity.
DC LINE SENSE
Color blocks are for
layout information
RLS-1 8.06Mohm
RLS
210K
RLS+1
8.06Mohm
RLS+2
8.06Mohm
RING2
TIP2A
150
TIP2A
2
DIODE BRIDGE
DB1
TIP2
FXO INTERFACE
A
B
C
D
E
F
G
H
Line Module User Guide
Either DB1 or U14 and U15 will be used.
Footprints may overlap.
BR-
Space to unrelated metal in mils.
RZTX
3.32K
CBR
0.01uF, >350V
3
DNP
U15
*Spacing should be 150mil from green section to fuchsia section.
RGAT
47R
CREF 0.1uF
OFF_HOOK is active low
CID is active low
1.82M
RSNP+2
RSNP-1
RTXF
1001.82M 100
150*
CPC5621
CSNP-
VDDM
TXSM
TXTX+
TX
-MODE
GND
-OH
RING
-CID
RXRX+
SNP+
SNPRXF
RX
IC2
S
Heatpad on all levels from front to back, with maximum via holes.
make pad area as large as possible.
Q1 CPC5602C
D1 2
G
D2 4
1
FXO Line State Table
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1 (true)
0 (false)
RMODE
DNP
CID Control (DISCONNECT)
CFA
0.1uF
CTX0.1uF
RTX
80.6K
CTX1
0.1uF
OFF_HOOK (C1)
TP10
RHA
100K
TP2
RING_DET
RTX1
200K
CVDDM1
0.1uF
RVDDM
10
DAA Line State (Le78D11)
AGND
TP6
TP3
OFF_HOOK
0.22uF
CRX+
TP1
0.22uF
CTX+
CID
TP5
TP4
VIN_FXO
VOUT2
CVDDM
10uF
3.3V
Le71HR0073 Reference Design Schematic (cont.)
Le71HR0073
+
-
6.6.2
CSW2
IC2
U14, U15
U5
F1
QSW1,
DSW1,
DD3
DD1,
J1
J2, J3
LSW1,
LVREG1,
DB1
OV1
Q1
PTCA1, PTCB1
U1
U2
U3
UT1,
J4, J5
TP0,TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8,
TP9, TP10
RLIM1,
RBD1,
RDC1,
RREF
RIMT1, RHA, RVIN2
RRAMP
RVS1,
RSA21, RSB21, RSA11, RSB11
DXAPU, R28, RVOUT1,
RDCS1A,RDCS1B
RDCS2
R29
RGAT
R30, R31
RHNT, RMODE, C63
RHTF
RHTX
RLS
RLS-1,RLS+1,RLS-2,RLS+2
RNTF
RNTS
RNTX
RPB
RRXF
RSNP
RSNP-1,RSNP+1, RSNP-2,RSNP+2
RTX
RTX1
RTXF
RVDDL
RVDDM
RZDC
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
8
59
60
61
62
63
64
65
66
67
68
69
37
9
10
11
12
13
14
Le71HR0073 BOM
Reference Designator
CIMT
CHS1,
CBD1, CDCS
CBR
CGAT
CNTS
CSNP-,CSNP+
CTX+, CRX+
CVDDM
CNPR1,C1,C2,C3,CVCC,CREF,CVDDM1,
C62,CTX1,CTX-,CFA
CVRG12, CESR1,
CHP1,
CLPF1,
CREG11, CFL11,CFL12,
CSW1
0
1
2
3
4
5
6
7
8
Item
1
1
1
1
3
1
1
4
3
2
1
1
1
2
3
1
1
1
4
1
1
1
1
1
1
4
1
1
1
1
1
1
11
1
2
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
2
1
220uF
0.1uF
1.5uF
4.7uF
1uF
0.1uF
0.1uF
200pF
1000pF
27nF
0.01uF
100pF
0.1
220PF
0.22uF
10uF
Value
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP_RES
CHIP RES
CHIP RES
CHIP_RES
CHIP_RES
CHIP_RES
CHIP_RES
CHIP_RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
CHIP RES
test points
0.1
180
20K
69.8K
100K
280K
475K
237K
10K
6.49M
1.69M
23.2K
47
2.55K
DNP
143K
340K
210K
8.06Mohm
309K
1M
154K
68.1
130K
1.5M
1.82M
80.6K
200K
60.4K
2
10
8.2
DNP
LITELINK
ALF BRIDGE SCHOTTKY
LINE MON
1206
1A
transistor
diode
dual diode
dual diode
header
header
inductor
47uH
inductor
150uH
BR_RECT
1A
TRAN SUPP
VAR13
PWR MOS
PTC
50
IC
IC
IC
surge suppressor
dog-born 100 mil
-
aluminum electrolytic
ceramic cap
ceramic cap
tantalum cap
ceramic cap
ceramic cap
ceramic cap
11
2
1
1
3
1
ceramic cap
ceramic cap
ceramic cap
ceramic cap
ceramic cap
ceramic cap
ceramic cap
ceramic cap
ceramic cap
Part Type
1
1
2
1
1
1
2
2
1
Qty
Le71HR0073 Reference Design BOM
34
-
350V
-
600V
5KV
250V
25V
200V
6.3V
6.3V
300V
50V
16V
50V
50V
16V
300V
16V
100V
2000V
10V
10V
Voltage/Wattage
Zarlink Semiconductor Inc.
5%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
5%
5%
1%
-
10%
20%
10%
10%
20%
10%
10%
10%
10%
10%
10%
10%
10%
10%
5% Tol, 1% Match
10%
10%
Tolerance
Le71HR0073
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/4W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/4W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
Wattage
1210
0805
0603
0603
0603
0603
0603
1206
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
1206
0603
0603
0603
0603
0603
0603
1206
0603
0603
0603
0603
0603
0603
44-TQFP
44-eTQFP
8SOIC-208
D008
100mil
DIL
DO-214AA
SOT223
DIP32_SOL
SOT23
SOIC-8
1206
SOT-223
SMB
SOT-23
SOT-23
2.54mm
1.27mm
12.5sq
radial
1206
0805
3216
1825
0805
0603
0603
0603
0603
0805
0603
1206
1808
0603
1206
Package
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SM
X
X
X
X
X
X
TH
Panasonic ERJ_14RSJR10U DigiKey P.10SCT-ND
Panasonic ERJ-6ENF1820
Panasonic ERJ-3EKF2002V
Panasonic ERJ-3EKF6982V
Panasonic ERJ-3EKF1003V
Panasonic ERJ-3EKF2803V
Panasonic ERJ-3EKF4753V
Panasonic ERJ-8ENF2373V
Panasonic ERJ-3EKF1002V
IMS RCI-0603-6494F
IMS RCI-0603-1694F
IMS RCI-0603-2322F
IMS RCI-0603-47R0F
IMS RCI-0603-2551F
IMS RCI-0603-1433F
IMS RCI-0603-3403F
IMS RCI-0603-2103F
IMS RCI-0603-8064F
IMS RCI-0603-3093F
IMS RCI-0603-1004F
IMS RCI-0603-1543F
IMS RCI-0603-68R1F
IMS RCI-0603-1303F
AVX CR10155GT
IMC RCI-1206-1824F
AVX CR10803FT
IMS RCI-0603-2003F
AVX CR10603FT
AVX CR102R0FT
AVX CR10100FT
AVX CR108R2FT
Do not populate
Clare CPC5621
Infineon BAT240A
Clare CPC5710N
Littlefuse 429.001
Zetex FZT955
General Semiconductor ES2C
Fairchild MMBD4148CC
Digi_Key BAV99ZXTR-ND
Samtec SSQ-113-01-S-D
Samtec SMS-110-01-S-D
Cooper Coiltronics DR127-470
Coilcraft 1812LS154X_B
Shindengen S1NB60
Teccor P3100SC
Clare CPC5602C
Asiacom MZ2L-50R
Le78D110VC rev. A2 VoSLAC
Le77S112TC VoSLIC
Dallas Semiconductor DS2433S
Bourns TISP61089BDR
place buss wire between two holes
Nichicon / UPW1E221MPH
GMC31X7R104K200NT
Panasonic ECJ-2YB0J155K
Panasonic ECS-T0JY475R
Tecate CMC300105KX1825T060
Digi-key / PCC 1840CT-ND, 0805
Panasonic ECJ-1VB1C104K
Panasonic ECJ-1VB1H201K
Panasonic ECJ-1VB1H102K
Kemet C0603C273K4RAC
AVX 12067C103KAT1A
Tecate CMC016101KY0603T
Tecate CMC100104KX0603T
Tecate CMC-2K0/221FN1808T#1-10
Tecate CMC010224KY0603T
Tecate CMC010106KX51206T
Vendor / Part Number
Line Module User Guide
Le71HR0073
6.7
Line Module User Guide
LAYOUT PLOTS
Figure 6–2 Component Copper Layer
Confidential Release Under Legerity NDA
Figure 6–3 Ground Plane Layer
Confidential Release Under Legerity NDA
35
Zarlink Semiconductor Inc.
Le71HR0073
Line Module User Guide
Figure 6–4 Power Plane Layer
Confidential Release Under Legerity NDA
Figure 6–5 Solder Copper Layer
Confidential Release Under Legerity NDA
36
Zarlink Semiconductor Inc.