LatticeECP2 Advanced Evaluation Board User's Guide

LatticeECP2™ Advanced Evaluation Board
User’s Guide
January 2009
Revision: EB23_01.6
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Introduction
The LatticeECP2 Advanced Evaluation Board provides a convenient platform to evaluate, test and debug user
designs and IP cores targeted to the LatticeECP2-50 device. The main features of this board are listed below:
• LatticeECP2 FPGA with a 1.2V DC core in a 672-ball fpBGA package (default LatticeECP2-50 FPGA)
• SPI Serial Flash device included for low-cost, non-volatile configuration storage
• Two 64-bit DDR2 SO-DIMM module connectors (DDR2 DIMMs are not included)
• VHDM connectors for SPI4.2 transmit and receive interfaces
• Tri-speed (10/100/1000 Mbit) Ethernet PHY that includes RJ-45, magnetics and spark gap
• Directly wired RJ-45 connector
• Samtec TFM-140-31-S-D-LC connector for interfacing with TI DSP motherboards through the peripheral interface
• RS-232 interface chip and 9-pin D-sub connector
• USB 1.1 transceiver and USB type-A and type-B connectors
• Two 8-bit DIP switches
• Discrete LEDs and 7-segment LED
• Compact Flash connector for type I and type II Compact Flash cards (Compact Flash cards not included)
• LCD module connector (LCD module not included)
• Prototyping areas with access to 103 I/O pins
• Selectable I/O bank voltages
• Four pairs of SMA connectors for high speed differential signals
• Oscillator socket for both half-size and full-size oscillators
• 3.3V, 2.5V, 1.8V, 1.2V and ADJ (adjustable voltage) powers generated from a single 5V to 28V power source
• Power Manager ispPAC®-POWR1220AT8 chip for monitoring 3.3V, 2.5V, 1.8V, 1.2V, ADJ voltages and DDR VREF,
VTT voltages
• Interface for ispVM® System programming support
Also Included:
• 5V/3A AC adapter with international wall plugs
• ispDOWNLOAD® Cable (HW-DL-3C or equivalent)
Additional Resources
Additional resources related to the LatticeECP2 Advanced Evaluation Board (including updated documentation,
and sample programs) can be found at the following URL:
www.latticesemi.com/products/developmenthardware/fpgafspcboards/ecp2advancedevaluationboa.cfm.
Electrical, Mechanical, and Environmental Specifications
The nominal board dimensions are 7.5 inches by 8.5 inches. The environmental specifications are as follows:
• Operating temperature: 0°C to 55°C
• Storage temperature: -40°C to 75°C
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• Humidity: <95% without condensation
• 5V to 28V DC (20 watts max.)
Resources relating to the LatticeECP2 Advanced Evaluation Board can be found at:
www.latticesemi.com/products/developmenthardware/fpgafspcboards/ecp2advancedevaluationboa.cfm
Figure 1. LatticeECP2 Advanced Evaluation Board
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Evaluation Board User’s Guide
Lattice Semiconductor
Features
LatticeECP2 Device
This board features a LatticeECP2 FPGA with a 1.2V DC core in a 672-ball fpBGA package. Any LatticeECP2 density
in this package can be accommodated, though the default density is the LatticeECP2-50. A complete description of
this device can be found in the LatticeECP2 Family Data Sheet on the Lattice web site at www.latticesemi.com.
General Board Functions and Settings
Other than specific functions such as LCD, CF, DDR2 or SPI4.2, the general board functions and their settings are
described in this section.
Power Setup
The board is supplied by a single 5V to 28V DC power supply. On-board regulators will provide the necessary supply voltages. The on-board regulators supply 3.3V, 2.5V, 1.8V, 1.2V, and an adjustable voltage (VCC_ADJ). The
adjustable voltage is set by the potentiometer VR1 and can be set to a value between 1.22V and 3.25V. The DC
power may be applied through the power jack at J54 using an AC adapter with a 5V to 28V DC output range.
Requirements for the power jack are listed in Table 1. Other than using the AC adapter, the DC power may also be
applied using a workbench power supply through the banana jacks at J51 (VCC_IN) and J42 (GND). The workbench power supply voltage has to be between 5V and 28V.
Table 1. Power Jack J54 Specifications
Polarity
Positive Center
Inside Diameter
0.1” (2.5mm)
Outside Diameter
0.218” (5.5mm)
Current Capacity
Up to 4A
Power may also be supplied directly for each individual supply rail using banana jack connectors. To enable this
mode of operation, the appropriate fuses must be removed. All power sources must be regulated to the specifications in Table 2. No special power sequencing is required for the evaluation board.
Table 2. Individual Control of Supplies
Supply
Jack
Fuse
Requirement
3.3V
J49
F5 (3.0A)
+/- 5%
2.5V
J4
F1 (3.0A)
+/- 5%
1.8V
J11
F2 (10.0A)
+/- 5%
1.2V
J17
F3 (3.0A)
+/- 5%
VCC_ADJ
J38
F4 (1.5A)
User-defined
Power Voltage Monitoring
Lattice’s ispPAC Power Manager II device, the ispPAC-POWR1220AT8, is used for monitoring various voltages on
the board. There are six LEDs used to indicate the status of the monitoring voltages. If the monitoring voltage is not
in the +/- 5% voltage window, the corresponding LED will flash; otherwise, the LED will stay ON. Table 3 shows
these six voltages and the corresponding LEDs.
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Table 3. Individual Monitoring of Six Power Voltages
Voltage
LED
Monitoring Voltage Range
3.3V
D5
3.3V +/- 5%
2.5V
D6
2.5V +/- 5%
1.8V
D7
1.8V +/- 5%
1.2V
D8
1.2V +/- 5%
VREF
D9
0.9V +/- 5%
VTT
D10
0.9V +/- 5%
For the VCC_ADJ adjustable voltage, the ispPAC-POWR1220AT8 will detect the voltage rail and show the status
using five LEDs. Each of these five LEDs indicates a particular voltage range. If the VCC_ADJ is in one of the voltage ranges, the corresponding LED will be turned ON and the other LEDs will be turned OFF; otherwise, these five
LEDs will be turned ON and then OFF sequentially so that you will see a light moving between the LEDs. The five
LEDs and corresponding voltages are listed in Table 4.
Table 4. Monitoring of VCC_ADJ Power Voltages
LED
Indicating Voltage Range
D11
3.3V +/- 5%
D12
2.5V +/- 5%
D13
1.8V +/- 5%
D14
1.5V +/- 5%
D15
1.2V +/- 5%
LatticeECP2 I/O Bank Voltage Setting
The jumpers listed in Table 5 allow the user to select the voltage (VCCIO) applied to each of the eight I/O banks of
the LatticeECP2 device. Certain restrictions apply depending on which features of the board are being used.
Table 5. VCCIO Selection Jumper
sysIO™ Bank
Jumper
0
J14
1
J39
2
J40
3
J41
4
J28
7
J27
5
6
Jumper on Pins
1-3 -> VCC_3.3V
2-4 -> VCC_2.5V
3-5 -> VCC_1.8V
4-6 -> VCC_ADJ
Tied to 1.8V
(Cannot be changed)
NA
Depending on the optional devices installed, some sysIO banks may have restrictions. For J14, J27, J28, J39, J40,
and J41, select only one bank voltage position at that jumper. For example, attaching more than one jumper to
J14’s six square pins will short supplies.
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Table 6. sysIO Bank Considerations
Bank
Setting
0
2.5V if Ethernet interface used. 3.3V if TI peripheral interface used.
1
3.3V if LCD, Compact Flash or on-board oscillator used.
2
2.5V if SPI4.2 interface used.
3
2.5V if SPI4.2 interface used.
4
3.3V if USB or RS-232 interfaces used.
5
6
7
Tied to 1.8V (cannot be changed).
Any
The following tables detail the various I/O standards supported by the LatticeECP2 sysIO structures. More information can be found in TN1102, LatticeECP2 sysIO Usage Guide.
Table 7. Mixed Voltage I/O Support
Output sysIO Standards
Input sysIO Standards
VCCIO
1.2V
1.2V
Yes
1.5V
Yes
1.8V
Yes
2.5V
Yes
3.3V
Yes
1.5V
1.8V
Yes
Yes
2.5V
3.3V
1.2V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1.5V
1.8V
2.5V
3.3V
Yes
Yes
Yes
Yes
For example, if VCCIO is 3.3V, signals from devices powered by 1.2V, 2.5V, or 3.3V can be input and the thresholds
will be correct, assuming the user has selected the desired input level using ispLEVER® software. Output levels are
tied directly to VCCIO.
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Table 8. sysIO Standards Supported per Bank
Top Side
Banks 0-1
Description
Right Side
Banks 2-3
Bottom Side
Banks 4-5
Left Side
Banks 6-7
I/O Buffers
Single-ended
Single-ended and
Differential
Single-ended
Single-ended and
Differential
Output Standards
Supported
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL18_I, II
HSTL15 Class I
HSTL18 Class I, II
HSTL15 Class I
HSTL18 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
SSTL18D Class I, II
SSTL25D Class I, II,
SSTL33D Class I, II
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D_I, II
HSTL15D Class I
HSTL18D Class I, II
HSTL15D Class I, II
HSTL18D Class I, II
HSTL15D Class I
HSTL18D Class I, II
HSTL15D Class I
HSTL18D Class I, II
LVDS25E1
LVPECL1
BLVDS1
RSDS1
LVDS
LVDS25E1
LVPECL1
BLVDS1
RSDS1
Inputs
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
Clock Inputs
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
PCI Support
PCI33 without clamp
PCI33 without clamp
PCI33 with clamp
PCI33 without clamp
PCI33 with clamp (ECP2M)
LVDS Output Buffers
PCI33
LVDS25E1
LVPECL1
BLVDS1
RSDS1
LVDS (3.5mA) Buffers2
LVDS
LVDS25E1
LVPECL1
BLVDS1
RSDS1
LVDS (3.5mA) Buffers2
1. These differential standards are implemented by using a complementary LVCMOS driver with external resistor pack.
2. Available only on 50% of the I/Os in the bank.
Prototype Areas
For general purpose I/O testing or monitoring, numerous test points are provided for direct access. The test points
are grouped together and arranged in a grid pattern according to their associated I/O bank and are labeled with the
associated pin locations on the silkscreen of the board. For bank 4 and bank 7, each test point also comes with an
adjacent GND via.
Differential Signal Connections
There are four pairs of SMA connectors and one RJ-45 connector connected directly to the LatticeECP2 differential
I/O pairs.
The eight SMA connectors are provided for clocks or general purpose, user-definable signals. The center pin is
wired to an I/O pin and the outer case is soldered to ground. Table 9 details to which I/O pin each SMA connector
is wired.
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Table 9. SMA Connectors
Location
I/O Ball
Polarity
SysIO Bank
Description
J5
L1
Pair#0 P
7
PL25A / LUM0_SPLLT_IN_A
J6
M2
Pair#0 N
7
PL25B / LUM0_SPLLC_IN_A
J22*
K23*
Pair#1 P
2
RUM0_SPLLT_IN_A / PR25A
J21
J23
Pair#1 N
2
RUM0_SPLLC_IN_A / PR25B
J31
J25
Pair#2 P
2
RUM0_SPLLT_IN_A / PR26A
J32
J26
Pair#2 N
2
RUM0_SPLLC_IN_A / PR26B
J8
H13
Pair#3 P
0
PCLKT0_0 / PT46A
J9
H14
Pair#3 N
0
PCLKC0_0 / PT46B
Note: The SMA connector on J22 is shared with the on-board oscillator. When this SMA connector is used, the jumper on
J18 must be removed.
RJ-45 Connectors
There are two RJ-45 connectors, J1 and J2, on the evaluation board. J1 is a simple RJ-45 female connector provided for general-purpose interfacing to the LatticeECP2 device. J2 is a full-featured Ethernet PHY connection with
internal magnetics and spark gap. The connections for J1 are listed in Table 10. J2 is described in more detail in
the Ethernet section later in this user’s guide.
Table 10. J1 RJ-45 Connections
J1 Pin
I/O Ball
Polarity
sysIO Bank
Description
1
J19
Pair#0 P
2
PR13A
2
K19
Pair#0 N
2
PR13B
3
H22
Pair#1 P
2
PR15A
6
J22
Pair#1 N
2
PR15B
4
L19
Pair#2 P
2
PR17A
5
K20
Pair#2 N
2
PR17B
7
G25
Pair#3 P
2
PR19A
8
G26
Pair#3 N
2
PR19B
Oscillator
The 3.3V oscillator socket (Y2) accepts both full-size and half-size oscillators and can route to different clock
inputs, depending on its position within the socket, see Figure 2. The board is shipped with an EPSON programmable oscillator programmed to 33.33MHz.
The 16-pin socket will allow connection to PLL clock pin K23 when the top of the oscillator is aligned to socket pins
1 and 16. Note that the SMA connector on J22 is shared with the on-board oscillator. When installing the oscillator,
connect the clock to PLL clock pin K23. The SMA connector on J22 cannot be used and the jumper on J18 needs
to be installed.
When the bottom of the oscillator is aligned to socket pins 8 and 9, the clock is provided to primary clock pin D14.
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Figure 2. On-board Oscillator
SPI Serial Flash
SPI Serial Flash are available in three package styles. The device included on this board is an 8-pin, 16 Mbit SPI
Flash, sufficient to store two bitstreams simultaneously in order to support SPIm mode.
Configuration/Programming Headers
Two programming headers are provided on the evaluation board, providing access to the LatticeECP2 JTAG port
and sysCONFIG™ port. The JTAG connector is a 1x10 header and the sysCONFIG connector is a 2x17 header.
The JTAG port also provides loop-through connectors to allow for easy daisy chaining of multiple boards. With
proper jumper selection (see next section) standard IDC ribbon cable can be used without the need to swap any
wires on the cable.
The pinouts for these headers are provided in the following tables.
Note: A parallel port ispDOWNLOAD® cable is included with each LatticeECP2 Advanced board. When using a
parallel port (1x8) ispDOWNLOAD cable, connect pin 1 of the cable to pin 1 of the 1x10 JTAG header.
LatticeECP2 Configuration
Two programming headers, J45 and J46, are provided on the evaluation board, providing access to the
LatticeECP2 JTAG port and the ispPAC-POWR1220AT8 JTAG port. The pinouts for the headers are provided in
Table 11.
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Table 11. JTAG Programming Headers
Jumper on J34 (None on J55)
Pin
1
Jumper on J55 (None on J34)
J45 Function
J46 Function
J45 Function
J46 Function
VCC (3.3V)
VCC (3.3V)
VCC (3.3V)
Not used
2
TDO of ispPAC-POWR1220AT8 TDO of LatticeECP2 TDO of ispPAC-POWR1220AT8
Not used
3
TDI of ispPAC-POWR1220AT8
TDI of LatticeECP2
TDI of LatticeECP2
Not used
4
NC
NC
NC
Not used
5
NC
NC
NC
Not used
6
TMS of both chips
TMS of both chips
TMS of both chips
Not used
7
GND
GND
GND
Not used
8
TCK of ispPAC-POWR1220AT8
TCK of LatticeECP2
TCK of both chips
Not used
9
NC
DONE of LatticeECP2
NC
Not used
10
NC
INITN of LatticeECP2
NC
Not used
J34 and J55 control the functions of the two programming headers. When a jumper is installed on J34, the programming header J45 is connected to the JTAG port of the ispPAC-POWR1220AT8 and is used for programming
the ispPAC-POWR1220AT8 only; the programming header J46 is connected to the JTAG port of LatticeECP2 and
used for programming the LatticeECP2 only.
When the jumper is moved from J34 to J55, the JTAG ports of the LatticeECP2 and ispPAC-POWR1220AT8 are
chained together. In this case, the programming header J45 is connected to the JTAG port of the LatticeECP2 first
and then chained with the JTAG port of ispPAC-POWR1220AT8. The programming header J46 should not be used
when the JTAG ports are chained together.
Table 12. sysCONFIG Header Pinout (J37)
Pin
Function
Function
CCLK
1
2
Ground
BUSY / SISPI
3
4
D6
DI/D0
5
6
VCC_3.3V
D7 / DOUT1
7
8
INITN
DONE
9
10
PROGRAMN
D7
11
12
Ground
D6
13
14
Ground
D5
15
16
Ground
D4
17
18
Ground
D3
19
20
Ground
D2
21
22
Ground
D1
23
24
Ground
1
D0
25
26
Ground
CSN1
27
28
WRITEN
CS1N1
29
30
CFG0
VCC_3.3V
31
32
CFG1
Ground
33
34
CFG2
1. See section below on jumpers
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Switches
The board includes three push-button switches and two 8-bit switches for implementing basic static input functions.
Switches 2, 3 and 4 (SW2, SW3 and SW4) are momentary switches. The pull-up resistors associated with these
switches are wired to 3.3V. Pushing the switches down produces a low (0), otherwise it produces a high (1). The
signals controlled by SW3 and SW4 are debounced by MC14490 (U12) before connecting to an LatticeECP2 I/O
pin. Table 13 shows the control relationship between the switches, LatticeECP2 and ispPAC-POWR1220AT8 I/O
pins.
Table 13. Momentary Switches
SW4
SW3
SW21
Connection
AE20 of LatticeECP2
V19 of LatticeECP2
(PROGRAMN)
Pin 97 of
ispPAC-POWR1220AT81
User-definable
Yes
No
Yes1
Debounced
Yes
Yes
No
1. SW2 signal is also connected (wire-AND) to position#1 of SW1. Therefore, when position#1 of SW1 is in the down position, the SW2 signal
(ispPAC-POWR1220AT8 pin 97) will be low even when SW2 is not being pushed.
Switch 1 and 5 (SW1 and SW5) on the right side and the upper side of the board are 8-pin DIP switches. The pullup resistors associated with these switches are wired to 3.3V. A switch in the down position produces a low (0), the
up position produces a high (1). Same as SW3 and SW4, all signals of SW5 are debounced before connecting to
LatticeECP2 I/O pins. Table 14 shows the SW5 connections to the LatticeECP2 and Table 15 shows the SW1 connections to the ispPAC-POWR1220AT8 I/O pins.
Table 14. 8-Position Switch SW5
Switch (Position#)
LatticeECP2 I/O Ball
sysIO Bank
SW5 (position#1)
W19
4
SW5 (position#2)
AA21
4
SW5 (position#3)
AF24
4
SW5 (position#4)
AE24
4
SW5 (position#5)
Y20
4
SW5 (position#6)
AB22
4
SW5 (position#7)
Y21
4
SW5 (position#8)
AB23
4
Switch (Position#)
ispPAC-POWR1220AT8 I/O Pin
Pin Name
SW1 (position#1)
97
IN1
SW1 (position#2)
1
IN2
SW1 (position#3)
2
IN3
SW1 (position#4)
4
IN4
SW1 (position#5)
6
IN5
Table 15. 8-Position Switch SW1
SW1 (position#6)
7
IN6
SW1 (position#7)
89
VPS0
SW1 (position#8)
90
VPS1
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LEDs
Eight user-definable LEDs are provided on the lower right side of the board. These LEDs are each wired to a separate general purpose I/O as defined in Table 16. The current limiting resistors associated with these LEDs are wired
to 2.5V, but it is safe to use any FPGA I/O voltage. The LED will light when its associated I/O pin is driven low.
Table 16. Connection between LEDs and LatticeECP2
LED
LatticeECP2 I/O Ball
Bank
LED
LatticeECP2 I/O Ball
Bank
D16
AF23
4
D20
AB20
4
D17
AE23
4
D21
AC20
4
D18
AD23
4
D22
AB21
4
D19
AC23
4
D23
AC22
4
Table 17 describes the three LEDs associated with the dedicated programming pins.
Table 17. Programming LEDs
LED
Pin
Color
D24
PROGRAMN
Yellow
D26
INIT
Red
D25
DONE
Green
Function
On when signal is low
On when initializing
On when configuration is complete
7-Segment Display
The 7-segment LED located near the eight LEDs is controlled by the LatticeECP2 bank 4 I/O pins. The connections
of the segments are shown in Figure 3.
Figure 3. 7-Segment Display
LCD Module Connector (LCD Module Not Included)
The LCD module connector (J56) is a 2x9 header. This 18-pin header is compatible with quite a few character LCD
modules. Table 18 shows the pin function of the header and the connections to bank 1 of the LatticeECP2 FPGA.
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Table 18. LCD Header Connection
Pin #
Function
LatticeECP2 I/O Ball
Pin #
Function
LatticeECP2 I/O Ball
1
Anode
—
2
Cathode (GND)
—
3
VSS (GND)
—
4
VDD(5V)
—
5
VO
—
6
RS
B13
7
R/W
A12
8
E
A13
9
DB0
E14
10
DB1
A15
11
DB2
G14
12
DB3
C15
13
DB4
H15
14
DB5
F15
15
DB6
H17
16
DB7
D15
17
Anode
—
18
Cathode (GND)
—
The VR3 potentiometer is used to limit the current that flows through the backlight LED on the LCD module. The
VR2 potentiometer is used to adjust the VO voltage that controls the LCD contrast.
When the following LCD modules are used, connect pin 1 to 16 to the backlight LCD module or connect pin 1 to 14
to the non-backlight LCD module.
• Optrex
– C-51505 Series: 20 characters x 2 lines
When the following LCD modules are used, connect pin 3 to 18 to the backlight LCD module or connect pin 3 to 16
to the non-backlight LCD module.
• Lumex
– LCM-S01601 Series: 16 characters x 1 line
– LCM-S00802 Series: 8 characters x 2 lines
– LCM-S01602 Series: 16 characters x 2 lines
– LCM-S02002 Series: 20 characters x 2 lines
– LCM-S02402 Series: 24 characters x 2 lines
– LCM-S04002 Series: 40 characters x 2 lines
– LCM-S02004 Series: 20 characters x 4 lines
– LCM-S02404 Series: 24 characters x 4 lines
• Varitronix
– MDLS-20189 Series: 20 characters x 1 line
– MDLS-20265 Series: 20 characters x 2 lines
– MDLS-24265 Series: 24 characters x 2 lines
– MDLS-40266 Series: 40 characters x 2 lines
CompactFlash
The CompactFlash connector (J47) on the board accepts both type-I and type-II CompactFlash cards. The connections between the connector pins and the LatticeECP2 I/Os are shown in Table 19. All the pins are connected to
bank 1 I/Os.
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Table 19. CompactFlash Connection
Pin #
Function
1
2
3
4
5
6
LatticeECP2 I/O
Pin #
Function
LatticeECP2 I/O
GND
—
26
CD1
G17
D3
B15
27
D11
B19
D4
A16
28
D12
D19
D5
G15
29
D13
B20
D6
E15
30
D14
B21
D7
D17
31
D15
C19
7
CE1/CS0
C17
32
CE2/CS1
E19
8
A10
B16
33
VS1
A21
9
OE/ATASEL
C18
34
IORD
A22
10
A9
B17
35
IOWR
D20
11
A8
A17
36
WE
C20
12
A7
H18
37
READY/IREQ/INTRQ
B23
13
VCC
—
38
VCC
—
14
A6
F16
39
CSEL
B22
15
A5
G16
40
VS2
E20
16
A4
E16
41
RESET
C22
17
A3
A18
42
WAIT/IORDY
F19
18
A2
B18
43
INPACK/DMARQ
E21
19
A1
D18
44
REG/DMACK
A23
20
A0
E17
45
BVD2/SPKR/DASP
A24
21
D0
A19
46
BVD1/STSCHG/PDIAG
H19
22
D1
A20
47
D8
F20
23
D2
F17
48
D9
J18
24
WP/IOIS16/IOCS16
G19
49
D10
G20
25
CD2
E18
50
GND
—
USB 1.1
To implement the USB interface, the board contains a USB 1.1 transceiver MAX3454EETE (or NCN2500MNR2
from On Semiconductor), a type-A connector and a type-B USB connector.
Table 20. Header Settings for Configuring USB Interface as USB Host
Header/Connector
Jumper Position
Description
J26
Pin 1 and 2
Drive USB transceiver ENUM pin to GND to disconnect the internal 1.5K resistor
between Vtrm and D+ or D-.
J25 (D+)
Pin 1 and 2
Pull D+ signal low through an external 15K resistor.
J23 (D-)
Pin 1 and 2
Pull D- signal low through an external 15K resistor.
J19
Pin 1 and 2
Provide 5V power to the external USB device.
J30 (USB type A)
—
Type A is used while implementing USB host.
J20 (USB type B)
—
This connector is not used in this configuration.
14
LatticeECP2 Advanced
Evaluation Board User’s Guide
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Table 21. Header Settings for Configuring USB Interface as a USB Device
Header/Connector
Jumper Position
Description
J26
Pin 2 and 3
Drive USB transceiver ENUM pin to 3.3V to connect the internal 1.5K resistor
between Vtrm and D+ or D-.
J25 (D+)
Pin 2 and 3
Disconnect D+ signal from the external 15K pull-down.
J23 (D-)
Pin 2 and 3
Disconnect D- signal from the external 15K pull-down.
J19
Pin 2 and 3
No 5V power is provided when implementing USB device.
J30 (USB type A)
—
This connector is not used in this configuration.
J20 (USB type B)
—
Type A is used while implementing USB host.
The connections between the USB 1.1 transceiver MAX3454EETE (or NCN2500MNR2 from On Semiconductor)
and the LatticeECP2 I/O are shown in Table 22.
Table 22. Connections Between USB 1.1 Transceiver and LatticeECP2
Pin #
MAX3454EETE
NCN2500MNR2
LatticeECP2 I/O
Description
1
SPD
DSPD
AB17
Connect to LatticeECP2 bank 4 I/O
2
RCV
RCV
AE13
Connect to LatticeECP2 bank 4 I/O
3
VP
VP
AD15
Connect to LatticeECP2 bank 4 I/O
4
VM
VM
AC15
Connect to LatticeECP2 bank 4 I/O
5
NC
EN_Vobus#
—
Connect to 3.3V
6
GND
GND
—
Connect to GND
7
SUS
SPND
AF13
8
NC
NC
—
9
OE#
OE#
Y15
10
D-
D-
—
Connect to USB connectors through 33 Ohm resistor
Connect to LatticeECP2 bank 4 I/O
No connect
Connect to LatticeECP2 bank 4 I/O
11
D+
D+
—
Connect to USB connectors through 33 Ohm resistor
12
Vtrm
Vreg
—
Connect to GND though a capacitor
13
ENUM
Vobus
—
Connect to J26 pin 2
14
Vbus
Vusb
—
Connect to USB connectors
15
VL
Vcc
—
Connect to 3.3V
16
NC
EN_RPU
—
Connect to J26 pin 2
RS-232
The RS-232 interface on this board includes a RS-232 interface chip (MAX3232), a 9-pin D-sub female connector
and four headers. This RS-232 interface can be configured to DCE or DTE by changing the jumper settings of J10,
J12, J15 and J16 headers. These headers are used to connect the MAX3232 to the D-sub connector. Installing
jumpers on pin 1 and pin 2 of these headers configures the RS-232 to DCE. Installing jumpers on pin 2 and pin 3 of
these headers configures the RS-232 to DTE. The connections and functions of the signals between MAX3232
and LatticeECP2 stay the same for DCE and DTE configurations. They are listed in Table 23.
Table 23. Connections Between MAX3232 and ECP2
Signal Name
MAX3232 Pin
LatticeECP2 I/O Ball
LatticeECP2 Bank
LatticeECP2 I/O
/CTS
9 (R2OUT)
AA19
4
Input
RXD
12 (R1OUT)
W17
4
Input
TXD
11 (T1IN)
Y19
4
Output
/RTS
10 (T2IN)
Y17
4
Output
15
LatticeECP2 Advanced
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Lattice Semiconductor
DDR2
Two 200-pin SODIMM sockets included on the board provide a built-in 64-bit interface to standard 1.8V DDR2
SDRAM memory modules. The required VREF and VTT voltages, as well as termination of each signal to VTT are
provided. Performance has been verified at above the 533Mbps data rate for one module with 1T clocking. The
control lines for both modules are wired to drive as a 2T connection. Expect some reduction in max data rate when
driving two modules with 1T signaling. Write mode dynamic ODT at the memory modules is fully supported, while
read mode ODT at the controller (FPGA) is approximated with external terminations optimized for best performance.
Socket J3 is a reverse orientation version of socket J7. On some boards, the information “2.5V STD 52” is written in
raised-lettering on this socket component. Ignore this marking. This is a 1.8V DDR2 socket. Additionally, please
exercise caution when using DDR2 memory modules in J7 sockets with this marking. It is possible for modules to
physically shift position, which in turn will short Pin 1 to pin 3, shorting VREF to VSS, and shutting down the power
regulator for VTT and VREF. This will not damage the board or memory module, but the DDR2 memory will not
respond when this situation is present.
When using a single DDR2 memory module, use socket J7.
The following memory modules are examples which can be used in the 200-pin SODIMM socket. This list is provided for reference purposes only, and is not intended to be a complete list or endorsement of these products.
• Crucial (Micron) MT8HTF6464HDY (512MB)
• Patriot PSD251253382S (512MB)
• Micron MT8HTF3264HDY (256MB)
• Kingston KVR667D2S5/256
Table 24. DDR2 Interface to SODIMM Sockets
Description
LatticeECP2
I/O Ball
sysIO Bank
J7
(Closer to LatticeECP2)
J3
(Further Away)
DDR2_DQ0
AE12
5
5
5
DDR2_DQ1
AB14
5
7
7
DDR2_DQ2
AA15
5
17
17
DDR2_DQ3
AD14
5
19
19
DDR2_DQ4
W14
5
4
4
DDR2_DQ5
Y14
5
6
6
DDR2_DQ6
AB13
5
14
14
DDR2_DQ7
AF12
5
16
16
DDR2_DM0
AF10
5
10
10
DDR2_DQS0_P
AE11
5
13
13
DDR2_DQS0_N
AB11
5
11
11
DDR2_DQ8
AB15
5
23
23
DDR2_DQ9
Y13
5
25
25
DDR2_DQ10
AF8
5
35
35
DDR2_DQ11
AE8
5
37
37
DDR2_DQ12
AC12
5
20
20
DDR2_DQ13
AD12
5
22
22
DDR2_DQ14
AC14
5
36
36
DDR2_DQ15
AD13
5
38
38
DDR2_DM1
Y12
5
26
26
DDR2_DQS1_P
AC13
5
31
31
16
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 24. DDR2 Interface to SODIMM Sockets (Continued)
Description
LatticeECP2
I/O Ball
DDR2_DQS1_N
AA13
5
29
29
DDR2_DQ16
AB11
5
43
43
DDR2_DQ17
AD8
5
45
45
DDR2_DQ18
AC9
5
55
55
DDR2_DQ19
AA11
5
57
57
DDR2_DQ20
AB9
5
44
44
DDR2_DQ21
AD9
5
46
46
DDR2_DQ22
AB8
5
56
56
DDR2_DQ23
AB10
5
58
58
DDR2_DM2
AC8
5
52
52
sysIO Bank
J7
(Closer to LatticeECP2)
J3
(Further Away)
DDR2_DQS2_P
AE6
5
51
51
DDR2_DQS2_N
AF6
5
49
49
DDR2_DQ24
AE5
5
61
61
DDR2_DQ25
AF5
5
63
63
DDR2_DQ26
AC5
5
73
73
DDR2_DQ27
AD5
5
75
75
DDR2_DQ28
AA7
5
62
62
DDR2_DQ29
AB7
5
64
64
DDR2_DQ30
AD4
5
74
74
DDR2_DQ31
AE4
5
76
76
DDR2_DM3
AF4
5
67
67
DDR2_DQS3_P
AA6
5
70
70
DDR2_DQS3_N
AB6
5
68
68
DDR2_DQ32
W8
6
123
123
DDR2_DQ33
AD3
6
125
125
DDR2_DQ34
W7
6
135
135
DDR2_DQ35
AC2
6
137
137
DDR2_DQ36
AE2
6
124
124
DDR2_DQ37
AD2
6
126
126
DDR2_DQ38
Y7
6
134
134
DDR2_DQ39
Y8
6
136
136
DDR2_DM4
W5
6
130
130
DDR2_DQS4_P
AB3
6
131
131
DDR2_DQS4_N
AB2
6
129
129
DDR2_DQ40
U7
6
141
141
DDR2_DQ41
U6
6
143
143
DDR2_DQ42
U8
6
151
151
DDR2_DQ43
V8
6
153
153
DDR2_DQ44
AA1
6
140
140
DDR2_DQ45
AB1
6
142
142
DDR2_DQ46
Y3
6
152
152
DDR2_DQ47
Y4
6
154
154
DDR2_DM5
U3
6
147
147
DDR2_DQS5_P
W3
6
148
148
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LatticeECP2 Advanced
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Table 24. DDR2 Interface to SODIMM Sockets (Continued)
Description
LatticeECP2
I/O Ball
DDR2_DQS5_N
W4
6
146
146
DDR2_DQ48
T6
6
157
157
DDR2_DQ49
W1
6
159
159
DDR2_DQ50
R5
6
173
173
DDR2_DQ51
Y2
6
175
175
DDR2_DQ52
V2
6
158
158
DDR2_DQ53
W2
6
160
160
DDR2_DQ54
U2
6
174
174
DDR2_DQ55
R4
6
176
176
DDR2_DM6
P3
6
170
170
sysIO Bank
J7
(Closer to LatticeECP2)
J3
(Further Away)
DDR2_DQS6_P
R6
6
169
169
DDR2_DQS6_N
R7
6
167
167
DDR2_DQ56
P6
6
179
179
DDR2_DQ57
V1
6
181
181
DDR2_DQ58
P8
6
189
189
DDR2_DQ59
U1
6
191
191
DDR2_DQ60
P5
6
180
180
DDR2_DQ61
P4
6
182
182
DDR2_DQ62
N5
6
192
192
DDR2_DQ63
P7
6
194
194
DDR2_DM7
N7
6
185
185
DDR2_DQS7_P
T1
6
188
188
DDR2_DQS7_N
T2
6
186
186
DDR2_A0
W6
6
102
102
DDR2_A1
Y6
6
101
101
DDR2_A2
W10
5
100
100
DDR2_A3
Y10
5
99
99
DDR2_A4
W11
5
98
98
DDR2_A5
AA10
5
97
97
DDR2_A6
U4
6
94
94
DDR2_A7
AD10
5
92
92
DDR2_A8
AC10
5
93
93
DDR2_A9
AA12
5
91
91
DDR2_A10
V4
6
105
105
DDR2_A11
W12
5
90
90
DDR2_A12
AB12
5
89
89
DDR2_A13
AF9
5
116
116
DDR_BA0
U5
6
107
107
DDR_BA1
V3
6
106
106
DDR_BA2
AE9
5
85
85
DDR2_CK0_P
V9
5
30
—
DDR2_CK0_N
W9
5
32
—
DDR2_CK1_P
W13
5
164
—
18
LatticeECP2 Advanced
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Table 24. DDR2 Interface to SODIMM Sockets (Continued)
Description
LatticeECP2
I/O Ball
sysIO Bank
J7
(Closer to LatticeECP2)
DDR2_CK1_N
DDR2_CK2_P
J3
(Further Away)
AA14
5
166
—
N3
6
—
30
DDR2_CK2_N
N4
6
—
32
DDR2_CK3_P
AC1
6
—
164
DDR2_CK3_N
AD1
6
—
166
DDR2_CKE0
AE10
5
79
79
DDR2_CKE1
T7
6
80
80
DDR2_S0_N
Y1
6
110
—
DDR2_S1_N
AC7
5
115
—
DDR2_S2_N
V5
6
—
110
DDR2_S3_N
Y5
6
—
115
DDR2_RAS_N
AD7
5
108
108
DDR2_CAS_N
R3
6
113
113
DDR2_WE_N
AA2
6
109
109
DDR2_ODT0
M5
6
114
—
DDR2_ODT1
M4
6
119
—
DDR2_ODT2
AE3
5
—
114
DDR2_ODT3
AC4
5
—
119
DDR2_SDA
C8
0
195
195
DDR2_SCL
D8
0
197
197
SPI 4.2
Two 6x10 VHDM backplane connectors, J35 and J36 are provided for SPI4.2 interfaces. Connector J35 includes
necessary data pairs and control signals for transmit data, while J36 has been configured for receive data. Standard 100-ohm differential termination is provided for all applicable receive signal pairs of J36. The J35 and J36 connections to the LatticeECP2 are listed in Table 25 and Table 26.
Table 25. SPI4.2 Transmit Connections
J35 Pin
Description
LatticeECP2 I/O Ball
sysIO Bank
A1
SPI4_TDAT_P14
P22
3
A2
SPI4_TDAT_P12
M25
3
A3
SPI4_TDAT_P10
K22
2
A4
SPI4_TDAT_P8
J24
2
A7
SPI4_TDAT_P6
F25
2
A8
SPI4_TDAT_P4
G23
2
A9
SPI4_TDAT_P2
C25
2
A10
SPI4_TDAT_P0
C23
2
B1
SPI4_TDAT_N14
P23
3
B2
SPI4_TDAT_N12
M26
3
B3
SPI4_TDAT_N10
L21
2
B4
SPI4_TDAT_N8
K24
2
B7
SPI4_TDAT_N6
F26
2
B8
SPI4_TDAT_N4
G24
2
B9
SPI4_TDAT_N2
D25
2
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Table 25. SPI4.2 Transmit Connections (Continued)
J35 Pin
Description
LatticeECP2 I/O Ball
sysIO Bank
B10
SPI4_TDAT_N0
D23
2
C1
SPI4_TCTL_P
F21
2
C5
SPI4_TSTAT0
M23
2
C6
SPI4_TSCLK
N23
2
D1
SPI4_TCTL_N
E22
2
D5
SPI4_TSTAT1
N24
2
E1
SPI4_TDAT_P15
M22
2
E2
SPI4_TDAT_P13
L25
3
E3
SPI4_TDAT_P11
N25
3
E4
SPI4_TDAT_P9
R19
3
E6
SPI4_TDCLK_P
K25
2
E7
SPI4_TDAT_P7
G22
2
E8
SPI4_TDAT_P5
C26
2
E9
SPI4_TDAT_P3
E25
2
E10
SPI4_TDAT_P1
H25
2
F1
SPI4_TDAT_N15
L22
2
F2
SPI4_TDAT_N13
L26
3
F3
SPI4_TDAT_N11
N26
3
F4
SPI4_TDAT_N9
P20
3
F6
SPI4_TDCLK_N
K26
2
F7
SPI4_TDAT_N7
H21
2
F8
SPI4_TDAT_N5
D26
2
F9
SPI4_TDAT_N3
E26
2
F10
SPI4_TDAT_N1
H26
2
Table 26. SPI4.2 Receive Connections
J36 Pin
Description
LatticeECP2 I/O Ball
sysIO Bank
A1
SPI4_RDAT_P0
R23
3
A2
SPI4_RDAT_P2
T21
3
A3
SPI4_RDAT_P4
R21
3
A4
SPI4_RDAT_P6
T22
3
A7
SPI4_RDAT_P8
U26
3
A8
SPI4_RDAT_P10
Y26
3
A9
SPI4_RDAT_P12
W26
3
A10
SPI4_RDAT_P14
U25
3
B1
SPI4_RDAT_N0
R24
3
B2
SPI4_RDAT_N2
R22
3
B3
SPI4_RDAT_N4
N22
3
B4
SPI4_RDAT_N6
T20
3
B7
SPI4_RDAT_N8
V26
3
B8
SPI4_RDAT_N10
AA26
3
B9
SPI4_RDAT_N12
W25
3
B10
SPI4_RDAT_N14
U24
3
C5
SPI4_RSCLK
M24
2
20
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Table 26. SPI4.2 Receive Connections (Continued)
J36 Pin
Description
LatticeECP2 I/O Ball
sysIO Bank
C6
SPI4_RSTAT0
N21
3
C10
SPI4_RCTL_P
N20
3
D6
SPI4_RSTAT1
N18
3
D10
SPI4_RCTL_N
N19
3
E1
SPI4_RDAT_P1
P19
3
E2
SPI4_RDAT_P3
P25
3
E3
SPI4_RDAT_P5
R25
3
E4
SPI4_RDAT_P7
U20
3
E5
SPI4_RDCLK_P
T26
3
E7
SPI4_RDAT_P9
U23
3
E8
SPI4_RDAT_P11
V25
3
E9
SPI4_RDAT_P13
U19
3
E10
SPI4_RDAT_P15
V23
3
F1
SPI4_RDAT_N1
P21
3
F2
SPI4_RDAT_N3
P26
3
F3
SPI4_RDAT_N5
R26
3
F4
SPI4_RDAT_N7
T19
3
F5
SPI4_RDCLK_N
T25
3
F7
SPI4_RDAT_N9
U22
3
F8
SPI4_RDAT_N11
V24
3
F9
SPI4_RDAT_N13
U21
3
F10
SPI4_RDAT_N15
W24
3
Ethernet PHY
In the upper-left corner of the board is U1, a National Semiconductor Gigabit Ethernet PHY (DP83865). The
LatticeECP2 FPGA interacts with the PHY over a Media Independent Interface (MII). The PHY is connected to an
RJ45 connector J2 on the Media Dependent Interface (MDI). The RJ45 connector J2 has built in magnetics and
spark-gap capacitor.
The PHY is available on the board in order to demonstrate the Lattice Ethernet Media Access (MAC) IP core. However, it is also possible to use the PHY to evaluate a custom MAC solution.
Refer to the schematic and the National Semiconductor DP83865 Data Sheet for detailed information about the
operation of the Ethernet PHY interface on this device. Refer to Table 27 for a description of the Ethernet PHY connections.
Table 27. 10/100/1000 Ethernet PHY Connection Summary
Description
LatticeECP2 I/O
sysIO Bank
ETH_CLK_TO_MAC
C4
0
ETH_COL
B3
0
ETH_CRS
B2
0
ETH_EGP0
(low, install R1 to pull high)
—
ETH_EGP2
G5
0
ETH_EGP4
G6
0
ETH_EGP5
B4
0
ETH_EGP6
D5
0
21
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Table 27. 10/100/1000 Ethernet PHY Connection Summary (Continued)
Description
LatticeECP2 I/O
sysIO Bank
ETH_EGP7
C5
0
ETH_GTX_CLK
E9
0
ETH_MAC_CLK_EN
C3
0
ETH_MDC
F11
0
ETH_MDIO
E10
0
ETH_RESET_N
A4
0
ETH_RX_CLK
A3
0
ETH_RX_D0
E5
0
ETH_RX_D1
E6
0
ETH_RX_D2
F7
0
ETH_RX_D3
E7
0
ETH_RX_D4
G7
0
ETH_RX_D5
G8
0
ETH_RX_D6
C1
0
ETH_RX_D7
C2
0
ETH_RX_DV
D4
0
ETH_RX_ER
D3
0
ETH_TX_CLK
D9
0
ETH_TX_D0
H9
0
ETH_TX_D1
F8
0
ETH_TX_D2
F10
0
ETH_TX_D3
E8
0
ETH_TX_D4
D7
0
ETH_TX_D5
C7
0
ETH_TX_D6
B5
0
ETH_TX_D7
A5
0
ETH_TX_EN
G10
0
ETH_TX_ER
H10
0
TI DSP Motherboard Peripheral Connector
The 80-pin Samtec connector TFM-140-31-S-D-LC installed at the upper-left corner on the bottom side of the
board is used for connecting to the peripheral connector of Texas Instruments DSP motherboards. With this peripheral connector and proper LatticeECP2 FPGA design, the board can be a daughter card for the DSP motherboards. There are two connectors on the DSP motherboard; a memory connector, and a peripheral connector for
attaching daughter cards. The memory connector is an interface (EMIF) used for connecting the DSP to different
types of memory devices. Note that only the peripheral connector is implemented on the LatticeECP2 Advanced
Engineering board. Refer to Table 28 for a description of the peripheral interface connections based on the “Future
Daughtercard Interface” section of the TI’s TMS320 Cross-Platform Daughtercard Specification Revision 1.0.
Table 28. TI DSP Motherboard Peripheral Interface Connection
J57 Pin#
Signal
I/O
Description
1
12V
Vcc
12V voltage supply pin
NC (Connected to TP28)
2
-12V
Vcc
-12V voltage supply pin
NC (Connected to TP34)
3
GND
Vss
System ground
GND
4
GND
Vss
System ground
GND
22
Connection to LatticeECP2
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 28. TI DSP Motherboard Peripheral Interface Connection (Continued)
J57 Pin#
Signal
I/O
5
5V
Vcc
5V voltage supply pin
Description
Connection to LatticeECP2
VCC_5.0V
6
5V
Vcc
5V voltage supply pin
VCC_5.0V
7
GND
Vss
System ground
8
GND
Vss
System ground
9
5V
Vcc
5V voltage supply pin
VCC_5.0V
10
5V
Vcc
5V voltage supply pin
VCC_5.0V
11
N/C
—
Reserved
NC
12
N/C
—
Reserved
NC
13
N/C
—
Reserved
NC
14
N/C
—
Reserved
NC
15
N/C
—
Reserved
NC
16
N/C
—
Reserved
NC
17
N/C
—
Reserved
NC
Reserved
GND
GND
18
N/C
—
19
3.3V
Vcc
3.3V voltage supply pin
VCC_3.3V
NC
20
3.3V
Vcc
3.3V voltage supply pin
VCC_3.3V
21
DC_CLKXb
I/O
Secondary serial port transmit clock
E12
22
DC_CLKSb
I
Secondary serial port clock source
B6
23
DC_FSXb
I/O
Secondary serial port transmit frame sync
B9
24
DC_DXb
O
25
GND
Vss
System ground
GND
26
GND
Vss
System ground
GND
27
DC_CLKRb
I/O
Secondary serial port receive clock
Secondary serial port transmit data
A6
A9
28
N/C
—
Reserved
NC
29
DC_FSRb
I/O
Secondary serial port receive frame sync
H12
30
DC_DRb
I
Secondary serial port receive data
G11
31
GND
Vss
System ground
GND
32
GND
Vss
System ground
GND
33
DC_CLKXa
I/O
Primary serial port transmit clock
G13
34
DC_CLK_Sa
I
Primary serial port clock source
H11
35
DC_FSXa
I/O
Primary serial port frame sync
C10
36
DC_Dxa
O
Primary serial port transmit data
D10
37
GND
Vss
System ground
GND
38
GND
Vss
System ground
GND
39
DC_CLKRa
I/O
Primary serial port receive clock
C12
40
N/C
—
Reserved
NC
41
DC_FSRa
I/O
Primary serial port receive frame sync
B10
42
DC_DRa
I
Primary serial port receive data
F12
43
GND
Vss
System ground
GND
44
GND
Vss
System ground
GND
45
DC_TOUTa
O
Primary timer output
A10
46
DC_TINPa
I
47
N/C
—
48
DC_INTb
I
Primary timer input
B7
Reserved
NC
Secondary interrupt
A7
23
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Table 28. TI DSP Motherboard Peripheral Interface Connection (Continued)
J57 Pin#
Signal
I/O
49
DC_TOUTb
O
Description
50
DC_TINPb
I
51
GND
Vss
System ground
GND
52
GND
Vss
System ground
GND
53
DC_INTa
I
Primary interrupt
D12
54
NC
—
Reserved
NC
55
NC
—
Reserved
NC
56
NC
—
Reserved
NC
57
NC
—
Reserved
NC
58
NC
—
Reserved
NC
59
DC_RESET#
O
System reset
E13
Reserved
Secondary timer output
Secondary timer input
Connection to LatticeECP2
F13
C9
60
NC
—
61
GND
Vss
System ground
GND
NC
62
GND
Vss
System ground
GND
63
DC_CNTLb
O
Daughtercard control
C13
64
DC_CNTLa
O
Daughtercard control
E11
65
DC_STATb
I
Daughtercard status
B11
66
DC_STATa
I
Daughtercard status
B8
67
DC_INTc
I
Third interrupt
A11
68
DC_INTd
I
Fourth interrupt
A8
69
NC
—
Reserved
NC
70
NC
—
Reserved
NC
71
NC
—
Reserved
NC
72
NC
—
Reserved
NC
73
NC
—
Reserved
NC
Reserved
74
NC
—
75
GND
Vss
System ground
GND
NC
76
GND
Vss
System ground
GND
77
GND
Vss
System ground
GND
78
DC_CLKOUT
O
Daughtercard clock
G12
79
GND
Vss
System ground
GND
80
GND
Vss
System ground
GND
24
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Default Jumper Settings
The evaluation board is shipped with default jumper positions as shown in Figure 4. Some jumper settings are
required for bitstream downloading and display functionality.
Figure 4. Default Jumper Settings
Initial Setup and Handling
The following discussion is recommended reading prior to removing the evaluation board from the static shielding
bag and may or may not apply to your particular use of the board.
CAUTION: The devices on the board can be damaged by improper handling.
25
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
The devices on the evaluation board contain fairly robust ESD (Electro Static Discharge) protection structures
within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example
of ESD characterization requirements). Even so, the devices are static sensitive to conditions that exceed their
designed in protection. For example: higher static voltages, as well as lower voltages with lower series resistance
or larger capacitance than the respective ESD specifications require can potentially damage or degrade the
devices on the evaluation board.
As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while handling the evaluation board when it is removed from the static shielding bag. If you will not be using the board for a
while, it’s best to put it back in the static shielding bag. Please save the static shielding bag and packing box for
future storage of the board when it is not in use.
When reaching for the board, it is recommended that you first touch the outside threaded portion of one of the gold
SMA connectors. This will neutralize any static voltage difference between your body and the board prior to any
contact with signal I/O.
CAUTION: To minimize the possibility of ESD damage, the first and last electrical connections to the board, should
always be from test equipment chassis ground to the J42 GND (black banana jack).
Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment
to the J42 GND. Connecting the board ground to test equipment chassis ground will decrease the risk of ESD damage to the I/O on the board as the initial connections to the board are made. Likewise, when unplugging cables
from the evaluation board, the last connection unplugged, should be the chassis GND connection to J42 GND. If
you have signal sources that are floating with respect to chassis GND, attempt to neutralize any static charge on
that signal source prior to attaching it to the evaluation board.
If you are holding or carrying the board while it’s not in a static shielding bag, please keep one finger on the
threaded portion of one of the gold SMA connectors. This will keep the board at the same voltage potential as your
body until you can pick up the static shielding bag and put the board back in it.
Configuring/Programming the Board
Requirements
• PC with Lattice’s ispVM System version 16.0 (or later) programming software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option
to install these drivers is included as part of the ispVM System setup.
ispVM System software can be downloaded from the Lattice web site at www.latticsemi.com/ispvm.
• Any Lattice ispDOWNLOAD Cable (Parallel port or USB) (pDS4102-DL2x, HW7265-DL3x, HW-USB-2x, etc.).
See the ispDOWNLOAD Cables Data Sheet for specifications and instructions for the use of these cables.
For a complete discussion of the LatticeECP2’s configuration and programming options, refer to TN1108,
LatticeECP2 sysCONFIG Usage Guide.
SRAM Configuration Using SPI Flash
The LatticeECP2 device is SRAM-based, so it must remain powered on to retain its configuration when programming the SRAM. The LatticeECP2 SRAM can be configured easily via the on board SPI Flash, which in turn can be
programmed using the JTAG port and ispVM. The on-board SPI Flash retains its programmed bitstreams when
power is off, and can quickly load programmed bitstreams into the LatticeECP2 device when power is applied. The
following steps describe the procedure required to program the SPI Flash device on the board.
1. Check that the jumpers are installed as shown in Figure 4.
2. Connect the ispDOWNLOAD cable to the PC, and to the header on the board at J46. Note: When using a 1x8
download cable, connect to the 1x10 header by justifying the alignment to pin 1 (Vcc).
26
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any
other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device
and render the board inoperable.
3. Connect the LatticeECP2 Evaluation Board to an external 5V supply.
4. Start the ispVM System software.
5. Press the SCAN button located in the toolbar of the ispVM System software. The LatticeECP2 device should
be automatically detected. The resulting screen should be similar to Figure 5.
Figure 5. ispVM System Interface
6. Double-click the device as shown in Figure 5 to open the Device Information Dialog, as shown in Figure 6.
Select the Device Access Options and select SPI Flash Programming as shown in Figure 7.
27
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Figure 6. Device Information Dialog
Figure 7. SPI Serial Flash Device Dialog
7. Select Browse and point to the location of the bitstream file. This example uses the LatticeECP2 Advanced
Evaluation Board sample design bitstream. This is available for download from the Lattice web site at:
www.latticesemi.com/products/developmenthardware/fpgafspcboards/ecp2advancedevaluationboa.cfm.
Select Flash Device and in the Select Device window, change the selections as shown in Figure 8. Press OK
to close the “Select Device” window.
28
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Figure 8. Select Device Dialog
8. Check that the SPI Serial Flash Device window now appears as shown in Figure 9 and press OK to close the
SPI Serial Flash Device window.
Figure 9. SPI Serial Flash Device Dialog
9. Check that the Device Information window appears as shown in Figure 10 and press OK to close the Device
Information window.
29
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
Figure 10. Device Information Dialog
10. Check that the LSC ispVM System window appears as it does in Figure 11.
Figure 11. ispVM System Interface
11. To begin the download of the bitstream into the SPI Flash, press the GO menu button. You will see a small
counter display window start up and then that window will change to a Processing address window. A blue section of that Processing window will start to fill in from the left side until it reaches the right side of the window.
When downloading to SPI Flash is complete, ispVM will then begin to verify the downloaded bitstream loaded
into the SPI Flash with another small processing window and blue bar moving across it.
30
LatticeECP2 Advanced
Evaluation Board User’s Guide
Lattice Semiconductor
12. Upon successful verification of the downloaded bitstream to SPI Flash, the LatticeECP2 device can then be
programmed by pressing the PROGRAMN button (SW3) on the evaluation board.
13. If you have loaded the LatticeECP2 Advanced Evaluation Board sample program, you should now see the
LatticeECP2 evaluation board’s LED digit display incrementing from 0 to 9 and a to f, the digit decimal point
should be blinking, and the LEDs below the digit should show the internal counter state while the digit count is
incrementing.
14. If you cycle the power to the evaluation board, you will need to push the PROGRAMN (SW3) button again to
reload the bitstream from the SPI Flash into the LatticeECP2 device.
Ordering Information
Description
Ordering Part Number
LatticeECP2 Advanced Evaluation Board
(RoHS Compliant)
LFE2-50E-H-EVN
LatticeECP2 Advanced Evaluation Board
(Non-RoHS, Obsolete)
LFE2-50E-H-EV
China RoHS Environment-Friendly
Use Period (EFUP)
10
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: [email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
Change Summary
October 2006
01.0
Initial release.
February 2007
01.1
Updated DDR2 section.
March 2007
01.2
Added Ordering Information section.
April 2007
01.3
Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
June 2007
01.4
Updated DDR2 text section.
October 2007
01.5
Updated Placement and Dimensions schematic in Appendix A.
January 2009
01.6
Updated ordering information.
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
31
32
A
B
C
D
(Sheet 2)
4
5
(Sheet 9,10)
3
4
3
Bank 3
Bank 2
Bank
8
Bank 4
Prototyping
(Sheet 2) Support
USB &
RS-232
Bank 5
Bank 6
ECP2
FPGA
(Sheet 7)
2
Da t e :
S
ize
Size
A
2
D
ocum ent Number
Nu m b e r
Document
Sh e e t
1
1
of
14
B
Re v
Rev
Lattice Semiconductor Corporation
(Sheet 4)
(Sheet 5)
(Sheet 6)
1
LatticeECP2 Advanced Engineering Board 672 fpBGA
Title
Switches &
LEDs
Programming
SPI4.2 Rx
SPI4.2 Tx
LCD &
Compact Flash &
OSC
Bank 1
TI
EMIF
Bank 0
Bank 7
Ethernet
(Sheet 8) (Sheet 7)
DDR2
SDRAM
Support
(Sheet 11) Prototyping
FPGA
Power
Pins
Power
(Sheet 12,13)
5
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Appendix A. Schematics
Figure 12.
A
B
C
P(L1)
N(M2)
J6
SMA Connector AEP 9650-1113-005
S
J5
SMA Connector AEP 9650-1113-005
S
J1
J2
TP103
TP81
TP63
TP54
K6
K7
J3
K4
TP42
TP53
TP31
TP20
J5
J4
TP62
TP52
H1
H2
H3
H4
TP79
TP101
TP102
TP80
H7
J8
G2
G1
TP19
TP11
G4
G3
TP51
TP61
F2
F1
TP78
TP100
H8
J9
TP30
TP41
TP10
TP1
E2
E1
H6
H5
TP77
TP99
E4
E3
TP50
TP60
VCC_1.2V
100
C171
0.01uF
0402
VCC_1.2V
R87
0
5
Run the VCCPLL trace
directly from the 1.2V
power source.
[13]
R89
0
R90
[12]
VCC_3.3V
C172
0.1uF
0402
TP105
TP84
K1
L2
TP104
TP83
LFEC250-fpBGA672
VCCAUX_7
VCCAUX_7
LUM0_VCCPLL
PL26A / LUM0_SPLLT_FB_A
PL26B / LUM0_SPLLC_FB_A
PL25A / LUM0_SPLLT_IN_A
PL25B / LUM0_SPLLC_IN_A
PL24A(H) / LDQS24
PL24B(H)
PL23A
PL23B
PL19A
PL19B
PL18A(H)
PL18B(H)
PL17A
PL17B
PL16A(H) / LDQS16
PL16B(H)
PL15A
PL15B
PL14A(H)
PL14B(H)
PL13A
PL13B
PL12A(H)
PL12B(H)
PL11A
PL11B
PL10A(H)
PL10B(H)
PL9A
PL9B
PL8A(H) / LDQS8
PL8B(H)
PL7A
PL7B
PL6A(H)
PL6B(H)
PL5A
PL5B
DQS Group
DQS Group
VCCIO_7
VCCIO_7
VCCIO_7
VCCIO_7
VCCIO_7
PCLKT7_0 / PL44A
PCLKC7_0 / PL44B
PL43A(H)
PL43B(H)
PL42A
PL42B
LDQS41 / PL41A(H)
PL41B(H)
PL40A
PL40B
PL39A(H)
PL39B(H)
PL38A
PL38B
PL37A(H)
(1 of 10)
TP33
TP14
TP108
TP86
TP22
TP2
M6
N8
R1
R2
M7
N9
J7
F4
L4
M10
M9
TP107
TP85
P1
P2
TP32
TP43
L6
K5
TP21
TP44
TP13
TP12
L8
K8
L7
L5
TP106
N1
9
8
7
6
5
4
3
2
1
D
E
F
G
BANK7
H
J
K
L
M
N
P
4
R
GND
GND
GND
GND
GND
GND
GND
GND
Test Points Array on Component Side
K9
L9
M8
M1
N2
L1
M2
K3
K2
TP64
TP82
Differential Pair Traces
1
1
F6
F5
DQS Group
DQS Group
TP29
TP40
BANK7
PL2A(H) / VREF2_7
PL2B(H) / VREF1_7
C115
0.1uF
0402
1
C116
0.1uF
0402
C117
0.01uF
0402
[11]
10uF Ceramic X5R
0805
2
C173
VCCIO_7
C118
0.01uF
0402
3
3
[3]
USB[0..5]
AE14
AF14
AA16
W15
TP161
TP149
BANK4
LFEC250-fpBGA672
VCCAUX_4
VCCAUX_4
PB64A
PB64B
PB63A
PB63B
PB62A
PB62B
PB61A
PB61B
PB60A / BDQS60
PB60B
PB59A
PB59B
PB58A
PB58B
PB57A
PB57B
PB56A
PB56B
PB55A
PB55B
PB54A
PB54B
PB53A
PB53B
PB52A
PB52B
PB51A / BDQS51
PB51B
PB50A
PB50B
PB49A / PCLKT4_0
PB49B / PCLKC4_0
VCCIO_4
VCCIO_4
VCCIO_4
VCCIO_4
VCCIO_4
VREF2_4 / PB82A
VREF1_4 / PB82B
PB81A
PB81B
PB80A
PB80B
PB79A
PB79B
BDQS78 / PB78A
PB78B
PB77A
PB77B
PB76A
PB76B
PB75A
PB75B
PB74A
PB74B
PB70A
PB70B
BDQS69 / PB69A
PB69B
PB68A
PB68B
PB67A
PB67B
PB66A
PB66B
PB65A
PB65B
(4 of 10)
SEVEN_SEG2
SEVEN_SEG3
SEVEN_SEG4
SEVEN_SEG5
SEVEN_SEG6
SEVEN_SEG7
AD20
AE21
AF21
AF22
AE22
AD22
AC16
AC21
U15
V15
Y18
2
W
AF
AE
AD
AC
AB
AA
Y
14 15 16 17 18 19 20
BANK4
GND
GND
GND
GND
GND
GND
GND
GND
Title
[4]
C137
0.01uF
0402
SWITCH[0..7]
[4]
1
Sheet
Prototyping Support
Document N
umber
Document
Number
2
o
off
14
B
R
ev
Rev
Lattice Semiconductor Corporation
Date:
Size
Size
C
C139
0.1uF
0402
[3]
RS232_[0..3]
LED[0..7] [4]
C141
0.01uF
0402
[11]
10uF Ceramic X5R
0805
2
C129
VCCIO_4
SWITCH6
SWITCH7
SWITCH4
SWITCH5
SWITCH0
SWITCH1
SWITCH2
SWITCH3
Y21
AB23
[4]
SEVEN_SEG[0..7]
GSRN
RS232_2
RS232_3
RS232_0
RS232_1
Y20
AB22
C138
0.1uF
0402
LED6
LED7
1
AF24
AE24
W19
AA21
AB21
AC22
LED4
LED5
LED2
LED3
AD23
AC23
AB20
AC20
LED0
LED1
AF23
AE23
1
TP201
SEVEN_SEG0
SEVEN_SEG1
AA20
W18
RS232_TXD
RS232_RTS_N
RS232_CTS_N
RS232_RXD
AF20
AE20
Y19
Y17
AA19
W17
Test Points Array on Component Side
V16
V17
AF18
AF19
VCC_3.3V
W16
AA17
TP203
TP202
AF17
AE18
TP204
TP190
TP148
TP160
AB19
AE19
AC19
AE17
AC18
AD19
AD17
AD18
Y16
AB18
AE16
AF16
AE15
AF15
AC17
AB16
TP167
TP189
TP177
TP191
TP178
TP183
TP185
TP184
TP158
TP168
TP192
TP205
TP193
TP206
TP179
TP169
AB17
Y15
USB_SPD
USB_OE_N
TP194
TP207
USB4
USB5
AE13
AF13
USB_RCV
USB_SUS
USB2
USB3
AD15
AC15
USB_VP
USB_VM
USB0
USB1
U5D
2
DQS Group
DQS Group
D
1
2
1
2
DQS Group
DQS Group
D2
D1
1
2
1
2
TP76
TP98
1
2
1
2
U5A
1
2
1
4
1
2
1
2
33
2
5
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 13. Prototyping Support
34
A
B
C
[2] RS232_[0..3]
RS232_TXD
RS232_RTS_N
RS232_2
RS232_3
5
R109
RS232_RXD
RS232_1
C144
0.1uF
0402
R102
R105
R103
USB0
USB1
USB2
USB3
USB4
USB5
RS232_CTS_N
USB[0..5]
RS232_0
[2]
0
0
0
0
USB_VP
USB_VM
USB_RCV
USB_SUS
USB_SPD
USB_OE_N
C130
0.1uF
0402
3
4
2
7
1
9
16
13
MAX3454EETE
VP
VM
RCV
SUS (SPND)
SPD (DSPD)
OE#
1
NC (EN_Vobus#)
NC
VTRM (Vreg)
2
VBUS (Vusb)
D+
DGND
C19
0.1uF
0402
LV_RTS_N
LV_TXD
LV_RXD
LV_CTS_N
4
C18
0.1uF
0402
MH2
MH1
GND
D+
DVBUS
J30
6
5
4
3
2
1
R144
R143
C175
1uF Ceramic X5R
0402
33
33
C143
0.1uF
0402
16
1
3
4
5
2
6
11
10
13
8
MAX3232
TSSOP16
VCC
C1+
C1C2+
C2V+
V-
T1IN
T2IN
R1IN
R2IN
U15
GND
T1OUT
T2OUT
R1OUT
R2OUT
Used when the FPGA is
configured as USB host.
USB Series-A Receptacle Molex 67643-2910
14
11
10
6
5
8
12
VCC_3.3V
USB(Type A)
QFN16
15
VL (Vcc)
MAX3454EETE (or NCN2500MNR2)
NC (EN_RPU)
ENUM (VObus)
U7
C132
1uF Ceramic X5R
0402
1
2
VCC_3.3V
4
3
2
1
15
14
7
12
9
1
2
3
2
1
1
2
3
D-
VBUS
J20
HEADER 3
J25
3
3
1
2
3
HV_RXD
RXD Selection
J16
HV_RTS_N
TXD Selection
HV_TXD
HEADER 3
1
2
3
HEADER 3
1
2
3
HV_CTS_N
HEADER 3
J15
HEADER 3
1
2
3
/RTS Selection
J12
/CTS Selection
J10
2
2
1
[13]
1
6
2
7
3
8
4
9
5
11
10
(Female)
RS-232
1
Sheet
USB 1.1 & RS-232
ocument N
Document
Number
D
umber
3
off
o
14
B
Rev
Rev
Lattice Semiconductor Corporation
Date:
Size
Size
C
Title
CONNECTOR DB9 Norcomp 182-009-212-161
J13
Wired as DCE (default) ->
installed Jumpers on pin 1-2 of all headers
Wired as DTE ->
installed Jumpers on pin 2-3 of all headers
Wired as USB Host ->
installed Jumpers on pin 1-2 of all headers
Wired as USB Device ->
installed Jumpers on pin 2-3 of all headers
VCC_5.0V
USB(Type B)
USB Series-B Receptacle Molex 67068-8000
D+
4
HEADER 3
HEADER 3
GND
1
2
3
J19
R142
15K
1
2
3
J23
R120
15K
Used when the FPGA is
configured as USB device.
C176
4.7uF Ceramic X5R
0603
HEADER 3
J26
1
2
[12] VCC_3.3V
1
2
4
3
3
5 MH1
4
6 MH2
D
5
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 14. USB 1.1 and RS-232
A
B
C
D
ON
VCC_3.3V
PROGRAMN
220
220
220
220
220
220
220
220
LED 0603 Green
D23
LED 0603 Green
D22
LED 0603 Green
D21
LED 0603 Green
D20
LED 0603 Green
D19
LED 0603 Green
D18
LED 0603 Green
D17
LED 0603 Green
D16
SW DIP-8 CTS 194-8MST
SW5
5
U11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSEG_B
SSEG_E
SSEG_D
SSEG_DP
SSEG_C
SSEG_G
R166
R171
R170
R169
R168
R167
SSEG_A
R164
SSEG_F
R165
VCC_3.3V
R177
10K
VCC_3.3V
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
SEVEN_SEG1
SEVEN_SEG4
SEVEN_SEG3
SEVEN_SEG7
SEVEN_SEG2
SEVEN_SEG6
SEVEN_SEG0
SEVEN_SEG5
SEVEN_SEG[0..7]
[2]
Installed = Fast Read (0Bx) (default)
Removed = Normal Read (03x)
Note: Not all SPI Serial Flash
support Fast Read
0402
0402
0402
0402
0402
0402
0402
0402
1
2
HEADER 2
J29
VCC
/HOLD
C
D
C191
0.01uF
0402
C190
0.01uF
0402
7
9
1
14
3
12
5
10
7
9
1
14
3
12
5
10
GND
Aout
Bout
Cout
Dout
Eout
Fout
MC14490
GND
Aout
Bout
Cout
Dout
Eout
Fout
VDD
Debouncer
OSCin
OSCout
Ain
Bin
Cin
Din
Ein
Fin
U13
MC14490
OSCin
OSCout
Ain
Bin
Cin
Din
Ein
Fin
TDI
TCK
TMS
TDO
TDI
TCK
TMS
TDO
8
15
2
13
4
11
6
16
8
15
2
13
4
11
6
16
VCC_3.3V
VDD
Debouncer
U12
J46:
JTAG header
for ECP2
J45:
JTAG header
for ispPAC
VCC
TCK
VCC_3.3V
TDO
SWITCH0
SWITCH1
SWITCH2
SWITCH3
SWITCH4
SWITCH5
SWITCH6
SWITCH7
TP171
TP173
TP170
TP172
TMS
ECP2
FPGA
GSRN
TDI
GSRN
4
J16
ATDI
TCK
Gate
SOT-23
VCC_3.3V
VCC_3.3V
Source
Drain
SWITCH[0..7] [2]
VCC_3.3V
TMS
TDO
TDISEL
VCC
FPGA_PROGRAMN
[2]
TDI
ispPAC
HVOUT
Power Supplies
8
7
6
5
(16Mbit)
SPI0_Q
10K
SST25VF016B-50-4C-S2AF
/S
Q
/W
VSS
SPIFASTN
R141
1
2
3
4
U10
SPI Serial Flash
3
R175
Gate
R174
R173
470
470
470
PROGRAM
D24
FPGA_D0
TP164
[4]
TP165
FPGA_DONE
TP166
FPGA_INITN
On when INITN low
D26
LED 0603 Red
INIT
Source
Q13
BSS138LT1
SOT-23
Drain
On when DONE high
D25
LED 0603 Green
DONE
FPGA_PROGRAMN
On when PROGRAMN low
LED 0603 Yellow
VCC_3.3V
R163 10K
FPGA_D7
For chaining ECP2 and
ispPAC together:
(1) Remove the jumper on J34
and install it on J55.
(2) Connect the download
cable to J45.
J14
When TDISEL=0 (J34 short),
ATDI is selected.
When TDISEL=1 (J34 open),
TDI is selected.
CONFIGURATION (2): J34 open and J55 short
J45 => for programming both EC2 and ispPAC (JTAG chained together)
J46 => not used
1
3
4
5
6
7
8
2
(W19) (AA21) (AF24) (AE24) (Y20) (AB22) (Y21) (AB23)
R188
10K
[2]
470
470
470
470
470
470
470
470
3
CONFIGURATION (1): J34 short and J55 open (default setting)
J45 => for ispPAC programming only
J46 => for ECP2 programming only
LED[0..7]
Seven Segment Display Fairchild MAN4710A
738milX386mil
cathode A
cathode F
annode1
NC1
NC2
NC3
cathode E
cathode D
cathode DP
cathode C
cathode G
NC4
cathode B
annode2
DIP_SWITCH0
DIP_SWITCH1
DIP_SWITCH2
DIP_SWITCH3
DIP_SWITCH4
DIP_SWITCH5
DIP_SWITCH6
DIP_SWITCH7
R194 R195 R196 R197 R198 R199 R200 R201
10K
10K
10K
10K
10K
10K
10K
10K
SW3
SW PUSHBUTTON Panasonic EVQP2H02B
SW4
SW PUSHBUTTON Panasonic EVQP2H02B
R45
LED(AC22)
R44
LED(AB21)
R42
LED(AC20)
R40
LED(AB20)
R39
LED(AC23)
R38
LED(AD23)
R37
LED(AE23)
R36
(AD22)
4
7 Segment Display
DP(Pin 9)
(AD20)
(W18)
LED(AF23)
(AE21)
D(Pin 8)
(AE22)
G(Pin 11)
(AA20)
GSRN
(AE20)
[13] VCC_2.5V
(AF21)
(AF22)
F(Pin 2)
A(Pin 1)
B(Pin 13)
C(Pin 10)
5
V22
W23
FPGA_D7
FPGA_D0
1
2
3
2
1
2
3
HEADER 3
J44
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
FPGA_CSSPI1N
CSN
R176
10K
FPGA_D[0..7]
HEADER 3
J43
HEADER 3
1
2
3
VCC_3.3V
CON10
C150
0.1uF
0402 J46
CON10
C32
0.1uF
0402 J45
LFEC250-fpBGA672
XRES
PR77A / CS1N
PR77B / WRITEN
PR76A / D0
PR76B / CSN
PR75A / D2
PR75B / D1
PR74A / D4
PR74B / D3
PR73A / D6 / SPID1
PR73B / D5
PR72A / DI / CSSPI0N
PR72B / D7 / SPID0
JTAG header
for ECP2
J48
FPGA_CCLK
1
2
3
PWR_TMS
HEADER 17X2
J37
CFG2
R193
10K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
FPGA_TCK
FPGA_TMS
FPGA_TDO
FPGA_TDI
PWR_TDI
[12]
CFG1
R192
10K
WRITEN
CFG0
CFG1
CFG2
1
2
3
R202
10K
CFG0
R189
10K
HEADER 2
J55
HEADER 2
1
Sheet
4
of
Program, Switches & LEDs
Document Number
14
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
Title
[12]
J34
FPGA_D6
1
2
1
2
C177
0.1uF
0402
VCC_3.3V
VCC_3.3V
FPGA_PROGRAMN
FPGA_DONE
FPGA_INITN
HEADER 3
J50
VCC_3.3V
R136
10K
R161
4.7K
R135
10K
R203
10K
TDISEL
C170
0.01uF
0402
R134
10K
VCC_3.3V
FPGA_INITN
FPGA_PROGRAMN
HEADER 3
1
2
3
[12]
[12]
[12]
[12]
[12]
J52
PWR_TCK
FPGA_TDO
FPGA_TDI
FPGA_TMS
FPGA_TCK
CFG2
CFG1
CFG0
PWR_TDO
PWR_ATDI
V18
AE25
AA5
AA8
AB4
AC3
AB5
V19
AD25
AB24
AA22
AD24
W20
AC24
TP128
1
sysCONFIG Connector
FPGA_DONE
FPGA_D7
FPGA_D6
FPGA_D5
FPGA_D4
FPGA_D3
FPGA_D2
FPGA_D1
FPGA_D0
CSN
CS1N
VCC_3.3V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
HEADER 3
J53
FPGA_CCLK
FPGA_SISPI
FPGA_CSSPI0N
CS1N
R172
10K
[12]
FPGA_DONE
FPGA_INITN
FPGA_TCK
FPGA_TMS
FPGA_TDO
FPGA_TDI
VCC_3.3V
PWR_TCK
PWR_TMS
PWR_TDO
PWR_ATDI
VCCIO_8
VCCIO_8
TDO
TDI
TMS
TCK
VCCJ
PROGRAMN
DONE
INITN
CCLK
CFG2
CFG1
CFG0
(9 of 10)
PWR_3.3V_10A
PR71A / BUSY / SISPI
PR71B / DOUT/CSON / CSSPI1N
BANK8
U5I
2
JTAG header
for ispPAC
10K 1%
H16
Y22
W21
CS1N
WRITEN
R107
AB25
AC25
CSN
W22
Y23
AC26
AD26
FPGA_D4
FPGA_D3
FPGA_D2
FPGA_D1
AB26
AA25
FPGA_CSSPI0N
FPGA_D7
FPGA_D6
FPGA_D5
Y25
Y24
FPGA_SISPI
FPGA_CSSPI1N
R162 4.7K
C146
0.1uF
0402
VCC_3.3V
1
2
1
2
E(Pin 7)
16
15
14
13
12
11
10
9
35
1
2
3
4
5
6
7
8
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 15. Program, Switches and LEDs
A
B
R108
100
C168
5.6nF
0402
[13] VCC_1.2V
5
[12] VCC_3.3V
C155
0.1uF
0402
SPI4_RDAT_P1
SPI4_RDAT_N1
SPI4_TDAT_P14
SPI4_TDAT_N14
SPI4_RDAT_P4
SPI4_RDAT_N4
SPI4_TDAT_P11
SPI4_TDAT_N11
SPI4_RCTL_P
SPI4_RCTL_N
SPI4_TDAT_P12
SPI4_TDAT_N12
SPI4_RSTAT0
SPI4_RSTAT1
T18
U18
P18
R20
P19
P21
P22
P23
R21
N22
N25
N26
N20
N19
M25
M26
N21
N18
L25
L26
LFEC250-fpBGA672
VCCAUX_3
VCCAUX_3
RLM0_VCCPLL
RLM0_PLLCAP
PR53A
PR53B
PR52A(H)
PR52B(H)
PR51A
PR51B
PR50A(H) / RDQS50
PR50B(H)
PR49A
PR49B
PR48A(H)
PR48B(H)
PR47A / VREF1_3
PR47B / VREF2_3
PR46A(H) / PCLKT3_0
PR46B(H) / PCLKC3_0
BANK3
U5E
DQS Group
SPI4_TDAT_P13
SPI4_TDAT_N13
C24
0.01uF
0402
Run the VCCPLL trace
directly from the 1.2V
power source.
[6]
[6]
100
[6]
[6]
to SPI4.2 Tx
VHDM connector
on Page-06
R111
to SPI4.2 Tx
VHDM connector
on Page-06
100
[6]
[6]
to SPI4.2 Tx
VHDM connector
on Page-06
R124
[6]
[6]
to SPI4.2 Tx
VHDM connector
on Page-06
1
2
1
2
C
DQS Group
PR59A
PR59B
RDQS58 / PR58A(H)
PR58B(H)
PR57A
PR57B
PR56A(H)
PR56B(H)
PR55A
PR55B
PR54A(H)
PR54B(H)
(5 of 10)
VCCIO_3
VCCIO_3
VCCIO_3
VCCIO_3
VCCIO_3
PR70A
PR70B
PR69A(H)
PR69B(H)
PR68A
PR68B
RDSQ67 / PR67A(H)
PR67B(H)
PR66A
PR66B
PR65A(H)
PR65B(H)
RLM0_GPLLT_FB_A / PR64A
RLM0_GPLLC_FB_A / PR64B
RLM0_GPLLT_IN_A / PR63A(H)
RLM0_GPLLC_IN_A / PR63B(H)
RLM0_GDLLT_FB_A / PR61A
RLM0_GDLLC_FB_A / PR61B
RLM0_GDLLT_IN_A / PR60A(H)
RLM0_GDLLC_IN_A / PR60B(H)
DQS Group
D
4
4
SPI4_RDAT_P5
SPI4_RDAT_N5
R25
R26
SPI4_RDAT_P9
SPI4_RDAT_N9
SPI4_RDAT_P8
SPI4_RDAT_N8
SPI4_RDAT_P11
SPI4_RDAT_N11
SPI4_RDAT_P12
SPI4_RDAT_N12
SPI4_RDAT_P13
SPI4_RDAT_N13
SPI4_RDAT_P10
SPI4_RDAT_N10
SPI4_RDAT_P15
SPI4_RDAT_N15
U25
U24
U23
U22
U26
V26
V25
V24
W26
W25
U19
U21
Y26
AA26
V23
W24
C145
0.1uF
0402
1
R126
R33
R114
R131
R119
[6]
[6]
C149
0.1uF
0402
C164
0.01uF
0402
100
100
100
100
100
100
100
100
100
R132
100
100
100
100
100
C165
0.01uF
0402
100
to SPI4.2 Tx
VHDM connector
on Page-06
10uF Ceramic X5R
0805
2
C167
[11]
R129
R133
R125
R35
R128
R130
R127
R34
R123
SPI4_RDCLK_P
SPI4_RDCLK_N
VCCIO_3
SPI4_RDAT_P14
SPI4_RDAT_N14
U20
T19
AA23
R17
R18
T23
V20
SPI4_RDAT_P7
SPI4_RDAT_N7
T26
T25
SPI4_RDAT_P6
SPI4_RDAT_N6
SPI4_RDAT_P2
SPI4_RDAT_N2
T21
R22
T22
T20
SPI4_RDAT_P3
SPI4_RDAT_N3
SPI4_RDAT_P0
SPI4_RDAT_N0
SPI4_TDAT_P9
SPI4_TDAT_N9
P25
P26
R23
R24
R19
P20
1
5
1
2
1
2
1
2
36
2
Rx
3
SPI4_RDAT_N9
SPI4_RDAT_N11
SPI4_RDAT_N13
SPI4_RDAT_N15
TDAT_N9
TDAT_N11
TDAT_N13
TDAT_N15
TDAT_N1
TDAT_N3
TDAT_N5
TDAT_N7
TDCLK_N
SPI4_RDAT_N1
SPI4_RDAT_N3
SPI4_RDAT_N5
SPI4_RDAT_N7
SPI4_RDCLK_N
SPI4_RDAT_P1
SPI4_RDAT_P3
SPI4_RDAT_P5
SPI4_RDAT_P7
SPI4_RDCLK_P
TDAT_P9
TDAT_P11
TDAT_P13
TDAT_P15
TDAT_P1
TDAT_P3
TDAT_P5
TDAT_P7
TDCLK_P
SPI4_RCTL_N
SPI4_RDAT_P9
SPI4_RDAT_P11
SPI4_RDAT_P13
SPI4_RDAT_P15
TSTAT1
TCTL_N
SPI4_RSTAT1
TCTL_P
SPI4_RSCLK
SPI4_RCTL_P
[6]
TDAT_N8
TDAT_N10
TDAT_N12
TDAT_N14
SPI4_RDAT_N8
SPI4_RDAT_N10
SPI4_RDAT_N12
SPI4_RDAT_N14
SPI4_RSTAT0
TDAT_N0
TDAT_N2
TDAT_N4
TDAT_N6
SPI4_RDAT_N0
SPI4_RDAT_N2
SPI4_RDAT_N4
SPI4_RDAT_N6
TSCLK
TSTAT0
TDAT_P8
TDAT_P10
TDAT_P12
TDAT_P14
TDAT_P0
TDAT_P2
TDAT_P4
TDAT_P6
SPI4_RDAT_P8
SPI4_RDAT_P10
SPI4_RDAT_P12
SPI4_RDAT_P14
SPI4_RDAT_P0
SPI4_RDAT_P2
SPI4_RDAT_P4
SPI4_RDAT_P6
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND_L1
GND_L2
GND_L3
GND_L4
GND_L5
GND_L6
GND_L7
GND_L8
GND_L9
GND_L10
GND_K1
GND_K2
GND_K3
GND_K4
GND_K5
GND_K6
GND_K7
GND_K8
GND_K9
GND_K10
GND_J1
GND_J2
GND_J3
GND_J4
GND_J5
GND_J6
GND_J7
GND_J8
GND_J9
GND_J10
GND_H1
GND_H2
GND_H3
GND_H4
GND_H5
GND_H6
GND_H7
GND_H8
GND_H9
GND_H10
GND_G1
GND_G2
GND_G3
GND_G4
GND_G5
GND_G6
GND_G7
GND_G8
GND_G9
GND_G10
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
MOLEX VHDM 74057-1002
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
J36
To LatticeEC FPGA
FPGA
ECP2
Tx
Component Side View
3
2
2
Rx
A10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D10
D1
D2
D3
D4
D5
D6
D7
D8
D9
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
F10
F1
F2
F3
F4
F5
F6
F7
F8
F9
SPI4.2 Rx
Document Number
1
Sheet
5
of
14
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
Title
Component Side View
A1
A2
A3
A4
A5
A6
A7
A8
A9
1
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 16. SPI4.2 Rx
A
B
C
D
GND_L1
GND_L2
GND_L3
GND_L4
GND_L5
GND_L6
GND_L7
GND_L8
GND_L9
GND_L10
GND_K1
GND_K2
GND_K3
GND_K4
GND_K5
GND_K6
GND_K7
GND_K8
GND_K9
GND_K10
GND_J1
GND_J2
GND_J3
GND_J4
GND_J5
GND_J6
GND_J7
GND_J8
GND_J9
GND_J10
GND_H1
GND_H2
GND_H3
GND_H4
GND_H5
GND_H6
GND_H7
GND_H8
GND_H9
GND_H10
GND_G1
GND_G2
GND_G3
GND_G4
GND_G5
GND_G6
GND_G7
GND_G8
GND_G9
GND_G10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
SPI4_TDAT_N14
SPI4_TDAT_N12
SPI4_TDAT_N10
SPI4_TDAT_N8
RDAT_N14
RDAT_N12
RDAT_N10
RDAT_N8
5
Category-5 Cable
Pairing Information:
(1,2), (3,6), (4,5), (7,8)
SPI4_TDAT_P15
SPI4_TDAT_P13
SPI4_TDAT_P11
SPI4_TDAT_P9
SPI4_TDAT_P13
SPI4_TDAT_P11
SPI4_TDAT_P9
SPI4_TSTAT1
SPI4_TDAT_N13
SPI4_TDAT_N11
SPI4_TDAT_N9
RJ45_P1
RJ45_P3
RJ45_P6
RJ45_P7
RJ-45
1
3
5
7
J1
S
1
RJ45_P[1..8]
from
bank 3
on Page-05
from
bank 3
on Page-05
from
bank 3
on Page-05
from
bank 3
on Page-05
4
measurement across CAT-5 cable
(Not an Ethernet Port)
C26
D26
SPI4_TDAT_P5
SPI4_TDAT_N5
C156
0.1uF
0402
RJ45_P7
RJ45_P8
SPI4_TDAT_P6
SPI4_TDAT_N6
RJ45_P5
RJ45_P6
SPI4_TDAT_P3
SPI4_TDAT_N3
RJ45_P3
RJ45_P4
SPI4_TDAT_P4
SPI4_TDAT_N4
K18
L18
L20
G25
G26
F25
F26
L19
K20
E25
E26
H22
J22
G23
G24
J19
K19
E24
F22
C25
D25
TP127
TP123
SPI4_TDAT_P2
SPI4_TDAT_N2
C24
B24
G22
H21
TP134
TP136
SPI4_TDAT_P7
SPI4_TDAT_N7
B25
D24
C23
D23
TP135
TP132
H20
G21
F21
E22
TP121
TP122
RJ45_P1
RJ45_P2
FPGA
ECP2
C157
0.01uF
0402
[13]
[12]
3
VCCIO_2
VCCIO_2
VCCIO_2
VCCIO_2
VCCIO_2
PCLKT2_0 / PR44A
PCLKC2_0 / PR44B
PR43A(H)
PR43B(H)
PR42A
PR42B
RDQS41 / PR41A(H)
PR41B(H)
PR40A
PR40B
PR39A(H)
PR39B(H)
PR38A
PR38B
PR37A(H)
PR37B(H)
RUM0_SPLLT_FB_A / PR26A
RUM0_SPLLC_FB_A / PR26B
RUM0_SPLLT_IN_A / PR25A
RUM0_SPLLC_IN_A / PR25B
RDQS24 / PR24A(H)
PR24B(H)
PR23A
PR23B
(6 of 1 0)
Run the VCCPLL trace
directly from the 1.2V
power source.
VCC_1.2V
VCC_3.3V
LFEC250-fpBGA672
VCCAUX_2
VCCAUX_2
RUM0_VCCPLL
PR19A
PR19B
PR18A(H)
PR18B(H)
PR17A
PR17B
PR16A(H) / RDQS16
PR16B(H)
PR15A
PR15B
PR14A(H)
PR14B(H)
PR13A
PR13B
PR12A(H)
PR12B(H)
PR11A
PR11B
PR10A(H)
PR10B(H)
PR9A
PR9B
PR8A(H) / RDQS8
PR8B(H)
PR7A
PR7B
PR6A(H)
PR6B(H)
PR5A
PR5B
PR2A(H) / VREF1_2
PR2B(H) / VREF2_2
BANK2
U5F
F23
J20
L23
M17
M18
M23
N24
K22
L21
N23
M24
K25
K26
M19
M20
M22
L22
M21
K21
J24
K24
J25
J26
K23
J23
H25
H26
H23
H24
Rx
Tx
0
0
R118
R122
C154
0.1uF
0402
1
C158
0.1uF
0402
10uF Ceramic X5R
0805
2
[5]
C162
0.01uF
0402
SPI4_RSCLK
R121
100
R115
100
[11]
C185
VCCIO_2
SPI4_TSTAT0
SPI4_TSTAT1
SPI4_TDAT_P10
SPI4_TDAT_N10
SPI4_TSCLK
SPI4_RSCLK
SPI4_TDCLK_P
SPI4_TDCLK_N
TP117
TP116
SPI4_TDAT_P15
SPI4_TDAT_N15
TP115
TP118
SPI4_TDAT_P8
SPI4_TDAT_N8
0
0
R116
R113
SPI4_TDAT_P1
SPI4_TDAT_N1
TP120
TP119
Component Side View
Differential Pair Traces
SPI4_TDAT_P0
SPI4_TDAT_N0
SPI4_TCTL_P
SPI4_TCTL_N
Pair#0_N(K19)
Pair#2_P(L19)
Pair#1_N(J22)
Pair#3_N(G26)
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
1
J21
SMA Connector AEP 9650-1113-005
N(J23)
[5]
[5]
S
J22
SMA Connector AEP 9650-1113-005
P(K23)
RJ-45
Connector
RJ-45 Connector for signal quality
2
4
6
8
RJ45_P2
RJ45_P5
RJ45_P4
RJ45_P8
Differential Pair Traces
SPI4_TDCLK_N
RDCLK_N
RDAT_N7
SPI4_TDAT_N7
RDAT_N5
SPI4_TDAT_N5
RDAT_N3
SPI4_TDAT_N3
SPI4_TDAT_N1
RDAT_N1
SPI4_TDAT_N15
SPI4_TDAT_N13
SPI4_TDAT_N11
SPI4_TDAT_N9
RDCLK_P
SPI4_TDCLK_P
SPI4_TDAT_P7
SPI4_TDAT_P5
SPI4_TDAT_P3
SPI4_TDAT_P1
RDAT_N15
RDAT_N13
RDAT_N11
RDAT_N9
RDAT_P7
RDAT_P5
RDAT_P3
RDAT_P1
RDAT_P15
RDAT_P13
RDAT_P11
RDAT_P9
RSTAT1
SPI4_TCTL_N
SPI4_TSTAT0
SPI4_TSCLK
RSTAT0
RSCLK
RCTL_N
SPI4_TCTL_P
SPI4_TDAT_N14
SPI4_TDAT_N12
SPI4_TDAT_P14
SPI4_TDAT_P12
RCTL_P
SPI4_TDAT_N6
SPI4_TDAT_N4
SPI4_TDAT_N2
SPI4_TDAT_N0
SPI4_TDAT_P6
SPI4_TDAT_P4
SPI4_TDAT_P2
SPI4_TDAT_P0
RDAT_P6
RDAT_P4
RDAT_P2
RDAT_P0
RDAT_N6
RDAT_N4
RDAT_N2
RDAT_N0
SPI4_TDAT_P14
SPI4_TDAT_P12
SPI4_TDAT_P10
SPI4_TDAT_P8
RDAT_P14
RDAT_P12
RDAT_P10
RDAT_P8
Pair#0_P(J19)
Pair#1_P(H22)
Pair#2_N(K20)
Pair#3_P(G25)
MOLEX VHDM 74057-1002
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
J35
From LatticeEC FPGA
HEADER 2
1
2
DQS Group
DQS Group
DQS Group
J18
DQS Group
Installing jumper on pin 1 and 2
will connect the on-board
oscillator clock output to the PLL
clock input on ECP2 ball K23.
The pad of Pin 2 is directly
put on the trace of the differential
pair to minimize the trace stub.
No extra trace stub is created on
the differential pair trace.
3
1
2
4
1
2
[7] OSC_PLLCLK
11
12
11
12
1
2
5
1
2
1
2
1
2
37
1
1
P(J25)
Tx
N(J26)
C163
0.01uF
0402
2
J32
SMA Connector AEP 9650-1113-005
S
J31
SMA Connector AEP 9650-1113-005
S
2
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
M
K
H
G
F
E
D
C
B
19 20 21 22 23 24 25
Test Points Array
on Component Side
Component Side View
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
1
Date:
Size
C
Title
SPI4.2 Tx
Document Number
1
Sheet
6
of
14
Lattice Semiconductor Corporation
BANK2
B
Rev
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 17. SPI4.2 Tx
A
B
C
[12]
CF_A06
CF_A05
CF_A04
CF_A03
CF_A02
CF_A01
CF_A00
CF_D00
CF_D01
CF_D02
CF_WP
CF_CD2
CF11
CF12
CF13
CF14
CF15
CF16
CF17
CF18
CF19
CF20
CF21
CF22
5
TI_EMIF12
TI_EMIF9
TI_EMIF10
TI_EMIF11
TI_EMIF6
TI_EMIF7
TI_EMIF8
TI_EMIF5
TI_EMIF3
TI_EMIF4
TI_EMIF2
TI_EMIF0
TI_EMIF1
TP34
VCC_3.3V
VCC_5.0V
CF_D03
CF_D04
CF_D05
CF_D06
CF_D07
CF_CE1
CF_A10
CF_OE
CF_A09
CF_A08
CF_A07
CF0
CF1
CF2
CF3
CF4
CF5
CF6
CF7
CF8
CF9
CF10
CF[0..45]
1
3
VCC_3.3V
J47
Hirose MI20-50PD-SF
GND
CD1
D03
D11
D04
D12
D05
D13
D06
D14
D15
D07
CE1/CE1/CS0 CE2/CE2/CS1
A10
VS1
IORD
OE/OE/ATASEL
A09
IOWR
A08
WE
A07
READY/IREQ/INTRQ
VCC
VCC
A06
CSEL
A05
VS2
A04
RESET
A03
WAIT/WAIT/IORDY
A02 INPACK/INPACK/DMARQ
A01
REG/REG/DMACK
BVD2/SPKR/DASP
A00
D00
BVD1/STSCHG/PDIAG
D01
D08
D02
D09
D10
WP/IOIS16/IOCS16
CD2
GND
PC Card Memory Mode/
PC Card I/O Mode/
True IDE Mode
CF[0..45]
C188
0.1uF
0402
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Samtec TFM-140-31-S-D-LC
-12V
12V
GND
GND
5V
5V
GND
GND
5V
5V
RES
RES
RES
RES
RES
RES
RES
RES
3.3V
3.3V
DC_CLKXb
DC_CLKSb
DC_DXb
DC_FSXb
GND
GND
RES
DC_CLKRb
DC_FSRb
DC_DRb
GND
GND
DC_CLKSa
DC_CLKXa
DC_DXa
DC_FSXa
GND
GND
RES
DC_CLKRa
DC_DRa
DC_FSRa
GND
GND
DC_TINPa
DC_TOUTa
DC_INTb
RES
DC_TINPb
DC_TOUTb
GND
GND
RES
DC_INTa
RES
RES
RES
RES
RES
DC_RESET#
GND
GND
DC_CNTLa
DC_CNTLb
DC_STATa
DC_STATb
DC_INTd
DC_INTc
RES
RES
RES
RES
RES
RES
GND
GND
DC_CLKOUT
GND
GND
GND
J57
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
R180
100K
TI EMIF Peripheral Connector
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
Compact Flash Connector
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
C181
0.1uF
0402
R181
100K
4
R186
100K
R184
100K
R182
47K
R179
47K
2
4
6
8
10
12
14
16
18
R185
47K
R183
47K
LCD_RS
LCD_E
LCD_DB1
LCD_DB3
LCD_DB5
LCD_DB7
R187
100K
LCD5
LCD6
LCD7
LCD8
LCD9
LCD10
R178
100K
CF35
CF36
CF37
CF38
CF39
CF40
CF41
CF42
CF43
CF44
CF45
CF_CSEL
CF_VS2
CF_RESET
CF_WAIT
CF_INPACK
CF_REG
CF_BVD2
CF_BVD1
CF_D08
CF_D09
CF_D10
TI_EMIF25
TI_EMIF26
TI_EMIF27
TI_EMIF24
TI_EMIF23
TI_EMIF22
TI_EMIF21
TI_EMIF19
TI_EMIF20
TI_EMIF17
TI_EMIF18
TI_EMIF15
TI_EMIF16
TI_EMIF13
TI_EMIF14
TP28
CF23
CF24
CF25
CF26
CF27
CF28
CF29
CF30
CF31
CF32
CF33
CF34
CF_CD1
CF_D11
CF_D12
CF_D13
CF_D14
CF_D15
CF_CE2
CF_VS1
CF_IORD
CF_IOWR
CF_WE
CF_READY
TI_EMIF[0..27]
TI EMIF
Connector
Ultra DMA is not supported
Traces from the ECP2 to
the CF connector must
be less than 6 inches
Compact Flash
Connector
CF_BVD1
CF42
VCC_3.3V
CATHODE
VDD
RS
E
DB1
DB3
DB5
DB7
CATHODE
LCD_Connector
ANODE
VSS
VO
R/W
DB0
DB2
DB4
DB6
ANODE
CF_BVD2
CF41
D
1
3
5
7
9
11
13
15
17
CF_VS1
CF30
1
3
J56
CF_VS2
CF36
Contrast
Adjustment
VR2
20K POT Murata PV36Y203C01
PV37W
2
LCD0
LCD_R/W
LCD1
LCD_DB0
LCD2
LCD_DB2
LCD3
LCD_DB4
LCD4
LCD_DB6
CF_INPACK
CF39
Backlight
Adjustment
CF_WP
CF21
VCC_5.0V
CF_READY
CF34
VR3
100 POT Murata PV36Y101C01
PV37W
ANODE
2
CF_WAIT
CF38
VCC_5.0V
CF_CD1
CF23
[13]
CF_CD2
CF22
CF[0..45]
LCD[0..10]
3
LCD_DB0
LCD_DB2
LCD1
LCD2
CF_D07
CF_CE1
CF_A10
CF_OE
CF_A09
CF_A08
CF_A07
CF_A06
CF4
CF5
CF6
CF7
CF8
CF9
CF10
CF11
CF_A03
CF_A02
[12] VCC_3.3V
CF14
CF15
CF_A05
CF_A04
CF_D05
CF_D06
CF2
CF3
CF12
CF13
CF_D03
CF_D04
CF0
CF1
LCD_DB5
LCD_DB7
J16
J17
A18
B18
G16
E16
H18
F16
B17
A17
B16
C18
D17
C17
G15
E15
B15
A16
F15
D15
B14
A14
A15
C15
LCD_DB1
LCD_DB3
LCD7
LCD8
PAC_SDA
PAC_SCL
B13
A13
LCD_RS
LCD_E
LCD5
LCD6
LCD9
LCD10
H15
H17
LCD_DB4
LCD_DB6
LCD3
LCD4
C14
D13
E14
G14
B12
A12
TP109
LCD_R/W
LCD0
TP111
TP110
D14
F14
TP112
LUMEX or Equiv. use pins 3-18
OPTREX 51505 or Equiv. use pins 1-16
LCD Connector
C192
0.1uF
0402
3
LFEC250-fpBGA672
VCCAUX_1
VCCAUX_1
PT64A
PT64B
PT63A
PT63B
PT62A
PT62B
PT61A
PT61B
PT60A
PT60B
PT59A
PT59B
PT58A
PT58B
PT57A
PT57B
PT56A
PT56B
PT55A
PT55B
PT54A
PT54B
PT53A
PT53B
PT52A
PT52B
PT51A
PT51B
PT50A
PT50B
PT49A
PT49B
PT48A / PCLKT1_0
PT48B / PCLKC1_0
BANK1
U5G
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC_3.3V
C147
0.1uF
0402
PT65A
PT65B
2
C148
0.1uF
0402
VCCIO_1
VCCIO_1
VCCIO_1
VCCIO_1
VCCIO_1
VREF1_1 / PT82A
VREF2_1 / PT82B
PT81A
PT81B
PT80A
PT80B
PT79A
PT79B
PT78A
PT78B
PT77A
PT77B
PT76A
PT76B
PT75A
PT75B
PT74A
PT74B
PT71A
PT71B
PT70A
PT70B
PT69A
PT69B
PT68A
PT68B
PT67A
PT67B
PT66A
PT66B
C152
0.01uF
0402
D16
D21
G18
J15
K15
D22
E23
J18
G20
H19
F20
A23
A24
F19
E21
E20
C22
B23
B22
D20
C20
A21
A22
C19
E19
B20
B21
B19
D19
E18
G17
F17
G19
A19
A20
D18
E17
OSC_PCLK
CF16
CF17
CF_D09
CF_D10
F
E
D
C
B
PAC_SDA
PAC_SCL
PAC_SDA
PAC_SCL
I2C interface
[12]
[12]
BANK1
12 13 14 22 23
Test Points Array
on Component Side
1
1
Sheet
7
LCD, CF, TI EMIF & OSC
Document Number
of
14
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
Title
CF[0..45]
10uF Ceramic X5R
0805
2
C183
VCCIO_1
C153
0.01uF
0402
1
CF44
CF45
CF_BVD1
CF_D08
TP113
TP114
CF40
CF41
CF42
CF43
CF_REG
CF_BVD2
CF36
CF37
CF38
CF39
CF_WAIT
CF_INPACK
CF34
CF35
CF_READY
CF_CSEL
CF_VS2
CF_RESET
CF30
CF31
CF32
CF33
CF_VS1
CF_IORD
CF28
CF29
CF26
CF27
CF24
CF25
CF22
CF23
CF20
CF21
CF18
CF19
CF_IOWR
CF_WE
CF_D15
CF_CE2
CF_D13
CF_D14
CF_D11
CF_D12
CF_CD2
CF_CD1
CF_D02
CF_WP
CF_D00
CF_D01
[6]
[11]
OSC_PLLCLK
CF_A01
CF_A00
OSC1(D14)
OSC_PLLCLK
OSC2(K23)
(7 o f 1 0 )
DIPSOC-8x2
Y2
(33.33 MHz OSC Installed)
Oscillator Socket
2
1
2
4
1
5
1
2
1
2
38
2
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 18. LCD, CF, IT EMF and OSC
A
B
C
A3
A4
C3
C4
ETH_RX_CLK
ETH_RESET_N
ETH_MAC_CLK_EN
ETH_CLK_TO_MAC
DDR2_SDA
DDR2_SCL
J10
J11
D5
C5
C56
0.01uF
0402
0.1uF
0402
C64
C65
0.01uF
0402
0.1uF
0402
C62
ETH_EGP[0..7]
LFEC250-fpBGA672
VCCAUX_0
VCCAUX_0
PT23A
PT23B
PT22B
PT10A
PT10B
PT9A
PT9B
PT8A
PT8B
PT7A
PT7B
PT6A
PT6B
PT5A
PT5B
PT4A
PT4B
PT3A
PT3B
1
0.01uF
0402
C63
0.01uF
0402
C66
C67
0.1uF
0402
C78
0.01uF
0402
0.1uF
0402
C74
C79
0.01uF
0402
5
Bypass for IO_VDD pins. Bypass every other
IO_VDD pair, alternating 0.1 and 0.01uF caps.
0.1uF
0402
C59
VCC_2.5V
Bypass for VDD_CORE and VDD pins. Bypass every
other VDD pair, alternating 0.1 and 0.01uF caps.
0.1uF
0402
C55
Place caps close to GPHY
Decoupling Caps
[12] VCC_3.3V
ETH_EGP6
ETH_EGP7
ETH_EGP5
DDR2_SDA
DDR2_SCL
[10,12]
[10,12]
B4
B2
B3
ETH_CRS
ETH_COL
I2C interface
D3
D4
ETH_RX_ER
ETH_RX_DV
ETH_RX_D6 C1
ETH_RX_D7 C2
ETH_RX_D4 G7
ETH_RX_D5 G8
F7
E7
E5
E6
ETH_RX_D2
ETH_RX_D3
ETH_RX_D0
ETH_RX_D1
TI_EMIF4
TI_EMIF5
TI_EMIF6
TI_EMIF7
TI_EMIF8
TI_EMIF9
TI_EMIF10
TI_EMIF11
D10
F12
B7
A7
C9
E11
B8
A8
TI_EMIF20
TI_EMIF21
TI_EMIF22
TI_EMIF23
B10
A10
F13
D12
D11
D6
G9
J12
K12
H13
H14
B11
A11
[13]
0.01uF
0402
C77
4
33
33
33
33
33
[13]
C106
0.1uF
0402
ETH_MDIO
ETH_MDC
R71
ETH_CRS
ETH_COL
PHY_TX_D[0..7]
VCC_2.5V
TI_EMIF[0..27]
C60
10pF
0402
[7]
C109
0.01uF
0402
C112
0.01uF
0402
1
1
33
33
R24
R25
62
60
40
39
79
PHY_TX_EN
PHY_TX_CLK
PHY_CRS
PHY_COL
PHY_GTX_CLK
N(H14)
R52
324
0402
LED 0603 Green
D2
R53
2K
0402
J9
SMA Connector AEP 9650-1113-005
S
R72
2K
0402
X1
X0
61
PHY_TX_ER
R7
1M
0402
76
75
72
71
68
67
66
65
PHY_TX_D0
PHY_TX_D1
PHY_TX_D2
PHY_TX_D3
PHY_TX_D4
PHY_TX_D5
PHY_TX_D6
PHY_TX_D7
3
R50
324
0402
23
27
28
31
32
24
87
86
80
81
57
PHY_RX_CLK
P(H13)
C72
10pF
0402
2K
33
R12
41
PHY_RX_ER
PHY_RX_DV
44
56
55
52
51
50
47
46
45
PHY_RX_D0
PHY_RX_D1
PHY_RX_D2
PHY_RX_D3
PHY_RX_D4
PHY_RX_D5
PHY_RX_D6
PHY_RX_D7
J8
SMA Connector AEP 9650-1113-005
S
to TI EMIF
connector
on Page-07
Place xtal
close to
G-PHY
25MHz
HC-49/U
Y1
Differential
Pair
Traces
R100
100
33
33
33
R23
R22
R13
ETH_RX_ER
ETH_RX_DV
ETH_RX_CLK
Place termination
resistors TX_D0-7,
TX_ER, TX_EN,
GTX_CLK as close to
FPGA as possible
using 50 ohm
impedence traces.
33
33
33
33
33
33
33
33
R14
R15
R16
R17
R18
R19
R20
R21
ETH_RX_D0
ETH_RX_D1
ETH_RX_D2
ETH_RX_D3
ETH_RX_D4
ETH_RX_D5
ETH_RX_D6
ETH_RX_D7
Place R close to CLOCK_IN
PHY_TX_ER
PHY_TX_EN
PHY_TX_D6
PHY_TX_D7
PHY_TX_D4
PHY_TX_D5
PHY_TX_D2
PHY_TX_D3
PHY_TX_D0
PHY_TX_D1
10uF Ceramic X5R
0805
2
VCC_2.5V
1
C111
0
0
Bypass for BG_VDD
0.1uF
0402
C76
C105
0.1uF
0402
R101
R98
TI_EMIF26
TI_EMIF27
TI_EMIF24
TI_EMIF25
TI_EMIF18
TI_EMIF19
E13
C13
TI_EMIF16
TI_EMIF17
H12
G13
TI_EMIF14
TI_EMIF15
C10
C12
B9
A9
TI_EMIF12
TI_EMIF13
TI_EMIF2
TI_EMIF3
G12
E12
TI_EMIF0
TI_EMIF1
B6
A6
DDR2_SDA
DDR2_SCL
ETH_MDIO
ETH_MDC
ETH_TX_CLK
ETH_GTX_CLK R91
ETH_TX_ER R92
ETH_TX_EN R97
ETH_TX_D6 R93
ETH_TX_D7 R95
33
33
33
33
ETH_TX_D2 R74
ETH_TX_D3 R84
ETH_TX_D4 R83
ETH_TX_D5 R85
33
33
ETH_TX_D0 R86
ETH_TX_D1 R88
G11
H11
C8
D8
E10
F11
D9
E9
H10
G10
B5
A5
D7
C7
F10
E8
H9
F8
VCCIO_0
C70
10uF Ceramic X5R
0805
VCC_1.8V
[11]
VCCIO_0
VCCIO_0
VCCIO_0
VCCIO_0
VCCIO_0
PCLKT0_0 / PT46A
PCLKC0_0 / PT46B
PT45A
PT45B
PT44A
PT44B
PT43A
PT43B
PT42A
PT42B
PT41A
PT41B
PT40A
PT40B
PT39A
PT39B
PT38A
PT38B
PT37A
PT37B
PT36A
PT36B
PT35A
PT35B
PT34A
PT34B
PT33A
PT33B
PT32A
PT32B
PT31A
PT31B
PT30A
PT30B
PT29A
PT29B
PT28A
PT28B
PT27A
PT27B
PT26A
PT26B
PT25A
PT25B
PT24A
PT24B
(8 of 10)
Place termination
resistors RX_D0-7,
RX_ER, RX_DV, RX_CLK,
TX_CLK, CRS, COL
as close to the
G-PHY as possible
using 50 ohm impedence
traces.
3
/ RGMII_RXD0
/ RGMII_RXD1
/ RGMII_RXD2
/ RGMII_RXD3
22uF
1
SizeB
0.01uF
1 0402
D1
LED 0603 Green
R51
2K
0402
VCC_2.5V
DP83865
TM0
TMS
TDO
TDI
TRST
TCK
CLOCK_OUT
CLOCK_IN
MDIO
MDC
GTX_CLK / RGMII_TXC
CRS / RGMII_SEL1
COL
TX_CLK / RGMII_SEL0
TX_EN / RGMII_TX_CTL
TX_ER
TXD0 / RGMII_TXD0
TXD1 / RGMII_TXD1
TXD2 / RGMII_TXD2
TXD3 / RGMII_TXD3
TXD4
TXD5
TXD6
TXD7
RX_CLK
RX_DV / RGMII_RXC
RX_ER / RGMII_RX_CTL
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
U1
C57
2
C3
2
C52
2
22uF
1
SizeB
Place these close to G-PHY
101
BG_VDD
98
PGM_VDD0
11
19
25
35
48
63
73
92
R5
R6
10
0402
18
0402
RX_VDD
Giga Phyter
10/100/1000
Giga Phyter V
CORE_VDD1
CORE_VDD2
CORE_VDD3
CORE_VDD4
CORE_VDD5
CORE_VDD6
CORE_VDD7
CORE_VDD8
BAN K0
PT2A / VREF1_0
PT2B / VREF2_0
PHY_GTX_CLK
G5
G6
1
2
2
VCC_1.8V
R65
49_9
0402
R61
49_9
0402
C58
0.01uF
0402
MDID+
MDDCT
MDID-
MDIC+
MDCCT
MDIC-
MDIB+
MDBCT
MDIB-
LED2+
LED2LED1+
LED1-
SHLD1
SHLD2
7
8
4
5
3
6
1
2
16
15
14
13
19
20
2
Place 49 ohm termination resistors as
close as possible to G-PHY.
The associated 0.01uF capacitor should
be placed close to the 49 ohm resistors.
VCC_2.5V
8
7
9
MDIA_BUS6
MDIA_BUS7
J2
MDIA+
MDACT
MDIA-
RJ-45 Belfuse 0826-1A1T-23
3
1
2
MDIA_BUS5
MDIA_BUS4
MDIA_BUS3
MDIA_BUS1
4
6
5
R64
49_9
0402
R60
49_9
0402
MDIA_BUS2
R63
49_9
0402
R59
49_9
0402
11
12
10
R62
49_9
0402
R58
49_9
0402
MDIA_BUS0
C42
0.01uF
0402
MDIA_BUS[0..7]
ETH_EGP[0..7]
RESET_N
85
33
13
14
17
18
95
94
89
88
1
2
3
6
7
8
9
10
ETH_EGP4
ETH_EGP5
ETH_EGP6
ETH_EGP7
ETH_EGP2
ETH_EGP0
R2
2K
0402
R69
470
1
2
0402
R66
470
1
2
0402
ETH_MAC_CLK_EN
C47
0.01uF
0402
MDIA_BUS6
MDIA_BUS7
MDIA_BUS4
MDIA_BUS5
0402
0402
R68
2K
0402
C48
0.01uF
0402
2K
2K
C73
1uF Ceramic X5R
0402
ETH_RESET_N
R73
R67
C51
0.01uF
0402
VCC_2.5V
(Do not
populate)
ETH_MAC_CLK_EN
PULL_UP
VCC_2.5V
R1
2K
0402
R4
2K
0402
R3
324
0402
Date:
Size
C
R56
324
0402
ETH_EGP4
ETH_EGP7
R55
2K
0402
VCC_2.5V
MDI IO traces must be 50 ohm impedence.
Ethernet
Document Number
1
Sheet
8
of
14
B
Rev
Lattice Semiconductor Corporation
ETH_EGP7
MH1 and MH2
are 0.100"
diameter plated
through holes
Title
MH2
MH1
MHOLE_1 MHOLE_1
0.100_PTH 0.100_PTH
Ethernet RJ45 Connector
C43
0.01uF
0402
MDIA_BUS0
MDIA_BUS1
MDIA_BUS2
MDIA_BUS3
ETH_EGP[0..7]
(Do not
populate)
ETH_EGP0
VCC_2.5V
Place caps close to RJ45 jack TX1
R70
33
ETH_RESET_N
1
Place 9.76K resistor as close
to G-PHY as possible
Giga Phyter address = 01h
102
34
84
R57
9.76K 1%
2
1
0402
MDI_P4
MDI_N4
MDI_P3
MDI_N3
120
121
126
127
MDI_P2
MDI_N2
MDI_P1
MDI_N1
114
115
108
109
ETH_CLK_TO_MAC
CLK_TO_MAC
(Hard Reset)
GP0 (PHYAD0 / DUPLEX_LED)
GP1 (PHYAD1)
GP2 (PHYAD2)
GP3 (PHYAD3)
GP4 (PHYAD4)
GP5 (MULTI_EN)
GP6 (MDIX_EN)
GP7 (MAC_CLK_EN)
EGP0 (NC_MODE)
EGP1
EGP2 (Interrupt)
EGP3 (TX_TCLK)
EGP4 (SPEED0 / ACT_LED)
EGP5 (SPEED1 / LINK10)
EGP6 (DUPLEX_EN / LINK100)
EGP7 (AN_EN / LINK1000)
VDD_SEL
REF_SEL
BG_REF
MDID_P
MDID_N
MDIC_P
MDIC_N
MDIB_P
MDIB_N
MDIA_P
MDIA_N
VCC_2.5V
100
103
105
111
117
123
VDD0
RX_DVDD0
VDD1
VDD2
VDD3
VDD4
ETH_RX_D[0..7]
1
ETH_EGP2
ETH_EGP4
1
1
2
2
4
15
21
29
37
42
53
58
69
83
77
90
U5H
1
PULL_DN
ETH_EGP5
96
VDD25_0
IO_VDD1
IO_VDD2
IO_VDD3
IO_VDD4
IO_VDD5
IO_VDD6
IO_VDD7
IO_VDD8
IO_VDD9
O_VDD0
IO_VDD10
IO_VDD11
RJ45
4
1
5
ETH_EGP6
1
2
1
2
D
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
VSS0
PGM_VSS0
IO_VSS1
CORE_VSS1
CORE_VSS2
IO_VSS2
CORE_VSS3
IO_VSS3
CORE_VSS4
IO_VSS4
IO_VSS5
CORE_VSS5
IO_VSS6
IO_VSS7
CORE_VSS6
IO_VSS8
CORE_VSS7
IO_VSS9
O_VSS0
IO_VSS10
CORE_VSS8
IO_VSS11
RX_DVSS0
VSS1
CD_VSS1
CD_VSS2
VSS2
CD2_VSS1
CD2_VSS2
VSS3
CD3_VSS1
CD3_VSS2
VSS4
CD4_VSS1
CD4_VSS2
1
1
2
1
2
2
1
2
1
2
2
1
2
1
2
2
1
2
1
2
1
2
1
2
2
1
2
1
99
97
5
12
20
16
26
22
36
30
38
49
43
54
64
59
74
70
82
78
93
91
104
106
107
110
112
113
116
118
119
122
124
125
128
2
1
2
2
1
2
1
2
39
1
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 19. Ethernet
A
B
C69
0.1uF
0402
VREF
DDR2_DQ31
DDR2_DM3
[10]
[10]
DDR2_DQ16
[10]
[10] SODIMM_ODT2
[10] SODIMM_S2_N
[10] SODIMM_A10
[10] SODIMM_A0
[10] SODIMM_ODT1
[10]
[10] SODIMM_ODT3
[10] SODIMM_S1_N
SODIMM_CAS_N
33 741X083
RN37
C140
220uF
SizeD
5
RN8
1
2
3
4
RN15
1
2
3
4
22
22
AE5
AF5
AA7
AB7
AC5
AD5
AA6
AB6
V9
W9
741X083
DDR2_ODT2
8
DDR2_S2_N
7
DDR2_A10
6
DDR2_A0
5
741X083
DDR2_ODT1
8
DDR2_ODT3
7
DDR2_S1_N
6
DDR2_CAS_N
5
[13]
33 741X083
RN33
C90
0.01uF
0402
[10] SODIMM_BA2
[10] SODIMM_CKE1
[10] SODIMM_CKE0
[10]
[10]
[10] SODIMM_A13
SODIMM_ODT0
[10] SODIMM_S0_N
[10] SODIMM_RAS_N
C193
0.001uF
0402
LFEC250-fpBGA672
VCCAUX_5
VCCAUX_5
PB27A
PB27B
PB26A
PB26B
PB25A
PB25B
PB24A / BDSQ24
PB24B
PB23A
PB23B
PB22A
PB22B
PB21A
PB21B
PB20A
PB20B
PB10A
PB10B
PB9A
PB9B
PB8A
PB8B
PB7A
PB7B
PB6A / BDSQ6
PB6B
PB5A
PB5B
PB4A
PB4B
PB3A
PB3B
PB2A / VREF2_5
PB2B / VREF1_5
BANK5
U5C
C194
0.001uF
0402
V10
V11
Y11
AB11
AB9
AD9
AA11
AC9
AE6
AF6
AB8
AB10
C189
0.1uF
0402
VCC_1.8V
W11
AA10
DDR2_A4
DDR2_A5
AC8
AD8
W10
Y10
DDR2_A2
DDR2_A3
DDR2_S1_N AC7
DDR2_RAS_N AD7
VTT
33 741X083
RN34
VTT
DDR2_DQ20
DDR2_DQ21
[10]
[10]
DDR2_ODT3
AE4
AF4
AE3
AF3
AC4
AD4
DDR2_ODT2
VCC_3.3V
DDR2_DQ19
DDR2_DQ18
[10]
[10]
DDR2_DQS2_P
DDR2_DQS2_N
DDR2_DQ22
DDR2_DQ23
[10]
[10]
[10]
[10]
DDR2_DM2
DDR2_DQ17
DDR2_DQ28
DDR2_DQ29
DDR2_DQ24
DDR2_DQ25
[10]
[10]
[10]
[10]
[10]
[10]
DDR2_DQ26
DDR2_DQ27
DDR2_DQS3_P
DDR2_DQS3_N
[10]
[10]
[10]
[10]
[10]DDR2_CK0_P
[10]DDR2_CK0_N
DDR2_DQ30
[10]
[13]
(Left end of VTT island)
1
2
C
VREF
1
2
D
1
2
3
4
8
7
6
5
1
2
5
1
2
3
4
8
7
6
5
1
2
DQS Group
DQS Group
1
2
4
C91
0.01uF
0402
DDR2_A9
DDR2_A11
DDR2_A12
AA12
W12
AB12
Y12
4
741X083 22
8
7
6
5
RN7
1
2
3
4
DDR2_BA2
DDR2_CKE1
DDR2_CKE0
741X083
DDR2_A13
8
DDR2_ODT0
7
DDR2_S0_N
6
DDR2_RAS_N
5
RN19
1
2
3
4
22
[13]
VCC_1.2V
C68
0.1uF
0402
VREF
DDR2_DQ62
DDR2_DQ63
DDR2_CK2_P
DDR2_CK2_N
DDR2_DM7
DDR2_DQ59
DDR2_DQ57
[10]
[10]
DDR2_DQ46
DDR2_DQ47
DDR2_DM5
DDR2_DQ49
DDR2_DQ51
DDR2_DQ43
DDR2_DQ41
DDR2_DQ42
DDR2_DQ40
DDR2_DQ44
DDR2_DQ45
[13]
C23
0.01uF
0402
VCC_3.3V
C89
0.1uF
0402
[10]
[10] SODIMM_A8
[10] SODIMM_A9
SODIMM_A12
[10] SODIMM_A5
[10] SODIMM_A6
[10] SODIMM_A7
[10] SODIMM_A11
33 741X083
RN39
3
DDR2_A10
DDR2_S2_N
DDR2_BA1
DDR2_BA0
DDR2_A6
VCC_1.8V
DDR2_CKE1
741X083 22
8
7
6
5
RN18
1
2
3
4
C107
5.6nF
0402
VCC_3.3V
BANK6
C195
0.001uF
0402
LFEC250-fpBGA672
VCCAUX_6
VCCAUX_6
LLM0_VCCPLL
LLM0_PLLCAP
PL70A
PL70B
PL69A(H)
PL69B(H)
PL68A
PL68B
PL67A(H) / LDQS67
PL67B(H)
PL66A
PL66B
PL65A(H)
PL65B(H)
C196
0.001uF
0402
PL64A / LLM0_GPLLT_FB_A
PL64B / LLM0_GPLLC_FB_A
PL63A(H) / LLM0_GPLLT_IN_A
PL63B(H) / LLM0_GPLLC_IN_A
PL61A / LLM0_GDLLT_FB_A
PL61B / LLM0_GDLLC_FB_A
PL60A(H) / LLM0_GDLLT_IN_A
PL60B(H) / LLM0_GDLLC_IN_A
PL59A
PL59B
PL58A(H) / LDQS58
PL58B(H)
PL57A
PL57B
PL56A(H)
PL56B(H)
PL55A
PL55B
PL54A(H)
PL54B(H)
PL53A
PL53B
PL52A(H)
PL52B(H)
PL51A
PL51B
PL50A(H) / LDQS50
PL50B(H)
PL49A
PL49B
PL48A(H)
PL48B(H)
PL47A / VREF2_6
PL47B / VREF1_6
PL46A(H) / PCLKT6_0
PL46B(H) / PCLKC6_0
DDR2_A8
DDR2_A9
DDR2_A12
SODIMM_BA0
SODIMM_BA1
[10]
[10] SODIMM_S3_N
SODIMM_WE_N
[10] SODIMM_A2
[10] SODIMM_A4
[10] SODIMM_A1
[10] SODIMM_A3
33 741X083
RN35
All the 741X083 devices
on this page with 22 ohm
value tied to FPGA, should
be placed physically near
the FPGA.
C33
0.1uF
0402
T9
U9
R8
T8
V8
U6
U8
U7
AA1
AB1
W3
W4
Y3
Y4
V4
V5
V3
U5
U3
U4
T5
T7
741X083
DDR2_A5
8
DDR2_A6
7
DDR2_A7
6
DDR2_A11
5
RN20
1
2
3
4
22
33 741X083
RN36
VTT
W1
Y2
R6
R7
T6
R5
V2
W2
R4
U2
P3
R3
U1
V1
P5
P4
P8
P6
T1
T2
N5
P7
N3
N4
N7
P9
U5B
DQS Group
M4
M5
DDR2_S0_N
Y1
DDR2_WE_N AA2
DDR2_CAS_N
DDR2_ODT1
DDR2_ODT0
Run the VCCPLL trace
directly from the 1.2V
power source.
[10]
[10]
[10]
[10]
[10]
[10]
DDR2_DQS5_P
DDR2_DQS5_N
[10]
[10]
[10]
[10]
[10]
DDR2_DQ48
DDR2_DQ50
DDR2_DQ52
DDR2_DQ53
DDR2_DQ55
DDR2_DQ54
DDR2_DQS6_P
DDR2_DQS6_N
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
DDR2_DM6
[10]
[10]
[10]
DDR2_DQ60
DDR2_DQ61
[10]
[10]
DDR2_DQ58
DDR2_DQ56
DDR2_DQS7_P
DDR2_DQS7_N
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
VCC_1.2V
3
2
W6
W5
741X083 22
8
7
6
5
RN17
1
2
3
4
C95
0.1uF
0402
DDR2_S3_N
DDR2_WE_N
DDR2_BA0
DDR2_BA1
DMx: data mask
DQx: data
DQSx: data strobe diff pair
CKx: clock x diff pair
SCL: clock
SDA: data
SA: address
VDDSPD: power
Date:
Size
C
Title
1
Sheet
DDR2 SDRAM FPGA
Document Number
9
of
ODTx: On die termination enable
CAS: Column select
RAS: Row select
WE: Write enable
CKEx: clock enable
Sx: SODIMM select
BAx: bank address
Ax: address
1
Lattice Semiconductor Corporation
On die
terms
SODIMM
EEPROM
External
SSTL_18
terms
C87
10uF Ceramic X5R
0805
[13]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
VCC_1.8V
DDR2_DQ35
DDR2_DQ33
DDR2_DQ38
DDR2_DQ39
DDR2_DQ34
DDR2_DQ32
[10]
[10]
[10]
[10]
[10]
DDR2_DQS4_P
DDR2_DQS4_N
DDR2_DQ36
DDR2_DQ37
DDR2_CK3_P
DDR2_CK3_N
DDR2_DM4
VCC_1.8V
DDR2_A1
DDR2_S3_N
DDR2_A0
741X083
DDR2_A2
8
DDR2_A4
7
DDR2_A1
6
DDR2_A3
5
RN16
1
2
3
4
22
C94
0.1uF
0402
R10
AA4
R9
V7
T4
AC2
AD3
Y7
Y8
W7
W8
AB3
AB2
AE2
AD2
Y6
Y5
AC1
AD1
33 741X083
RN38
VTT
C93
0.01uF
0402
VCCIO_6
VCCIO_6
VCCIO_6
VCCIO_6
VCCIO_6
PL78A
PL78B
PL77A(H)
PL77B(H)
PL76A
PL76B
LDQS75 / PL75A(H)
PL75B(H)
PL74A
PL74B
PL73A(H)
PL73B(H)
PL72A
PL72B
PL71A(H)
PL71B(H)
(2 of 10)
C92
0.01uF
0402
2
1
1
2
Smaller value caps should be placed
directly under the ECP2 device. Larger
value caps can be placed further out.
DDR2_DQ0 [10]
DDR2_DQ7 [10]
C86
10uF Ceramic X5R
0805
33 741X083
RN40
[10]
[10]
DDR2_DQ3 [10]
DDR2_DQ2 [10]
DDR2_DQS0_P
DDR2_DQS0_N
C97
0.1uF
0402
VTT
[10]
[10]
[10]
DDR2_DQ5 [10]
DDR2_DQ1 [10]
DDR2_DQ4
DDR2_DQ6
DDR2_DM0
VCC_1.8V
DDR2_CKE0
[10]
[10]
[10]
[10]
[10]
[10]
DDR2_CK1_P [10]
DDR2_CK1_N [10]
DDR2_DQ8
DDR2_DQ9
DDR2_DQ11
DDR2_DQ10
DDR2_DQ15
DDR2_DQ14
[10]
[10]
[10]
[10]
[10]
DDR2_DQS1_P
DDR2_DQS1_N
DDR2_DQ13
DDR2_DQ12
DDR2_DM1
AC11
AC6
U12
V12
Y9
AE12
AF12
AD14
AA15
AE11
AF11
Y14
AB14
W14
AB13
AE10
AF10
W13
AA14
AE9
AF9
AB15
Y13
AE8
AF8
AD13
AC14
AC13
AA13
DDR2_BA2
DDR2_A13
DDR2_A8
DDR2_A7
AD12
AC12
VCC_1.8V
VCC_1.8V
AE7
AF7
AC10
AD10
All the 741X083 devices
on this page with 33 ohm
value tied to VTT, should
be placed near and after
the 2nd DDR2 DIMM
socket (the one furthest
from the FPGA).
C96
0.1uF
0402
VCCIO_5
VCCIO_5
VCCIO_5
VCCIO_5
VCCIO_5
PCLKT5_0 / PB44A
PCLKC5_0 / PB44B
PB43A
PB43B
BDQS42 / PB42A
PB42B
PB41A
PB41B
PB40A
PB40B
PB39A
PB39B
PB38A
PB38B
PB37A
PB37B
PB36A
PB36B
PB35A
PB35B
PB34A
PB34B
BDQS33 / PB33A
PB33B
PB32A
PB32B
PB31A
PB31B
PB30A
PB30B
PB29A
PB29B
PB28A
PB28B
(3 of 10)
DQS Group
DQS Group
1
1
2
3
4
8
7
6
5
2
1
1
2
1
2
3
4
2
1
2
3
4
8
7
6
5
1
8
7
6
5
1
2
1
2
DQS Group
DQS Group
1
2
3
4
8
7
6
5
2
1
2
3
4
8
7
6
5
1
2
DQS Group
1
2
3
4
8
7
6
5
1
2
40
2
JB
14
B
Rev
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 20. DDR2 SDRAM FPGA
A
B
C
D
[9] SODIMM_ODT3
[9] SODIMM_S3_N
SODIMM_CAS_N
SODIMM_A10
SODIMM_BA0
SODIMM_WE_N
SODIMM_A5
SODIMM_A3
SODIMM_A1
SODIMM_A12
SODIMM_A9
SODIMM_A8
SODIMM_BA2
SODIMM_CKE0
SODIMM_DQ26
SODIMM_DQ27
SODIMM_DM3
SODIMM_DQ24
SODIMM_DQ25
SODIMM_DQ18
SODIMM_DQ19
SODIMM_DQS2_N
SODIMM_DQS2_P
SODIMM_DQ16
SODIMM_DQ17
?????????
SODIMM_DQ10
SODIMM_DQ11
SODIMM_DQS1_N
SODIMM_DQS1_P
SODIMM_DQ8
SODIMM_DQ9
SODIMM_DQ2
SODIMM_DQ3
SODIMM_DQS0_N
SODIMM_DQS0_P
at
modules
VTT
DDR2_SDA
DDR2_SCL
VCC_2.5V
SODIMM_DQ58
SODIMM_DQ59
SODIMM_DM7
SODIMM_DQ56
SODIMM_DQ57
SODIMM_DQ50
SODIMM_DQ51
SODIMM_DQS6_N
SODIMM_DQS6_P
SODIMM_DQ48
SODIMM_DQ49
SODIMM_DQ42
SODIMM_DQ43
SODIMM_DM5
SODIMM_DQ40
SODIMM_DQ41
SODIMM_DQ34
SODIMM_DQ35
SODIMM_DQ32
SODIMM_DQ33
C61
47uF Ceramic X5R
SODIMM_DQS4_N
1206
SODIMM_DQS4_P
C9
0.1uF
0402
SODIMM_DQ0
SODIMM_DQ1
VCC_1.8V
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
n.c.
VSS
DQ26
DQ27
VSS
CKE0
VDD
n.c.
NC/BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
S1#
VDD
ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
n.c.
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ20
DQ21
VSS
n.c.
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
n.c.
n.c.
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
n.c.
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
VCC_1.8V
C82
0.01uF
0402
5
at modules
C108
0.1uF
0402
C53
0.1uF
0402
C83
0.1uF
0402
1.8V DDR2 200-pin SO-DIMM Standard
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
J3B
1.8V DDR2 200-pin SO-DIMM Standard
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J3A
SODIMM_S2_N[9]
SODIMM_DQ26
SODIMM_DQ27
SODIMM_CKE0
C54
0.01uF
0402
C84
0.01uF
0402
2K
VCC_2.5V
C85
0.1uF
0402
C98
0.01uF
0402
[13] VTT
EEPROM SA = 001
R54
0402
SODIMM_DQ62
SODIMM_DQ63
SODIMM_DQS7_N
SODIMM_DQS7_P
SODIMM_DQ60
SODIMM_DQ61
SODIMM_DQ54
SODIMM_DQ55
SODIMM_DM6
SODIMM_CK3_P
SODIMM_CK3_N
SODIMM_DQ52
SODIMM_DQ53
SODIMM_DQ46
SODIMM_DQ47
SODIMM_DQS5_N
SODIMM_DQS5_P
SODIMM_DQ44
SODIMM_DQ45
SODIMM_DQ38
SODIMM_DQ39
SODIMM_DM4
SODIMM_DQ36
SODIMM_DQ37
SODIMM_A13
[9] SODIMM_A10
[9] SODIMM_BA0
[9] SODIMM_WE_N
SODIMM_ODT1
4
[13]
VTT
VCC_1.8V
C142
0.01uF
0402
at modules
VCC_1.8V
C119
0.01uF
0402
[8,12] DDR2_SDA
[8,12] DDR2_SCL
[13] VCC_2.5V
SODIMM_DQ58
SODIMM_DQ59
SODIMM_DM7
SODIMM_DQ56
SODIMM_DQ57
SODIMM_DQ50
SODIMM_DQ51
SODIMM_DQS6_N
SODIMM_DQS6_P
SODIMM_DQ48
SODIMM_DQ49
SODIMM_DQ42
SODIMM_DQ43
SODIMM_DM5
SODIMM_DQ40
SODIMM_DQ41
SODIMM_DQ34
SODIMM_DQ35
SODIMM_DQ32
SODIMM_DQ33
C44
47uF Ceramic X5R
SODIMM_DQS4_N
1206
SODIMM_DQS4_P
[9]
[9] SODIMM_CAS_N
[9] SODIMM_S1_N
at
modules
SODIMM_ODT2[9]
[9] SODIMM_A5
[9] SODIMM_A3
[9] SODIMM_A1
SODIMM_BA1
SODIMM_RAS_N
[9] SODIMM_A12
[9] SODIMM_A9
[9] SODIMM_A8
SODIMM_A4
SODIMM_A2
SODIMM_A0
[9] SODIMM_BA2
[9]
SODIMM_DM3
SODIMM_DQ24
SODIMM_DQ25
SODIMM_DQ18
SODIMM_DQ19
SODIMM_DQS2_N
SODIMM_DQS2_P
SODIMM_DQ16
SODIMM_DQ17
SODIMM_A11
SODIMM_A7
SODIMM_A6
SODIMM_CKE1
SODIMM_DQ30
SODIMM_DQ31
SODIMM_DQS3_N
SODIMM_DQS3_P
SODIMM_DQ28
SODIMM_DQ29
SODIMM_DQ22
SODIMM_DQ23
SODIMM_DM2
SODIMM_DQ20
SODIMM_DQ21
?????????
SODIMM_DQ10
SODIMM_DQ11
SODIMM_DQS1_N
SODIMM_DQS1_P
SODIMM_DQ14
SODIMM_DQ15
SODIMM_CK2_P
SODIMM_CK2_N
SODIMM_DQ2
SODIMM_DQ3
SODIMM_DQS0_N
SODIMM_DQS0_P
SODIMM_DQ0
SODIMM_DQ1
VREF
VCC_1.8V
SODIMM_DQ8
SODIMM_DQ9
C80
0.1uF
0402
C49
0.01uF
0402
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
n.c.
VSS
DQ26
DQ27
VSS
CKE0
VDD
n.c.
NC/BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
S1#
VDD
ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
n.c.
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ20
DQ21
VSS
n.c.
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
n.c.
n.c.
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
n.c.
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
C45
0.1uF
0402
C104
0.1uF
0402
C46
0.01uF
0402
C39
0.1uF
0402
C40
0.01uF
0402
1.8V DDR2 200-pin SO-DIMM Reverse
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
J7B
1.8V DDR2 200-pin SO-DIMM Reverse
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J7A
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
C41
0.1uF
0402
3
EEPROM SA = 000
SODIMM_DQ62
SODIMM_DQ63
SODIMM_DQS7_N
SODIMM_DQS7_P
SODIMM_DQ60
SODIMM_DQ61
SODIMM_DQ54
SODIMM_DQ55
SODIMM_DM6
SODIMM_CK1_P
SODIMM_CK1_N
SODIMM_DQ52
SODIMM_DQ53
SODIMM_DQ46
SODIMM_DQ47
SODIMM_DQS5_N
SODIMM_DQS5_P
SODIMM_DQ44
SODIMM_DQ45
SODIMM_DQ38
SODIMM_DQ39
SODIMM_DM4
SODIMM_DQ36
SODIMM_DQ37
SODIMM_ODT0
SODIMM_A13
[9]
SODIMM_BA1
SODIMM_RAS_N [9]
SODIMM_S0_N [9]
SODIMM_A4
SODIMM_A2
SODIMM_A0
SODIMM_A11
SODIMM_A7
SODIMM_A6
SODIMM_CKE1
SODIMM_DQ30
SODIMM_DQ31
SODIMM_DQS3_N
SODIMM_DQS3_P
SODIMM_DQ28
SODIMM_DQ29
SODIMM_DQ22
SODIMM_DQ23
SODIMM_DM2
SODIMM_DQ20
SODIMM_DQ21
SODIMM_DQ14
SODIMM_DQ15
SODIMM_CK0_P
SODIMM_CK0_N
SODIMM_DM1
SODIMM_DQ12
SODIMM_DQ13
SODIMM_DQ6
SODIMM_DQ7
SODIMM_DM0
SODIMM_DQ4
SODIMM_DQ5
C114
0.1uF
0402
3
1
2
4
SODIMM_DM1
SODIMM_DQ12
SODIMM_DQ13
SODIMM_DQ6
SODIMM_DQ7
SODIMM_DM0
SODIMM_DQ4
SODIMM_DQ5
VREF
1
2
1
2
1
2
C50
0.01uF
0402
5
VREF
SODIMM_DQS0_P
SODIMM_DQS0_N
SODIMM_DM0
SODIMM_DQ0
SODIMM_DQ1
SODIMM_DQ5
SODIMM_DQ4
SODIMM_DQ13
SODIMM_DQ12
SODIMM_DQ7
SODIMM_DQ6
[13]
SODIMM_DQ25
SODIMM_DQ24
SODIMM_DQ19
SODIMM_DQ18
SODIMM_DQS2_P
SODIMM_DQS2_N
SODIMM_DM2
SODIMM_DQ17
SODIMM_DQ16
SODIMM_DQ21
SODIMM_DQ20
SODIMM_DQ9
SODIMM_DQ8
SODIMM_DQ3
SODIMM_DQ2
SODIMM_DQ15
SODIMM_DQ14
SODIMM_DQ11
SODIMM_DQ10
SODIMM_DM1
SODIMM_DQS1_P
SODIMM_DQS1_N
SODIMM_CK1_N
SODIMM_CK1_P
SODIMM_CK0_N
SODIMM_CK0_P
SODIMM_DM3
SODIMM_DQS3_P
SODIMM_DQS3_N
SODIMM_DQ31
SODIMM_DQ30
SODIMM_DQ27
SODIMM_DQ26
SODIMM_DQ29
SODIMM_DQ28
SODIMM_DQ23
SODIMM_DQ22
0402
33
R82
0402
0402
33
R76
R75
33
0402
R81
33
100
100
100
VTT
100
100
100
VTT
100
100
100
VTT
100
100
100
VTT
33
33
RN32
1
2
3
4
RN29
1
2
3
4
33
RN31
1
2
3
4
RN21
1
2
3
4
RN22
1
2
3
4
RN24
1
2
3
4
33
33
33
33
RN23
1
2
3
4
RN56
RN54
RN53
33
RN26
1
2
3
4
RN25
1
2
3
4
33
33
RN28
1
2
3
4
RN57
RN58
RN55
33
RN27
1
2
3
4
RN59
RN60
RN63
33
RN62
RN64
RN61
RN30
1
2
3
4
DDR2_CK1_N [9]
DDR2_CK1_P [9]
DDR2_CK0_N [9]
DDR2_CK0_P [9]
1
2
3
4
8
7
6
5
VREF
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
3
4
8
7
6
5
1
2
3
4
1
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
2
SODIMM_CK3_N
SODIMM_CK3_P
SODIMM_CK2_N
SODIMM_CK2_P
741X083
8
DDR2_DQS3_P [9]
7
DDR2_DQS3_N [9]
6
5
DDR2_DM3 [9]
741X083
8
DDR2_DQ31
7
DDR2_DQ30
6
DDR2_DQ27
5
DDR2_DQ26
741X083
8
DDR2_DQ29
7
DDR2_DQ28
6
DDR2_DQ23
5
DDR2_DQ22
741X083
741X083
741X083
741X083
8
DDR2_DQ25
7
DDR2_DQ24
6
DDR2_DQ19
5
DDR2_DQ18
741X083
8
DDR2_DM2 [9]
7
6
DDR2_DQS2_P [9]
5
DDR2_DQS2_N [9]
741X083
8
DDR2_DQ17
7
DDR2_DQ16
6
DDR2_DQ21
5
DDR2_DQ20
741X083
741X083
741X083
741X083
8
DDR2_DQ9
7
DDR2_DQ8
6
DDR2_DQ3
5
DDR2_DQ2
741X083
8
DDR2_DQ15
7
DDR2_DQ14
6
DDR2_DQ11
5
DDR2_DQ10
741X083
8
DDR2_DQS1_P
7
DDR2_DQS1_N
6
5
DDR2_DM1
741X083
741X083
741X083
[9]
[9]
[9]
[9]
[9]
[9]
[9]
741X083
8
DDR2_DQS0_P
7
DDR2_DQS0_N
6
DDR2_DM0
5
DDR2_DQ0
741X083
8
DDR2_DQ1
7
DDR2_DQ5
6
DDR2_DQ4
5
[9]
[9]
[9]
[9]
R77
R78
R79
R80
33
33
33
33
SODIMM_DQS4_P
SODIMM_DQS4_N
SODIMM_DM4
SODIMM_DQ37
SODIMM_DQ36
SODIMM_DQ33
SODIMM_DQ32
SODIMM_DQ35
SODIMM_DQ34
SODIMM_DQ39
SODIMM_DQ38
All the 741X083
devices on this
page with 100 ohm
value tied to VTT
should be placed
near the FPGA.
741X083
8
DDR2_DQ13
7
DDR2_DQ12
6
DDR2_DQ7
5
DDR2_DQ6
741X083
741X083
741X083
2
SODIMM_DQ40
SODIMM_DQ45
SODIMM_DQ44
SODIMM_DM5
SODIMM_DQ43
SODIMM_DQ42
SODIMM_DQ47
SODIMM_DQ46
SODIMM_DQS5_P
SODIMM_DQS5_N
SODIMM_DQ41
0402
0402
0402
0402
33
33
RN6
1
2
3
4
RN14
1
2
3
4
33
RN12
1
2
3
4
RN10
1
2
3
4
RN9
1
2
3
4
RN1
1
2
3
4
33
33
33
33
RN11
1
2
3
4
RN41
RN47
RN48
33
RN3
1
2
3
4
RN2
1
2
3
4
33
33
RN4
1
2
3
4
RN42
RN43
RN49
33
RN13
1
2
3
4
RN51
RN44
RN50
33
RN5
1
2
3
4
RN45
RN46
RN52
1
741X083
8
DDR2_DQ61
7
DDR2_DQ60
6
DDR2_DQ57
5
DDR2_DQ56
741X083
8
DDR2_DM7
7
6
DDR2_DQ63
5
DDR2_DQ62
1
Sheet
10
DDR2 SDRAM SO-DIMM
Document Number
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
741X083
8
DDR2_DQ59
7
DDR2_DQ58
6
DDR2_DQS7_P
5
DDR2_DQS7_N
741X083
741X083
741X083
[9]
[9]
[9]
[9]
[9]
[9]
[9]
741X083
8
DDR2_DQS6_P
7
DDR2_DQS6_N
6
5
DDR2_DM6
741X083
8
DDR2_DQ49
7
DDR2_DQ48
6
DDR2_DQ53
5
DDR2_DQ52
741X083
8
DDR2_DQ55
7
DDR2_DQ54
6
DDR2_DQ51
5
DDR2_DQ50
741X083
741X083
741X083
741X083
8
DDR2_DQ40
7
DDR2_DQ45
6
DDR2_DQ44
5
DDR2_DM5
741X083
8
DDR2_DQ43
7
DDR2_DQ42
6
DDR2_DQ47
5
DDR2_DQ46
741X083
8
7
DDR2_DQS5_P
6
DDR2_DQS5_N
5
DDR2_DQ41
741X083
741X083
741X083
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
741X083
8
DDR2_DQS4_P
7
DDR2_DQS4_N
6
DDR2_DM4
5
741X083
8
DDR2_DQ37
7
DDR2_DQ36
6
DDR2_DQ33
5
DDR2_DQ32
741X083
8
DDR2_DQ35
7
DDR2_DQ34
6
DDR2_DQ39
5
DDR2_DQ38
741X083
741X083
741X083
of
14
JB
All the 741X083 devices
and discrete resistors on
this page with 33 ohm
value tied to FPGA, should
be placed physically near
the FPGA.
100
100
100
VTT
100
100
100
VTT
100
100
100
VTT
100
100
100
VTT
Lattice Semiconductor Corporation
Date:
Size
C
Title
DDR2_CK3_N [9]
DDR2_CK3_P [9]
DDR2_CK2_N [9]
DDR2_CK2_P [9]
SODIMM_DQ61
SODIMM_DQ60
SODIMM_DQ57
SODIMM_DQ56
SODIMM_DQ63
SODIMM_DQ62
SODIMM_DM7
SODIMM_DQ59
SODIMM_DQ58
SODIMM_DQS7_P
SODIMM_DQS7_N
SODIMM_DM6
SODIMM_DQS6_P
SODIMM_DQS6_N
SODIMM_DQ49
SODIMM_DQ48
SODIMM_DQ53
SODIMM_DQ52
SODIMM_DQ55
SODIMM_DQ54
SODIMM_DQ51
SODIMM_DQ50
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
41
1
2
B
Rev
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 21. DDR2 SDRAM SO-DIMM
A
B
C
D
5
VCC_1.2V
VCC_1.2V
AA24
AA18
AD21
AD6
AA3
AA9
AD11
AD16
AE1
AE26
A2
A25
C11
C16
AF2
AF25
B1
B26
C6
C21
M14
M13
L12
L13
L14
L15
M11
M12
M15
M16
N11
N16
P11
P16
R11
R12
R15
R16
T12
T13
T14
T15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
VCC CORE
U5J
C136
0.01uF
0402
C128
0.1uF
0402
C120
0.01uF
0402
C102
0.1uF
0402
LFEC250-fpBGA672
1
2
1
2
1
2
1
2
1
2
1
2
C121
0.01uF
0402
C103
0.1uF
0402
C122
0.01uF
0402
C110
0.1uF
0402
F18
F24
F3
F9
J13
J14
J21
J6
K10
K11
K13
K14
K16
K17
L10
L11
L16
L17
L24
L3
N10
N12
N13
N14
N15
N17
P10
P12
P13
P14
P15
P17
R13
R14
T10
T11
T16
T17
T24
T3
U10
U11
U13
U14
U16
U17
V13
V14
V21
V6
C123
0.01uF
0402
C113
0.1uF
0402
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
(10 of 10)
1
2
1
2
1
2
1
2
1
4
C124
0.01uF
0402
C133
0.1uF
0402
C125
0.01uF
0402
C134
0.1uF
0402
C126
0.01uF
0402
C135
0.1uF
0402
[13]
[13]
[13]
VCC_ADJ
VCC_2.5V
VCC_1.8V
VCC_1.2V
VCC_3.3V
VCC_2.5V
VCC_3.3V
VCC_2.5V
VCC_3.3V
VCC_2.5V
VCC_3.3V
VCC_2.5V
VCC_ADJ
VCC_2.5V
VCC_1.8V
VCC_1.2V
VCC_1.8V
J41
HEADER 3X2
VCC_ADJ
VCC_1.8V
J40
HEADER 3X2
VCC_ADJ
VCC_1.8V
J39
HEADER 3X2
VCC_ADJ
VCC_1.8V
J14
HEADER 3X2
VCC_ADJ
VCC_2.5V
[8]
[7]
[6]
[5]
SPI4.2 Rx
VCCIO_3
SPI4.2 Tx & RJ-45
VCCIO_2
Compact Flash & LCD
VCCIO_1
Ethernet & TI EMIF
VCCIO_0
C1
10uF Ceramic X5R
0805
C131
10uF Ceramic X5R
0805
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10
CON1 CON1 CON1 CON1 CON1 CON1 CON1 CON1 CON1 CON1
3
VCC_ADJ
VCC_1.2V
VCC_3.3V
VCC_2.5V
VCC_3.3V
VCC_2.5V
C71
10uF Ceramic X5R
0805
C169
10uF Ceramic X5R
0805
2
2
VCC_1.8V
J27
HEADER 3X2
VCC_ADJ
VCC_1.8V
J28
HEADER 3X2
VCC_ADJ
C174
10uF Ceramic X5R
0805
C159
10uF Ceramic X5R
0805
[2]
VCC_1.8V
C14
10uF Ceramic X5R
0805
1
[2]
Test points
VCCIO_7
C161
10uF Ceramic X5R
0805
1
Sheet
FPGA Power Pins
Document Number
11
of
14
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
Title
Seven Segment Display, LEDs, Switches,
USB, and RS-232
VCCIO_4
C186
10uF Ceramic X5R
0805
C166
10uF Ceramic X5R
0805
1
2
VCC_3.3V
GND Pins for Signal Probing
1
[13]
1
2
1
2
VCC_3.3V
1
VCC_3.3V
1
[12]
1
1
2
Bulk Capacitors
1
1
2
1
2
3
1
4
1
1
2
1
2
2
4
6
1
3
5
2
4
6
1
3
5
2
4
6
1
3
5
2
4
6
1
3
5
1
2
1
2
1
2
1
2
1
2
1
2
2
4
6
1
3
5
2
4
6
1
3
5
1
2
1
2
5
1
42
1
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 22. FPGA Power Pins
A
B
C
16
15
14
13
12
11
10
9
1
1
2
3
S
BANANA JACK
J42
2.5mm Pin, (+)
5.5mm Barrel, (-)
1
VCC_IN
Power Input
+5 to +28VDC
J54
PWR JACK
RAPC712
S
BANANA JACK
J51
VCC_IN
5
VTT
VCC_1.2V
VCC_3.3V
VCC_2.5V
VCC_1.8V
D29
1N5820
267-05
[13] VCC_5.0V
[13]
[13]
[13]
[13]
[13]
VREF
VCC_ADJ
SW DIP-8 CTS 194-8MST
SW1
1
2
3
4
5
6
7
8
SW2
SW PUSHBUTTON Panasonic EVQP2H02B
ON
R94
4.7K
VMON1+
VMON1GS
VMON2+
VMON2GS
VMON3+
VMON3GS
VMON4+
VMON4GS
VMON5+
VMON5GS
VMON6+
VMON6GS
VMON7+
VMON7GS
VMON8+
VMON8GS
VMON9+
VMON9GS
VMON10+
VMON10GS
VMON11+
VMON11GS
VMON12+
VMON12GS
R96
4.7K
TP133
1
2
3
Off
3.3V On/Off Switch
SW6
EG1257
On
C37
0.001uF
0402
C38
100uF AVX Tantalum TPSE107K020R0150
SizeE
47
46
50
48
52
51
54
53
56
55
58
57
62
61
64
63
66
65
68
67
70
69
72
71
R99
4.7K
R158
10K
R159
10K
POWR1220AT8
Lattice
ispPAC
U8
C36
2200pF
0402
R49
10K
0402
4
PWR_SCL
PWR_SDA
7
8
5
4
3
1
Vosence
Vprog
Ith
FCB
Run/SS
EXTVcc
1
3
5
10
11
12
14
13
R157
10K
R191
10
0402
3
[13]
EN_ADJ
R190
10K
0402
4
4
[13]
[13]
3 2 1
8 7 6 5
3 2 1
8 7 6 5
Q12
MMBT2222ALT
SOT-23
DIS_1.2V
DIS_2.5V
3
C34
0.47uF Ceramic X5R
R46
0603
10K
0402
10
0402
C187
4.7uF Ceramic X5R
0603
59-10
1N5819
D28
R47
R160
10K
TP126
TP155
TP154
TP153
TP152
TP151
TP150
TP129
TP130
73
74
75
79
80
82
83
84
95
TP143
TP147
TP131
40
42
85
86
C2012X5ROJ475M
BG
INTVcc
Boost
SW
TG
TK
PLDCLK
TRIM8
TRIM7
TRIM6
TRIM5
TRIM4
TRIM3
TRIM2
TRIM1
HVOUT4
HVOUT3
HVOUT2
HVOUT1
[7]
ADJ_1.2V
ADJ_1.5V
ADJ_1.8V
ADJ_2.5V
ADJ_3.3V
PWR_GOOD_VTT
PWR_GOOD_VREF
PWR_GOOD_1.2V
PWR_GOOD_1.8V
PWR_GOOD_2.5V
PWR_GOOD_3.3V
DIS_1.2V
DIS_2.5V
[4]
[4]
[4]
[4]
[4]
[4]
25
24
23
21
20
19
18
17
16
15
14
12
11
10
9
8
15
TDISEL
PWR_TDO
PWR_TDI
PWR_ATDI
PWR_TMS
PWR_TCK
HEADER 3X2
J33
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
SMBA/OUT5
2
4
6
PAC_SCL
DDR2_SCL[8,12]
DC-DC converter traces >= 10mil
U14
LTC1775CS
VCCPROG
39
D
R104
4.7K
VCCD
VCCD
VCCD
13
38
94
R106
4.7K
5
97
1
2
4
6
7
VCCINP
IN1
IN2
IN3
IN4
IN5
IN6
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
3
22
36
43
88
98
R110
4.7K
89
90
VPS0
VPS1
VCCA
60
R112
4.7K
TP125
96
MCLK
[7] PAC_SDA
TP124
RESETb
91
[8,12] DDR2_SDA
93
92
SDA
SCL
87
45
R117
4.7K
1
2
4
Vin
GNDA
GNDA
33
34
31
30
28
37
32
16
VCCJ
TDO
TDI
ATDI
TMS
TCK
TDISEL
SGND
6
PGND
9
[13]
EN_5.0V
Q11
MMBT2222ALT
SOT-23
R140
10K
2.5V
1.8V
1
2
R145
R146
R147
R148
R149
R150
Source
PWR_3.3V_3A
Q9
NTR4501N 20V 3.2A
SOT-23
Drain
PWR_3.3V_10A
Source
Drain
F5
2
2
PWR_3.3V_10A
C35
10uF Ceramic X5R
0805
C179
0.1uF
0402
1
[4,13]
C184
0.1uF
0402
MOSFET
PWR_3.3V_10A
C180
0.1uF
0402
+3.3V
10A
C15
10uF Ceramic X5R
0805
ADJ, 1.5A
+1.2V, 3A
+1.8V, 10A
+2.5V, 3A
+3.3V, 3A
+5.0V, 1A
Date:
Size
C
Power_1
Document Number
1
Sheet
12
of
14
Lattice Semiconductor Corporation
Title
ispPAC
C29
470uF KEMET T510X477K006AS
SizeD
3A FUSE Littelfuse 154003
383milX198mil
1
J49
BANANA JACK
VCC_3.3V
[2,3,4,5,6,7,8,9,11]
C178
0.1uF
0402
Power
Input
+5~28V
+3.3VDC
330
330
330
330
330
330
330
330
330
330
2
C27
470uF KEMET T510X477K006AS
SizeD
L5
10uH Coilcraft DO5010H-103ML
15.24mmX18.54mm
Gate
Gate
SOT-23
3.3V Power Good
2.5V Power Good
1.8V Power Good
1.2V Power Good
VREF Power Good
R151
R152
R153
R154
R155
330
[13]
S3S5_1.8V
Q10
MMBT2222ALT
SOT-23
VTT Power Good
D27
Q7
Si4840DY
SO-8
403-03
MBRS340
Q8
Si4840DY
SO-8
R48
100
LED 0603 Green
D5
LED 0603 Green
D6
LED 0603 Green
D7
LED 0603 Green
D8
LED 0603 Green
D9
D10
LED 0603 Green
D11
LED 0603 Green
LED 0603 Green 3.3V
D12
LED 0603 Green
D13
LED 0603 Green
D14
D15
LED 0603 Green1.5V
1.2V
ADJ Voltage Indicators
R156
10K
1
2
1
2
5
1
2
1
2
S
1
1
43
2
B
Rev
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 23. Power 1
A
B
C
D
[12]
[12]
DIS_1.2V
PWR_3.3V_10A
DIS_2.5V
PWR_3.3V_10A
VREF
VTT
VCC_1.8V
VCC_1.8V
S
1
HI HI
LO HI
LO LO
S0
S3
S4/S5
G
1
VTTREF
C101
0.033uF Ceramic
0402
VREF
C8
10uF Ceramic X5R
0805
VTT
C160
10uF Ceramic X5R
0805
G
R10
10K
U2
TPS64203DVB
/EN
GND
FB
5
C81
10uF Ceramic X5R
0805
R30
10K
1
2
3
TPS64203DVB
/EN
GND
FB
U4
SW
VIN
ISENSE
Q6
Si2323DS Vishay Siliconix SOT23
SOT-23
1
2
3
SW
VIN
ISENSE
Q1
Si2323DS Vishay Siliconix SOT23
SOT-23
Another P-Channel MOSFET option
in SOT23 package
DRAIN_1.2
GATE_1.2
PWR_3.3V_10A
C22
10uF Ceramic X5R
0805
VTT
1
2
3
4
5
6
7
8
9
10
U3
6
5
4
6
5
4
R32
100
R31
10
100
R9
10
0.1uF
VBST
DRVH
LL
DRVL
PGND
CS
V5IN
PGOOD
S5
S3
0402
4
C16
1800p
0402
DRAIN_1.2
P-Channel
MOSFET
GATE_1.2
C6
1800p
0402
DRAIN_2.5
P-Channel
MOSFET
GATE_2.5
TPS51116PWP
R26
4
VBST
C99
VLDOIN
VTT
VTTGND
VTTSNS
GND
MODE
VTTREF
COMP
VDDQSSNS
VDDQSET
PWR_1.8V
On
On
On
On
On
Off(Hi-Z)
Off(Discharge) Off(Discharge) Off(Discharge)
VDDQ
F2
10A FUSE Littelfuse 154010
383milX198mil
2
Another P-Channel MOSFET option
in SOT23 package
DRAIN_2.5
GATE_2.5
PWR_3.3V_10A
S3 S5
STATE
C11
0.1uF
0402
C7
10uF Ceramic X5R
0805
[8,9,10,11,12]
+1.8VDC
1
1
2
BANANA JACK
S
2
1
2
J11
1
20
19
18
17
16
15
14
13
12
11
4
3
2
1
G
D
D
D
S
D
D
D
D3
D4
B320A Diodes Inc.
SMA_PKG
R27
10K
PGOOD
CS_1.8
3 2 1
VCC_2.5V
C151
0.01uF
0402
100K
1
1uF Ceramic X5R
2
0402
C17
10uF Ceramic X5R
0805
C127
0.1uF
0402
C20
1
1uF Ceramic X5R
2
0402
F3
3A FUSE Littelfuse 154003
383milX198mil
+1.2VDC
3
C21
100uF Parasonic SP-CAP EEF-HD0J101R
SizeD
PWR_1.2V
VCC_1.2V
VCC_1.2V
39K 1% YAGEO 0402
J17
BANANA JACK
C4
100uF Parasonic SP-CAP EEF-HD0J101R
SizeD
C2
F1
3A FUSE Littelfuse 154003
383milX198mil
C75
10uF Ceramic X5R
0805
+2.5VDC
J4
BANANA JACK
C10
4.7uF Ceramic X5R
0603
VCC_5.0V
C88
150uF Panasonic SP-CAP EEF-HE0J151R
1
2 SizeD
VCC_2.5V
R8
42.2K 1% YAGEO 0402
R11
10uF Ceramic X5R
0805
C100
150uF Panasonic SP-CAP EEF-HE0J151R
2 SizeD
1
5.1K
PWR_2.5V
R29
R28
Q3
IRF7832
SO-8
N-Channel
MOSFET
[2,5,6,9,11,12]
C5
4.7pF
0402
L3
2
1
6.2uH Sumida CDRH6D38-6R2
Q5
Si5447DC
1206-8
B320A Diodes Inc.
SMA_PKG
4
SOURCE
N-Channel
MOSFET
PWR_3.3V_10A
Q4
IRF7821
SO-8
C13
3
L2
1
2
1.0uH Vishay IHLP-5050FD-ER-1R0-M-01
3 2 1
DRAIN 8 7 6 5
SOURCE
4
DRAIN 8 7 6 5
10uF Ceramic X5R
0805
[4,8,10,11,12]
1
2
6.2uH Sumida CDRH6D38-6R2
L1
Q2
Si5447DC
1206-8
GATE_1.8L
LL_1.8
GATE_1.8H
C12
S
1
2
1
1
2
[12]
[12]
EN_ADJ
PWR_3.3V_10A
EN_5.0V
[12]
[12]
S3S5_1.8V
PWR_3.3V_10A
PWR_3.3V_10A
1
2
5
1
2
1
2
1
2
R139
10K
1
2
3
4
5
6
7
8
NC
VOUT
VOUT
VOUT
FB
GND
LBO
EN
TPS61030PWP
SW
SW
PGND
PGND
PGND
VBAT
LBI
SYNC
U6
16
15
14
13
12
11
10
9
VCC_5.0V
VCC_5.0V
+5.0VDC
[7,12]
C31
4.7uF Ceramic X5R
0603
2
R41
10K
1
2
EN
VIN
U9
FB
VOUT
5
4
TPS78601KTT
2
VCC_ADJ
PWR_ADJ
VCC_ADJ
C28
10uF Ceramic X5R
0805
C30
2.2uF Ceramic X5R
0603
F4
1.5A FUSE Littelfuse 15401.5
383milX198mil
Power_2
Document Number
1
Sheet
13
of
14
B
Rev
Lattice Semiconductor Corporation
Date:
Size
C
Title
R43
30.1K 1% YAGEO 0402
J38
BANANA JACK
R138
221K 1% YAGEO 0603
VR1
50K POT Murata PV36Y503C01
PV37W
[11,12]
C26
2.2uF Ceramic X5R
0603
220uF AVX Tantalum TPSD227K010R0150
2 SizeD
1
R137
2.0M 1% YAGEO 0603
C25
1
(Adjustable between 1.2V to +3.3V)
L4
6.8uH Sumida CDRH124-6R8
1
2
VCC_ADJ
C182
10uF Ceramic X5R
0805
2
3
D
S
D
1
2
5
6
7
8
4
3
2
1
G
D
D
D
S
D
D
D
5
6
7
8
2
1
2
1
2
1
2
1
2
1
2
S
1
2
1
GND
3
1
2
S
1
2
1
44
1
A
B
C
D
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 24. Power 2
45
4
3
2
Lattice Semiconductor Corporation
A
A
Date:
C
1
Sheet
14
of
14
B
Placement
& Dimension (7.5"x8.5")
Document Number
Size
Rev
B
B
5
Title
1
C
2
C
3
D
4
D
5
Lattice Semiconductor
LatticeECP2 Advanced
Evaluation Board User’s Guide
Figure 25. Placement and Dimensions (7.5” x 8.5”)