Le5711

Le5711
Dual Subscriber Line Interface Circuit
VE580 Series
Data Sheet
Features
Document ID#: 81132
•
Dual-channel SLIC device with small footprint
•
On-chip Thermal Management (TMG) feature in
Normal and Reverse Polarity
•
Control states: Active (Normal and Reverse
Polarity), Standby, and Disconnect
•
On-hook transmission
•
Low standby power
•
–39 to –58 V battery operation
•
Two-wire impedance set by single external
impedance
•
Device level thermal shutdown
•
Set on-chip constant-current feed
•
Programmable ring-trip detect threshold
•
Only +5 V and battery supply required
Version 3
May 2011
Ordering Information
44-pin eTQFP (Green)1 Tray2
50 dB Reverse Polarity
Le57D111BTC
1.
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
2.
For delivery using a tape and reel packing system, add a "T"
suffix to the OPN (Ordering Part Number) when placing an
order.
the Zarlink QLSLAC™ device, another member of the
VE580 series, combined with the Le5711 device
provides a programmable line circuit that can be
configured for varying requirements.
Related Literature
C11
TMG1
080748 Le5711 Evaluation Board User’s Guide
C21
•
DET1
Fulfills the following China specifications: GF0029002.1
080754 Le58QL061/063 QLSLAC™ Data Sheet
CAS
•
•
IREF
Meets requirements for countries such as: China,
Korea, Japan, Taiwan, and Australia
080753 Le58QL02/021/031 QLSLAC™ Data
Sheet
DET2
•
•
C12
Ideal for low cost, high performance linecard
applications (CO, DLC)
C22
•
TMG2
Applications
Description
The innovative Le5711 dual-channel SLIC device is
designed for high-density POTS applications requiring
a small footprint SLIC device with significant power
savings. By combining the line interface of two
channels into one SLIC device, the Le5711 device
enables the design of a low cost, high performance,
and fully programmable line interface for multiple
country applications worldwide. The on-chip Thermal
Management (TMG) feature allows for significantly
reduced power dissipation on the device. The Le5711
device is offered in a space-saving package type, 44pin eTQFP. The small footprint of the SLIC device
allows designers to save board space, increasing the
density of lines on the board. The Le5711 device is
also designed to significantly reduce the number of
external components required for linecard design.
A2 (TIP)
HP2
CH2
2-W
Interface
CH2
Input
Decoder
and Control
Common
Bias
CH1
Input
Decoder
and Control
A1 (TIP)
CH1
2-W
Interface
B1 (RING
CH2
CH2
CH1
CH1
CH1
Power Feed
Controller
Ring Trip
Detector
Ring Trip
Detector
Power Feed
Controller
Off-Hook
Detector
CH1
Signal
Transmission
CH2
Off-Hook
Detector
RSN2
CH2
Signal
Transmission
B2 (RING)
VTX2
HP1
BGND2
VTX1
RSN1
Figure 1 - Block Diagram
Zarlink offers a range of compatible codec/filters that
perform the codec function in a line card. In particular
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007-2011, Zarlink Semiconductor Inc. All Rights Reserved.
AGND/
DGND
VCC
CDC1
DB1
DAC
DB2
CDC2
VBAT
BGND1
Le5711
Data Sheet
Revision History
Below are the changes from the September 2007 version to the May 2011 version.
Page
1
Item
Ordering Information
Description
Obsoleted Le57D111DJC package.
2
Zarlink Semiconductor Inc.
Le5711
Data Sheet
Table of Contents
1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.0 Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Signal Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Power Feed Controller and Common Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Input Decoder and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Off-Hook Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6 Ring-Trip Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.0 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.0 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1 Transmission Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2 Crosstalk Between Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.3 Longitudinal Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.4 Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.5 Line Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.6 Power Supply Rejection Ratio at the Two-Wire Interface, Active Normal State . . . . . . . . . . . . . . . . . . . . 13
6.7 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.8 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.9 RFI Rejection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.10 Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.11 Logic Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.12 Ring-Trip Detector Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.13 Loop Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.14 SLIC Device Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.15 User-Programmable Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.16 DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.17 Test Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.0 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.0 Line card Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.1 44-Pin eTQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3
Zarlink Semiconductor Inc.
Le5711
Data Sheet
List of Figures
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Feed Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3 - Two-to-Four Wire Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4 - Four-to-Two Wire Insertion Loss and Balance Return Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5 - Longitudinal Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6 - Two-Wire Return Loss Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7 - RFI Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8 - Le5711 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
Zarlink Semiconductor Inc.
Le5711
1.0
Data Sheet
Product Description
The Le5711 device is designed for long loop high-density POTS applications requiring a low power, small footprint
SLIC. The Le5711 device increases linecard density by integrating two SLIC devices into a single 32 pin package.
This reduction in board space allows for higher density linecard, which allows for amortizing common hardware
across more channels. The Le5711 device gives linecard designers a simple control interface that supports four
states: Active, Reverse Polarity, Standby, and Disconnect (Ringing). The Le5711 device is low cost and high
performance, providing key features required for POTS markets requiring only loop start. The device includes a
thermal management resistor for reducing power dissipation.
2.0
Block Descriptions
2.1
Two-Wire Interface
The two-wire interfaces provide DC current and send voice signals to a telephone apparatus connected to the
linecard with a two-wire line. The two-wire interface also receives the returning voice signals from the telephone
transmitter.
2.2
Signal Transmission
The RSN input current controls the receive current sent to the two-wire interface. The AC line voltage is sensed by
a differential amplifier between the Ai (TIP) and HPi leads.* The output of this amplifier is equal to the AC metallic
components of the line voltages and is output at VTXi. The transmission circuit also contains a longitudinal
feedback circuit to shunt longitudinal signals to a DC bias voltage. The longitudinal feedback does not affect
metallic signals.
*Note:
"i" denotes channel number
2.3
Power Feed Controller and Common Bias
The power feed controllers have three sections: (1) the battery feed circuit, (2) the reverse polarity circuit, and (3)
the common bias circuit. The battery feed circuit regulates the amount of DC current and voltage supplied to the
telephone over a wide range of loop resistance. The reverse polarity circuit provides the capability to reverse the
loop current for pay telephone key pad disable and other applications. The bias circuit provides a filtered reference
voltage, which is offset from the subscriber line voltage, and a signal which sets the current limit.
2.4
Input Decoder and Control
The input decoder and control block provides a means for a microprocessor or SLAC IC to control such system
states as Active, Standby, Disconnect (Ringing), and Reverse Polarity. The input decoder and control block has
TTL-compatible inputs, which set the operating states of the SLIC device. It also provides the supervision signal
sent back to the controller.
2.5
Off-Hook Detector
The most important loop monitoring function is off-hook detection. Loop current is programmed for both channels
by a single resistor. Loop detect threshold is typically 1/3 of the programmed Loop current in the Active and
Reverse Polarity states.
2.6
Ring-Trip Detector
In the Disconnect state, the ring-trip detector is active. While the DBi pin is more negative than the DAC pin, the
DET pin will be high to indicate on hook. When an off hook condition occurs, the DBi pin becomes more positive
than the DAC pin, and the DET pin will go low to indicate off hook during ringing (ring-trip) has been detected. The
system implements the Ringing state using external control of a ring relay in combination with the Disconnect SLIC
state, which enables the ring-trip detector.
5
Zarlink Semiconductor Inc.
Le5711
TMG 1
NC
HP 1
RSVD 1
NC
NC
VTX 1
NC
RSN 1
CDC 1
Connection Diagrams
DET 1
3.0
Data Sheet
44 43 42 41 40 39 38 37 36 35 34
C21
1
33
C11
2
32
B1 (RING)
NC
3
31
A1 (TIP)
AGND/DGND
4
30
DB 1
VCC
5
29
DAC
NC
6
28
NC
CAS
7
27
VBAT
IREF
8
26
DB 2
C12
9
25
A2 (TIP)
C22
10
24
B2 (RING)
DET 2
11
23
BGND 2
44-Pin eTQFP
Exposed Pad
BGND 1
TMG 2
HP 2
NC
RSVD 2
NC
NC
VTX 2
NC
NC
RSN 2
CDC 2
12 13 14 15 16 17 18 19 20 21 22
Note:
1.
Pin 1 is marked for orientation.
2.
NC = No Connect
3.
The exposed heat sink pad on the bottom of the eTQFP package is connected to the battery supply (VBAT pin). Do not connect to GND.
6
Zarlink Semiconductor Inc.
Le5711
4.0
Data Sheet
Pin Descriptions
Pin Name
Type
Description
A1 (TIP)
Output
Output of A (TIP) power amplifier of channel 1.
A2 (TIP)
Output
Output of A (TIP) power amplifier of channel 2.
AGND/DGND
Ground
Analog and digital ground.
B1 (RING)
Output
Output of B (RING) power amplifier of channel 1.
B2 (RING)
Output
Output of B (RING) power amplifier of channel 2.
BGND1
Ground
Battery (power) ground of channel 1
BGND2
Ground
Battery (power) ground of channel 2.
C11
Input
C21
Input
C12
Input
C22
Input
CAS
Capacitor
Pin for capacitor to filter reference voltage when operating in anti-saturation
region.
CDC1
Capacitor
DC feed filter capacitor of channel 1.
CDC2
Capacitor
DC feed filter capacitor of channel 2.
RSVD1
Input
Reserved. Connect to VCC.
RSVD2
Input
Reserved. Connect to VCC.
DAC
Input
Ring-trip negative of both channels. Negative input to ring-trip comparator.
DB1
Input
Ring-trip positive of channel 1. Positive input to ring-trip comparator.
DB2
Input
Ring-trip positive of channel 2. Positive input to ring-trip comparator.
DET1
Output
Switch-hook/Ring-trip detector output of channel1. Logic low indicates that a
detector is tripped.
DET2
Output
Switch-hook/Ring-trip detector output of channel 2. Logic low indicates that a
detector is tripped.
HP1
Capacitor
Connect High-pass filter capacitor from HP1 to B1 (RING).
HP2
Capacitor
Connect High-pass filter capacitor from HP2 to B2 (RING).
IREF
Resistor
Connection for reference resistor that programs loop detector threshold and DC
feed current of both channels.
NC
—
RSN1
Input
State decoder inputs of channel 1.
State decoder inputs of channel 2.
No Connect. This pin is not internally connected.
Receive Summing Node of channel 1. In the Active and Polarity Reversed states,
the current (both AC and DC) between A1 (TIP) and B1 (RING) is equal to 500
times the current into this pin. The networks that program receive gain and twowire impedance of channel 1 connect to this node.
7
Zarlink Semiconductor Inc.
Le5711
Data Sheet
Pin Name
Type
Description
RSN2
Input
Receive Summing Node of channel 2. In the Active and Polarity Reversed states,
the current (both AC and DC) between A2 (TIP) and B2 (RING) is equal to 500
times the current into this pin. The networks that program receive gain and twowire impedance of channel 2 connect to this node.
TMG1
Output
Thermal management of channel 1. External resistor connects from TMG1 to
VBAT to offload power from the SLIC device.
TMG2
Output
Thermal management of channel 2. External resistor connects from TMG2 to
VBAT to offload power from the SLIC device.
VBAT
Battery
Battery supply and connection to substrate.
VCC
Power
+5 V power supply.
VTX1
Output
Transmit audio signal of channel 1. This output is a scaled version of the A and B
metallic voltage. VTX also sources the two-wire input impedance programming
network.
VTX2
Output
Transmit audio signal of channel 2. This output is a scaled version of the A and B
metallic voltage. VTX2 also sources the two-wire input impedance programming
network.
Exposed Pad
Battery
The exposed thermal management pad must be in thermal contact with an
exposed copper plate with an electrical potential of battery supply (VBAT pin).
8
Zarlink Semiconductor Inc.
Le5711
5.0
Electrical Characteristics
5.1
Absolute Maximum Ratings
Data Sheet
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods
can affect device reliability.
Storage temperature
–55 to +150º C
VCC with respect to AGND
–0.4 to +7.0 V
VBAT with respect to AGND
+0.4 to –61V
BGND1, BGND2 with respect to AGND
+3 to –3 V
A1 (TIP), A2 (TIP), B1 (RING), B2 (RING) with respect to BGND:
Continuous
VBAT to + 1 V
10 ms (F = 0.1 Hz)
–70 to +5 V
1 µs (F = 0.1 Hz)
–80 to +8 V
250 ns (F = 0.1 Hz)
–90 to +12 V
Current from A1 (TIP), A2 (TIP), B1 (RING), B2 (RING)
±150 mA
DB1, DB2, and DAC inputs:
Voltage on ring-trip inputs
VBAT to 0 V
Current into ring-trip inputs
±10 mA
C11, C21, C12, C22
–0.4 to VCC + 0.4 V
Input Voltage
Maximum power dissipation, continuous:
TA = 70º C, No heat sink
In 44-pin eTQFP
(see note 1)
JA
Thermal Data (Junction to Ambient):
In 44-pin eTQFP package
(see note 2)
JC
Thermal Data (Junction to Case):
In 44-pin eTQFP package
(see note 2)
ESD Immunity (Human Body Model)
JESD22 Class 1C compliant
Notes:
1.
Thermal limiting circuitry on the chip will shut down the circuit at a junction temperature of about 165ºC. Continuous operation above 145ºC
junction temperature may degrade device reliability.
2.
The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Refer to the Thermal
Management for the Le5711 and Le5712 Dual SLIC Devices Application Note for details.
9
Zarlink Semiconductor Inc.
Le5711
Data Sheet
Package Assembly
The green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and
antimony-free materials. The leads possess a matte-tin plating which is compatible with conventional board
assembly processes or newer lead-free board assembly processes. The peak soldering temperature should not
exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
5.2
Operating Ranges
Zarlink guarantees the performance of this device over commercial (0 to 70ºC) and industrial (-40 to 85ºC)
temperature ranges by conducting electrical characterization over each range and by conducting a production test
with single insertion coupled to periodic sampling. These characterization and test procedures comply with section
4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance Requirements for Telecommunications
Equipment.
Ambient Temperature
40° to 85°C
VCC
4.75 to 5.25 V
VBAT
–39 to –58 V
DB1, DB2, and DAC
VBAT to –2 V
AGND
0V
BGND1, BGND2 with respect to AGND
–100 to + 100 mV
Load resistance on VTX to ground
20 k minimum
Note:
The operating ranges define those limits between which the device operates and is guaranteed under the noted test conditions.
10
Zarlink Semiconductor Inc.
Le5711
6.0
Specifications
6.1
Transmission Performance
Description
2-wire return loss
Data Sheet
Test Conditions (See Note 1)
Min.
200 Hz to 3.4 kHz (See Figure 6 on
page 19)
26
Typ.
Analog output (VTX)
impedance
Max.
Unit
Note
dB
3, 5
20

3
+50
mV
3
Analog (VTX) output offset
voltage
–50
Overload level, 2-wire
Active or Reverse Polarity state
2.5
Overload level
On hook
1.1
THD (Total Harmonic
Distortion)
0 dBm
–64
–50
+7 dBm
–55
–40
THD, On hook
0 dBm
6.2
dB
2a
2b
4
–36
Crosstalk Between Channels
Description
Crosstalk coupling loss
6.3
Vpk
Test Conditions (See Note 1)
Min.
Typ.
F = 200 Hz to 3.4 kHz
Max.
80
Unit
Note
dB
3
Longitudinal Capability
(See Figure 5 on page 19.)
Description
Test Conditions (See Note 1)
Min.
Longitudinal to metallic L-T, L-4
balance
200 Hz to 3.4 kHz, 0º C to +70º C
50
Longitudinal signal generation
4-L
200 Hz to 3.4 kHz
40
Longitudinal current per pin (A
or B)
Active state (off hook)
8.5
Longitudinal impedance at A or
B
Idle Channel Noise
Typ.
Max.
Unit
dB
20
mArms
0 to 100 Hz
25
pin
C-Message, RL = 600 
7
12
dBrnC
–83
–78
dBmp
Psophometric, 600 
11
Zarlink Semiconductor Inc.
Note
3
6
3
Le5711
6.4
Data Sheet
Insertion Loss
(See Figure 3 and Figure 4 on page 18.)
Description
Test Conditions (See Note 1)
Min.
Typ.
Max.
Gain accuracy, 4-to-2-wire
0 dBm, 1 kHz
–0.20
0
+0.20
Gain accuracy, 2-to-4-wire
and 4-to-4-wire
0 dBm, 1 kHz
–9.74
–9.54
–9.34
Gain accuracy, 4-to-2-wire
On hook
–0.35
+0.35
Gain accuracy over
frequency
300 to 3.4 kHz
relative to 1 kHz
–0.15
+0.15
Gain tracking
+3 dBm to –55 dBm
relative to 0 dBm
–0.15
+0.15
Gain tracking, On hook
0 dBm to –37 dBm
+3 dBm to 0 dBm
–0.15
–0.35
+0.15
+0.35
12
Zarlink Semiconductor Inc.
Unit
Note
dB
3
Le5711
6.5
Data Sheet
Line Characteristics
Description
Test Conditions (See Note 1)
IL, Short Loops, Active state
IL, Long Loops, Active state
IL, Accuracy, Standby state
RLDC = 1930 , BAT = –42.75 V,
TA = 25°C
RL = 0
VAB, Open Circuit voltage
VBAT = –48 V
6.6
Typ.
Max.
26.4
30
33.6
18
19
IL
0.7IL
1.3IL
100
+38.3
Test Conditions (See Note 1)
µA
+40.3
Min.
Typ.
40
VCC
50 Hz to 3.4 kHz
VRIPPLE = 100 mVRMS
30
VBAT
50 Hz to 3.4 kHz
VRIPPLE = 500 mVPP
28
V
Max.
Unit
Note
dB
4
50
Power Dissipation
Description
Typ.
Max.
On hook, both channels, Standby
state
40
100
On hook, both channels, Active state
380
540
Test Conditions (See Note 1)
Min.
Off hook, both channels, Active state
RL = 300 , RTMG = 1600 
1400
1700
One channel, Active state
One channel, Standby state
RL = 300 , RTMG = 1600 
720
1050
6.8
Note
Power Supply Rejection Ratio at the Two-Wire Interface, Active Normal State
Description
6.7
Unit
mA
VBAT – 3V
I L =  --------------------------------  T A = 25C
  R + 3.2 k 
L
IL, Loop current, Disconnect
state
Min.
Unit
Note
mW
Supply Currents
Description
ICC,
On-hook VCC supply current
IBAT,
On-hook VBAT supply current
Test Conditions (See Note 1)
Typ.
Max.
Both channels, Standby state
2.5
4.0
Both channels, Active state,
BAT = –48 V
9.0
12.0
Both channels, Standby state
0.5
1.5
Both channels, Active state,
BAT = –48 V
6.5
8.5
13
Zarlink Semiconductor Inc.
Min.
Unit
mA
Note
Le5711
6.9
Data Sheet
RFI Rejection
(See Figure 7 on page 19.)
Description
VTX1 or VTX2
6.10
Test Conditions
Min.
Typ.
Max.
Unit
Note
f = .01 to 100 MHz
HF gen output = 1.5 Vrms
CAXi = CBXi = 33 nF
1
mVr
ms
3
CAXi = CBXi = 2.2 nF
3
Logic Inputs
(Applies to C11, C12, C21, and C22.)
Description
Test Conditions
VIH, Input High voltage
Min.
Typ.
2.0
Unit
Note
V
VIL, Input Low voltage
0.8
IIH, Input High current
–75
IIL, Input Low current
–400
6.11
Max.
40
µA
Logic Output
(Applies to DET1 and DET2.)
Description
Test Conditions (See Note 1)
VOL, Output Low voltage
IOUT = 0.3 mA
VOH, Output High voltage
IOUT = –0.1 mA
6.12
Min.
Typ.
Max.
Unit
Note
0.40
V
2.4
Ring-Trip Detector Input
(Applies to DAC, DB1, and DB2.)
Description
Test Conditions (See Note 1)
Bias Current
Min.
Typ.
–500
–50
VBAT 1
Common Mode Range
14
Zarlink Semiconductor Inc.
Max.
Unit
nA
2
V
Note
Le5711
6.13
Data Sheet
Loop Detector
Description
Test Conditions (See Note 1)
Min.
Typ.
Max.
Off-hook threshold
Active
9
11
On-hook threshold
Active
8.5
10.5
Off-hook threshold
Standby
4
6
On-hook threshold
Standby
3.8
5.8
0
2
Hysteresis
Unit
Note
mA
Notes:
1.
Unless otherwise noted, the test conditions are set up by the Le5711 device test circuit as illustrated in Figure 8 on page 20.
2.
a. Overload level is defined as THD = 1%.
b. Overload level is defined when THD = 1.5%.
3.
Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
4.
This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
5.
Group delay can be greatly reduced by using a ZT network such as that shown in Figure 6. The network reduces the group delay to less
than 2 µs and increases 2WRL. The effect of group delay on linecard performance also may be compensated by synthesizing complex
impedance with the QLSLAC™ device.
6.
Minimum current level guaranteed not to cause a false loop detect.
6.14
SLIC Device Decoding
(For i, Channel = 1 or 2)
State
C2i
C1i
Two-Wire Status
0
0
0
Disconnect
Ring-Trip Detector
1
0
1
Active
Loop Detector
2
1
1
Polarity Reversed (Le57D111
devices only)
Loop Detector
3
1
0
Standby
Loop Detector
15
Zarlink Semiconductor Inc.
DETx Output
Le5711
6.15
Data Sheet
User-Programmable Components
Equation
Description
Z Ti = 166.7  Z 2WIN – 2R F 
ZTi* is connected between the VTX and RSN pins. The
fuse resistors are RF, and Z2WIN is the desired 2-wire
AC input impedance. When computing ZTi, the internal
current amplifier pole and any external stray
capacitance between VTX and RSN must be taken
into account.
ZL
500Z T
Z RXi = -------------  --------------------------------------------------------G 42L
Z T + 166.7  Z L + 2R F 
ZRXi* is connected from VRX to RSN. ZTi is defined
above, and G42L is the desired receive gain.
450
R REF = --------------I LOOP
C DC = 1.5 F
ILOOP is the desired loop current in the constantcurrent region.
Loop detect threshold is typically 1/3 of programmed
Loop current.
1
C CAS = ------------------------------------------170 k  2  f c
CCAS is the regulator filter capacitor and fc is the
desired filter cut-off frequency.
V BAT – 3 V
I STANDBY = --------------------------------3200  + R L
Standby loop current (resistive region).
Thermal Management Equations (Active, and Reverse Polarity states for one channel)
V BATMAX – 6 V – I LMIN  2R F + R LMIN 
R TMG  ----------------------------------------------------------------------------------------------------- – 40 
I LMIN
RTMG is connected from TMG to VBAT and limits
power within the SLIC device in Active and Off-Hook
states.
2
 V BAT – 6 V –  I L   R L + 2R F   
P RTMG = --------------------------------------------------------------------------------------------  R TMG
2
 R TMG + 40  
Power dissipated in the TMG resistor, RTMG, during
Active and Off-Hook states.
Power dissipated per channel in the SLIC device while
in Active state.
2
P SLIC = V BAT  I L – P RTMG – R L  I L  + 0.12 W
Note:
* "i" denotes channel number
16
Zarlink Semiconductor Inc.
Le5711
6.16
Data Sheet
DC Feed Characteristics
Load Line (Typical)
Vbat = -48V
2a
2b
3b
Vbat = -42V
On-Hook
Switch-hook Threshold:
3a
Vbat = -38V
1
Off-Hook
150
I SWTH = -------------R REF
R REF = 15 k
Regions:
1.
Constant current region:
 450 
V AB1 = I L R L' = -------------- R L' , where RL' = R L + 2R F
R REF
2a. Battery-independent anti-sat (Off-hook):
V AB2a = 43.6 V – I L 303 
2b. Battery-independent anti-sat (On-hook):
V AB2b = V AB2a – 3.5 V
3a. Battery tracking anti-sat (Off-hook):
V AB3a = V BAT – 1.8 V – I L 111 
3b. Battery tracking anti-sat (On-hook):
V AB3b = V AB3a – 0.33  V BAT + 10.8
17
Zarlink Semiconductor Inc.
Le5711
Data Sheet
IREF
A (TIP)
RREF
a
RL
IL
SLIC
b
CDC
B (RING)
CDC
Figure 2 - Feed Programming
6.17
Test Circuits
VTX 1
VTX 2
A 1, A 2 (TIP)
RL
SLIC
2
V AB
VL
RT
AGND
RL
RRX
2
B 1, B 2 (RING)
RSN 1
RSN 2
IL2-4 = 20 log(V TX / V AB )
Figure 3 - Two-to-Four Wire Insertion Loss
A 1, A 2 (TIP)
VTX 1
VTX 2
SLIC
V AB
RT
RL
AGND
RRX
B 1, B 2 (RING)
RSN 1
RSN 2
IL4-2 = 20 log(V AB / V RX )
V RX
BRS = 20 log(V TX / V RX )
Figure 4 - Four-to-Two Wire Insertion Loss and Balance Return Signals
18
Zarlink Semiconductor Inc.
Le5711
1
ωC
VTX 1
VTX 2
A1, A 2 (TIP)
<< RL
RL
2
S1
Data Sheet
SLIC
C
VL
RT
VAB
AGND
VL
RL
S2
2
RRX
RSN 1
B1, B 2 (RING) RSN 2
VRX
S2 Open, S1 Closed
S2 Closed, S1Open
L-T Long. Bal. = 20 log(V AB / V L)
4-L Long. Sig. Gen. = 20 log(V L / V RX )
L-4 Long. Bal. = 20 log(3V TX / V L)
Figure 5 - Longitudinal Balance
ZD = 600 Ω
VTX 1
VTX 2
A1, A 2 (TIP)
RT
2
RTA
SLIC
R
VM
VS
AGND
ZIN = 600 Ω
R
RTB
RT
2
CT = 120 pF
RSN 1
B1, B 2 (RING) RSN
2
ZD : The desired impedance;
eg., the characteristic impedance of the line
RRX = 124 K
Return loss = –20 log (2V M / V S )
Figure 6 - Two-Wire Return Loss Test Circuit
L1
200Ω
C1
50Ω
A 1, A 2 (TIP)
RF 1
200Ω
HF
GEN
50 Ω
CAX
RF 2
50Ω
C2
L2
B 1, B 2 (RING)
CBX
VTX 1
VTX 2
SLIC
under test
80% amplitude modulated
Modulation frequency = 1 kHz
Figure 7 - RFI Test Circuit
19
Zarlink Semiconductor Inc.
Le5711
Data Sheet
VCC
+5V
BGND 1,2
DB 1
DB 1
VCC RSVD 1,2
Le5711
AGND/
DGND
VTX 1
VTX 1
RT1 100 kΩ
CAX 1
2.2 nF
TIP 1
RSN 1
A1 (TIP)
HP 1
CHP1
RRX1
CDC 1
CH1
1.5 µF
100 nF
RING 1
B1 (RING)
CBX1
2.2 nF
1600 Ω
BAT
1600 Ω
CDC1
DET 1
RTMG1
DVBH
VRX 1
150 kΩ
DET 1
C1 1
C1 1
C2 1
C2 1
TMG 1
IREF
VBAT
CAS
RREF
15 kΩ
CCAS
0.33 µF
TMG 2
RTMG2
DB 2
VTX 2
DB 2
DAC
VTX 2
RT2 100 kΩ
DAC
RRX2
RSN 2
CAX2
2.2 nF
CH2
A2 (TIP)
TIP 2
CHP2
CBX2
2.2 nF
150 kΩ
CDC 2
CDC2
1.5 µF
HP 2
100 nF
RING 2
VRX 2
B2 (RING)
DET 2
DET 2
C1 2
C1 2
C2 2
C2 2
RL, R LAC = 600 Ω
ILOOP = 30 mA
BAT = - 52 V
Figure 8 - Le5711 Test Circuit
20
Zarlink Semiconductor Inc.
Le5711
7.0
Data Sheet
Application Circuit
VBAT
RING_SOURCE
RR2
400 Ω
RR1
400 Ω
RSR3
1.82 MΩ
RSR1
1.82 MΩ
RTH1
1 MΩ
20 MΩ
RDAC
DAC
Q1
RSR4
2 MΩ
RSR2
2 MΩ
CRT2
47 nF
RTH2
909 kΩ
CTH
100 nF
Shared between 4
DSLIC packages
CRT1
47 nF
RS1
DB1
RS2
DB2
VCC
+5V
BGND1,2
DB1
50 Ω
22 nF
CP
RING1
CHP1
100 nF
1/2
U2
100 nF
RR1
AGND/
DGND
U1
Le5711
0.01 µF
VTX1
RT1
HP1
CDC1
CH1
RHP1
15 kΩ
RF1B
50 Ω
RSN1
A1 (TIP)
RR1
RR1
BAT
VCC RSVD1,2
CAX1
RF1A
TIP1
DB1
B1 (RING)
DVBH
2.49 kΩ
RTMG2
124 kΩ
VRX1
CDC1
DET1
C11
C11
C21
C21
TMG1
IREF
VBAT
CAS
RREF
15 kΩ
CCAS
TMG2
2.49 kΩ
0.1 µF
CRSN1
DET1
RTMG1
BAT
RRX1
VTX1
1.5 µF
CBX1
22 nF
RS1
CTX1
83.3 kΩ
330 nF
0.01 µF
DB2
DB2
DAC
DAC
BAT
CP
RING2
50 Ω
CH2
RR2
U3
1/2
U2
CDC2
CHP2
100 nF
RHP2
15 kΩ
RF2B
50 Ω
83.3 kΩ CTX2
0.1 µF
RRX1
124 kΩ
CRSN2
VTX2
VRX2
CDC2
1.5 µF
HP2
B2 (RING)
CBX2
22 nF
RS2
RSN2
A2 (TIP)
100 nF
RR2
RT1
CAX2
22 nF
RF2A
TIP2
VTX2
RLAC = 600 Ω
ILOOP = 30 mA
ANALOG
GROUND
BAT = - 52 V
21
Zarlink Semiconductor Inc.
DET2
DET2
C12
C12
C22
C22
BATTERY
GROUND
DIGITAL
GROUND
Le5711
8.0
Data Sheet
Line card Parts List
The following list defines the parts and part values required to meet target specification limits for channel i of the line
card (i = 1,2).
Item
Quantity
Type
Value
Tol.
Rating
CAX1, CBX1,
CAX2, CBX2
4
Capacitor (X7R)
22 nF
20%
100 V
CHP1, CHP2, CP
3
Capacitor (X7R)
100 nF
20%
100 V
Capacitor (X7R)
100 nF
20%
50 V
CTH
CRT1, CRT2
2
Capacitor (X7R)
47 nF
20%
50 V
CDC1, CDC2
2
Capacitor (X7R)
1.5 µF
20%
5V
CTX1, CTX2
2
Capacitor (X7R)
0.01 µF
20%
5V
CRSN1, CRSN2
2
Capacitor (X7R)
0.1 µF
20%
5V
RF1A, RF1B,
RF2A, RF2B
2
PTC or Fusible
50 
RREF
1
SMT
15 k
1%
1/10 W
RT1, RT2
2
SMT
83.3 k
1%
1/10 W
RRX1, RRX2
2
SMT
124 k
1%
1/10 W
RHP1, RHP2
2
SMT
15 k
1%
1/10 W
DVBH
1
MURS 120 (D0-41)
DIODE
RR1, RR2
2
SMT
400 
5
1W
U2
1
TISP6NTP2A
RSR2, RSR4
2
SMT
2 M
1%
1/10 W
RSR1, RSR3
2
SMT
1.82 M
1%
1/10 W
U1
1
Le5711 device
RTMG1 RTMG2
2
SMT
1.8 k
5%
1W
CCAS
1
Capacitor (X7R)
330 nF
20%
100 V
RTH1
*
SMT
1 M
1%
1/10 W
RTH2
*
SMT
909 k
1%
1/10 W
RDAC
*
SMT
20 M
5%
1/10 W
Q1
*
NPN
BC639
Comments
50 V
Note:
1.
* Shared between four DualSLIC device packages
2.
Refer to the Thermal Management for the Le5711 and Le5712 Dual Devices Application Note for particular conditions.
22
Zarlink Semiconductor Inc.
Note
1
2
Le5711
9.0
Physical Dimensions
9.1
44-Pin eTQFP
Symbol
A
A1
A2
D
D1
E
E1
R2
R1
Ө
Ө 1
Ө 2
Ө 3
Min
0.05
0.95
0.08
0.08
0 deg
0 deg
11 deg
11 deg
Nom
1.00
12 BSC
10 BSC
12 BSC
10 BSC
3.5 deg
12 deg
12 deg
Max
1.20
0.15
1.05
0.20
7 deg
13 deg
13 deg
Symbol
c
L
L1
S
b
e
D2
E2
aaa
bbb
ccc
ddd
N
Data Sheet
Min
0.09
0.45
0.20
0.17
Nom
0.60
1.00 REF
0.20
0.80 BSC
8.00
8.00
0.20
0.20
0.10
0.20
44
Max
0.20
0.75
0.27
Notes:
1. Controlling dimension in millimeter unless otherwise specified.
2. Dimensions “D1” and “E1” do not include mold protrusion. Allowable protrusion is
0.25mm per side.
“D1” and “E1” are maximum plastic body size dimensions including mold mismatch.
3. Dimension “b” does not include Dambar protrusion. Allowable Dambar protrusion
shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08mm.
4. Dambar can not be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages.
5. Square dotted line is E-Pad outline.
6. “N” is the total number of terminals.
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing.
23
Zarlink Semiconductor Inc.
Le5711
Data Sheet
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
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This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
trademarks of Zarlink Semiconductor Inc.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
24
Zarlink Semiconductor Inc.