IC Card Interface ICs IC card interface ICs with Built-in DC / DC Converter BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F No.09056EAT02 ●Overview BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV and BD8907F are an interface IC for a 3V or 5V smart card. It works as a bidirectional signal buffer between a smart card and a controller. Also, it supplies 3V or 5V power to a smart card. With electrostatic breakdown voltage of more than HBM: ±6000V, it protects the card contact pins. ●Features 1) 3 half duplex bidirectional buffers 2) Protection against short-circuit for all the card contact pins 3) Card power source (VREG) of 3V or 5V 4) Overcurrent protection for card power source 5) Built-in thermal shutdown circuit 6) Built-in supply voltage detector 7) Automatic start-up/shutdown sequence function for card contact pin Start-up sequence: driven by a signal from controller (CMDVCCB↓) Shutdown sequence: driven by a signal from controller (CMDVCCB↑) and fault detection (card removal, short circuit of card power, IC overheat detection, VDD or VDDP drop) 8) Card contact pin ESD voltage ≧ ±6000V 9) 2MHz - 26MHz integrated crystal oscillator 10) Programmable for clock division of output signal by 1, 1/2, 1/4, and 1/8 11) RST output control by RSTIN input signal (positive output) 12) One multiplexed card status output by OFFB signal ●Line up matrix Input Voltage Resistor to set VDD voltage detector VDD VDDP Operating temperature Package BD8904F External 2.7V - 5.5V 3.0V - 5.5V -40°C - +85°C SOP28 BD8904FV External 2.7V - 5.5V 3.0V - 5.5V -40°C - +85°C SSOP-B28 BD8905F External 2.7V - 5.5V 3.0V - 5.5V -25°C - +85°C SOP28 BD8906F Built-in 3.0V - 5.5V 3.0V - 5.5V -25°C - +85°C SOP28 Part No. BD8906FV Built-in 3.0V - 5.5V 3.0V - 5.5V -25°C - +85°C SSOP-B28 BD8907F Built-in 3.0V - 5.5V 3.0V - 5.5V -40°C - +85°C SOP28 ●Application Interface for smart cards Interface for B-CAS cards www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/15 2009.07 - Rev.A Technical Note BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F ●Absolute maximum ratings (Ta=25°C) Parameter Symbol Rating Unit VDD VDDP VIN VOUT VREG Vn Tjmax Tstg -0.3 - 6.5 -0.3 - 6.5 V V -0.3 - +6.5 V -0.3 - +6.5 -0.3 - +14.0 +150 -55 - +150 V V °C °C VDD Input Voltage VDDP Input Voltage I/O Pin Voltage Card Contact Pin Voltage Charge Pump Pin Voltage Junction Temperature Storage Temperature BD8904F BD8905F BD8906F Power Dissipation BD8907F BD8904FV BD8906FV Note Pin : XTAL1, XTAL2, VSEL, RSTIN, AUX1C, AUX2C, IOC, CLKDIV1, CLKDIV2, CMDVCCB, OFFB, PORADJ, S2 Pin : PRES, PRESB, CLK, RST, IO, AUX1, AUX2 Pin : VCH, S1 Ta=-40 - +85°C Ta=-25 - +85°C Ta=-25 - +85°C Ta=-40 - +85°C Ta=-40 - +85°C Ta=-25 - +85°C 750 mW Ptot 1060 * Refer to the following package power dissipation •This product is not designed to be radiation tolerant. •Absolute maximum ratings are not meant for guarantee of operation. ●Operating Conditions Parameter Symbol Operating temperature Topr VDD Input Voltage VDD VDDP Input Voltage VDDP MIN -40 -25 2.7 3.0 4.5 3.0 3.1 3.0 3.0 Limits TYP 5.0 5.0 MAX +85 +85 5.5 5.5 5.5 4.5 4.5 3.1 5.5 Unit °C °C V V V V V V V Note BD8904F, BD8904FV, BD8907F BD8905F,BD8906F, BD8906FV BD8904F, BD8904FV, BD8905F BD8906F,BD8906FV, BD8907F VREG=5V; Ivreg ≤ 60mA VREG=5V; Ivreg ≤ 20mA, Except BD8904FV VREG=5V; Ivreg ≤ 25mA, Application to BD8904FV VREG=5V; Ivreg ≤ 20mA, Application to BD8904FV VREG=3V; Ivreg ≤ 60mA ●Package Power Dissipation The power dissipation of the package will be as follows in case that ROHM standard PCB is used. Use of this device beyond the following the power dissipation may cause permanent damage. BD8904F, BD8905F, BD8906F, BD8907F: Pd=750mW; BD8904FV, BD8906FV : Pd=1060mW; however, reduce 6mW per 1°C when used Ta≥25°C. however, reduce 8.5mW per 1°C when used Ta≥25°C. 3 ROHM standard PCB: Size: 70×70×1.6 (mm ), Material: FR4 glass epoxy board (copper plate area of 3% or less) 0.8 1.2 1.1 0.7 1.0 0.6 0.9 0.8 0.5 Pd [W] Pd [W] 0.7 0.4 0.6 0.5 0.3 0.4 0.2 0.3 0.2 0.1 0.1 0.0 0.0 -40 -20 0 20 40 60 80 100 120 140 160 -40 Ta [℃] www.rohm.com 0 20 40 60 80 100 120 140 160 Ta [℃] Fig. 1 Power Dissipation of BD8904F, BD8905F, BD8906F, BD8907F © 2009 ROHM Co., Ltd. All rights reserved. -20 Fig. 2 Power Dissipation of BD8904FV, BD8906FV 2/15 2009.07 - Rev.A Technical Note BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F ●Block Diagram 2.7V - 5.5V 3.0V - 5.5V VDD VDDP REF CHGPUMP S1 VREF VREF VDD CHARGE PUMP doubler doubler DETREF R1 PGND VDD PORADJ S2 VDET VREF R2 VCH VDD 2.7MHz OSC VDD LVS EN1 VDD VREF TSD ALARM CLKUP VSEL POWER_ON ALARM TSD EN2 LVS VREG OFFB CARD REG RSTIN EN5 LVS CMDVCCB CGND VCC ALARM RST BUF RST LVS SEQUENCER 3V/5V CLK BUF CLK EN CLKDIV1 CLK DIV CLKDIV2 EN4 CLK VDD PRES XT OSC 2MHz - 26MHz AUX1C VDD MAX 1MHz VREG IO TRANS VDD MAX 1MHz IO TRANS VDD MAX 1MHz AUX2 VREG LVS IOC AUX1 VREG LVS AUX2C VDD PRESB LVS XTAL2 VDD EN3 XTAL1 IO TRANS IO GND Fig. 3 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/15 2009.07 - Rev.A BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F ●Pin Description Pin No. Pin Name I/O Signal Level Technical Note Pin Function 1 CLKDIV1 I VDD Clock frequency selection input 1 2 CLKDIV2 I VDD Clock frequency selection input 2 3 VSEL I VDD Card supply voltage selection input; “H”: VREG=5V, “L”: VREG=3V 4 PGND S GND GND for charge pump 5 S2 I/O - 6 VDDP S VDDP 7 S1 I/O - 8 VCH I/O - 9 PRESB I VDD 10 PRES I VDD 11 IO I/O VREG Card contact I/O data line; Pulled up to VREG with a 11kΩ resistor 12 AUX2 I/O VREG Card contact I/O data line; Pulled up to VREG with a 11kΩ resistor 13 AUX1 I/O VREG Card contact I/O data line; Pulled up to VREG with a 11kΩ resistor 14 CGND S GND 15 CLK O VREG Card clock output 16 RST O VREG Card reset output 17 VREG O VREG Card supply voltage; Connect a capacitor (ESR < 100mΩ) of 100nF 220nF between VREG and CGND 18 (BD8904F) (BD8904FV) (BD8905F) 18 (BD8906F) (BD8906FV) (BD8907F) Capacitor connection for charge pump (between S1/S2): C = 100nF (ESR < 100mΩ) Power supply for charge pump Capacitor connection for charge pump (between S1/S2): C = 100nF (ESR < 100mΩ) Charge pump output: Decoupling capacitor; Connect C = 100nF (ESR < 100mΩ) between VCH and PGND Card presence contact input (active “L”) When PRES or PRESB is active, the card is considered ‘present’ and a built-in debounce feature of 8ms (typ.) is activated. Pulled up to VDD with a 2MΩ resistor. Card presence contact input (active “H”) When PRES or PRESB is active, the card is considered ‘present’ and a built-in debounce feature of 8ms (typ.) is activated. Pulled down to GND with a 2MΩresistor. GND Power-on reset threshold adjustment voltage input ; set with an external resistor bridge PORADJ I Normally used OPEN. Input voltage range: 0V - VDD voltage Can also be used at VDD or GND potential. TEST 19 CMDVCCB I VDD Activation sequence command input; The activation sequence starts by signal input (H→L) from the host 20 RSTIN I VDD Card reset signal input 21 VDD S VDD Input power source pin 22 GND S GND GND 23 OFFB O VDD Alarm output pin (active “L”) NMOS output pulled up to VDD with a 20kΩ resistor 24 XTAL1 I VDD Crystal connection or input for external clock 25 XTAL2 O VDD Crystal connection (leave open pin when external clock source is used) 26 IOC I/O VDD Host data I/O line; Pulled up to VDD with a 11kΩ resistor 27 AUX1C I/O VDD Host data I/O line; Pulled up to VDD with a 11kΩ resistor 28 AUX2C I/O VDD Host data I/O line; Pulled up to VDD with a 11kΩ resistor www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/15 2009.07 - Rev.A BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F ●Pin Function Diagram Pin Pin Name No. 1 CLKDIV1 2 CLKDIV2 3 VSEL 4 PGND 5 Pin Function Diagram VDDP 7 S1 8 VCH 9 PRESB Pin Name 10 PRES 11 IO 12 AUX2 13 AUX1 14 CGND 15 CLK 16 RST Pin Function Diagram -------------------------- S2 6 Pin No. Technical Note -------------------------- www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 5/15 -------------------------- 2009.07 - Rev.A BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F Pin No. Pin Name Pin No. Pin Name 17 VREG 23 OFFB PORADJ 24 XTAL1 TEST 25 XTAL2 26 IOC 27 AUX1C 28 AUX2C Pin Function Diagram Technical Note Pin Function Diagram 18 19 20 CMDVCC B RSTIN 21 VDD -------------------------- 22 GND -------------------------- www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/15 2009.07 - Rev.A Technical Note BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F ●Package For “XX” in the product name below, substitute 04 for BD8904, 05 for BD8905, 06 for BD8906 and 07 for BD8907. Package Name: SOP28 (Max. dimension including burr: 18.85) BD89XXF Lot No 1PIN MARK (UNIT : mm) Fig. 4 SOP28 Package Outer Dimension Package Name: SSOP-B28 (Max. dimension including burr: 10.35) BD89XXFV Fig. 5 SSOP-B28 Package Outer Dimension www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/15 2009.07 - Rev.A BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F Technical Note ●Function 1) Power Supply Power supply pins are VDD and VDDP. Set VDD at the same voltage as the signal from the system controller. VDDP and PGND are the power source and GND for the charge pump circuit, respectively, and the power source for the card. The VSEL pin setting determines the supply voltage of 3V (VSEL: L) or 5V (VSEL: H) from the VREG pin to the card. 2) VDD input voltage detector By connecting the resistance bridge (R1, R2: Fig. 3) to the PORADJ pin, you can set the VDD supply voltage detector (VDETR, VDETF: Fig.5). Approximately 16ms (BD8904F/FV, BD8905F) or 8ms (BD8906F/FV, BD8907F) after VDD voltage becomes higher than VDETR (internal reset), power-on reset (alarm) will be cancelled and the IC will go into sleep mode until the CMDVCCB signal turns from H to L. The IC will initiate the shutdown sequence toward the card contact pin if VDD voltage is decreased below VDETF. Calculating resistance bridge R1 and R2 for supply voltage detector (Applicable to BD8904F, BD8904FV and BD8905F; excludes BD8906F, BD8906FV and BD8907F) The following equations can be used to calculate the alarm reset voltage (VDETR) and low voltage detection voltage (VDETF): Please ensure that VDETF is set at over 2.3V. ◆ PORADJ pin voltage at VDD startup: VDDTHR PORADJ pin voltage at VDD shutdown: VDDTHF R1 VDETR 1 VDD THR R2 R1 1 VDDTHF VDETF R2 Vth2+Vhys2 Vth2 VDD ALARM (internal signal) tW tW Power ON Input power drop Power OFF パワーオン 電源ドロップ パワーオフ tw = (BD8904F/FV, BD8905F): 16ms, (BD8906F/FV, BD8907F): 8ms Fig. 6 VDD Input Voltage Detection 3) Operation sequence 3-1) Wait mode When VDD voltage becomes higher than VDTER, power-on reset (alarm) is released and the IC will be in wait mode until the CMDVCCB signal turns from H to L. In this mode, the VDD supply voltage detector (VDET), thermal shutdown circuit (TSD), reference circuit (VREF), crystal oscillation circuit (XT OSC) and internal oscillator circuit (OSC) are activated. IOC, AUX1C and AUX2C are pulled up to VDD with an 11kΩ resistor and all the card contact pins are at Lo level. 3-2) Card insertion Card presence is detected by PRES pin or PRESB pin. When either of the PRES pin or PRESB pin is active, a card is assumed to be present. Table 1 PRES “High” active PRESB “Lo” active When a card is present in sleep mode, either one of the card presence identification pins, PRES (“H” active) or PRESB (“L” active) becomes active. OFFB will become “H” after approximately 8ms (debounce time). If a card is present before the VDD power source is applied and the internal reset is released, it is internally reset and OFFB becomes “H” after the debounce time. The PRES pin is pulled down to GND with a 2MΩ resistor and the PRESB pin is pulled up to VDD with a 2MΩ resistor. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/15 2009.07 - Rev.A Technical Note BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F 3-3) Activation sequence When OFFB is in the “High” state and the CMDVCCB signal from the controller turns from H to L, the activation sequence starts to activate each functional block in the following order: The RST outputs signals based on the RSTIN input, being reset approximately 200μsec after the CMDVCCB signal turns from H to L. The RSTIN input becomes effective approximately 300ns after I/O TRANS turns ON. If RSTIN becomes Lo after RSTIN becomes effective and before RST output is released, the CLK signal is output. If RSTIN is High when the RST output is released, the CLK signal is output as soon as the RST output is released. (Refer to Fig. 6-1, Fig. 6-2 and Fig. 6-3) CHARGE PUMP ON (VCH voltage output) ↓ CARDREG ON (VREG output) ↓ I/O TRANS ON (All I/O Bus: Pull-up) ↓________________________________________________ ↓ ↓ When RSTIN remains High until RST is released ↓ (RSTIN≠Always High) ↓(RSTIN=Always High) ↓ ↓ CLK BUF ON (CLK output) CLK, RST BUF ON (CLK output, RST release) ↓ RST BUF ON (RST release) [Activation sequence under different RSTIN input timings] CMDVCCB CMDVCCB VCH VCH VREFG VREFG ART I/O ART I/O CLK CLK Min:200ns RSTIN RSTIN RST RST IOUC IOUC t0 t1 t2 t3 t4 t5= tact t0 t1 Fig. 7 Activation sequence 1 t2 t3 t4 t5= tact Fig.8 Activation sequence 2 CMDVCCB VCH VREFG ART I/O CLK t1: VCH startup time = typ 21.4μs, (max. 30μs) t2: VREG startup time = typ 57μs, (max. 80μs) t3: I/O ON time = typ 116.2μs, (max. 150μs) t4: CLK output release time (t4-t3)= Min 200ns, (max. 450μs) RSTIN t5: RST release time (activation time) RST IOUC t0 t1 t2 t3 t4 = typ 187.4μs, (max. 240μs) t5= tact Fig.9 Activation sequence 3 (not supported by ISO7816-3) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/15 2009.07 - Rev.A Technical Note BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F 3-4) Deactivation sequence When the CMDVCCB input turns from L to H or the alarm signal (described later) is detected, the following deactivation sequence is initiated in the following order transitioning to the wait mode. RST BUF OFF (RST: Lo) ↓ CLK BUF OFF (CLK: Lo) ↓ I/O TRANS OFF (I/O Bus on the controller side: Pull-up) ↓ (I/O Bus on the card side: Lo) ↓ CARDREG OFF (VREG: Lo) ↓ CHARGE PUMP OFF CMDVCCB t11: CLK OFF time = typ. 11.9μs t12: I/O OFF time = typ. 23.7μs t13: Start time of VREG fall = typ. 35.6μs t14: Start time of VCH fall = typ. 118.5μs RST CLK I/O tde: Operational sequence completion time= Max. 100μs VREG VCH t11 t12 t13 tde t10 t14 Fig.10 Deactivation sequence 4) CHARGE PUMP The charge pump circuit is the power supply for CARD REG output. It activates when the CMDVCCB input turns from H to L. It functions as a voltage doubler or voltage follower by the VDDP voltage. The VCH output becomes a power source for the CARDREG circuit. As the charge pump circuit takes a high charge current, place two capacitors (one between S1-S2, and the other between VCH-PGND) as close as possible to the IC so that the ESR becomes less than 100mΩ. Also, place a capacitor between VDDP and PGND as close as possible to the IC so that the ESR becomes less than 100mΩ. 5) CARD REG CARD REG supplies power to the IC card through the VREG pin. The VREG output voltage can be switched between 3V and 5V by the VSEL pin setting. Table 2 VSEL pin setting VSEL VREG output voltage VDDP Input Voltage MAX current 0 1 3V 5V 3.0V ≤ VDDP ≤ 5.5V 60mA 3.0V ≤ VDDP < 4.5V 20mA 3.0V ≤ VDDP < 3.1V 20mA 3.1V ≤ VDDP < 4.5V 25mA 4.5V ≤ VDDP ≤ 5.5V 60mA Remark Except BD8904FV Application to BD8904FV This regulator has an over-current limiter circuit. It generates an internal alarm with a load current of approximately 140mA or more and enters into the deactivation sequence. Also, the output voltage is regarded as abnormal if it becomes less than 0.6V in the case where VREG is 3V or becomes less than 1V in the case where VREG is 5V, and the output current is shut off. At this point, an internal alarm signal is generated and the deactivation sequence is initiated. Connect a capacitor of 100nF, 220nF or 330nF between VREG and CGND as close as possible to the VREG pin, in order to reduce the output voltage variation as much as possible. Also, ensure that ESR is kept at less than 100mΩ. CARD REG output is also a power source for the CLK and RST output. Therefore, the CLK and RST output level is the same as the VREG output level. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/15 2009.07 - Rev.A BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F Technical Note 6) I/O data transitions Three data lines, IOC - IO, AUX1C - AUX1 and AUX2C - AUX2 transmit two-way data independently of each other. Pins for the controller side, IOC, AUX1C and AUX2C are pulled up with an 11kΩ resistor to High (VDD voltage) and card contact pins, IO, AUX1 and AUX2 are set to Lo until I/O TRANS becomes ON during the activation sequence. When I/O TRANS becomes On, IC becomes idle mode and all the I/O pins are pulled up with an 11kΩ. The IOC, AUX1C and AUX2C pins keep VDD voltage (High) and the IO, AUX1 and AUX2 pins go to’ VREG voltage (High). The pin which turns from H to L first becomes the master and the other output side becomes the slave between the pins on the controller side and card contact pins. Then the data are transferred from the master side to the slave side. When both signal levels become High, they become idle. When the signal transits from L to H and it passes over a threshold, an active pull-up (100 ns or less) works to drive the data High at high speed. After the active pull-up is completed, the pin is pulled up with an 11kΩ resistor. This function enables signal transmission up to 1MHz. Also, an over-current limiter of 15mA works in the card contact pins, IO, AUX1 and AUX2. 7) Card clock supply Card clock is supplied from the CLK pin divides the input frequency of XTAL1 pin by 1, 1/2, 1/4 and 1/8 with the CLKDIV1 and CLKDIV2 pin setting. The clock division switching time is within the 8 clocks of the XTAL1 signal (refer to Table 3). The input signal to the XTAL1 pin is made by a crystal oscillator (2MHz - 26MHz) between the XTAL1 pin and XTAL2 pin or external pulse signal. To ensure the duty factor of 45% - 55% at the CLK pin, the duty of the XTAL1 pin should be 48% - 52% and the transition time should be within 5% of the frequency. To guarantee a 45% - 55% duty, use it with a clock division of 1/2, 1/4 or 1/8 depending on the wiring layout on the PCB. Table 3 Clock frequency selection (fXTAL: Frequency of XTAL1) CLKDIV1 CLKDIV2 fclk 0 0 fXTAL 8 0 1 fXTAL 4 1 1 fXTAL 2 1 0 f XTAL 1 8) RSTIN input, RST output The RSTIN input becomes effective after the CMDVCCB signal input turns from H to L, activation sequence is initiated and approximately 300ns after I/O TRANS turns ON. The RST output is released in approximately 200μsec after the CMDVCCB signal turns from H to L to output signal based on the RSTIN input. 9) Fault detection When the following fault state is detected, the circuit enters the wait mode after it generates an internal alarm signal and is deactivated. If a card is not present, it remains in the wait mode. • • • • • When the VREG pin becomes less than 1V (VSEL=H) or 0.6V (VSEL=L), or is loaded high current(TYP: 150mA) When the VDD voltage is less than the threshold voltage (detected by supply voltage detector) When an overheating is detected by the thermal shutdown circuit When VCH pin voltage drops to an abnormal level When the card is removed during operation or the card is not present from the beginning (PRES=L and PRESB=H) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 11/15 2009.07 - Rev.A BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F Technical Note 10) OFFB output The OFFB output pin indicates that the IC is ready to operate. It is pulled up to VDD with a 20kΩ resistor. When the IC is in ready state, OFFB is High. The OFFB outputs OFF state (Lo) when a fault state is detected. When a card is present, the fault state is released and CMDVCCB becomes High, the internal alarm is released and the OFFB output becomes High. PRES OFFB CMDVCCB tdebounce tdebounce tdebounce = typ 8ms VREG Shutdown by card removal カード取り外しによる停止動作 Shutdown by short-circuiting of pins 端子ショート等による停止動作 Fig. 11 OFFB, CMDVCCB, PRES, VREG operation ●An example of software control スタート Start OFFB=H ? No (card not inserted) No（カード未挿入） Yes（カード検出） Yes (card detected) Error message 1 エラーメッセージ１ “Insert a card” 「カードを挿入してください」 Set CMDVCCB HL CMDVCCBをH→Lへ End 終了 アクティベーション開始 Initiate Activation ↓ DC/DC On (VCH) DC/DCオン（VCH） ↓ Regulator ON (VREG) レギュレータオン（VREG） ↓ IO Enabled (IO) IOイネーブル（IO） OFFB=L ? No alarm アラームなし Initiate card カード通信開始 communication RSTINをL→H Set RSTIN LH ↓ 完了 Completed Alarm detected アラーム検出 ・カード抜け Card removed ・過電流検出 Overcurrent detected Supply voltage drop ・電源電圧降下 Increased temperature ・温度上昇 Error message 2 エラーメッセージ２ “Error during communication” 「通信中にエラーが発生しました」 CMDVCCBをL→Hへ Turn CMDVCCB LH デアクティベーション開始 Initiate deactivation ↓ IOディセーブル（IO） IO disabled (IO) ↓ Regulator OFF (VREG) レギュレータオフ（VREG） ↓ DC/DC OFF (VCH) DC/DCオフ（VCH） デアクティベーション開始 Initiate deactivation ↓ IOディセーブル（IO） IO disabled (IO) ↓ Regulator OFF (VREG) レギュレータオフ（VREG） ↓ DC/DC OFF (VCH) DC/DCオフ（VCH） CMDVCCBをL→Hへ Set CMDVCCB LH *※LSIがホスト側でアラームを検出できた Ensure to set CMDVCCB LH to enable confirmation that LSI can detect ことを確認するため、 an alarm at the host side 必ずCMDVCCBをL→Hにしてください 終了 End 終了 End Fig. 12 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. An example of software control 12/15 2009.07 - Rev.A Technical Note BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F ●Application examples 100nF +5.0V 100nF 100nF CLKDIV1 CLKDIV2 VSEL PGND S2 VDDP S1 VCH PRESB PRES IO AUX2 AUX1 CGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 BD890XF 10μF +3.3V AUX2C AUX1C IOC 15pF 220Ω XTAL2 XTAL1 15pF OFFB GND VDD 100nF RSTIN +3.3V CMDVCCB PORADJ (TEST: BD8906F/FV, BD8907F) VREG VDD RST CLK 58.1KΩ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CONTROLLER 100nF 41.9KΩ CARD CONNECTION 0.22uF VDD C5 C1 C6 C2 C7 C3 C8 C4 * Pin 18 on BD8906F/FV, BD8907F is 100KΩ normally open. When PORADJ is not used K1 with BD8904F/FV,BD8905F, pull it up to K2 VDD. Fig. 13 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 13/15 2009.07 - Rev.A BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F Technical Note ●Function of pin 18 on different devices The function of pin 18 (PORADJ/TEST) for BD8904F/FV and BD8905F is different from BD8906F/FV and BD8907F; switched as indicated in the following diagram but the common chip is used. Internal resistance bridge for BD8906F/FV,BD8907F Switches to PORADJ pin connection for BD8904F/FV, BD8905F , and to internal resistance bridge connection for BD8906F/FV and BD8907F. Detector signal Pin18: PORADJ or TEST External resistance bridge for BD8904F/FV, BD8905F Switched to GND or VDD by a wire inside IC Fig. 14 ●Notes for use 1) Two capacitors for a charge pump should be placed as close as possible to the IC between S1 and S2 and between VCH and PGND so that the ESR becomes less than 100mΩ. 2) The capacitor for the VREG pin should be placed as close as possible to the IC between VREG and CGND so that the ESR becomes less than 100mΩ. 3) Connect capacitors of over 10μF+0.1μF between VDD and GND and between VDDP and GND as close as possible to the IC so that the ESR becomes less than 100mΩ to reduce the power line noise. We recommend the use of capacitors with the largest possible capacitance. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14/15 2009.07 - Rev.A Technical Note BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F ●Ordering part number B D 8 Part No. 9 0 4 F Part No. 8904,8905 8906,8907 V - Package F : SOP28 FV : SSOP-B28 E 2 Packaging and forming specification E2: Embossed tape and reel SOP28 <Tape and Reel information> 18.5 ± 0.2 (MAX 18.85 include BURR) 15 0.3MIN 7.5±0.2 9.9±0.3 28 1 Tape Embossed carrier tape Quantity 1500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 14 0.11 2.2±0.1 0.15 ± 0.1 0.1 1.27 0.4 ± 0.1 1pin Reel (Unit : mm) Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. SSOP-B28 <Tape and Reel information> 10 ± 0.2 (MAX 10.35 include BURR) 15 0.3Min. 1 Embossed carrier tape Quantity 2000pcs E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 14 0.15 ± 0.1 0.1 1.15 ± 0.1 Tape Direction of feed 5.6 ± 0.2 7.6 ± 0.3 28 0.1 0.65 0.22 ± 0.1 1pin (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Reel 15/15 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.07 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. 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