TDA8034T; TDA8034AT Smart card interface Rev. 2.0 — 12 November 2010 Product data sheet 1. General description The TDA8034T/TDA8034AT is a cost-effective analog interface for asynchronous and synchronous smart cards operating at 5 V or 3 V. Using few external components, the TDA8034T/TDA8034AT provides all supply, protection and control functions between a smart card and the microcontroller. 2. Features and benefits Integrated circuit smart card interface in an SO16 package 5 V or 3 V smart card supply One protected half-duplex bidirectional buffered I/O line (C7) VCC regulation: 5 V ± 5 % or 3 V ± 5 % using two low ESR multilayer ceramic capacitors: one of 220 nF and one of 470 nF current spikes of 40 nA/s (VCC = 5 V and 3 V) or 15 nA/s (VCC =1.8 V) up to 20 MHz, with controlled rise and fall times and filtered overload detection of approximately 120 mA Thermal and short-circuit protection for all card contacts Automatic activation and deactivation sequences triggered by a short-circuit, card take-off, overheating, falling VDD, VDD(INTF) or VDDP Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV External clock input up to 26 MHz connected to pin XTAL1 Card clock generation up to 20 MHz using pin CLKDIV1 with synchronous frequency changes of: 1∨2 fxtal or 1∨4 fxtal on TDA8034T fxtal or 1∨2 fxtal on TDA8034AT Non-inverted control of pin RST using pin RSTIN Compatible with ISO 7816, NDS and EMV 4.2 payment systems Supply supervisor for killing spikes during power on and off: using a fixed threshold using an external resistor bridge with threshold adjustment Built-in debouncing on card presence contacts (typically 4.5 ms) Multiplexed status signal using pin OFFN 3. Applications Pay TV Electronic payment TDA8034T; TDA8034AT NXP Semiconductors Smart card interface Identification Bank card readers 4. Quick reference data Table 1. Quick reference data VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VDDP power supply voltage pin VDDP 4.85 5 5.5 V VDD supply voltage pin VDD 2.7 3.3 3.6 V VDD(INTF) interface supply voltage pin VDD(INTF) 1.6 3.3 VDD + 0.3 V IDD supply current Shutdown mode - - 35 μA IDDP power supply current Shutdown mode; fxtal stopped - - 5 μA Active mode; fCLK = 1∨2 fxtal; no load - - 1.5 mA Shutdown mode - - 6 μA ICC < 65 mA DC 4.75 5.0 5.25 V current pulses of 40 nA/s at ICC < 200 mA; t < 400 ns 4.65 5.0 5.25 V Supply interface supply current IDD(INTF) Card supply voltage: pin VCC VCC [1] supply voltage active mode 5 V card Vripple(p-p) peak-to-peak ripple voltage from 20 kHz to 200 MHz - - 350 mV ICC supply current VCC = 0 V to 5 V or 3 V - - 65 mA tdeact deactivation time see Figure 7 on page 10 35 90 250 μs Ptot total power dissipation Tamb = −25 °C to +85 °C - - 0.25 W Tamb ambient temperature −25 - +85 °C General [1] To meet these specifications, VCC should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of either 100 nF or one 220 nF and one 470 nF. 5. Ordering information Table 2. Ordering information Type number TDA8034T Package Name Description Version SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TDA8034AT TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 2 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 6. Block diagram 10 μF 100 nF VDD 14 100 nF GND VDDP 9 13 SUPPLY INTERNAL REFERENCE VOLTAGE SENSE PRESN RSTIN CMDVCCN OFFN CLKDIV1 INTERNAL OSCILLATOR CLKUP EN1 ALARMN PVCC 7 VCC LDO 12 VCC 470 nF SEQUENCER EN4 5 15 LEVEL SHIFTER RESET GENERATOR 11 RST CLOCK GENERATOR 10 CLK EN3 6 CLOCK CIRCUITRY EN2 CLK CARD CONNECTOR CMDVCCN DETECTION THERMAL PROTECTION I/OUC 220 nF 4 16 CRYSTAL OSCILLATOR 3 1 I/O TRANSCEIVER 8 I/O C5 C1 C6 C2 C7 C3 C8 C4 TDA8034T TDA8034AT 2 VDD(INTF) 100 nF Fig 1. XTAL1 XTAL2 001aak989 Block diagram TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 3 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 7. Pinning information 7.1 Pinning XTAL1 1 16 I/OUC XTAL2 2 15 OFFN VDD(INTF) 3 14 VDD RSTIN 4 CMDVCCN 5 CLKDIV1 6 11 RST PRESN 7 10 CLK I/O 8 TDA8034T TDA8034AT 13 VDDP 12 VCC 9 GND 001aak990 Fig 2. Pin configuration (SO16) 7.2 Pin description Table 3. Pin description Symbol Pin Supply Type[1] Description XTAL1 1 VDD I crystal connection input XTAL2 2 VDD O crystal connection output VDD(INTF) 3 VDD(INTF) P interface supply voltage RSTIN 4 VDD(INTF) I microcontroller card reset input; active HIGH CMDVCCN 5 VDD(INTF) I microcontroller start activation sequence input; active LOW CLKDIV1 6 VDD(INTF) I sets the clock frequency on pin CLK; see Table 4 on page 7 PRESN 7 VDD(INTF) I card presence contact input; active LOW[2] I/O 8 VCC I/O card input/output data line (C7)[3] GND 9 - G ground CLK 10 VCC O card clock (C3) RST 11 VCC O card reset (C2) VCC 12 VCC P card supply (C1); decouple to pin GND using one 470 nF capacitor close to pin VCC and one 220 nF capacitor close to card socket contact C1 with an ESR < 100 mΩ[4] VDDP 13 VDDP P low-dropout regulator input supply voltage VDD 14 VDD P digital supply voltage OFFN 15 VDD(INTF) O NMOS interrupt to microcontroller[5]; active LOW; see Section 8.9 on page 10 I/OUC 16 VDD(INTF) I/O microcontroller input/output data line[6] [1] I = input, O = output, I/O = input/output, G = ground and P = power supply. [2] If pin PRESN is HIGH, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter this, the TDA8034T/TDA8034AT has a built-in debouncing timer (typically 4.5 ms). [3] Uses an internal 11 kΩ pull-up resistor connected to pin VCC. [4] Using a 220 nF capacitor increases the noise margin on pin VCC. TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 4 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface [5] Uses an internal 20 kΩ pull-up resistor connected to pin VDD(INTF). [6] Uses an internal 10 kΩ pull-up resistor connected to pin VDD(INTF). 8. Functional description Remark: Throughout this document the ISO 7816 terminology conventions have been adhered to and it is assumed that the reader is familiar with these. 8.1 Power supplies The power supply voltage ranges are as follows: • VDDP: 4.85 V to 5.5 V • VDD: 2.7 V to 3.6 V All interface signals to the system controller are referenced to VDD(INTF). All card contacts remain inactive during power up or power down. After powering up the device, pin OFFN remains LOW until pin CMDVCCN is set HIGH and pin PRESN is LOW. During power down, pin OFFN goes LOW when VDDP falls below the falling threshold voltage (Vth). The internal oscillator frequency (fosc(int)) is only used during the activation sequences. When the card is not activated (pin CMDVCCN is HIGH), the internal oscillator is in low frequency mode to reduce power consumption. This device has a Low Drop-Off (LDO) voltage regulator connected to pin VCC, and is used instead of a DC-to-DC converter. It ensures a minimum VCC of 4.75 V and that the power supply voltage on pin VDDP does not fall below 4.85 V for a maximum load current of 65 mA. 8.2 Voltage supervisor VDD(INTF) VDD VDD REFERENCE VOLTAGE VDDP 5 V or 3 V 001aak991 Fig 3. TDA8034T_TDA8034AT Product data sheet Voltage supervisor circuit All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 5 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface The voltage supervisor monitors the voltage of the VDDP and VDD supplies providing both Power-On Reset (POR) and supply drop-out detection during a card session. The supervisor threshold voltages for VDDP and VDD are set internally. As long as VDD is less than Vth + Vhys, the IC remains inactive irrespective of the command line levels. After VDD has reached a level higher than Vth + Vhys, the IC remains inactive for the duration of tw. The output of the supervisor is sent to a digital controller in order to reset the TDA8034T/TDA8034AT. This defined reset pulse of approximately 8 ms, i.e. (tw = 1024 × 1∨ fosc(int)low), is used internally to maintain the IC in the Shutdown mode during the supply voltage power on; see Figure 4. A deactivation sequence is performed when either VDD or VDDP falls below Vth. Remark: fosc(int)low is the low frequency (or inactive) mode of the defined fosc(int) parameter. Vth + Vhys Vth VDD ALARMN (internal signal) tw power on tw supply dropout power off 001aak993 Fig 4. Voltage supervisor waveforms 8.3 Clock circuits The clock signal from pin CLK to the card is either supplied by an external clock signal connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and XTAL2. The TDA8034T/TDA8034AT automatically detects if an external clock is connected to XTAL1, eliminating the need for a separate pin to select the clock source. Automatic clock source detection is performed on each activation command (falling edge of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is checked during a time window defined by the internal oscillator. If a clock is detected, the internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator is started. When an external clock is used, it is mandatory that the clock is applied to pin XTAL1 before the falling edge of the signal on pin CMDVCCN. TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 6 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface DIGITAL enclkin clkxtal MULTIPLEXER CRYSTAL XTAL1 XTAL2 001aak992 enclkin and clkxtal are internal signal names. Fig 5. Basic layout for using an external clock The clock frequency is selected using pin CLKDIV1 to be either 1∨2 fxtal or 1∨4 fxtal on TDA8034T or fxtal or 1∨2 fxtal on TDA8034AT as shown in Table 4. The frequency change is synchronous and as such during transition, no pulse is shorter than 45 % of the smallest period. In addition, only the first and last clock pulse around the change has the correct width. When dynamically changing the frequency, the modification is only effective after 10 clock periods on pin XTAL1. The duty cycle of fxtal on pin CLK should be between 45 % and 55 %. If an external clock is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %. When the frequency of the clock signal on pin CLK is either 1∨2 fxtal or 1∨4 fxtal on TDA8034T or fxtal or 1∨2 fxtal on TDA8034AT, the frequency dividers guarantee a duty cycle between 45 % and 55 %. Table 4. Clock configuration Pin CLKDIV1 level Pin CLK level TDA8034T TDA8034AT HIGH 1∨ f 2 xtal 1∨ f 2 xtal LOW 1∨ f 4 xtal fxtal 8.4 Input and output circuits When pins I/O and I/OUC are pulled HIGH using an 11 kΩ resistor between pins I/O and VCC and/or between pins I/OUC and VDD(INTF), both lines enter the idle state. Pin I/O is referenced to VCC and pin I/OUC to VDD(INTF), thus allowing operation at VCC ≠ VDD(INTF). The first side on which a falling edge occurs becomes the master. An anti-latch circuit disables falling edge detection on the other line, making it the slave. After a time delay td, the logic 0 present on the master-side is sent to the slave-side. When the master-side returns logic 1, the slave-side sends logic 1 during time delay (tw(pu)). After this sequence, both master and slave sides return to their idle states. The active pull-up feature ensures fast LOW-to-HIGH transitions making the TDA8034T/TDA8034AT capable of delivering more than 1 mA, up to an output voltage of 0.9VCC, at a load of 80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the internal pull-up resistor value and load current. The current sent to and received from the card’s I/O lines is limited to 15 mA at a maximum frequency of 1 MHz. TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 7 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 8.5 Shutdown mode After a power-on reset, if pin CMDVCCN is HIGH, the circuit enters the Shutdown mode, ensuring only the minimum number of circuits are active while the TDA8034T/TDA8034AT waits for the microcontroller to start a session. • all card contacts are inactive. The impedance between the contacts and GND is approximately 200 Ω. • • • • pin I/OUC is high-impedance using the 11 kΩ pull-up resistor connected to VDD(INTF) the voltage generators are stopped the voltage supervisor is active the internal oscillator runs at its lowest frequency (fosc(int)low) 8.6 Activation sequence The following device activation sequence is applied when using an external clock; see Figure 6: 1. Pin CMDVCCN is pulled LOW (t0). 2. The internal oscillator is triggered (t0). 3. The internal oscillator changes to high frequency (t1). 4. VCC rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2). 5. Pin I/O is driven HIGH (t3). 6. The clock on pin CLK is applied to the C3 contact (t4). 7. Pin RST is enabled (t5). Calculation of the time delays is as follows: • • • • • t1 = t0 + 384 × 1∨fosc(int)low t2 = t1 t3 = t1 + 17T / 2 t4 = driven by host controller; > t3 and < t5 t5 = t1 + 23T / 2 Remark: The value of period T is 64 times the period interval of the internal oscillator at high frequency (1∨fosc(int)high); t3 is called td(start) and t5 is called td(end). TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 8 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface CMDVCCN XTAL VCC I/O ATR CLK > 200 ns RSTIN RST I/OUC OSCINT low frequency t1 = t2 t0 high frequency t4 td(start) td(end) = tact 001aai966 OSCINT = internal oscillator. Fig 6. Activation sequence at t3 8.7 Deactivation sequence When a session ends, the microcontroller sets pin CMDVCCN HIGH. The TDA8034T/TDA8034AT then executes an automatic deactivation sequence by counting the sequencer back to the inactive state (see Figure 7) as follows: 1. Pin RST is pulled LOW (t11). 2. The clock is stopped, pin CLK is LOW (t12). 3. Pin I/O is pulled LOW (t13). 4. VCC falls to 0 V (t14). The deactivation sequence is completed when VCC reaches its inactive state. 5. VCC < 0.4 V (tdeac) 6. All card contacts become low-impedance to GND. However, pin I/OUC remains pulled up to VDD using the 11 kΩ resistor. 7. The internal oscillator returns to its low frequency mode. Calculation of the time delays is as follows: • • • • • TDA8034T_TDA8034AT Product data sheet t11 = t10 + 3T / 64 t12 = t11 + T / 2 t13 = t11 + T t14 = t11 + 3T / 2 tdeac = t11 + 3T / 2 + VCC fall time All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 9 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e. ± 25 μs). CMDVCC RST CLK I/O VCC XTAL1 OSCINT low frequency high frequency t10 t11 t12 t13 t14 tdeact 001aak995 OSCINT = internal oscillator. Fig 7. Deactivation sequence 8.8 VCC regulator The VCC buffer is able to continuously deliver up to 65 mA at VCC = 5 V or 3 V. The VCC buffer has an internal overload protection with a threshold value of approximately 120 mA. This detection is internally filtered, enabling spurious current pulses up to 200 mA with a duration of a few milliseconds to be drawn by the card without causing deactivation. However, the average current value must stay below maximum; see Table 8. 8.9 Fault detection The following conditions are monitored by the fault detection circuit: • • • • • • Short-circuit or high current on pin VCC Card removal during transaction VDDP falling VDD falling VDD(INTF) falling Overheating Fault detection monitors two different situations: • Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in the reader and HIGH if the card is in the reader. Any voltage drop on VDD is detected by the voltage supervisor. This generates an internal power-on reset pulse but does not act upon the pin OFFN signal. The card is not powered-up and short-circuits or overheating are not detected. TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 10 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface • In card sessions, pin CMDVCCN is LOW: when pin OFFN goes LOW, the fault detection circuit triggers the automatic emergency deactivation sequence (see Figure 8). When the microcontroller resets pin CMDVCCN to HIGH, after the deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN returns to HIGH. This check identifies the fault as either a hardware problem or a card removal incident. On card insertion or removal, bouncing can occur in the PRESN signal. This depends on the type of card presence switch in the connector (normally open or normally closed) and the mechanical characteristics of the switch. To correct for this, a debouncing feature is integrated in to the TDA8034T/TDA8034AT. This feature operates at a typical duration of 4.5 ms (tdeb = 640 × (1∨fosc(int)low). Figure 9 on page 12 shows the operation of the debouncing feature. On card insertion, pin OFFN goes HIGH after the debounce time has elapsed. When the card is extracted, the automatic card deactivation sequence is performed on the first HIGH/LOW transition on pin PRESN. After this, pin OFFN goes LOW. OFFN PRESN RST CLK I/O VCC XTAL OSCINT high frequency t10 Fig 8. TDA8034T_TDA8034AT Product data sheet t12 t13 tdeact low frequency t14 001aai971 Emergency deactivation sequence after card removal All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 11 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface PRESN OFFN CMDVCCN tdeb tdeb (1) VCC (2) 001aal411 (1) Deactivation caused by card withdrawal. (2) Deactivation caused by short-circuit. Fig 9. Operation of debounce feature with pins OFFN, CMDVCCN, PRESN and VCC 8.10 Automatic determining of card supply voltage The supply voltage (VCC) that the card requires is determined automatically by monitoring the duration of the HIGH state (logic 1) on pin CMDVCCN before the activation command (CMDVCCN falling edge) occurs. If pin CMDVCCN stays HIGH for more than 30 ms, activation occurs with VCC set to 5 V. If pin CMDVCCN stays HIGH for less than 15 ms, activation occurs with VCC set to 3 V. To activate the card at VCC = 5 V, pin CMDVCCN must stay HIGH for t0 > 30 ms before going LOW (logic 0). CMDVCCN t0 3 V or 5 V 5V VCC 001aak998 Fig 10. Card activation, VCC = 5 V, t0 > 30 ms To activate the card at VCC = 3 V, pin CMDVCCN must stay HIGH for t0 < 15 ms before going LOW (logic 0). CMDVCCN t0 3 V or 5 V VCC 3V 001aak999 Fig 11. Card activation, VCC = 3 V, t0 < 15 ms If pin CMDVCCN is HIGH for more than 15 ms (t0 > 15 ms) but less than 30 ms, pin CMDVCCN must be set LOW for t1 (200 μs < t1 < 700 μs), and then HIGH for t2 (200 μs < t2 < 15 ms) before going LOW. TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 12 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface CMDVCCN t0 t1 t2 3 V or 5 V 3V VCC 001aal000 Fig 12. Card activation, VCC = 3 V, t0 > 15 ms If pin CMDVCCN is HIGH for more than 30 ms (card inactive), and if the card needs to be activated at 3 V, the sequence shown in Figure 12 applies: pin CMDVCCN must be set LOW for t1 (200 μs < t1 < 700 μs), and then HIGH for t2 (200 μs < t2 < 15 ms) before going LOW. 9. Limiting values Remark: All card contacts are protected against any short-circuit to any other card contact. Stress beyond the levels indicated in Table 5 can cause permanent damage to the device. This is a short-term stress rating only and under no circumstances implies functional operation under long-term stress conditions. Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDDP power supply voltage pin VDDP −0.3 +6 V VDD supply voltage pin VDD −0.3 +4.6 V VDD(INTF) interface supply voltage pin VDD(INTF) −0.3 +4.6 V VI input voltage pins CMDVCCN, CLKDIV1, RSTIN, OFFN, XTAL1, XTAL2, I/OUC −0.3 +4.6 V card contact pins PRESN, I/O, RST and CLK −0.3 +6 V −55 +150 °C Tamb = −25 °C to +85 °C - 0.25 W Tstg storage temperature Ptot total power dissipation Tj junction temperature - +125 °C Tamb ambient temperature −25 +85 °C VESD electrostatic discharge voltage Human Body Model (HBM) on card pins I/O, RST, VCC, CLK, PRESN; within typical application −6 +6 kV Human Body Model (HBM); all other pins −2 +2 kV Machine Model (MM); all pins −200 +200 V Field Charged Device Model (FCDM); all pins −500 +500 V 10. Thermal characteristics Table 6. Thermal characteristics Symbol Package name Parameter Conditions Typ Unit Rth(j-a) SO16 thermal resistance from junction to ambient in free air 94 K/W TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 13 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 11. Characteristics Table 7. Characteristics of IC supply voltage VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply VDDP power supply voltage pin VDDP 4.85 5 5.5 V VDD supply voltage pin VDD 2.7 3.3 3.6 V VDD(INTF) interface supply voltage pin VDD(INTF) 1.6 3.3 VDD + 0.3 V IDD supply current Shutdown mode - - 35 μA IDDP power supply current Shutdown mode - - 5 μA - - 1.5 mA fCLK = 2 fxtal; ICC = 65 mA - - 70 mA IDD(INTF) interface supply current Shutdown mode - - 6 μA Vth threshold voltage pin VDD 2.30 2.40 2.50 V pin VDDP 3.00 4.10 4.40 V Vhys hysteresis voltage pin VDD 50 100 150 mV pin VDDP 100 200 350 mV 5.1 8 10.2 ms 550 - 830 nF no load −0.1 - +0.1 V Io = 1 mA −0.1 - +0.3 V - - −1 mA ICC < 65 mA DC 4.75 5.0 5.25 V current pulses of 40 nA/s at ICC < 200 mA; t < 400 ns 4.65 5.0 5.25 V ICC < 65 mA DC 2.85 3.05 3.15 V current pulses of 40 nA/s at ICC < 200 mA; t < 400 ns 2.76 - 3.20 V - - 350 mV fxtal stopped Active mode fCLK = 1∨2 fxtal; no load 1∨ tw pulse width Card supply voltage: pin VCC [1] Cdec decoupling capacitance connected to VCC Vo output voltage [2] Shutdown mode Io output current Shutdown mode; pin VCC connected to ground VCC supply voltage active mode 5 V card 3 V card Vripple(p-p) peak-to-peak ripple voltage ICC supply current TDA8034T_TDA8034AT Product data sheet 20 kHz to 200 MHz VCC = 0 V to 5 V or 3 V - - 65 mA VCC shorted to ground 90 120 150 mA All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 14 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface Table 7. Characteristics of IC supply voltage …continued VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit SR slew rate 5 V card 0.055 0.180 0.300 V/μs 3 V card 0.040 0.180 0.300 V/μs Crystal oscillator: pins XTAL1 and XTAL2 Cext external capacitance pins XTAL1 and XTAL2 (depending on the crystal or resonator specification) - - 15 pF fxtal crystal frequency card clock reference; crystal oscillator 2 - 26 MHz fext external frequency external clock on pin XTAL1 0 - 26 MHz VIL LOW-level input voltage crystal oscillator −0.3 - +0.3VDD V external clock −0.3 - +0.3VDD(INTF) V VIH HIGH-level input voltage crystal oscillator 0.7VDD - VDD + 0.3 V external clock 0.7VDD(INTF) - VDD(INTF) + 0.3 V falling edge on pins I/O and I/OUC or vise versa - - 200 ns 200 - 400 ns Data lines: pins I/O and I/OUC td delay time tw(pu) pull-up pulse width fio input/output frequency on data lines - - 1 MHz Ci input capacitance on data lines - - 10 pF no load 0 - 0.1 V Io = 1 mA Data lines to the card: pin I/O[3] Vo output voltage Shutdown mode 0 - 0.3 V Io output current Shutdown mode; pin I/O grounded - - −1 mA VOL LOW-level output voltage IOL = 1 mA 0 - 0.3 V IOL ≥ 15 mA VCC − 0.4 - VCC V VOH HIGH-level output voltage no DC load 0.9VCC - VCC + 0.1 V IOH < −40 μA 0.75VCC - VCC + 0.1 V IOH ≥ −15 mA 0 - 0.4 V −0.3 - +0.8 V VCC = +5 V 0.6VCC - VCC + 0.3 V VCC = +3 V 0.7VCC - VCC + 0.3 V VIL LOW-level input voltage VIH HIGH-level input voltage Vhys hysteresis voltage - 50 - mV IIL LOW-level input current pin I/O; VIL = 0 V - - 600 μA IIH HIGH-level input current pin I/O; VIH = VCC - - 10 μA tr(i) input rise time VIL maximum to VIH minimum - - 1.2 μs tr(o) output rise time CL ≤ 80 pF; 10 % to 90 %; 0 V to VCC - - 0.1 μs TDA8034T_TDA8034AT Product data sheet pin I/O All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 15 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface Table 7. Characteristics of IC supply voltage …continued VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tf(i) input fall time VIL maximum to VIH minimum - - 1.2 μs tf(o) output fall time CL ≤ 80 pF; 10 % to 90 %; 0 V to VCC - - 0.1 μs Rpu pull-up resistance connected to VCC 7 9 11 kΩ Ipu pull-up current VOH = 0.9VCC; C = 80 pF −8 −6 −4 mA Data lines to the system: pin I/OUC[4] VOL LOW-level output voltage IOL = 1 mA 0 - 0.3 V VOH HIGH-level output voltage no DC load 0.9VDD(INTF) - VDD(INTF) + 0.1 V IOH ≤ 40 μA; VDD(INTF) > 2 V 0.75VDD(INTF) - VDD(INTF) + 0.1 V IOH ≤ 20 μA; VDD(INTF) < 2 V 0.75VDD(INTF) - VDD(INTF) + 0.1 V VIL LOW-level input voltage −0.3 - +0.3VDD(INTF) V VIH HIGH-level input voltage 0.7VDD(INTF) - VDD(INTF) + 0.3 V Vhys hysteresis voltage pin I/OUC - 0.14VDD(INTF) - V IIH HIGH-level input current VIH = VDD(INTF) - - 10 μA IIL LOW-level input current VIL = 0 V - - 600 μA Rpu pull-up resistance connected to VDD(INTF) 8 10 12 kΩ tr(i) input rise time VIL maximum to VIH minimum - - 1.2 μs tr(o) output rise time CL ≤ 30 pF; 10 % to 90 %; 0 V to VDD(INTF) - - 0.1 μs tf(i) input fall time VIL maximum to VIH minimum - - 1.2 μs tf(o) output fall time CL ≤ 30 pF; 10 % to 90 %; 0 V to VDD(INTF) - - 0.1 μs Ipu pull-up current VOH = 0.9VDD; C = 30 pF −1 - - mA Shutdown mode 100 150 200 kHz active state 2 2.7 3.2 MHz no load 0 - 0.1 V Io = 1 mA 0 - 0.3 V Internal oscillator fosc(int) internal oscillator frequency Reset output to the card: pin RST Vo output voltage Shutdown mode Io output current Shutdown mode; pin RST grounded - - −1 mA td delay time between pins RSTIN and RST; RST enabled - - 2 μs TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 16 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface Table 7. Characteristics of IC supply voltage …continued VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VOL LOW-level output voltage IOL = 200 μA; VCC = +5 V 0 - 0.3 V IOL = 200 μA; VCC = +3 V 0 - 0.2 V current limit IOL = 20 mA VCC − 0.4 - VCC V HIGH-level output voltage IOH = −200 μA 0.9VCC - VCC V current limit IOH = −20 mA 0 - 0.4 V tr rise time CL = 100 pF - - 0.1 μs tf fall time CL = 100 pF - - 0.1 μs no load 0 - 0.1 V Io = 1 mA VOH Clock output to the card: pin CLK Vo output voltage Shutdown mode 0 - 0.3 V Io output current Shutdown mode; pin CLK grounded - - −1 mA VOL LOW-level output voltage IOL = 200 μA 0 - 0.3 V current limit IOL = 70 mA VCC − 0.4 - VCC V VOH HIGH-level output voltage IOH = −200 μA 0.9VCC - VCC V 0 - 0.4 V - - 16 ns tr rise time current limit IOH = −70 mA CL = 30 pF [5] [5] tf fall time CL = 30 pF fCLK frequency on pin CLK operational δ duty cycle CL = 30 pF SR slew rate rise and fall; CL = 30 pF [5] - - 16 ns 0 - 20 MHz 45 - 55 % VCC = +5 V 0.2 - - V/ns VCC = +3 V 0.12 - - V/ns Control inputs: pins CLKDIV1 and RSTIN[6] VIL LOW-level input voltage −0.3 - 0.3VDD(INTF) V VIH HIGH-level input voltage 0.7 VDD(INTF) - VDD(INTF) + 0.3 V Vhys hysteresis voltage - 0.14 VDD(INTF) - IIL LOW-level input current VIL = 0 V - - 1 μA IIH HIGH-level input current - - 1 μA control input VIH = VDD(INTF) V Control input: pin CMDVCCN[6] VIL LOW-level input voltage −0.3 - 0.3VDD(INTF) V VIH HIGH-level input voltage 0.7VDD(INTF) - VDD(INTF) + 0.3 V Vhys hysteresis voltage - 0.14VDD(INTF) - V IIL LOW-level input current VIL = 0 V - - 1 μA IIH HIGH-level input current - - 1 μA TDA8034T_TDA8034AT Product data sheet control input VIH = VDD(INTF) All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 17 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface Table 7. Characteristics of IC supply voltage …continued VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit - - 100 Hz 5 V card; Figure 10 30 - - ms 3 V card; Figure 11, Figure 12 - - 15 ms fCMDVCCN frequency on pin CMDVCCN pulse width tw Card detection input[6][7] VIL LOW-level input voltage −0.3 - 0.3VDD(INTF) V VIH HIGH-level input voltage 0.7VDD(INTF) - VDD(INTF) + 0.3 V Vhys hysteresis voltage - 0.14VDD(INTF) - V IIL LOW-level input current 0 V < VIL < VDD(INTF) - - 5 μA IIH HIGH-level input current 0 V < VIH < VDD(INTF) - - 5 μA - 0.3 V pin PRESN OFFN output[8] VOL LOW-level output voltage IOL = 2 mA 0 VOH HIGH-level output voltage IOH = −15 μA 0.75VDD(INTF) - - V Rpu pull-up resistance connected to VDD(INTF) 16 24 kΩ 20 [1] To meet these specifications, VCC should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of either 100 nF or one 220 nF and one 470 nF. [2] Using decoupling capacitors of one 220 nF ± 20 % and one 470 nF ± 20 %. [3] Using the integrated 9 kΩ pull-up resistor connected to VCC. [4] Using the integrated 10 kΩ pull-up resistor connected to VDD(INTF). [5] The transition time and the duty factor definitions are shown in Figure 13 on page 19; δ = t1 / (t1 + t2). [6] Pins PRESN and CMDVCCN are active LOW; pin RSTIN is active HIGH; see Table 4 for states of pin CLKDIV1. [7] Pin PRESN has an integrated current source of 1.25 μA to VDD(INTF). [8] Pin OFFN is an NMOS drain, using an internal 20 kΩ pull-up resistor connected to VDD(INTF). Table 8. Protection characteristics Symbol Parameter Conditions Min Typ Max Unit IOlim output current limit pin I/O -15 - +15 mA pin VCC 135 175 225 mA pin CLK −70 - +70 mA pin RST −20 - +20 mA Isd shutdown current pin VCC 90 120 150 mA Tsd shutdown temperature at die - 150 - °C TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 18 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface Table 9. Timing characteristics Symbol Parameter Conditions Min Typ Max Unit tact activation time see Figure 9 on page 12 2090 - 4160 μs tdeact deactivation time see Figure 7 on page 10 35 90 250 μs td delay time CLK sent to card using an external clock td(start) = t3; see Figure 6 on page 9 2090 - 4112 μs td(end) = t5; see Figure 6 on page 9 2120 - 4160 μs 3.2 4.5 6.4 ms tdeb debounce time pin PRESN tr tf 90 % VOH 90 % (VOH + VOL) / 2 10 % 10 % VOL t1 t2 001aai973 Fig 13. Definition of output and input transition times 12. Application information MICROCONTROLLER VDD(INTF) VDD(INTF) C1 100 nF XTAL1 XTAL2 VDD(INTF) RSTIN CMDVCCN CLKDIV1 PRESN I/O TDA8034T TDA8034AT 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 CARD CONNECTOR C5 C1 C6 C2 C7 C3 C8 C4 I/OUC OFFN VDD VDDP C2 VDD VDDP 100 nF C3 100 nF VCC C4 10 μF RST CLK GND C6 220 nF C5 470 nF R4 0Ω 001aal003 Fig 14. Application diagram TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 19 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT109-1 (SO16) TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 20 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 21 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 16) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11 Table 10. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 11. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 16. TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 22 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 12. TDA8034T_TDA8034AT Product data sheet Abbreviations Acronym Description EMV Europay MasterCard VISA ESD ElectroStatic Discharge ESR Equivalent Series Resistor FCDM Field Charged Device Model HBM Human Body Model LDO Low Drop-Out MM Machine Model NMOS Negative-channel Metal-Oxide Semiconductor POR Power-On Reset All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 23 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 16. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA8034T_TDA8034AT v.2.0 20101112 Product data sheet - TDA8034T_TDA8034AT_1 Modifications: TDA8034T_TDA8034AT_1 TDA8034T_TDA8034AT Product data sheet • Table 3 “Pin description”: Table note [5] VDD changed into VDD(INTF) Table note [6] added IOUC, AUX1UC, AUX2UC referenced to new note [6] 20100205 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 - © NXP B.V. 2010. All rights reserved. 24 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 25 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 26 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 19. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Clock configuration . . . . . . . . . . . . . . . . . . . . . .7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .13 Thermal characteristics . . . . . . . . . . . . . . . . . .13 Characteristics of IC supply voltage . . . . . . . .14 Protection characteristics . . . . . . . . . . . . . . . .18 Timing characteristics . . . . . . . . . . . . . . . . . . .19 SnPb eutectic process (from J-STD-020C) . . .22 Lead-free process (from J-STD-020C) . . . . . .22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .23 Revision history . . . . . . . . . . . . . . . . . . . . . . . .24 TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 27 of 29 TDA8034T; TDA8034AT NXP Semiconductors Smart card interface 20. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration (SO16) . . . . . . . . . . . . . . . . . . . .4 Voltage supervisor circuit . . . . . . . . . . . . . . . . . . . .5 Voltage supervisor waveforms . . . . . . . . . . . . . . . .6 Basic layout for using an external clock. . . . . . . . .7 Activation sequence at t3. . . . . . . . . . . . . . . . . . . .9 Deactivation sequence . . . . . . . . . . . . . . . . . . . .10 Emergency deactivation sequence after card removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operation of debounce feature with pins OFFN, CMDVCCN, PRESN and VCC . . . . . . . . . . . . . . .12 Card activation, VCC = 5 V, t0 > 30 ms. . . . . . . . .12 Card activation, VCC = 3 V, t0 < 15 ms. . . . . . . . .12 Card activation, VCC = 3 V, t0 > 15 ms. . . . . . . . .13 Definition of output and input transition times . . .19 Application diagram . . . . . . . . . . . . . . . . . . . . . . .19 Package outline SOT109-1 (SO16) . . . . . . . . . . .20 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 TDA8034T_TDA8034AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0. — 12 November 2010 © NXP B.V. 2010. All rights reserved. 28 of 29 NXP Semiconductors TDA8034T; TDA8034AT Smart card interface 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 5 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 5 Clock circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Input and output circuits . . . . . . . . . . . . . . . . . . 7 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . 8 Activation sequence . . . . . . . . . . . . . . . . . . . . . 8 Deactivation sequence . . . . . . . . . . . . . . . . . . . 9 VCC regulator . . . . . . . . . . . . . . . . . . . . . . . . . 10 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 10 Automatic determining of card supply voltage 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal characteristics . . . . . . . . . . . . . . . . . 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information. . . . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Soldering of SMD packages . . . . . . . . . . . . . . 21 Introduction to soldering . . . . . . . . . . . . . . . . . 21 Wave and reflow soldering . . . . . . . . . . . . . . . 21 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Contact information. . . . . . . . . . . . . . . . . . . . . 26 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 November 2010 Document identifier: TDA8034T_TDA8034AT