TDA8025 IC card interface Rev. 01 — 6 April 2009 Product data sheet 1. General description The TDA8025 is a cost-effective analog interface for asynchronous smart cards operating at 3 V, 1.8 V or optionally, 1.2 V. Using few external components, the TDA8025 provides integrated supply, protection and control functions for a range of applications. 2. Features n n n n n n n n n n n n n n n Integrated circuit smart card interface 3 V, 1.8 V or 1.2 V smart card supply Low power consumption in inactive mode Three protected, half duplex, bidirectional buffered input/output lines (C4, C7 and C8) VCC regulation: u 3 V, 1.8 V or optionally 1.2 V at ± 5 % using one 220 nF and one 470 nF low ESR multilayer ceramic capacitor. u Current pulse handling for pulses of 40 nAs at VCC = 3 V, 15 nAs at VCC = 1.8 V or VCC = 1.2 V up to 20 MHz Thermal and short-circuit protection for all card contacts Automatic activation and deactivation sequences triggered by short-circuit, card take-off, overheating, falling VDD(INTF) and VDD(INTREGD) Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV Clock signal using the internal oscillator or an external crystal (≤ 26 MHz) connected to pin XTAL1 Card clock generation up to 20 MHz with synchronous frequency changes of fxtal, 1⁄ f 1 1 2 xtal, ⁄4 fxtal or ⁄8 fxtal using pins CLKDIV1 and CLKDIV2 Non-inverted control of pin RST using pin RSTIN NDS certified Supply supervisors during power on and off: u VDD(INTREGD) using a fixed threshold u VDD(INTF) using resistor bridge threshold adjustment Built-in debouncing on card presence contacts (typically 4.5 ms) Multiplexed status signal using pin OFFN 3. Applications n n n n Pay TV Electronic payment Identification Bank card readers TDA8025 NXP Semiconductors IC card interface 4. Quick reference data Table 1. Symbol Quick reference data Parameter Conditions Min Typ Max Unit regulator input supply voltage pin CONFIG = ground 3.6 5 5.5 V pin CONFIG = VDDI(REG); regulator is bypassed 3 3.3 3.6 V interface supply voltage pin CONFIG = ground 1.6 3.0 3.3 V pin CONFIG = VDDI(REG) and VDD(INTF) not connected to VDDI(REG) and VDD(INTREGD) 1.6 3.0 VDDI(REG) + 0.3 V pin CONFIG = VDDI(REG) with VDD(INTF) connected to VDDI(REG) and VDD(INTREGD) 3 3.3 3.6 V VDDI(REG) = 5 V; fxtal = stopped - - 300 µA VDDI(REG) = 5 V; fxtal = 10 MHz; fCLK = 1⁄8 fXTAL - - 2.5 mA Supplies VDDI(REG) VDD(INTF) IDDI(REG) regulator input supply current [1] inactive mode active mode VCC = 3 V; ICC = 65 mA - - 85 mA VCC = 1.8 V; ICC = 65 mA - - 85 mA VCC = 1.2 V; ICC = 30 mA - - 50 mA no load −0.1 - +0.1 V ICC = 1 mA −0.1 - +0.3 V ICC < 65 mA DC 2.85 3.05 3.15 V single current pulse −100 mA; 2 µs 2.76 3.05 3.20 V current pulses of 40 nAs at ICC < 200 mA; t < 400 ns 2.76 3.05 3.20 V 1.71 1.83 1.89 V Card supply voltage VCC supply voltage including ripple inactive mode active mode 3 V card: 1.8 V card: ICC < 65 mA DC single current pulse −100 mA; 2 µs 1.66 1.83 1.94 V current pulses of 15 nAs with ICC < 200 mA; t < 400 ns 1.66 1.83 1.94 V 1.2 V card: Vripple(p-p) peak-to-peak ripple voltage ICC < 30 mA DC 1.1 1.2 1.3 V single current pulse −100 mA; 2 µs 1.1 1.2 1.3 V current pulses of 15 nAs with ICC < 200 mA; t < 400 ns 1.10 1.2 1.3 V - - 350 mV pin VCC; 20 kHz to 200 MHz TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 2 of 38 TDA8025 NXP Semiconductors IC card interface Table 1. Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit ICC supply current 0 V to 3 V - - 65 mA 0 V to 1.8 V - - 65 mA 0 V to 1.2 V - - 30 mA slew rate up or down 0.02 0.14 0.26 V/µs tdeact deactivation time total sequence 35 80 100 µs Ptot total power dissipation Tamb = −25 °C to +85 °C - - 0.56 W Tamb ambient temperature −25 - +85 °C SR General [2] [1] To enable the microcontroller to provide the required maximum voltage input level on XTAL1, VDD(INTF) must not exceed VDD(INTREGD) + 0.3 V. See Section 8.1 on page 7 for specific limitations on the maximum VDD(INTF) voltage and Table 8 on page 23 for the limits of XTAL1. [2] See Figure 12 on page 18. 5. Ordering information Table 2. Ordering information Type number Package Name Description Version TDA8025HN HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 × 5 × 0.85 mm SOT617-1 TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 3 of 38 TDA8025 NXP Semiconductors IC card interface 6. Block diagram VDDI(REG) TEST2 10 µF GND 20 CONFIG 16 TEST4 TEST1 21 2 REGULATOR 3 32 TEST 24 TEST3 19 VDD(INTREGD) VDD(INTF) 10 µF SUPPLY R1 (1) VOLTAGE SENSE R2 PRES PRESN RSTIN CMDVCCN OFFN CLKDIV1 CLKDIV2 ENCLKIN VCC_SEL1 VCC_SEL2 INTERNAL OSCILLATOR INTERNAL REFERENCE PORADJ 25 100 nF TDA8025 CLKUP ALARMN 18 VCC EN1 10 VCC LOOP PVCC 14 CGND 470 nF 9 220 nF 22 SEQUENCER EN4 RESET GENERATOR 17 RST CLOCK GENERATOR 15 CLK 1 EN3 23 CLOCK CIRCUIT 6 INTERFACE 5 VDD(INTREGD) MULTIPLEXER 26 EN2 CLK THERMAL PROTECTION 7 Level shifter (VDD(INTF)) XTAL 8 OSCILLATOR (VDD(INTREGD)) 220 nF 4 27 28 29 30 I/O TRANSCEIVER 11 I/O I/O TRANSCEIVER 13 AUX1 I/O TRANSCEIVER 12 AUX2 C5 C1 C6 C2 C7 C3 C8 C4 31 100 nF XTAL1 VDD(INTF) XTAL2 AUX1UC I/OUC AUX2UC 001aai957 (1) Optional external resistor bridge. If this bridge is not needed, connect pin PORADJ to VDD(INTF). Fig 1. Block diagram TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 4 of 38 TDA8025 NXP Semiconductors IC card interface 7. Pinning information 25 PORADJ 26 ENCLKIN 27 XTAL2 28 XTAL1 29 I/OUC 30 AUX1UC terminal 1 index area 31 AUX2UC 32 TEST4 7.1 Pinning CMDVCCN 1 24 TEST3 TEST1 2 23 OFFN TEST2 3 22 RSTIN VDD(INTF) 4 CLKDIV2 5 21 VDDI(REG) 20 GND TDA8025 CONFIG 16 PRESN CLK 15 17 RST CGND 14 8 AUX1 13 VCC_SEL2 AUX2 12 19 VDD(INTREGD) 18 VCC I/O 11 7 9 6 PRES 10 CLKDIV1 VCC_SEL1 001aai958 Transparent top view Fig 2. Pin configuration (HVQFN32) 7.2 Pin description Table 3. Pin description Symbol Pin Type[1] Description CMDVCCN 1 I microcontroller start activation sequence input; active LOW TEST1 2 I test pin; connect to GND TEST2 3 I test pin; connect to GND VDD(INTF) 4 P interface supply voltage CLKDIV2 5 I sets the clock frequency; used together with pin CLKDIV1; see Table 4 on page 12 CLKDIV1 6 I sets the clock frequency; used together pin CLKDIV2; see Table 4 on page 12 VCC_SEL1 7 I optional 1.2 V selection control signal: active HIGH: VCC = 1.2 V active LOW: disables 1.2 V selection VCC_SEL2 8 I 3 V or 1.8 V selection control signal: active LOW: VCC = 3 V active HIGH: VCC = 1.8 V when pin VCC_SEL1 is active LOW PRESN 9 I card presence contact input; active LOW[2] PRES 10 I card presence contact input; active HIGH[2] I/O 11 I/O card input/output data line (C7)[3] AUX2 12 I/O card auxiliary 2 input/output data line (C8)[3] AUX1 13 I/O card auxiliary 1 input/output data line (C4)[3] TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 5 of 38 TDA8025 NXP Semiconductors IC card interface Table 3. Pin description …continued Symbol Pin Type[1] Description CGND 14 G card signal ground CLK 15 O card clock (C3) CONFIG 16 I 3.3 V or 5 V core regulator supply voltage selection; see Figure 3 on page 7 RST 17 O card reset (C2) VCC 18 P card supply (C1); decouple to pin CGND using one 470 nF and one 220 nF capacitor with an Equivalent Series Resistance (ESR) < 100 mΩ VDD(INTREGD) 19 P internally regulated supply voltage GND 20 G ground VDDI(REG) 21 P regulator input supply voltage RSTIN 22 I microcontroller card reset input; active HIGH OFFN 23 O NMOS interrupt to microcontroller[4]; active LOW; see Section 8.10 on page 19 TEST3 24 O test pin; do not connect to the application PORADJ 25 I power-on reset threshold adjustment input[4] ENCLKIN 26 I enable external clock on pin XTAL1; active HIGH XTAL2 27 O crystal connection pin; open when used with an external clock source XTAL1 28 I crystal connection pin; supply reference VDD(INTREGD) external clock input; supply reference VDD(INTF) I/OUC 29 I/O microcontroller input/output data line[4] AUX1UC 30 I/O microcontroller auxiliary 1 input/output data line[4] AUX2UC 31 I/O microcontroller auxiliary 2 input/output data line[4] TEST4 32 I test pin; connect to GND [1] I = input, O = output, I/O = input/output, G = ground and P = power supply. [2] If pin PRESN or pin PRES is true, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter this, the TDA8025 has a built-in debouncing timer (typically 4.5 ms). [3] Using the internal pull-up resistor connected to pin VCC. [4] Using the internal pull-up resistor connected to pin VDD(INTF). TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 6 of 38 TDA8025 NXP Semiconductors IC card interface 8. Functional description Remark: Throughout this document the ISO7816 terminology conventions have been adhered to and it is assumed that the reader is familiar with these. 8.1 Power supplies Two supply selections can be made using pin CONFIG (see Figure 3) depending on the active state of the pin: • pin CONFIG is LOW: supply is pin VDDI(REG). The voltage range of the pin is between 3.6 V and 5.5 V. The regulator output range is between 3 V and 3.6 V. • pin CONFIG is HIGH: supply pins VDDI(REG) and VDD(INTREGD) are connected together to bypass the regulator. Pin VDDI(REG) voltage is between 3 V and 3.6 V. Remark: VDD(INTF) must not exceed VDD(INTREGD) + 0.3 V. 10 µF VDDI(REG) 10 µF GND 20 CONFIG 16 100 nF 100 nF VDD(INTREGD) 21 GND 20 19 CONFIG 16 REGULATOR VDD(INTREGD) 21 19 REGULATOR SUPPLY SUPPLY INTERNAL REFERENCE INTERNAL REFERENCE VOLTAGE SENSE 10 µF VDDI(REG) 18 VCC VCC LOOP 470 nF 220 nF 14 CGND VOLTAGE SENSE 18 VCC VCC LOOP 470 nF 001aai959 3.6 V < VDDI(REG) < 5.5 V Fig 3. 220 nF 14 CGND 001aai960 3 V < VDD(INTREGD) < 3.6 V Power strategy The following examples illustrate the voltage restrictions for VDD(INTF). • CONFIG pin driven to GND: when VDD(INTREGD) is generated by the internal regulator, VDD(INTF) must not exceed 3.3 V. • CONFIG pin is driven by VDDI(REG) without VDD(INTF) tied to VDDI(REG) while VDD(INTREGD) is tied to VDDI(REG): VDD(INTF) must not exceed VDDI(REG) + 0.3 V. • CONFIG pin is driven by VDDI(REG) with VDD(INTF) tied to both VDDI(REG) and VDD(INTREGD): there no are restrictions for VDD(INTF). The TDA8025 is held in the reset state until VDD(INTREGD) reaches Vth + Vhys and PORADJ Vth + Vhys plus the tw(POR) delay. If the VDD(INTREGD) and PORADJ signals fall below Vth, an automatic contact deactivation is triggered. All interface signals to the microcontroller are referenced to VDD(INTF). In addition, all card contacts remain inactive during power-up and power-down cycles. TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 7 of 38 TDA8025 NXP Semiconductors IC card interface After powering up the device, pin OFFN remains LOW until pins CMDVCCN and PRES are both HIGH or pin CMDVCCN is HIGH and pin PRESN is LOW. During power off, pin OFFN is driven LOW when VDD(INTREGD) is below the falling threshold voltage (Vth). When pin CMDVCCN is HIGH, the internal oscillator frequency (fosc(int)) is switched to Low frequency (inactive) mode to reduce power consumption. 8.2 Voltage supervisors 8.2.1 Block diagram VDD(INTF) R1 PORADJ VDD(INTREGD) R2 VDD(INTREGD) REFERENCE VOLTAGE 001aai961 Fig 4. Voltage supervisor circuit 8.2.2 Description The voltage supervisors provide both the Power-On Reset (POR) and supply drop-out detection functions. They control the internal regulated supply voltage (VDD(INTREGD)) and the microcontroller interface supply voltage (VDD(INTF)) to ensure problem-free operation of the TDA8025. By monitoring both VDD(INTREGD) and VDD(INTF), the voltage supervisors ensure these voltages are high enough to ensure correct operation of the TDA8025 and flawless communication between it and the microcontroller. This information is combined and sent to the digital controller in order to reset the TDA8025. An extension of the power-on reset pulse width of ± 8 ms (tw(POR)) is used to maintain the TDA8025 in inactive mode after the supply voltage power on or off sequences (see Figure 5). Vth + Vhys Vth VDD(INTREGD) ALARMN (internal signal) tw(POR) Power on tw(POR) Supply dropout Power off 001aai962 Fig 5. Voltage supervisors VDD(INTREGD) and VDD(INTF) TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 8 of 38 TDA8025 NXP Semiconductors IC card interface 8.2.3 VDD(INTREGD) voltage supervisor with pin PORADJ connected to VDD(INTF) The TDA8025 remains in inactive mode irrespective of the levels on the command lines when • VDD(INTREGD) is less than Vth + Vhys (on pin VDD(INTREGD)) • Pin PORADJ (monitoring VDD(INTF)) is less than Vth + Vhys In both cases, this lasts for the duration of tw(POR) after VDD(INTREGD) (on pin VDD(INTREGD)) and VDD(INTF) (on pin VDD(INTF)) have reached a level higher than Vth + Vhys. Two threshold voltages (Vth) are set by the hardware as follows: • VDD(INTREGD) threshold voltage: is set to the minimum supply voltage (2.7 V) specified for the digital part of the TDA8025 • VDD(INTF) threshold voltage: is set to 1.24 V; see Table 8 on page 23 for detailed information. 8.2.4 VDD(INTF) voltage supervisor with external divider on pin PORADJ An external resistor bridge can be used to divide VDD(INTF) on pin PORADJ to adapt the detection threshold when monitoring the microcontroller interface supply voltage. Connecting the external resistor bridge as illustrated in Figure 4 on page 8 (R1 connected to VDD(INTF) and R2 connected to GND) to pin PORADJ overrides the internal threshold voltage Vth on pin VDD(INTF). The threshold voltage on pin VDD(INTF) is calculated as follows: 1 + R1 V th on pin V DD ( INTF ) = V bg ---------------- R2 (1) where • Vbg is the bandgap voltage When the resistor bridge is not used, pin PORADJ must be connected to pin VDD(INTF). 8.2.4.1 R1 and R2 resistor value calculation This section describes how to calculate the values for resistors R1 and R2, taking into account the IC detector threshold spread and the external resistance, while ensuring reliable activation. If for example, the controller is supplied by a regulator at 3.3 V ± 20 %. Activation can be triggered above VDD(INTF) = 3.3 V − 20 % (in this example 2.64 V). This activation threshold is defined as VDD(INTF)actmin; i.e. the minimum value of VDD(INTF) above which activation can always be triggered. In addition to this external input, activation is permitted provided all the following conditions are met (see Table 8 on page 23): card presence, IC temperature, VDD(INTF) and VDD(INTREGD) supplies, etc. TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 9 of 38 TDA8025 NXP Semiconductors IC card interface The voltage on PORADJ (VPORADJ) can be calculated as: V PORADJ = α × V DD ( INTF ) where: • VDD(INTF) is the interface supply voltage • ratio α 1 α = ---------------R1 1 + ------R2 (2) An activation can be triggered if V th ( max ) V DD ( INTF ) × α > V th ( max ) ⇒ V DD ( INTF ) > -------------------α (3) where • Vth(max) is the maximum rising external threshold voltage The resistance spread of R1 between a minimum value R1min and a maximum value R1max induces a spread of the ratio α. This is also true for R2. Based on this: V th ( max ) V DD ( INTF )actmin = ------------------α min (4) where 1 α min = ------------------------R1 max 1 + --------------R2 min (5) If ∆R1 is the maximum spread of R1 and ∆R2 is the maximum spread of R2 then: ∆R1 R1 max = R1 nom + ∆R1 = R1 nom ⋅ 1 + --------------- R1 nom (6) ∆R2 R2 min = R2 nom – ∆R2 = R2 nom ⋅ 1 – --------------- R2 nom (7) V th ( max ) 1 1 α min = ------------------------------------------------------------ = ----------------------------------------------- = --------------------------------------R1 nom ⋅ ( 1 + β ) V DD ( INTF )actmin ∆R1 R1 nom ⋅ 1 + --------------- 1 + ------------------------------------ R1 nom R2 nom ⋅ ( 1 – β ) 1 + --------------------------------------------------∆R2 R2 nom ⋅ 1 – --------------- R2 nom (8) where • where β is the accuracy ratio of R1 and R2 (R1 and R2 are considered to be of the same type). Then TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 10 of 38 TDA8025 NXP Semiconductors IC card interface R1 nom ( 1 – β ) V DD ( INTF )actmin --------------- = ----------------- ⋅ ---------------------------------------- – 1 (1 + β) R2 nom V th ( max ) (9) R sum R sum R2 nom = -----------------------------= ------------------------------------------------------------------------------------------R1 nom ( 1 – β ) V DD ( INTF )actmin 1 + ------------- 1 + ----------------- ⋅ ---------------------------------------- – 1 (1 + β) R2 nom V th ( max ) (10) If we target 1 % accuracy resistors (β = 0.01) and Rsum = 100 kΩ; Vth(max) = 1.33 V (see Table 8 on page 23) and VDD(INTF)actmin = 2.64 V then • R1nom = 50.88 kΩ • R2nom = 49.12 kΩ Deactivation always occurs when V th ( min ) V PORADJ < V th ( min ) ⇒ V DD ( INTF )deactmax = -----------------α max (11) where • Vth(min) is the minimum falling external threshold voltage • VDD(INTF)deactmax is the maximum value of VDD(INTF) below which deactivation always occurs • αmax V th ( min ) 1 α max = ----------------------------------------------- = --------------------------------------------R1 nom ⋅ ( 1 – β ) V DD ( INTF )deactmax 1 + ------------------------------------R2 nom ⋅ ( 1 + β ) (12) With the resulting values for R1nom, R2nom and β; Vth(min) = 1.17 V (see Table 8 on page 23) then VDD(INTF)deactmax is 2.28 V. 8.3 Clock circuits The clock signal (pin CLK) to the card is either generated by the clock signal input on pin XTAL1 or from a crystal (fxtal ≤ 26 MHz) connected between pins XTAL1 and XTAL2. The voltage level applied to pin ENCLKIN defines which clock signal is used. When pin ENCLKIN is HIGH, connect the external clock to pin XTAL1. Driving pin ENCLKIN LOW causes the external crystal to generate frequency fxtal. Using pins CLKDIV1 and CLKDIV2, the crystal frequency can be set to either fxtal, 1⁄2 fxtal, 1⁄4 fxtal or 1⁄8 fxtal. The frequency change is synchronous and as such during transition, no pulse is shorter than 45 % of the smallest period. In addition, only the first and last clock pulse around the change have the correct width. When dynamically changing the frequency, the modification is only effective after 10 periods of XTAL1. TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 11 of 38 TDA8025 NXP Semiconductors IC card interface The duty cycle on pin CLK should be between 45 % and 55 %. To ensure this, the following must be applied: • when the CLK frequency is fxtal: If an external clock is connected to pin XTAL1, the duty cycle should be between 48 % and 52 % with an input signal period transition time of less than 5 %. If a crystal is used to generate fxtal, the duty cycle on pin CLK should be between 45 % and 55 % depending on the layout, crystal characteristics and frequency. • when CLK frequency is either fxtal, 1⁄2 fxtal, 1⁄4 fxtal or 1⁄8 fxtal: The duty cycle is guaranteed between 45 % and 55 % of the period frequency divisions. When a crystal is used, it runs when pin ENCLKIN is driven LOW. CLKDIV1 6 CLKDIV2 5 15 CLK CLOCK CIRCUIT ENCLKIN 26 MULTIPLEXER XTAL OSCILLATOR 27 XTAL2 ≤ 26 MHz(1) 28 XTAL1 001aai963 (1) External crystal (optional). Fig 6. Clock circuits The clock signal is applied to the card based on the activation sequence as shown on the timing diagrams; see Figure 8 on page 15 to Figure 13 on page 19. When the signal applied to XTAL1 is controlled by the microcontroller, the clock signal is sent to the card only after the activation sequence finishes. Table 4. Clock configuration Clock circuitry definition (pins CLKDIV1 and CLKDIV2 can be changed simultaneously; a >10 XTAL1 period delay is needed. The minimum duration of any CLK state is 10 XTAL1 periods). CLKDIV1 CLKDIV2 CLK 0 0 1⁄ 8 fxtal 0 1 1⁄ 4 fxtal 1 1 1⁄ 2 fxtal 1 0 fxtal TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 12 of 38 TDA8025 NXP Semiconductors IC card interface 8.4 Input and output circuits When pins I/O and I/OUC are driven HIGH using an 11 kΩ resistor between pins I/O and VCC and/or between pins I/OUC and VDD(INTF), both lines enter the idle state. Pin I/O is referenced to VCC and pin I/OUC to VDD(INTF), thus allowing operation at VCC ≠ VDD(INTF). The first side on which a falling edge occurs becomes the master. An anti-latch circuit disables falling edge detection on the other line, making it the slave. After a time delay td(edge), the NMOS transistor on the slave-side is turned on. It then sends logic 0 to the master-side. When the master returns logic 1, the PMOS transistor on the slave side is turned on during the time delay (tpu). After this sequence, both the master and slave return to their idle states. The active pull-up feature ensures fast LOW-to-HIGH transitions making the TDA8025 capable of delivering more than 1 mA, up to an output voltage of 0.9 VCC, at a load of 80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the internal pull-up resistor value and load current. The current sent to and received from the card’s I/O lines is internally limited to 15 mA at a maximum frequency of 1 MHz. 001aai964 8 IOH I/O (A) 4 V I/O (V) V I/O 6 3 IOH I/O 4 2 2 1 0 0 20 40 60 0 100 80 t (ns) Fig 7. Output voltage and current on pins I/O, AUX1 and AUX2 as a function of time during LOW-to-HIGH transitions 8.5 Inactive mode After a power-on reset, the circuit enters the inactive mode, ensuring only the minimum number of circuits are active while the TDA8025 waits for the microcontroller to start a session. The inactive mode conditions are as follows: • all card contacts are inactive. The impedance between the contacts and GND is approximately 200 Ω. • pins I/OUC, AUX1UC and AUX2UC are high-impedance using the 11 kΩ pull-up resistor connected to VDD(INTF) • the voltage generators and crystal oscillator are stopped • the voltage supervisor is active • the internal oscillator runs in low frequency mode TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 13 of 38 TDA8025 NXP Semiconductors IC card interface 8.6 Activation sequence After the power-on and internal pulse width delay, the microcontroller checks the presence of the card using signal OFFN. • The card is present when pins OFFN and CMDVCCN are HIGH • The card is not present when pin OFFN is LOW and pin CMDVCCN is HIGH If the card is in the reader (either pin PRESN or pin PRES is true), the microcontroller can start a card session by pulling pin CMDVCCN LOW. When using an external crystal, the following sequence is applied (see Figure 8): 1. pin CMDVCCN is pulled LOW (t0) 2. the crystal oscillator is triggered 3. the internal oscillator changes to its high frequency (t1) 4. VCC rises either from 0 V to 3 V or 1.8 V on a controlled slope (t2) 5. pins I/O, AUX1 and AUX2 which were pulled LOW are driven HIGH (t3) 6. the clock (pin CLK) is applied to the C3 contact (t4) 7. pin RST is enabled (t5) Calculation of the time delays is as follows: • • • • • t1 = t0 + 2.13 ms t2 = t1 t3 = t1 + 5T/2 t4 = driven by host controller; > t3 and < t5 t5 = t1 + 11T/2 Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e. ±25 µs. t3 is called td(start) and t5 is called td(end). The clock is applied to the card in one of the following ways: • using pin RSTIN: The clock (pin CLK) start-up can be selected at either t3 or t5 using pin RSTIN. When pin RSTIN is HIGH and pin CMDVCCN is LOW, setting pin RSTIN to LOW between delays t3 and t5 sends signal CLK. Pin RSTIN should be held LOW until after delay t5. After passing t5, pin RST is a copy of pin RSTIN and has no further effect on pin CLK. It enables the microcontroller to precisely choose the CLK start by counting clock cycles from the falling edge of the RSTIN signal. • not using pin RSTIN: If this feature is not needed, set both pins CMDVCCN and RSTIN to LOW. The clock (pin CLK) will start at delay t3 (a minimum 200 ns after the input/output transition). After delay t5, pin RSTIN can be set HIGH to receive the card Answer To Request (ATR). Remark: Do not perform activation with pin RSTIN permanently pulled HIGH. TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 14 of 38 TDA8025 NXP Semiconductors IC card interface CMDVCCN XTAL VCC I/O ATR CLK RSTIN RST I/OUC OSCINT low frequency t0 Fig 8. high frequency t1 = t2 td(start) t4 td(end) = tact 001aai965 Activation sequence: CLK controlled by pin RSTIN with the crystal oscillator CMDVCCN XTAL VCC I/O ATR CLK > 200 ns RSTIN RST I/OUC OSCINT low frequency t0 Fig 9. high frequency t1 = t2 t4 td(start) td(end) = tact 001aai966 Activation sequence: CLK not controlled by pin RSTIN with the crystal oscillator The following sequence occurs when using an external clock connected to pin XTAL1 (see Figure 10): 1. external clock (XTAL1) started by the microcontroller (t0) 2. CMDVCCN is pulled LOW and the internal oscillator changes to its high frequency (t1) 3. VCC rises either from 0 V to 3 V or 0 V to 1.8 V on a controlled slope (t2) TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 15 of 38 TDA8025 NXP Semiconductors IC card interface 4. pins I/O, AUX1 and AUX2 are enabled (t3) 5. CLK is applied to the C3 contact (t4) 6. pin RST is enabled (t5) Calculation of the time delays is as follows: • • • • • t1 = t0 + 2.13 ms t2 = t1 = 3T/2 + 3(1⁄fosc(int)low) t3 = t1 + 5T/2 t4 = driven by the host controller; > t3 and < t5 t5 = t1 + 11T/2 Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e. ±25 µs). t3 is called td(start) and t5 is called td(end). fosc(int)low is the low (or inactive mode) frequency of the defined fosc(int) parameter. The CLK is applied to the card under control of pin RSTIN in exactly the same way as with the crystal oscillator. Remark: Do not perform activation with pin RSTIN permanently pulled HIGH. CMDVCCN XTAL1 VCC I/O ATR CLK RSTIN RST I/OUC OSCINT low frequency t0 high frequency t1 = t2 td(start) t4 td(end) = tact 001aai967 Fig 10. Activation sequence: CLK controlled by pin RSTIN with an external clock connected to pin XTAL1 TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 16 of 38 TDA8025 NXP Semiconductors IC card interface CMDVCCN XTAL1 VCC I/O ATR CLK > 200 ns RSTIN RST I/OUC OSCINT low frequency t0 high frequency t1 = t2 t4 td(start) td(end) = tact 001aai968 Fig 11. Activation sequence: CLK not controlled by pin RSTIN and with an external clock connected to pin XTAL1 8.7 Active mode When the activation sequence has finished, the TDA8025 is in active mode. This mode enables data exchange between the card and the microcontroller using the input and output lines. Depending on the layout and application test conditions, line C2 could become polluted with high frequency noise from line C3. For example, due to an additional 1 pF capacitance between lines C2/C3 and/or lines C2/C7. It is recommended that a 100 pF capacitor is added between line C2 and pin CGND, if this occurs. When building the application, the following recommendations should be adhered to: • Keep track C3 as far away as possible from other tracks. • Keep the connection between pin CGND and line C5 straight. The two capacitors on line C1 should be connected to this ground track. • Do not use ground loops between CGND and GND. Following these layout recommendations will ensure that noise remains within the specifications and jitter on line C3 is less than 100 ps. TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 17 of 38 TDA8025 NXP Semiconductors IC card interface 8.8 Deactivation sequence When a session is completed, the microcontroller sets pin CMDVCCN to HIGH. The circuit then executes an automatic deactivation sequence by counting the sequencer back to the inactive state (see Figure 12 and Figure 13): 1. pin RST is pulled LOW (t11) 2. the clock is stopped, pin CLK is LOW (t12) 3. pins I/O, AUX1 and AUX2 are pulled LOW (t13) 4. VCC falls to zero (t14). The deactivation sequence is completed when VCC reaches its inactive state 5. all card contacts become low-impedance to GND. However, pins I/OUC, AUX1UC and AUX2UC remain pulled up to VDD(INTREGD) using the 11 kΩ resistor 6. The internal oscillator returns to its low frequency mode Calculation of the time delays is as follows: • • • • t11 = t10 + 3T/64 t12 = t11 + T/2 t13 = t11 + T t14 = t11 + 3T/2 Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e. ±25 µs). CMDVCCN RST CLK I/O VCC XTAL OSCINT high frequency t10 t11 t12 t13 tdeact low frequency t14 001aai969 Fig 12. Deactivation sequence with a crystal oscillator TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 18 of 38 TDA8025 NXP Semiconductors IC card interface CMDVCCN RST CLK I/O VCC XTAL1 OSCINT high frequency t10 t11 t12 t13 tdeact low frequency t14 001aai970 Fig 13. Deactivation sequence with an external clock connected to pin XTAL1 8.9 VCC regulator Table 5. Selection of VCC using pins VCC_SEL1 and VCC_SEL2 VCC_SEL1 VCC_SEL2 VCC 0 0 3V 0 1 1.8 V 1 0 1.2 V 1 1 1.2 V The VCC buffer is able to continuously deliver up to: • 65 mA at 3 V • 65 mA at 1.8 V • 30 mA at 1.2 V The VCC buffer has an internal overload protection with a threshold value of ±135 mA. This detection is filtered, enabling spurious current pulses up to 200 mA with a duration of up to 200 ns to be drawn by the card without causing deactivation. However, the average current value must be below maximum. To enhance VCC stability, one 470 nF capacitor should be tied to pin CGND near pin 18 and one 220 nF capacitor should be tied to pin CGND near the C1 contact. Both capacitors should have an ESR < 100 mΩ. 8.10 Fault detection The following conditions are monitored by the fault detection circuit: • Short-circuit or high current on pin VCC • Card removal during transaction • VDD(INTREGD) falling TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 19 of 38 TDA8025 NXP Semiconductors IC card interface • VDD(INTF) falling • Overheating Fault detection monitors two different situations (see Figure 15 on page 21): 1. Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in the reader and HIGH if the card is in the reader. Any supply voltage drop on VDD(INTREGD) or VDD(INTF) is detected by the supply supervisor. This generates an internal power-on reset pulse but does not act upon the pin OFFN signal. The card is not powered-up and as such short-circuits and overheating are not detected. 2. Within card sessions, pin CMDVCCN is LOW: when pin OFFN falls LOW, the fault detection circuit triggers the automatic emergency deactivation sequence (see Figure 14). When the system controller resets pin CMDVCCN to HIGH, after the deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN returns to HIGH. This check identifies the fault as either a hardware problem or a card removal incident. On card insertion or removal, bouncing can occur in the PRES and/or PRESN signals. This depends on the type of card presence switch in the connector (normally open or normally closed) and the mechanical characteristics of the switch. To correct for this, a debouncing feature is integrated in to the TDA8025. This feature operates at a typical duration of 640 × (1⁄fosc(int)low). See Figure 15 for an overview of the debouncing feature. Remark: fosc(int)low is the low frequency (or inactive) mode of the defined fosc(int) parameter. On card insertion, pin OFFN goes HIGH after the debouncing time has elapsed. When the card is extracted, the automatic card deactivation sequence is performed on the first true or false transition on pin PRESN or pin PRES. After this pin OFFN goes LOW. OFFN PRESN RST CLK I/O VCC XTAL OSCINT high frequency t10 t12 t13 tdeact low frequency t14 001aai971 Fig 14. Emergency deactivation sequence after card removal TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 20 of 38 TDA8025 NXP Semiconductors IC card interface PRES OFFN CMDVCCN tdeb tdeb (1) VCC (2) 001aai972 (1) Deactivation caused by card removal. (2) Deactivation caused by short circuit. Fig 15. Operation of debounce feature pin OFFN in combination with pins CMDVCCN, PRES and VCC TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 21 of 38 TDA8025 NXP Semiconductors IC card interface 9. Limiting values Remark: All card contacts are protected against any short-circuit to any other card contact. Stress beyond the levels indicated in Table 6 can cause permanent damage to the device. This is a short-term stress rating only and under no circumstances implies functional operation under long-term stress conditions. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDDI(REG) regulator input supply voltage Conditions Min Max Unit −0.3 +5.5 V −0.3 +5.5 V pins CMDVCCN, TEST1, TEST2, CLKDIV2, CLKDIV1, VCC_SEL1, VCC_SEL2, CONFIG, RSTIN, OFFN, TEST3, PORADJ, ENCLKIN, XTAL2, XTAL1, I/OUC, AUX1UC and AUX2UC −0.3 +5.5 V card contact pins PRES, PRESN, I/O, RST, AUX1, AUX2 and CLK −0.3 +6.5 V −55 +150 °C - 0.56 W VDD(INTREGD) internal regulated supply voltage VI input voltage Tstg storage temperature Ptot total power dissipation Tj junction temperature - 150 °C Tamb ambient temperature −25 +85 °C VESD electrostatic discharge voltage pins I/O, RST, VCC, AUX1, CLK, AUX2, PRES and PRESN; within typical application −6 +6 kV Human Body Model (HBM); all pins; EIA/JESD22-A114-B, June 2000 −2 +2 kV Machine Model (MM); all pins; EIA/JESD22-A115-A, October 1997 −200 +200 V all pins, except corner pins −500 +500 V only corner pins (1, 8, 9, 16, 17, 24, 25 and 32) −750 +750 V Tamb = −25 °C to +85 °C Charged Device Model (CDM); 10. Thermal characteristics Table 7. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient with exposed pad soldered 42 K/W without exposed pad soldered 62 K/W TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 22 of 38 TDA8025 NXP Semiconductors IC card interface 11. Characteristics Table 8. Characteristics of IC supply voltage Tamb = 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol Parameter Conditions Min Typ Max Unit regulator input supply voltage pin CONFIG = ground 3.6 5 5.5 V pin CONFIG = VDDI(REG); regulator is bypassed 3 3.3 3.6 V Supply VDDI(REG) VDD(INTREGD) internal pin CONFIG = ground regulated supply voltage [1] 3 3.3 3.6 V VDD(INTF) interface supply voltage [2] IDDI(REG) regulator input supply current pin CONFIG = ground 1.6 3.0 3.3 V pin CONFIG = VDDI(REG) and VDD(INTF) not connected to VDDI(REG) and VDD(INTREGD) 1.6 3.0 VDDI(REG) + 0.3 V pin CONFIG = VDDI(REG) with VDD(INTF) connected to VDDI(REG) and VDD(INTREGD) 3 3.3 3.6 V VDDI(REG) = 5 V fxtal = stopped - - 300 µA VDDI(REG) = 5 V fxtal = 10 MHz; fCLK = 1⁄8 fxtal - - 2.5 mA inactive mode active mode VCC = 3 V; ICC = 65 mA - - 85 mA VCC = 1.8 V; ICC = 65 mA - - 85 mA VCC = 1.2 V; ICC = 30 mA - - 50 mA IDD(INTF) interface supply current - - 100 µA Vth threshold voltage pin VDD(INTREGD); falling 2.60 2.70 2.80 V pin VDD(INTREGD); rising 2.65 2.80 2.95 V pin PORADJ; falling 1.17 1.24 1.31 V pin PORADJ; rising 1.19 1.26 1.33 V pin VDD(INTREGD) 50 100 150 mV Vhys hysteresis voltage tw(POR) power-on reset pulse width 5 8 18 ms ∆Vth/∆T threshold voltage variation with temperature - - 0.25 mV/°C TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 23 of 38 TDA8025 NXP Semiconductors IC card interface Table 8. Characteristics of IC supply voltage …continued Tamb = 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol Parameter IL leakage current Card supply Conditions Min Typ Max Unit pin PORADJ < 0.5 V −0.1 +4 +10 µA pin PORADJ > 1 V −1 - +1 µA 550 - 830 nF no load −0.1 - +0.1 V ICC = 1 mA −0.1 - +0.3 V ICC < 65 mA DC 2.85 3.05 3.15 V single current pulse −100 mA; 2 µs 2.76 3.05 3.20 V current pulses of 40 nAs at ICC < 200 mA; t < 400 ns 2.76 3.05 3.20 V ICC < 65 mA DC 1.71 1.83 1.89 V single current pulse −100 mA; 2 µs 1.66 1.83 1.94 V current pulses of 15 nAs with ICC < 200 mA; t < 400 ns 1.66 1.83 1.94 V ICC < 30 mA DC 1.1 1.2 1.3 V single current pulse −100 mA; 2 µs 1.1 1.2 1.3 V current pulses of 15 nAs with ICC < 200 mA; t < 400 ns 1.10 1.2 1.3 V voltage[3] Cdec decoupling capacitance connected to VCC VCC supply voltage including ripple inactive mode active mode 3 V card: 1.8 V card: 1.2 V card: Vripple(p-p) peak-to-peak ripple voltage pin VCC; 20 kHz to 200 MHz - - 350 mV ICC supply current 0 V to 3 V - - 65 mA 0 V to 1.8 V - - 65 mA 0 V to 1.2 V - - 30 mA up or down 0.02 0.14 0.26 V/µs - - 15 pF SR slew rate Crystal oscillator: pins XTAL1 and XTAL2 Cext external capacitance pins XTAL1/XTAL2; depending on the crystal or resonator specification TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 24 of 38 TDA8025 NXP Semiconductors IC card interface Table 8. Characteristics of IC supply voltage …continued Tamb = 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol Parameter fxtal Conditions Min Typ Max Unit crystal frequency card clock reference; crystal oscillator 2 - 26 MHz fext external frequency external clock on pin XTAL1 0 - 26 MHz VIL LOW-level input voltage pin XTAL1 −0.3 - +0.3VDD(INTF) V VIH HIGH-level input voltage pin XTAL1 VDD(INTF) ≤ VDD(INTREGD) 0.7VDD(INTF) - VDD(INTF) + 0.3 V VDD(INTF) > VDD(INTREGD) 0.7VDD(INTF) - VDD(INTREGD) + 0.3 V - - 200 ns - - 100 ns Data lines: pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC td delay time falling edge on pins I/O and I/OUC or vise versa tw(pu) pull-up pulse width fio input/output frequency on data lines - - 1 MHz Ci input capacitance on data lines - - 10 pF no load 0 - 0.1 V Io = 1 mA - - 0.3 V - - −1 mA V Data lines to the card: pins I/O, AUX1 and AUX2[4] Vo output voltage inactive mode Io output current VOL LOW-level output IOL = 1 mA voltage IOL ≥ 15 mA 0 - 0.3 VCC − 0.4 - VCC V VOH HIGH-level output voltage no DC load 0.9VCC - VCC + 0.1 V IOH < −40 µA; 3 V 0.75VCC - VCC + 0.1 V IOH < −20 µA; 1.8 V or 1.2 V card 0.75VCC - VCC + 0.1 V current limit IOH = −15 mA 0 - 0.4 V VCC = +3 V −0.3 - +0.8 V VCC = +1.8 V −0.3 - +0.6 V VIL LOW-level input voltage from data lines when in inactive mode with pins grounded −0.3 - +0.4 V 0.6VCC - VCC + 0.3 V pin I/O - 350 - mV pin I/O; VIL = 0 V - - 600 µA VCC = +1.2 V VIH HIGH-level input voltage Vhys hysteresis voltage IIL LOW-level input current TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 25 of 38 TDA8025 NXP Semiconductors IC card interface Table 8. Characteristics of IC supply voltage …continued Tamb = 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol Parameter Conditions Min Typ Max Unit IIH HIGH-level input current pin I/O; VIH = VCC - - 10 µA tr(i) input rise time VIL maximum to VIH minimum - - 1.2 µs tr(o) output rise time CL ≤ 80 pF; 10 % to 90 %; 0 V to VCC - - 0.1 µs tf(i) input fall time VIL maximum to VIH minimum - - 1.2 µs tf(o) output fall time CL ≤ 80 pF; 10 % to 90 %; 0 V to VCC - - 0.1 µs Rpu pull-up resistance between I/O and VCC 8 11 13 kΩ IOH HIGH-level output current pin I/O when active pull-up; VOH = 0.9VCC; C = 80 pF −8 −6 −4 mA Data lines to the system: pins I/OUC, AUX1UC and AUX2UC[5] VOL LOW-level output IOL = 1 mA voltage 0 - 0.3 V VOH HIGH-level output voltage no DC load 0.9VDD(INTF) - VDD(INTF) + 0.1 V IOH ≤ 40 µA; VDD(INTF) > 2 V 0.75VDD(INTF) - VDD(INTF) + 0.1 V IOH ≤ 20 µA; VDD(INTF) < 2 V 0.75VDD(INTF) - VDD(INTF) + 0.1 V VIL LOW-level input voltage −0.3 - +0.3VDD(INTF) V VIH HIGH-level input voltage 0.7VDD(INTF) - VDD(INTF) + 0.3 V Vhys hysteresis voltage pin I/OUC - 0.19VDD(INTF) - V IIH HIGH-level input current pin I/OUC; VIH = VDD(INTF) - - 10 µA IIL LOW-level input current pin I/OUC; VIL = 0 V - - 600 µA Rpu pull-up resistance between I/OUC and VDD(INTF) 8 11 13 kΩ tr(i) input rise time VIL maximum to VIH minimum - - 1.2 µs tr(o) output rise time CL ≤ 80 pF; 10 % to 90 %; 0 V to VCC - - 0.1 µs tf(i) input fall time VIL maximum to VIH minimum - - 1.2 µs tf(o) output fall time CL ≤ 80 pF; 10 % to 90 %; 0 V to VCC - - 0.1 µs TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 26 of 38 TDA8025 NXP Semiconductors IC card interface Table 8. Characteristics of IC supply voltage …continued Tamb = 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol Parameter Conditions Min Typ Max Unit IOH HIGH-level output current pin I/OUC when active pull-up; VOH = 0.9VDD; C = 30 pF −1 - - mA Internal oscillator fosc(int) internal oscillator inactive mode frequency active mode 55 140 200 kHz 1.9 2.7 3.2 MHz Reset output to the card: pin RST Vo output voltage inactive mode no load 0 - 0.1 V Io = 1 mA - - 0.3 V Io output current when inactive and pin RST grounded 0 - −1 mA td delay time between pins RSTIN and RST; RST enabled - - 2 µs VOL LOW-level output IOL = 200 µA voltage current limit IOL = 20 mA 0 - 0.2 V VCC − 0.4 - VCC V HIGH-level output voltage IOH = −200 µA 0.9VCC - VCC V current limit IOH = −20 mA 0 - 0.4 V tr rise time CL = 100 pF; VCC = 3 V, 1.8 V or 1.2 V [6] - - 0.1 µs tf fall time CL = 100 pF; VCC = 3 V, 1.8 V or 1.2 V [6] - - 0.1 µs VOH Clock output to the card: pin CLK Vo output voltage inactive mode no load 0 - 0.1 V Io = 1 mA - - 0.3 V 0 - −1 mA Io output current VOL LOW-level output IOL = 200 µA voltage current limit IOL = 70 mA VOH HIGH-level output voltage pin CLK when inactive and grounded IOH = −200 µA current limit IOH = −70 mA 0 - 0.3 V VCC − 0.4 - VCC V 0.9VCC - VCC V 0 - 0.4 V tr rise time CL = 30 pF [6] - - 16 ns tf fall time CL = 30 pF [6] - - 16 ns [6] 45 - 55 % δ duty cycle except for fxtal; CL = 30 pF SR slew rate rise and fall; CL = 30 pF; VCC = 3 V or 1.8 V 0.2 - - V/ns CL = 30 pF; VCC = 1.2 V 0.1 - - V/ns TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 27 of 38 TDA8025 NXP Semiconductors IC card interface Table 8. Characteristics of IC supply voltage …continued Tamb = 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol Parameter Conditions Min Typ Control inputs: pins CLKDIV1, CLKDIV2, CMDVCCN, RSTIN, VCC_SEL2, VCC_SEL1 and Max Unit ENCLKIN[7] VIL LOW-level input voltage −0.3 - +0.3VDD(INTF) V VIH HIGH-level input voltage 0.7VDD(INTF) - VDD(INTF) + 0.3 V Vhys hysteresis voltage control inputs - 0.14VDD(INTF) - V IIL LOW-level input current VIL = 0 V - - 1 µA IIH HIGH-level input current VIH = VDD(INTF) - - 1 µA Control inputs CMDVCCN and CONFIG[7] fCMDVCCN frequency on pin CMDVCCN - - 150 kHz VIL LOW-level input voltage −0.3 - +0.3VDD(INTF) V VIH HIGH-level input voltage 0.7 VDD(INTREGD) - VDD(INTREGD) + 0.3 V Vhys hysteresis voltage pin CONFIG - 0.14VDD(INTF) - V IIL LOW-level input current VIL = 0 V - - 1 µA IIH HIGH-level input current VIH = VDD(INTREGD) - - 1 µA Card detection inputs: pins PRES and PRESN[7][8][9] VIL LOW-level input voltage −0.3 - +0.3VDD(INTREGD) V VIH HIGH-level input voltage 0.7 VDD(INTREGD) - VDD(INTREGD) + 0.3 V Vhys hysteresis voltage pins PRES and PRESN - 0.17 VDD(INTREGD) - V IIL LOW-level input current VIL = 0 V - - 5 µA IIH HIGH-level input current VIH = VDD(INTREGD) - - 5 µA 0 - 0.3 V OFFN output[10]: pin OFFN VOL LOW-level output IOL = 2 mA voltage VOH HIGH-level output voltage IOH = −15 µA 0.75VDD(INTF) - - V Rpu pull-up resistance to VDD 16 20 24 kΩ [1] Two decoupling capacitors connected in parallel to VDD(INTREGD) rated at 100 nF and 1 µF. TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 28 of 38 TDA8025 NXP Semiconductors IC card interface [2] To enable the microcontroller to provide the required maximum voltage input level on XTAL1, VDD(INTF) must not exceed VDD(INTREGD) + 0.3 V. See Section 8.1 on page 7 for specific limitations on the maximum VDD(INTF) voltage and Table 8 on page 23 for the limits of XTAL1. [3] To meet these specifications, VCC should be decoupled to pin CGND using two low ESR, ceramic multilayer capacitors one of 470 nF and one of 220 nF with an ESR of < 100 mΩ. [4] Using the internal pull-up resistor to VCC. [5] Using the internal pull-up resistor to VDD(INTF). [6] The transition time and the duty factor definitions are shown in Figure 16 on page 30; δ = t1/(t1 + t2). [7] Pins PRESN and CMDVCCN are active LOW. Pins RSTIN and PRES are active HIGH; see Table 4 on page 12 for pins CLKDIV1 and CLKDIV2; see Table 5 on page 19 for pins VCC_SEL1 and VCC_SEL2. [8] If PRESN or PRES is true, the card is considered to be present. A debouncing feature of 4.5 ms typical is built-in. [9] Pin PRES has an integrated current source to pin GND, pin PRES to VDD(INTREGD); the card is considered as present if at least one of the two inputs is true. [10] Pin OFFN is an NMOS drain, using an internal pull-up resistor to VDD(INTREGD). Table 9. Protection characteristics Symbol Parameter Conditions Min Typ Max Unit ICC supply current shutdown current on pin VCC 95 135 185 mA pin VCC 135 175 225 mA pin CLK −70 - +70 mA pin RST −20 - +20 mA pins I/O, AUX1 and AUX2 −15 - +15 mA - 150 - °C IIO input/output current Tsd shutdown temperature Table 10. Timing characteristics Symbol Parameter Conditions Min Typ Max Unit tact activation time total sequence with the crystal oscillator [1] 35 - 3000 µs external clock [2] 35 - 240 µs [3] 35 80 100 µs td(start) = t3 [1] 35 - 3000 µs td(end) = t5 [1] 160 - 3090 µs td(start) = t3 [2] 35 - 150 µs td(end) = t5 [2] 160 - 240 µs [4] 3.2 4.5 12 ms tdeact deactivation time total sequence td delay time CLK sent to a card with the crystal oscillator CLK sent to card using an external clock debounce time tdeb [1] See Figure 8 on page 15. [2] See Figure 10 on page 16. [3] See Figure 12 on page 18. [4] See Figure 15 on page 21. on pins PRES and PRESN TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 29 of 38 TDA8025 NXP Semiconductors IC card interface tf tr 90 % VOH 90 % (VOH + VOL)/2 10 % 10 % t1 VOL t2 001aai973 Fig 16. Definition of output and input transition times TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 30 of 38 TDA8025 NXP Semiconductors IC card interface 12. Application information VDD(INTF) MICROCONTROLLER VDD(INTF) R1 CMDVCCN TEST1 C5 100 nF PORADJ ENCLKIN XTAL2 XTAL1 I/OUC AUX1UC VDD(INTF) AUX2UC TEST4 VDD(INTF) R2 32 31 30 29 28 27 26 25 1 24 2 23 TEST2 3 VDD(INTF) 4 CLKDIV2 5 CLKDIV1 6 VCC_SEL1 7 VCC_SEL2 8 22 21 TDA8025 20 19 18 17 TEST3 RSTIN VDDI(REG) VCC 10 µF C4 100 nF RST C1 470 nF CONFIG CLK CGND AUX1 AUX2 I/O PRES C3 GND VDD(INTREGD) 9 10 11 12 13 14 15 16 PRESN VDDI(REG) OFFN VDD(INTREGD) CARD CONNECTOR C5 C1 C6 C2 C7 C3 C8 C4 K2 K1 C2 220 nF RD Ω VDDI(REG) 001aai974 Refer to Table 8 on page 23 and Section 8.1 “Power supplies” on page 7 for detailed information on the VDD(INTF) restrictions. Fig 17. Application diagram (3 V < VDDI(REG) < 3.6 V) TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 31 of 38 TDA8025 NXP Semiconductors IC card interface VDD(INTF) MICROCONTROLLER VDD(INTF) R1 CMDVCCN TEST1 C5 100 nF PORADJ ENCLKIN XTAL2 XTAL1 I/OUC AUX1UC VDD(INTF) AUX2UC TEST4 VDD(INTF) R2 32 31 30 29 28 27 26 25 1 24 2 23 TEST2 3 VDD(INTF) 4 CLKDIV2 5 CLKDIV1 6 VCC_SEL1 7 VCC_SEL2 8 22 21 TDA8025 20 19 18 17 TEST3 RSTIN VDDI(REG) C1 C6 C2 C7 C3 C8 C4 K2 K1 VCC 10 µF C3 10 µF RST C4 C1 470 nF CONFIG CLK CGND AUX1 AUX2 I/O PRESN PRES C5 C3 GND VDD(INTREGD) 9 10 11 12 13 14 15 16 CARD CONNECTOR VDDI(REG) OFFN 100 nF C2 220 nF RD Ω VDDI(REG) 001aaj350 Refer to Table 8 on page 23 and Section 8.1 “Power supplies” on page 7 for detailed information on the VDD(INTF) restrictions. Fig 18. Application diagram (3.6 V < VDDI(REG) < 5.5 V) TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 32 of 38 TDA8025 NXP Semiconductors IC card interface 13. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-1 terminal 1 index area A A1 E c detail X C e1 e 1/2 e 16 y y1 C v M C A B w M C b 9 L 17 8 e e2 Eh 1/2 e 1 terminal 1 index area 24 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 5.1 4.9 3.25 2.95 5.1 4.9 3.25 2.95 0.5 3.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT617-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18 Fig 19. Package outline SOT617-1 TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 33 of 38 TDA8025 NXP Semiconductors IC card interface 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 34 of 38 TDA8025 NXP Semiconductors IC card interface 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 20) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12 Table 11. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 12. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 20. TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 35 of 38 TDA8025 NXP Semiconductors IC card interface maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 20. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 13. Abbreviations Acronym Description ATR Answer To Request ESD ElectroStatic Discharge ESR Equivalent Series Resistance NMOS Negative-channel Metal-Oxide Semiconductor POR Power-On Reset PMOS Positive-channel Metal-Oxide Semiconductor 16. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA8025_1 20090406 Product data sheet - - TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 36 of 38 TDA8025 NXP Semiconductors IC card interface 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TDA8025_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 6 April 2009 37 of 38 TDA8025 NXP Semiconductors IC card interface 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.2.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 7 Voltage supervisors . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VDD(INTREGD) voltage supervisor with pin PORADJ connected to VDD(INTF) . . . . . . . . 9 8.2.4 VDD(INTF) voltage supervisor with external divider on pin PORADJ. . . . . . . . . . . . . . . . . . . 9 8.2.4.1 R1 and R2 resistor value calculation . . . . . . . . 9 8.3 Clock circuits. . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.4 Input and output circuits . . . . . . . . . . . . . . . . . 13 8.5 Inactive mode . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.6 Activation sequence . . . . . . . . . . . . . . . . . . . . 14 8.7 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.8 Deactivation sequence . . . . . . . . . . . . . . . . . . 18 8.9 VCC regulator . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.10 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 19 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22 10 Thermal characteristics. . . . . . . . . . . . . . . . . . 22 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 23 12 Application information. . . . . . . . . . . . . . . . . . 31 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33 14 Soldering of SMD packages . . . . . . . . . . . . . . 34 14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 34 14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 34 14.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 34 14.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 35 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 36 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 37 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37 17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18 Contact information. . . . . . . . . . . . . . . . . . . . . 37 19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 6 April 2009 Document identifier: TDA8025_1