HI2303 Evaluation Board Application Note Introduction The HI2303 evaluation kit can be used to examine the performance of the HI2303 triple 8-bit analog to digital converter (ADC). The evaluation board includes a buffered clock driver, voltage reference, triple A/D converter, data latches and triple D/A converter (DAC). Please refer to the functional block diagram in Figure 1. Evaluation Board The HI2303 evaluation board is a four layer board with a layout optimized for the best performance of the ADC. The optimization includes segmenting the analog and digital signals to prevent digital noise from degrading the analog-to-digital conversion process. The physical board is divided into an analog and digital area with supporting analog and digital ground planes. The power supplies hook-up is detailed in Table 1. Included in the application note is an electrical schematic of the evaluation board circuitry, a components layout, a components part list and views of the various board layers that make up the printed wiring board. Please refer to Figures 2 through 8. The user should feel free to copy the layout in their application. Refer to the components layout and the evaluation board electrical schematics for the following discussions. Table 1 lists the operational supply voltages for the evaluation board. Single supply operation of the converter is possible but the overall performance of the converter may degrade. TABLE 1. EVALUATION BOARD POWER SUPPLIES POWER SUPPLY NOMINAL VALUE CURRENT (TYP) AVDD 5.0V ±5% 170 AGND DVDD FUNCTION(S) SUPPLIED Analog power to ADC, Reference and DAC. Analog Ground 5.0V ±5% 80 Digital power to ADC, Clock, Latches and DAC. DGND Digital Ground March 1998 AN9783.1 capacitors. To bias the inputs at the desired 0.5 to 2.5V range bias tees are provided and can be set via potentiometers R24, R25 and R26. In addition, jumpers JP21, JP22 and JP23 may removed to disconnect the bias tee. Care should be taken to ensure the inputs do not exceed the absolute maximum ratings of the ADC. Reference Voltage Circuit The analog input range of the HI2303 is set by the voltage between VRT and VRB. The voltage can either be internally generated or for increased accuracy externally provided. Please refer to table 2 for the appropriate jumpers on the evaluation board to ENSURE the internal and external reference are not enabled at the same time to prevent permanent damage to the HI2303. Internal reference The internal reference is enabled by connecting VRBS to ANGD and VRTS to AVDD. The HI2303 will then generate approximately 2.5V and 0.6V for VRT and VRB respectively. An external voltage reference is also provided on the board. External Reference The external reference section contains two circuits which generate the top (VRT) and bottom (VRB) voltages. The precision reference is derived by using the Intersil ICL7663S programmable voltage regulator. For complete design theory please refer to the ICL7663 datasheet. As detailed in the datasheet, the output of the voltage regulator is defined in Equation 1. In addition, the sense pin is used along with the 10Ω resistors to provide short circuit protection of approximately 44mA. V REF = V SET ( R + R2/R1 ) (EQ. 1) VRT The top reference is derived by U3 and the supporting components which enables VRT to be adjusted, via the variable resistor R17, from 1.25V to approximately 2.7V. The nominal voltage of VRT should be set to 2.5V. VRB Analog Input The analog inputs to the HI2303 are obtained via BNC connectors J1, J2 and J3 for AIN, BIN and CIN respectively. The input is terminated by a 75Ω resistor and DC blocked by 1 The bottom reference is derived by U4 and the supporting components which allows VRB to be adjusted, via the variable resistor R21, from 0V to approximately 2.5V. The nominal voltage of VRB should be set to 0.5V. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 Application Note 9783 CONTROL SWITCHES 8 HI-3050 HI-2303 BIAS TEE 0.1µF CHANNEL 1 ADC AIN 8 DATA LATCHES 8 CHANNEL 1 DAC 75 AOUT 75 BIAS TEE 0.1µF CHANNEL 2 ADC BIN 8 DATA LATCHES 8 CHANNEL 2 DAC BOUT 75 75 BIAS TEE 0.1µF CIN CHANNEL 3 ADC 8 DATA LATCHES 8 CHANNEL 3 DAC COUT 75 75 VOLTAGE REFERENCE CLAMP DRIVER CLOCK DRIVER CLAMPIN CLOCKIN FIGURE 1. FUNCTIONAL BLOCK DIAGRAM Buffered Clock Driver In order to ensure rated performance of the HI2303, the duty cycle of the sample clock should be set to 50%. It must also have low phase noise and operate at standard TTL logic levels. It can be difficult to find a low phase noise generator that will provide a 50MHz squarewave at TTL logic levels. Consequently, the evaluation board is designed with a logic buffer (U2) acting as a voltage comparator to generate the sampling clock for the HI2303 when a sinewave (<±1.5V) is applied to the CLK input of the evaluation board. The sample clock sinewave is AC coupled into the input of the inverter and a discrete bias tee is used to bias the sinewave around the trigger level of the inverter’s input. The variable resistor varies the DC bias voltage added to the sinewave input allowing the user to adjust the duty cycle of the sampling clock to obtain the best performance from the ADC and to evaluate the effects of sample clock duty cycle on the performance of the converter. The sinewave to logic level compar2 ator drives a series of additional buffers that provides isolation between the three sample clocks used on the evaluation board. One clock drives the ADC clock input pin (AD_CLOCK), a second clock drives output data latches (LATCH_CLOCK), and the last clock provides the DAC reconstruct clock(DA_CLOCK). Reconstruction DAC To easily verify the performance of the ADC a reconstruction DAC is provided. The 10-bit HI3050 triple DAC was selected to ensure the user measures the real ADC performance without any degradation from the reconstruct DAC. The DAC is configured to convert the latched data into a 2V fullscale output. The fullscale output can be adjusted slightly via R9. The DAC is optimized for the fullscale output voltage of 1.8 to 2.0V so care should be exercised when operating outside of the designed range. Application Note 9783 TABLE 2. JUMPER SETTINGS JUMPER NAME PURPOSE JP1 ART IN Connects top external board references VRT to the reference top of Channel A (VART). For proper operation the top internal reference should not be selected via JP7. JP2 ARB IN Connects bottom external board references VRB to the reference bottom of Channel A (VARB). For proper operation the bottom internal reference should not be selected via JP8. JP3 BRT IN Connects top external board references VRT to the reference top of Channel B (VBRT). For proper operation the top internal reference should not be selected via JP10. JP4 BRB IN Connects bottom external board references VRB to the reference bottom of Channel B (VBRB). For proper operation the bottom internal reference should not be selected via JP11. JP5 CRT IN Connects top external board references VRT to the reference top of Channel C (VCRT). For proper operation the top internal reference should not be selected via JP13. JP6 CRB IN Connects bottom external board references VRB to the reference bottom of Channel C (VCRB). For proper operation the bottom internal reference should not be selected via JP14. JP7 ARTS Enables top internal reference of channel A. JP1 should be removed. JP8 ARBS Enables bottom internal reference of channel A. JP2 should be removed. JP9 AIO JP10 BRTS Enables top internal reference of channel B. JP3 should be removed. JP11 BRBS Enables bottom internal reference of channel B. JP4 should be removed. JP12 BIO JP13 CRTS Enables top internal reference of channel C. JP5 should be removed. JP14 CRBS Enables bottom internal reference of channel C. JP6 should be removed. JP15 CIO JP16 LATCH_EN3 Enables channel A latch (U5). JP17 L1_ENABLE Enables clock buffers. (U2). JP18 L2_DISABLE Disables clamp buffer. (U2). JP19 LATCH_EN1 Enables channel B latch (U7). JP20 LATCH_EN2 Enables channel C latch (U6). JP21 Cin Connects bias-T to C Channel input. JP22 Ain Connects bias-T to A Channel input. JP23 Bin Connects bias-T to B Channel input. JP24 XAOE Enable A Channel digital output. JP25 XBOE Enable B Channel digital output. JP26 XCOE Enable C Channel digital output. Connects digital clamp output to channel input. Remove if internal clamp function is not used. Connects digital clamp output to channel input. Remove if internal clamp function is not used. Connects digital clamp output to channel input. Remove if internal clamp function is not used. 3 Application Note 9783 Measured Performance TABLE 3. DYNAMIC PERFORMANCE The performance of the evaluation board was measured by capturing the ADC data and performing the Fast Fourier Transform (FFT) to derive Signal-to-Noise and Distortion Ratio (SINAD), Signal-to-Noise Ratio (SNR), Total Harmonic Distortion (THD) and Effective Number of Bits (ENOB). This data is summarized in Table 3 and graphically displayed in Figures 1 and 2. fIN (MHz) ENOB SINAD dB SNR dB THD dB 0.1 7.63 47.71 48.41 -54.91 1 7.51 49.96 48.14 -53.19 5 7.32 45.81 46.51 -54.1 10 7.01 43.97 46.90 -47.06 15 6.54 41.13 46.9 -42.46 20 6.18 38.96 47 -39.65 Note: Coherent testing is recommended in order to avoid the inaccuracies of windowing. 60 8 EFFECTIVE NUMBER OF BITS 40 dB 20 0 -20 SINAD dB SNR dB THD dB -40 -60 0.1 1 5 10 15 INPUT FREQUENCY (MHz FIGURE 2. SINAD, SNR AND THD vs fIN 4 20 7 6 ENOB 5 4 3 2 1 0 0.1 1 5 10 15 INPUT FREQUENCY (MHz) FIGURE 3. ENOB vs fIN (fCLOCK = 50MHz 20 Application Note 9783 FIGURE 4. TOP SILK SCREEN FIGURE 5. TOP SIGNAL LAYER 5 Application Note 9783 FIGURE 6. ANALOG AND DIGITAL GROUND PLANE FIGURE 7. ANALOG AND DIGITAL POWER PLANE 6 Application Note 9783 FIGURE 8. BOTTOM SIGNAL LAYER FIGURE 9. BOTTOM SILKSCREEN 7 Application Note 9783 FIGURE 10. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 8 Application Note 9783 CIN J3 2 C3 0.1µF AGND 1 R3 75 JP21 CIN DVDD AVDD AGND AVDD C35 0.01µF R24 10K DGND B1 B0 B4 B3 B2 C27 0.1µF A3 A2 A1 A0 B7 B6 B5 + A5 A4 C26 4.7µF 16V A7 A6 AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 B0 B1 B2 B3 B4 B5 B6 B7 AGND A0 A1 A2 A3 A4 A5 A6 A7 AGND TGR_OUT TGR AGND DVDD DGND DVDD DVDD B0 B1 B2 B3 B4 B5 B6 B7 DVSS DVSS A0 A1 A2 A3 A4 A5 A6 A7 TGR DVDD DVDD AVSS DVDD AGND C36 0.01µF DVDD + C31 0.1µF AGND VRB C1 0.1µF 1 VRT AVDD C2 0.1µF BIN 2 BIN J2 AGND R2 75 AGND 9 AIN VRT R25 10K AGND BRB C5 0.1µF AGND JP22 R1 75 ARB 2 JP4 BRB IN 2 AIN J1 1 ARBS JP2 ARB IN 1 2 DGND AGND 1 JP8 2 ARBS DGND JP23 AVDD 1 C30 4.7µF 16V R26 10K Application Note 9783 AVDD C0 AGND AIN AGND DVDD AGND A6 REF1 A7 REF0 A8 SEL A9 R39 5K R38 5K REF2 SY A4 CTL2 A3 CTL1 A2 CTL0 A1 JP26 1 S1 S1 S1 S1 S1 S1 S1 S1 S1 B10 B5 B6 B7 B8 B9 B4 B3 B2 B1 BIN DGND R36 5K R35 5K R34 5K R33 5K R28 5K R29 5K AVDD R3 5K C18 0.1µF AGND 10 A5 S1 DGND AGND BIN REF3 2 R37 5K 2 JP25 2 2 A10 AVDD BRT B IO C6 0.1µF 1 JP10 2 C4 0.1µF XBOE XAOE DVDD CLE BRTS ART JP1 ART IN 1 2 JP3 BRT IN XCOE CLAMP AD_CLOCK R31 5K 2 AD_CLK R32 5K 1 VRB C9 0.1µF R27 5K AIO AGND 2 AIO 1 JP12 1 JP9 BIO AIN VRT JP6 1 2 CRB IN 2 CRBS JP14 CLP JP24 C7 0.1µF AGND CRB AGND 1 BRBS 2 1 AGND JP11 AGND JP7 ARTS BRB BRB VRT 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ARB JP5 1 2 CRT IN AGND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 CIN BRB BIO BIN AVSS AVDD BRTS BRT ARTS ART AIO AVDD AIN AVSS ARBS ARB U1 HI2303JCQ ARB AGND C8 0.01µF AVSS CRB CRBS AVDD AVSS AVSS TEST CLE REF3 REF2 REF1 REF0 CLP CLK SEL SY CTL2 CTL1 CTL0 XCOE XBOE XAOE TEST AVDD AVDD BRBS CRT AVDD CIO CRTS C0 DVSS DVSS C3 C2 C1 C4 C6 C5 C7 ARBS AGND CRT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 DVDD DVDD B0 B1 B2 B3 B4 B5 B6 B7 DVSS DVSS A0 A1 A2 A3 A4 A5 A6 A7 TGR DVDD DVDD AVSS C19 0.01µF CIO 2 2 JP15 AVDD CIO AGND C16 0.01µF 1 JP13 BRTS 1 C0 C1 C2 C3 C4 C5 C6 C7 AVDD AVDD 2 C3 C2 C1 C4 C6 C5 C7 CIN Application Note 9783 DVDD DVDD R14 5K C39 0.01µF DGND R10 2K 2 2 DVDD JP18 L2_DISABLE 1 JP17 L1_ENABLE 1 CLOCK IN J4 R15 5K DGND C12 0.1µF U3 1 19 2 4 6 8 17 15 13 11 R11 75 DGND OEA OEB DA0 DA1 DA2 DA3 DB0 DB1 DB2 DB3 DGND DGND OA0 OA1 OA2 OA3 OB0 OB1 OB2 OB3 18 16 14 12 3 5 7 9 AD_CLOCK LATCH_CLOCK DA_CLOCK CLAMP 74FCT241T DVDD CLAMP IN J5 C13 47µF 10V R13 2K + R12 75 AVDD DGND DGND DGND C20 0.01µF AGND VRT U3 1 2 R16 10 3 4 + C14 10µF AGND SEN VIN+ VOUT2 VTC VOUT1 VSET GND SHDN 8 7 R17 500K 6 5 AGND ICL7663SIBA AVDD AGND C21 0.1µF VRB AGND U3 1 2 3 R21 10K + C15 10µF 4 SEN VIN+ VOUT2 VTC VOUT1 VSET GND SHDN 8 R19 200K 7 6 5 R20 200K ICL7663SIBA AGND 11 AGND AGND AGND J11 B_OUT AVDD AVDD AVDD R7 75 DVDD C23 0.01µF C40 0.01µF C24 0.01µF 2 1 JP19 LATCH_EN1 LATCH_CLOCK B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 TGR_OUT 7 D5 8 D6 9 D7 OE O3 16 O4 15 O5 14 CP O6 13 12 O7 U7 OE VCC Q0 D0 Q1 D1 Q2 D2 Q3 D3 Q4 D4 Q5 D5 Q6 D6 Q7 D7 Q8 D8 Q9 D9 GND CP AGND ROUT AVDD ROUT AVDD GOUT AVDD GOUT AVDD BOUT AVDD BOUT AVDD AGND 20 21 22 23 24 25 26 27 28 29 30 31 32 AGND 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 C10 0.1µF AVDD VREFR 24 23 22 21 20 19 18 17 16 15 14 13 DGND TGR_EXT DVDD CD74FCT82IAM DGND TGR_EXT C43 0.01µF DGND DGND R9 10K R6 ADJ_R 1.2K AGND AGND C11 0.1µF DA_CLOCK DA_CLOCK G9 (C7) DVCC 1 2 3 4 5 6 7 8 9 10 11 12 CE 5 D3 6 D4 BLK O2 17 O1 18 B9 4 D2 B6 (B4) B7 (B5) B8 (B6) B9 (B7) B5 O0 19 B4 (B2) B5 (B3) OE2 JP20 LATCH_EN2 B4 2 D0 3 D1 AGND COMP_B VREF_OUTB COMP_G VREF_OUTG COMP_R VREF_OUTR VREFB U8 VREFG HI3050JCQ VREFR ADJ_B ADJ_G ADJ_R AGND VBIAS DGND BCLK GCLK RCLK B8 12 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 G0 G1 G2 G3 G4 G5 G6 G7 G8 B7 13 B6 CP O7 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 B5 D7 OE 1 14 B4 O6 15 B3 D6 R8 75 64 63 62 61 60 59 58 57 56 55 54 53 52 G2 (C0) G3 (C1) G4 (C2) G5 (C3) G6 (C4) G7 (C5) G8 (C6) B2 DGND DGND O5 16 B2 (B0) B3 (B1) B1 B3 R22 5K D5 O4 U8 AVDD OE3 B0 DVDD DVDD D4 O3 DGND 17 U6 DGND R23 5K D3 CD74FCT574T DGND JP16 LATCH_EN3 1 2 C41 0.01µF O2 DGND Application Note 9783 DVDD 9 A7 R4 5K D2 18 J12 C_OUT B2 8 A6 O1 AGND C42 0.01µF AGND B1 A5 D1 19 DVDD 7 O0 B0 6 A4 AGND D0 C9 5 A3 A_OUT R5 75 AGND R2 (A0) R3 (A1) R4 (A2) R5 (A3) R6 (A4) R7 (A5) R8 (A6) R9 (A7) 12 4 A2 DVDD 2 3 A1 AGND U5 CD74FCT574T A0 C22 0.01µF AGND J10 D VDD AGND DGND AGND C25 0.01µF HI2303EVAL1 TRIPLE 8-BIT 50MHz A/D X__ Authorized to use a tighter tolerance part if the requested tolerance is not available. (Ex: Requested 10%, ok to use 5% or lower) _X__ Authorized to use a higher voltage part if the requested voltage is not available but not to exceed ____ volts. (Ex: Requested 16 volts but not to exceed 50 volts) NOTES: 1. The above action items will only be in effect if it will impact Intersil delivery schedule or if a part is not available due to a long lead time. 2. The purchased part will meet all form, fit and function requirements. 3. Substitute Component Authorization (SCA) will be submitted for any manufacturer/manufacturer part numbers 13 75Ω 1% Res, Chip 4.99kΩ R16, R18 Res, Chip 1 R6 5 2 6 QTY. PER PCB 1 8 R1, R2, R3, R5, R7, R8, R11, R12 Res, Chip 2 18 R4, R14, R15, R22, R23, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39 3 2 4 REFERENCE DESIGNATOR DESCRIPTION PART#/ VALUE DIEL WATTS MFGR 1206 1/8W Any 1% 1206 1/8W Any 10Ω 1% 1206 1/8W Any Res, Chip 1.2kΩ 1% 1206 1/8W Any R19, R20 Res, Chip 200kΩ 1% 1206 1/8W Any 5 R9, R21, R24, R25, R26 Trimmer Potentiometer 10kΩ 10% 3296W Bourns 7 2 R10, R13 Trimmer Potentiometer 2kΩ 10% 3296W Bourns 8 1 R17 Trimmer Potentiometer 500kΩ 10% 3296W Bourns 9 1 U1 Triple 8-Bit A/D HI2303JCQ MQFP Intersil 10 1 U2 Buffer CD74FCT241DTM SOIC Intersil 11 2 U3, U4 Programmable Voltage Regulator ICL7663SIBA SOIC Intersil 12 2 U5, U6 8-Bit Interface Registers CD74FCT574DTM SOIC Intersil 13 1 U7 10-Bit Interface Registers CD74FCT821CTM SOIC Intersil 14 1 U8 Triple 10-bit D/A HI3050JCQ MQFP Intersil 15 VOLT MFGR’S PART # COMMENTS Application Note 9783 TOL PKG SIZE RADIAL AXIAL LEAD SPACE LINE ITEM # HI2303EVAL1 TRIPLE 8-BIT 50MHz A/D X__ Authorized to use a tighter tolerance part if the requested tolerance is not available. (Ex: Requested 10%, ok to use 5% or lower) _X__ Authorized to use a higher voltage part if the requested voltage is not available but not to exceed ____ volts. (Ex: Requested 16 volts but not to exceed 50 volts) NOTES: 1. The above action items will only be in effect if it will impact Intersil delivery schedule or if a part is not available due to a long lead time. 2. The purchased part will meet all form, fit and function requirements. 3. Substitute Component Authorization (SCA) will be submitted for any manufacturer/manufacturer part numbers (Continued) 14 PKG SIZE RADIAL AXIAL LEAD SPACE LINE ITEM # QTY. PER PCB 16 0 Was C1, C2, C3 Cap 17 11 C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C27, C31 Cap, Chip 0.1µF 18 1 C13 Cap 47µF EIA CASE D 19 2 C14, C15 Cap, Chip 10µF EIA CASE B 20 22 C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C35, C36, C39, C40, C41, C42, C43 Cap, Chip 0.01µF 10% 1206 21 2 C26, C30 Cap, Chip 4.7µF 20% EIA CASE A 22 8 J1, J2, J3, J4, J5, J10, J11, J12 BNC Connector AMP 23 26 JP1-JP26 HEADER, 1X2 Berg Electronics/Any 69190-402 24 26 CON JUMPER, 1X2 Berg Electronics/Any 55-50275P (Black) 617-6600 25 4 Rubber Feet 26 6 HEADER, 2X8 27 6 Terminal REFERENCE DESIGNATOR DESCRIPTION PART#/ VALUE DIEL TOL 1µF VOLT WATTS MFGR EIA CASE A 10% 1206 Any, Panasonic MFGR’S PART # COMMENTS PCS2475CT Electrolytic PCC104BCT 10VWDC Any, Panasonic PCS2106CT Any, Panasonic PCC103BCT 16WVDC 3M Any Allied Any Cambion 160-2044-02-01 Application Note 9783 ECS_H1ED106R