V048F015T100 & V048F015M100 VTM Transformer Datasheet

Not recommended for New Designs
V048F015T100
V048F015M100
VTM
VTMTM
Transformer
• 48 V to 1.5 V V•I ChipTM Converter
• 125°C operation (TJ)
• 100.0 A (150.0 A for 1 ms)
• 1 µs transient response
• High density – 339 A/in3
• 3.5 million hours MTBF
• Small footprint – 80 A/in2
• Typical efficiency 89%
• Low weight – 0.5 oz (15 g)
• No output filtering required
©
Vf = 26.0 - 55 V
VOUT = 0.820 - 1.71 V
IOUT = 100.0 A
K = 1/32
ROUT = 1.1 mΩ max
• Pick & Place / SMD
or Through hole
Product Description
Absolute Maximum Ratings
The V048F015T100 V•I Chip transformer excels at speed,
density and efficiency to meet the demands of advanced
power applications while providing isolation from input
to output. It achieves a response time of less than 1 µs
and delivers up to 100.0 A in a volume of less than 0.295
in3 with unprecedented efficiency. It may be paralleled to
deliver higher power levels at an output voltage settable
from 0.820 to 1.71 Vdc.
The VTM V048F015T100’s nominal output voltage is 1.5
Vdc from a 48 Vdc input Factorized Bus, Vf, and is
controllable from 0.820 to 1.71 Vdc at no load, and from
0.710 to 1.61 Vdc at full load, over a Vf input range of
26.0 to 55 Vdc. It can be operated either open- or
closed-loop depending on the output regulation needs of
the application. Operating open-loop, the output voltage
tracks its Vf input voltage with a transformation ratio,
K = 1/32, for applications requiring an isolated output
voltage with high efficiency. Closing the loop back to an
input PRMTM regulator or DC-DC converter enables tight
load regulation.
A/in3
The 1.5 V VTM achieves a current density of 339
in
a V•I Chip package compatible with standard pick-andplace and surface mount assembly processes. The VTM’s
fast dynamic response and low noise eliminate the
need for bulk capacitance at the load, substantially
increasing system density while improving reliability
and decreasing cost.
Parameter
+In to -In
Values
Unit
-1.0 to 60
Vdc
100
Vdc
PC to -In
-0.3 to 7.0
Vdc
VC to -In
-0.3 to 19.0
Vdc
+Out to -Out
For 100 ms
-0.5 to 4.0
Vdc
Isolation voltage
2,250
Vdc
Output current
100.0
A
Continuous
Peak output current
150.0
A
For 1 ms
Input to output
Output power
161
W
Continuous
Peak output power
242
W
For 1 ms
225
°C
MSL 5
245
°C
MSL 6, TOB = 4 hrs
-40 to 125
-55 to 125
°C
°C
T-Grade
M-Grade
-40 to 125
-65 to 125
°C
°C
T-Grade
M-Grade
[a]
Case temperature during reflow
Operating junction temperature
Storage temperature
[b]
Notes:
[a] 245°C reflow capability applies to product with manufacturing date code 1001 and greater.
[b] The referenced junction is defined as the semiconductor having the highest temperature.
This temperature is monitored by a shutdown comparator.
Part Numbering
V
Voltage
Transformation
Module
048
F
Input Voltage
Designator
Configuration
F = J-lead
T = Through hole
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Notes
800-735-6200
V•I Chip Transformer
015
T
Output Voltage
Designator
(=VOUT x10)
100
Output Current
Designator
(=IOUT)
Product Grade Temperatures (°C)
Grade
Storage Operating (TJ)
T
-40 to125 -40 to125
M
-65 to125 -55 to125
V048F015T100
Rev. 3.3
Page 1 of 11
Electrical Specifications
Input Specs (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Min
Typ
Max
Input voltage range
26.0
48
Input dV/dt
Input overvoltage turn-on
Unit
Note
55
Vdc
Max Vin = 53 V, operating from -55°C to -40°C
1
V/µs
59.5
Vdc
55.1
Vdc
Input overvoltage turn-off
Input current
3.6
Input reflected ripple current
124
No load power dissipation
5.6
Internal input capacitance
4.0
Internal input inductance
Adc
mA p-p
7.8
Using test circuit in Figure 15; See Figure 1
W
µF
5
nH
Output Specs (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Min
Typ
0.820
0.710
0
Output voltage
Rated DC current
Peak repetitive current
Short circuit protection set point
Current share accuracy
Efficiency
Half load
Full load
Internal output inductance
Internal output capacitance
Output overvoltage setpoint
Output ripple voltage
No external bypass
94 µF bypass capacitor
Effective switching frequency
Line regulation
K
Load regulation
ROUT
Transient response
Voltage overshoot
Response time
Recovery time
Max
Unit
Note
1.71
1.61
100.0
Vdc
Vdc
Adc
No load
Full load
26.0 - 55 VIN
150.0
A
10
Adc
%
125
5
88.8
88.6
89.3
89.2
1.6
306
%
%
nH
µF
Vdc
1.7
200
2.8
100
14
2.9
0.0309
1/32
0.0316
0.9
1.1
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60
200
1
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3.0
mVp-p
mVp-p
MHz
Max pulse width 1ms, max duty cycle 10%,
baseline power 50%
Module will shut down
See Parallel Operation on Page 9
See Figure 3
See Figure 3
Effective value
Module will shut down
See Figures 2 and 5
See Figure 6
Fixed, 1.4 MHz per phase
VOUT = K•VIN at no load
mΩ
See Figure 16
mV
ns
µs
100.0 A load step with 100 µF CIN; See Figures 7 and 8
See Figures 7 and 8
See Figures 7 and 8
V•I Chip Transformer
V048F015T100
Rev. 3.3
Page 2 of 11
Electrical Specifications (continued)
Waveforms
Ripple vs. Output Current
Output Ripple (mVpk-pk)
120
100
80
60
40
20
0
0
10
20
30
40
50
60
70
80
90
100
Output Current (A)
Figure 2 — Output voltage ripple vs. output current at 48 Vf with no POL
bypass capacitance.
Figure 1 — Input reflected ripple current at full load and 48 Vf.
Efficiency vs. Output Current
Power Dissipation
20
95
Efficiency (%)
90
1.5 V
1.2 V
1.0 V
85
80
75
70
Power Dissipation (W)
1.5 V
1.2 V
1.0 V
16
12
8
4
0
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Output Current (A)
Output Current (A)
Figure 3 — Efficiency vs. output current.
Figure 4 — Power dissipation vs. output current.
Figure 5 — Output voltage ripple at full load and 48 Vf with no POL bypass
capacitance.
Figure 6 — Output voltage ripple at full load and 48 Vf with 94 µF ceramic
POL bypass capacitance and 20 nH distribution inductance.
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V048F015T100
Rev. 3.3
Page 3 of 11
Electrical Specifications (continued)
Figure 7 — 0-100.0 A load step with 100 µF input capacitance and no
output capacitance.
Figure 8 — 100.0-0 A load step with 100 µF input capacitance and no
output capacitance.
General
Parameter
Min
MTBF
MIL-HDBK-217F
Isolation specifications
Voltage
Capacitance
Resistance
Typ
Max
Unit
Note
3.5
Mhrs
25°C, GB
3,000
Vdc
pF
MΩ
Input to output
Input to output
Input to output
UL /CSA 60950-1, EN 60950-1
Low voltage directive
2,250
10
cTÜVus
CE Mark
RoHS
Agency approvals
Mechanical
Weight
Dimensions
Length
Width
Height
Peak compressive force applied to case (Z axis)
Thermal
Over temperature shutdown
Thermal capacity
Junction-to-case thermal impedance (RθJC)
Junction-to-board thermal impedance (RθJB)
See Mechanical Drawings, Figures 10 – 13
0.53/15
oz /g
1.28/ 32,5
0.87 / 22
0.265/ 6,73
5
in / mm
in / mm
in / mm
lbs.
125
130
9.3
1.1
2.1
6
135
°C
Ws /°C
°C / W
°C / W
Supported by J-leads only
Junction temperature
See Thermal Considerations on Page 9
Auxiliary Pins (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Primary Control (PC)
DC voltage
Module disable voltage
Module enable voltage
Current limit
Disable delay time
VTM Control (VC)
External boost voltage
External boost duration
Min
Typ
Max
Unit
Note
4.8
2.4
5.0
2.5
2.5
2.5
6
5.2
Vdc
Vdc
Vdc
mA
µs
VC voltage must be applied when module is enabled using PC
Source only
PC low to Vout low
Vdc
ms
Required for VTM start up without PRM
Maximum duration of VC pulse = 20 ms
2.4
12
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2.6
2.9
19
V•I Chip Transformer
V048F015T100
Rev. 3.3
Page 4 of 11
Pin / Control Functions
+In / -In DC Voltage Ports
The VTM input should be connected to the PRM output terminals.
Given that both the PRM and VTM have high switching frequencies, it
is often good practice to use a series inductor to limit high frequency
currents between the PRM output and VTM input capacitors. The input
voltage should not exceed the maximum specified. If the input voltage
exceeds the overvoltage turn-off, the VTM will shutdown. The VTM
does not have internal input reverse polarity protection. Adding a
properly sized diode in series with the positive input or a fused reverseshunt diode will provide reverse polarity protection.
4
3
2
+Out
B
B
C
C
D
D
F
G
H
J
K
TM – For Factory Use Only
-Out
VC – VTM Control
PC
L
L
M
M
N
N
P
P
R
R
Bottom View
Signal Name
+In
–In
TM
VC
PC
+Out
PC – Primary Control
Disable – If PC is left floating, the VTM output is enabled. To
disable the output, the PC port must be pulled lower than 2.4 V,
referenced to -In. Optocouplers, open collector transistors or relays
can be used to control the PC port. Once disabled, 14 V must be
re-applied to the VC port to restart the VTM.
-In
T
T
The Primary Control (PC) port is a multifunction port for controlling the
VTM as follows:
VC
J
+Out
The VC port is not intended to be used to supply VCC voltage to the
VTM for extended periods of time. If VC is being supplied from a source
other than the PRM, the voltage should be removed after 20 ms.
TM
H
K
The VC port is multiplexed. It receives the initial VCC voltage from an
upstream PRM, synchronizing the output rise of the VTM with the
output rise of the PRM. Additionally, the VC port provides feedback to
the PRM to compensate for the VTM output resistance. In typical
applications using VTMs powered from PRMs, the PRM’s VC port
should be connected to the VTM VC port.
+In
E
E
-Out
1
A
A
–Out
Pin Designation
A1-E1, A2-E2
L1-T1, L2-T2
H1, H2
J1, J2
K1, K2
A3-D3, A4-D4,
J3-M3, J4-M4
E3-H3, E4-H4,
N3-T3, N4-T4
Figure 9 — VTM pin configuration
Primary Auxiliary Supply – The PC port can source up to 2.4 mA
at 5 Vdc.
+Out / -Out DC Voltage Output Ports
The output and output return are through two sets of contact
locations. The respective +Out and –Out groups must be connected in
parallel with as low an interconnect resistance as possible. Within the
specified input voltage range, the Level 1 DC behavioral model shown
in Figure 16 defines the output voltage of the VTM. The current source
capability of the VTM is shown in the specification table.
To take full advantage of the VTM, the user should note the low output
impedance of the device. The low output impedance provides fast
transient response without the need for bulk POL capacitance. Limitedlife electrolytic capacitors required with conventional converters can be
reduced or even eliminated, saving cost and valuable board real estate.
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V048F015T100
Rev. 3.3
Page 5 of 11
Mechanical Drawings
TOP VIEW ( COMPONENT SIDE)
BOTTOM VIEW
NOTES:
mm
1. DIMENSIONS ARE inch .
2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3. PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
Figure 10 — V T M J-Lead mechanical outline; Onboard mounting
RECOMMENDED LAND PATTERN
( COMPONENT SIDE SHOWN )
NOTES:
mm
1. DIMENSIONS ARE inch .
2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3. PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
Figure 11 — VTM J-Lead PCB land layout information; Onboard mounting
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V•I Chip Transformer
V048F015T100
Rev. 3.3
Page 6 of 11
Mechanical Drawings (continued)
TOP VIEW ( COMPONENT SIDE )
BOTTOM VIEW
NOTES:
(mm)
1. DIMENSIONS ARE inch .
2. UNLESS OTHERWISE SPECIFIED TOLERANCES ARE:
X.X [X.XX] = ±0.25 [0.01]; X.XX [X.XXX] = ±0.13 [0.005]
3. RoHS COMPLIANT PER CST-0001 LATEST REVISION
DXF and PDF files are available on vicorpower.com
Figure 12 — V T M Through-hole mechanical outline
RECOMMENDED HOLE PATTERN
( COMPONENT SIDE SHOWN )
NOTES:
(mm)
1. DIMENSIONS ARE inch .
2. UNLESS OTHERWISE SPECIFIED TOLERANCES ARE:
X.X [X.XX] = ±0.25 [0.01]; X.XX [X.XXX] = ±0.13 [0.005]
3. RoHS COMPLIANT PER CST-0001 LATEST REVISION
DXF and PDF files are available on vicorpower.com
Figure 13 — VTM Through-hole PCB layout information
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V•I Chip Transformer
V048F015T100
Rev. 3.3
Page 7 of 11
Mechanical Drawings (continued)
RECOMMENDED LAND PATTERN
(NO GROUNDING CLIPS)
TOP SIDE SHOWN
NOTES:
1. MAINTAIN 3.50 [0.138] DIA. KEEP-OUT ZONE
FREE OF COPPER, ALL PCB LAYERS.
2. (A) MINIMUM RECOMMENDED PITCH IS 39.50 [1.555],
THIS PROVIDES 7.00 [0.275] COMPONENT
EDGE-TO-EDGE SPACING, AND 0.50 [0.020]
CLEARANCE BETWEEN VICOR HEAT SINKS.
(B) MINIMUM RECOMMENDED PITCH IS 41.00 [1.614],
THIS PROVIDES 8.50 [0.334] COMPONENT
EDGE-TO-EDGE SPACING, AND 2.00 [0.079]
CLEARANCE BETWEEN VICOR HEAT SINKS.
RECOMMENDED LAND PATTERN
(With GROUNDING CLIPS)
TOP SIDE SHOWN
3. V•I CHIP LAND PATTERN SHOWN FOR REFERENCE ONLY;
ACTUAL LAND PATTERN MAY DIFFER.
DIMENSIONS FROM EDGES OF LAND PATTERN
TO PUSH-PIN HOLES WILL BE THE SAME FOR
ALL FULL SIZE V•ICHIP PRODUCTS.
4. RoHS COMPLIANT PER CST-0001 LATEST REVISION.
5. UNLESS OTHERWISE SPECIFIED:
DIMENSIONS ARE MM [INCH].
TOLERANCES ARE:
X.X [X.XX] = ±0.3 [0.01]
X.XX [X.XXX] = ±0.13 [0.005]
6. PLATED THROUGH HOLES FOR GROUNDING CLIPS (33855)
SHOWN FOR REFERENCE. HEATSINK ORIENTATION AND
DEVICE PITCH WILL DICTATE FINAL GROUNDING SOLUTION.
Figure 14 — Hole location for push pin heat sink relative to V•I Chip
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Rev. 3.3
Page 8 of 11
Application Note
Parallel Operation
Input Impedance Recommendations
In applications requiring higher current or redundancy, VTMs can be
operated in parallel without adding control circuitry or signal lines. To
maximize current sharing accuracy, it is imperative that the source and
load impedance on each VTM in a parallel array be equal. If VTMs are
being fed by an upstream PRM, the VC nodes of all VTMs must be
connected to the PRM VC.
To take full advantage of the VTM’s capabilities, the impedance of the
source (input source plus the PC board impedance) must be low over a
range from DC to 5 MHz. Input bypass capacitance may be added to
improve transient performance or compensate for high source
impedance. The VTM has extremely wide bandwidth so the source
response to transients is usually the limiting factor in overall output
response of the VTM.
To achieve matched impedances, dedicated power planes within the PC
board should be used for the output and output return paths to the
array of paralleled VTMs. This technique is preferable to using traces of
varying size and length.
Anomalies in the response of the source will appear at the output of
the VTM, multiplied by its K factor of 1/32. The DC resistance of the
source should be kept as low as possible to minimize voltage deviations
on the input to the VTM. If the VTM is going to be operating close to
the high limit of its input range, make sure input voltage deviations will
not trigger the input overvoltage turn-off threshold.
The VTM power train and control architecture allow bi-directional
power transfer when the VTM is operating within its specified ranges.
Bi-directional power processing improves transient response in the
event of an output load dump. The VTM may operate in reverse,
returning output power back to the input source. It does so efficiently.
Input Fuse Recommendations
V•I Chips are not internally fused in order to provide flexibility in
configuring power systems. However, input line fusing of V•I Chips
must always be incorporated within the power system. A fast acting
fuse is required to meet safety agency Conditions of Acceptability. The
input line fuse should be placed in series with the +In port.
Thermal Considerations
V•I Chip products are multi-chip modules whose temperature
distribution varies greatly for each part number as well as with the
input /output conditions, thermal management and environmental
conditions. Maintaining the top of the V048F015T100 case to less than
100°C will keep all junctions within the V•I Chip below 125°C for most
applications. The percent of total heat dissipated through the top
surface versus through the J-lead is entirely dependent on the particular
mechanical and thermal environment. The heat dissipated through the
top surface is typically 60%. The heat dissipated through the J-lead
onto the PCB board surface is typically 40%. Use 100% top surface
dissipation when designing for a conservative cooling solution.
It is not recommended to use a V•I Chip for an extended period of time
at full load without proper heatsinking.
Application Notes
For VTM and V•I Chip application notes on soldering, thermal
management, board layout, and system design click on the link below:
http://www.vicorpower.com/technical_library/application_information/chips/
Input reflected ripple
measurement point
F1
7A
Fuse
C1
47 µF
Al electrolytic
+Out
+In
C2
0.47 μF
ceramic
TM
VC
PC
14 V +
–
-In
-Out
+Out
C3
94 µF
VTM
K
Ro
+
R3
5 mΩ
Load
-Out
–
Notes:
C3 should be placed close
to the load
R3 may be ESR of C3 or a
separate damping resistor.
Figure 15 — VTM test circuit
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V•I Chip Transformer
V048F015T100
Rev. 3.3
Page 9 of 11
Application Note (continued)
V•I Chip VTM Level 1 DC Behavioral Model for 48 V to 1.5 V, 100.0 A
ROUT
IOUT
+
+
0.9 mΩ
V•I
1/32 • Iout
VIN
IQ
117 mA
1/32 • Vin
+
+
–
VOUT
–
K
–
–
©
Figure 16 — This model characterizes the DC operation of the V•I Chip VTM, including the converter transfer function and its losses. The model enables
estimates or simulations of output voltage as a function of input voltage and output load, as well as total converter power dissipation or heat generation.
V•I Chip VTM Level 2 Transient Behavioral Model for 48 V to 1.5 V, 100.0 A
0.15 nH
+
0.9 mΩ
RRCIN
CIN
1/32 • Iout
CIN
+
+
–
4.0 µF
IQ
117 mA
+
RCOUT
R
OUT
0.6 mΩ
V• I
1.3 mΩ
VIN
LOUT = 1.6 nH
ROUT
IOUT
L IN = 5 nH
0.065 mΩ
1/32 • Vin
COUT
306 µF
VOUT
–
K
–
–
©
Figure 17 — This model characterizes the AC operation of the V•I Chip VTM including response to output load or input voltage transients or steady state
modulations. The model enables estimates or simulations of input and output voltages under transient conditions, including response to a stepped load
with or without external filtering elements.
In figures below;
K = VTM transformation ratio
RO = VTM output resistance
Vf = PRM output (Factorized Bus Voltage)
VO = VTM output
VL = Desired load voltage
FPA Adaptive Loop
0.01 μF
10 kΩ
VC
PC
TM
IL
NC
PR
PRM-AL
+In
VH
SC
SG
OS
NC
CD
ROS
RCD
+Out
Factorized
Bus (Vf)
0.4 μH
Vin
+Out
+In
+Out
TM
VC
PC
VTM
10 Ω
–In
– In
–Out
– Out
K
Ro – Out
L
O
A
D
Figure 18 — The PRM controls the factorized bus voltage, Vf, in proportion to output current to compensate for the output resistance, Ro, of the VTM. The VTM
output voltage is typically within 1% of the desired load voltage (VL) over all line and load conditions.
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Rev. 3.3
Page 10 of 11
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in
normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper
application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended
to the original purchaser only.
EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING,
BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
Vicor will repair or replace defective products in accordance with its own best judgement. For service under this
warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping
instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges
incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within
the terms of this warranty.
Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is
assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve
reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or
circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not
recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten
life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes
all risks of such use and indemnifies Vicor against all damages.
Vicor’s comprehensive line of power solutions includes high density AC-DC
and DC-DC modules and accessory components, fully configurable AC-DC
and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for
its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or
malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are
available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent
applications) relating to the products described in this data sheet. Interested parties should contact Vicor's
Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917;
7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for
use under 6,975,098 and 6,984,965
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: [email protected]
Technical Support: [email protected]
vicorpower.com
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V•I Chip Transformer
V048F015T100
Rev. 3.3
5/10
Electrical Specifications
Input Specs (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Min
Typ
Max
Input voltage range
26.0
48
Input dV/dt
Input overvoltage turn-on
Unit
Note
55
Vdc
Max Vin = 50 V, operating from -55°C to -20°C
1
V/µs
59.5
Vdc
55.1
Vdc
Input overvoltage turn-off
Input current
3.6
Input reflected ripple current
124
No load power dissipation
5.6
Internal input capacitance
4.0
Internal input inductance
Adc
mA p-p
7.8
Using test circuit in Figure 15; See Figure 1
W
µF
5
nH
Output Specs (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Min
Typ
0.820
0.710
0
Output voltage
Rated DC current
Peak repetitive current
Short circuit protection set point
Current share accuracy
Efficiency
Half load
Full load
Internal output inductance
Internal output capacitance
Output overvoltage setpoint
Output ripple voltage
No external bypass
94 µF bypass capacitor
Effective switching frequency
Line regulation
K
Load regulation
ROUT
Transient response
Voltage overshoot
Response time
Recovery time
Max
Unit
Note
1.71
1.61
100.0
Vdc
Vdc
Adc
No load
Full load
26 - 50 VIN
150.0
A
10
Adc
%
125
5
88.8
88.6
89.3
89.2
1.6
306
%
%
nH
µF
Vdc
1.7
200
2.8
100
14
2.9
0.0309
1/32
0.0316
0.9
1.1
vicorpower.com
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200
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3.0
mVp-p
mVp-p
MHz
Max pulse width 1ms, max duty cycle 10%,
baseline power 50%
Module will shut down
See Parallel Operation on Page 9
See Figure 3
See Figure 3
Effective value
Module will shut down
See Figures 2 and 5
See Figure 6
Fixed, 1.4 MHz per phase
VOUT = K•VIN at no load
mΩ
See Figure 16
mV
ns
µs
100.0 A load step with 100 µF CIN; See Figures 7 and 8
See Figures 7 and 8
See Figures 7 and 8
V•I Chip Transformer
V048F015T100
Rev. 3.3
Page 2 of 11
Electrical Specifications (continued)
Waveforms
Ripple vs. Output Current
Output Ripple (mVpk-pk)
120
100
80
60
40
20
0
0
10
20
30
40
50
60
70
80
90
100
Output Current (A)
Figure 2 — Output voltage ripple vs. output current at 48 Vf with no POL
bypass capacitance.
Figure 1 — Input reflected ripple current at full load and 48 Vf.
Efficiency vs. Output Current
Power Dissipation
20
95
Efficiency (%)
90
1.5 V
1.2 V
1.0 V
85
80
75
70
Power Dissipation (W)
1.5 V
1.2 V
1.0 V
16
12
8
4
0
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Output Current (A)
Output Current (A)
Figure 3 — Efficiency vs. output current.
Figure 4 — Power dissipation vs. output current.
Figure 5 — Output voltage ripple at full load and 48 Vf with no POL bypass
capacitance.
Figure 6 — Output voltage ripple at full load and 48 Vf with 94 µF ceramic
POL bypass capacitance and 20 nH distribution inductance.
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Rev. 3.3
Page 3 of 11
Electrical Specifications (continued)
Figure 7 — 0-100.0 A load step with 100 µF input capacitance and no
output capacitance.
Figure 8 — 100.0-0 A load step with 100 µF input capacitance and no
output capacitance.
General
Parameter
Min
MTBF
MIL-HDBK-217F
Isolation specifications
Voltage
Capacitance
Resistance
Typ
Max
Unit
Note
3.5
Mhrs
25°C, GB
3,000
Vdc
pF
MΩ
Input to output
Input to output
Input to output
UL /CSA 60950-1, EN 60950-1
Low voltage directive
2,250
10
cTÜVus
CE Mark
RoHS
Agency approvals
Mechanical
Weight
Dimensions
Length
Width
Height
Peak compressive force applied to case (Z axis)
Thermal
Over temperature shutdown
Thermal capacity
Junction-to-case thermal impedance (RθJC)
Junction-to-board thermal impedance (RθJB)
See Mechanical Drawings, Figures 10 – 13
0.53/15
oz /g
1.28/ 32,5
0.87 / 22
0.265/ 6,73
5
in / mm
in / mm
in / mm
lbs.
125
130
9.3
1.1
2.1
6
135
°C
Ws /°C
°C / W
°C / W
Supported by J-leads only
Junction temperature
See Thermal Considerations on Page 9
Auxiliary Pins (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Primary Control (PC)
DC voltage
Module disable voltage
Module enable voltage
Current limit
Disable delay time
VTM Control (VC)
External boost voltage
External boost duration
Min
Typ
Max
Unit
Note
4.8
2.4
5.0
2.5
2.5
2.5
6
5.2
Vdc
Vdc
Vdc
mA
µs
VC voltage must be applied when module is enabled using PC
Source only
PC low to Vout low
Vdc
ms
Required for VTM start up without PRM
Maximum duration of VC pulse = 20 ms
2.4
12
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V•I Chip Transformer
V048F015T100
Rev. 3.3
Page 4 of 11
Pin / Control Functions
+In / -In DC Voltage Ports
The VTM input should be connected to the PRM output terminals.
Given that both the PRM and VTM have high switching frequencies, it
is often good practice to use a series inductor to limit high frequency
currents between the PRM output and VTM input capacitors. The input
voltage should not exceed the maximum specified. If the input voltage
exceeds the overvoltage turn-off, the VTM will shutdown. The VTM
does not have internal input reverse polarity protection. Adding a
properly sized diode in series with the positive input or a fused reverseshunt diode will provide reverse polarity protection.
4
3
2
+Out
B
B
C
C
D
D
F
G
H
J
K
TM – For Factory Use Only
-Out
VC – VTM Control
PC
L
L
M
M
N
N
P
P
R
R
Bottom View
Signal Name
+In
–In
TM
VC
PC
+Out
PC – Primary Control
Disable – If PC is left floating, the VTM output is enabled. To
disable the output, the PC port must be pulled lower than 2.4 V,
referenced to -In. Optocouplers, open collector transistors or relays
can be used to control the PC port. Once disabled, 14 V must be
re-applied to the VC port to restart the VTM.
-In
T
T
The Primary Control (PC) port is a multifunction port for controlling the
VTM as follows:
VC
J
+Out
The VC port is not intended to be used to supply VCC voltage to the
VTM for extended periods of time. If VC is being supplied from a source
other than the PRM, the voltage should be removed after 20 ms.
TM
H
K
The VC port is multiplexed. It receives the initial VCC voltage from an
upstream PRM, synchronizing the output rise of the VTM with the
output rise of the PRM. Additionally, the VC port provides feedback to
the PRM to compensate for the VTM output resistance. In typical
applications using VTMs powered from PRMs, the PRM’s VC port
should be connected to the VTM VC port.
+In
E
E
-Out
1
A
A
–Out
Pin Designation
A1-E1, A2-E2
L1-T1, L2-T2
H1, H2
J1, J2
K1, K2
A3-D3, A4-D4,
J3-M3, J4-M4
E3-H3, E4-H4,
N3-T3, N4-T4
Figure 9 — VTM pin configuration
Primary Auxiliary Supply – The PC port can source up to 2.4 mA
at 5 Vdc.
+Out / -Out DC Voltage Output Ports
The output and output return are through two sets of contact
locations. The respective +Out and –Out groups must be connected in
parallel with as low an interconnect resistance as possible. Within the
specified input voltage range, the Level 1 DC behavioral model shown
in Figure 16 defines the output voltage of the VTM. The current source
capability of the VTM is shown in the specification table.
To take full advantage of the VTM, the user should note the low output
impedance of the device. The low output impedance provides fast
transient response without the need for bulk POL capacitance. Limitedlife electrolytic capacitors required with conventional converters can be
reduced or even eliminated, saving cost and valuable board real estate.
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Rev. 3.3
Page 5 of 11
Mechanical Drawings
TOP VIEW ( COMPONENT SIDE)
BOTTOM VIEW
NOTES:
mm
1. DIMENSIONS ARE inch .
2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3. PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
Figure 10 — V T M J-Lead mechanical outline; Onboard mounting
RECOMMENDED LAND PATTERN
( COMPONENT SIDE SHOWN )
NOTES:
mm
1. DIMENSIONS ARE inch .
2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3. PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
Figure 11 — VTM J-Lead PCB land layout information; Onboard mounting
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V048F015T100
Rev. 3.3
Page 6 of 11
Mechanical Drawings (continued)
TOP VIEW ( COMPONENT SIDE )
BOTTOM VIEW
NOTES:
(mm)
1. DIMENSIONS ARE inch .
2. UNLESS OTHERWISE SPECIFIED TOLERANCES ARE:
X.X [X.XX] = ±0.25 [0.01]; X.XX [X.XXX] = ±0.13 [0.005]
3. RoHS COMPLIANT PER CST-0001 LATEST REVISION
DXF and PDF files are available on vicorpower.com
Figure 12 — V T M Through-hole mechanical outline
RECOMMENDED HOLE PATTERN
( COMPONENT SIDE SHOWN )
NOTES:
(mm)
1. DIMENSIONS ARE inch .
2. UNLESS OTHERWISE SPECIFIED TOLERANCES ARE:
X.X [X.XX] = ±0.25 [0.01]; X.XX [X.XXX] = ±0.13 [0.005]
3. RoHS COMPLIANT PER CST-0001 LATEST REVISION
DXF and PDF files are available on vicorpower.com
Figure 13 — VTM Through-hole PCB layout information
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V048F015T100
Rev. 3.3
Page 7 of 11
Mechanical Drawings (continued)
RECOMMENDED LAND PATTERN
(NO GROUNDING CLIPS)
TOP SIDE SHOWN
NOTES:
1. MAINTAIN 3.50 [0.138] DIA. KEEP-OUT ZONE
FREE OF COPPER, ALL PCB LAYERS.
2. (A) MINIMUM RECOMMENDED PITCH IS 39.50 [1.555],
THIS PROVIDES 7.00 [0.275] COMPONENT
EDGE-TO-EDGE SPACING, AND 0.50 [0.020]
CLEARANCE BETWEEN VICOR HEAT SINKS.
(B) MINIMUM RECOMMENDED PITCH IS 41.00 [1.614],
THIS PROVIDES 8.50 [0.334] COMPONENT
EDGE-TO-EDGE SPACING, AND 2.00 [0.079]
CLEARANCE BETWEEN VICOR HEAT SINKS.
RECOMMENDED LAND PATTERN
(With GROUNDING CLIPS)
TOP SIDE SHOWN
3. V•I CHIP LAND PATTERN SHOWN FOR REFERENCE ONLY;
ACTUAL LAND PATTERN MAY DIFFER.
DIMENSIONS FROM EDGES OF LAND PATTERN
TO PUSH-PIN HOLES WILL BE THE SAME FOR
ALL FULL SIZE V•ICHIP PRODUCTS.
4. RoHS COMPLIANT PER CST-0001 LATEST REVISION.
5. UNLESS OTHERWISE SPECIFIED:
DIMENSIONS ARE MM [INCH].
TOLERANCES ARE:
X.X [X.XX] = ±0.3 [0.01]
X.XX [X.XXX] = ±0.13 [0.005]
6. PLATED THROUGH HOLES FOR GROUNDING CLIPS (33855)
SHOWN FOR REFERENCE. HEATSINK ORIENTATION AND
DEVICE PITCH WILL DICTATE FINAL GROUNDING SOLUTION.
Figure 14 — Hole location for push pin heat sink relative to V•I Chip
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Page 8 of 11
Application Note
Parallel Operation
Input Impedance Recommendations
In applications requiring higher current or redundancy, VTMs can be
operated in parallel without adding control circuitry or signal lines. To
maximize current sharing accuracy, it is imperative that the source and
load impedance on each VTM in a parallel array be equal. If VTMs are
being fed by an upstream PRM, the VC nodes of all VTMs must be
connected to the PRM VC.
To take full advantage of the VTM’s capabilities, the impedance of the
source (input source plus the PC board impedance) must be low over a
range from DC to 5 MHz. Input bypass capacitance may be added to
improve transient performance or compensate for high source
impedance. The VTM has extremely wide bandwidth so the source
response to transients is usually the limiting factor in overall output
response of the VTM.
To achieve matched impedances, dedicated power planes within the PC
board should be used for the output and output return paths to the
array of paralleled VTMs. This technique is preferable to using traces of
varying size and length.
Anomalies in the response of the source will appear at the output of
the VTM, multiplied by its K factor of 1/32. The DC resistance of the
source should be kept as low as possible to minimize voltage deviations
on the input to the VTM. If the VTM is going to be operating close to
the high limit of its input range, make sure input voltage deviations will
not trigger the input overvoltage turn-off threshold.
The VTM power train and control architecture allow bi-directional
power transfer when the VTM is operating within its specified ranges.
Bi-directional power processing improves transient response in the
event of an output load dump. The VTM may operate in reverse,
returning output power back to the input source. It does so efficiently.
Input Fuse Recommendations
V•I Chips are not internally fused in order to provide flexibility in
configuring power systems. However, input line fusing of V•I Chips
must always be incorporated within the power system. A fast acting
fuse is required to meet safety agency Conditions of Acceptability. The
input line fuse should be placed in series with the +In port.
Thermal Considerations
V•I Chip products are multi-chip modules whose temperature
distribution varies greatly for each part number as well as with the
input /output conditions, thermal management and environmental
conditions. Maintaining the top of the V048F015T100 case to less than
100°C will keep all junctions within the V•I Chip below 125°C for most
applications. The percent of total heat dissipated through the top
surface versus through the J-lead is entirely dependent on the particular
mechanical and thermal environment. The heat dissipated through the
top surface is typically 60%. The heat dissipated through the J-lead
onto the PCB board surface is typically 40%. Use 100% top surface
dissipation when designing for a conservative cooling solution.
It is not recommended to use a V•I Chip for an extended period of time
at full load without proper heatsinking.
Application Notes
For VTM and V•I Chip application notes on soldering, thermal
management, board layout, and system design click on the link below:
http://www.vicorpower.com/technical_library/application_information/chips/
Input reflected ripple
measurement point
F1
7A
Fuse
C1
47 µF
Al electrolytic
+Out
+In
C2
0.47 μF
ceramic
TM
VC
PC
14 V +
–
-In
-Out
+Out
C3
94 µF
VTM
K
Ro
+
R3
5 mΩ
Load
-Out
–
Notes:
C3 should be placed close
to the load
R3 may be ESR of C3 or a
separate damping resistor.
Figure 15 — VTM test circuit
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V048F015T100
Rev. 3.3
Page 9 of 11
Application Note (continued)
V•I Chip VTM Level 1 DC Behavioral Model for 48 V to 1.5 V, 100.0 A
ROUT
IOUT
+
+
0.9 mΩ
V•I
1/32 • Iout
VIN
+
+
–
IQ
117 mA
1/32 • Vin
VOUT
–
K
–
–
©
Figure 16 — This model characterizes the DC operation of the V•I Chip VTM, including the converter transfer function and its losses. The model enables
estimates or simulations of output voltage as a function of input voltage and output load, as well as total converter power dissipation or heat generation.
V•I Chip VTM Level 2 Transient Behavioral Model for 48 V to 1.5 V, 100.0 A
0.15 nH
+
0.9 mΩ
RRCIN
CIN
1/32 • Iout
CIN
+
+
–
4.0 µF
IQ
117 mA
+
RCOUT
R
OUT
0.6 mΩ
V• I
1.3 mΩ
VIN
LOUT = 1.6 nH
ROUT
IOUT
L IN = 5 nH
0.065 mΩ
1/32 • Vin
COUT
306 µF
VOUT
–
K
–
–
©
Figure 17 — This model characterizes the AC operation of the V•I Chip VTM including response to output load or input voltage transients or steady state
modulations. The model enables estimates or simulations of input and output voltages under transient conditions, including response to a stepped load
with or without external filtering elements.
In figures below;
K = VTM transformation ratio
RO = VTM output resistance
Vf = PRM output (Factorized Bus Voltage)
VO = VTM output
VL = Desired load voltage
FPA Adaptive Loop
0.01 μF
10 kΩ
VC
PC
TM
IL
NC
PR
PRM-AL
+In
VH
SC
SG
OS
NC
CD
ROS
RCD
+Out
Factorized
Bus (Vf)
0.4 μH
Vin
+Out
+In
+Out
TM
VC
PC
VTM
10 Ω
–In
– In
–Out
– Out
K
Ro – Out
L
O
A
D
Figure 18 — The PRM controls the factorized bus voltage, Vf, in proportion to output current to compensate for the output resistance, Ro, of the VTM. The VTM
output voltage is typically within 1% of the desired load voltage (VL) over all line and load conditions.
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Rev. 3.3
Page 10 of 11
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in
normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper
application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended
to the original purchaser only.
EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING,
BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
Vicor will repair or replace defective products in accordance with its own best judgement. For service under this
warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping
instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges
incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within
the terms of this warranty.
Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is
assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve
reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or
circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not
recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten
life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes
all risks of such use and indemnifies Vicor against all damages.
Vicor’s comprehensive line of power solutions includes high density AC-DC
and DC-DC modules and accessory components, fully configurable AC-DC
and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for
its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or
malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are
available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent
applications) relating to the products described in this data sheet. Interested parties should contact Vicor's
Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917;
7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for
use under 6,975,098 and 6,984,965
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: [email protected]
Technical Support: [email protected]
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