Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) PRM™ Regulator FEATURES DESCRIPTION • 45 V (38 to 55 VIN), non-isolated ZVS buck-boost regulator • 5 to 55 V adjustable output range • Building block for high efficiency DC-DC systems • 200 W Output Power in 0.57 in2 footprint • 97% typical efficiency, at full load • 1,300 W/in3 (81 W/cm3) Power Density • Enables a 48 V to 1.5 V, 130 A isolated, regulated solution with total footprint of 1.7 in2 (11 cm2) • Flexible “Remote Sense” architecture optimizes regulation / feedback loop design to fit application requirements • Current Feedback signal allows dynamic adjustment of current limit setpoint • 4.93 MHrs MTBF (MIL-HDBK-217Plus Parts Count) The V•I Chip PRM™ Regulator is a high efficiency converter, operating from a 38 to 55 Vdc input to generate a regulated 5 to 55 Vdc output. The ZVS Buck – Boost topology enables high switching frequency (~1 MHz) operation with high conversion efficiency. High switching frequency reduces the size of reactive components 3 enabling power density up to 1,300 W/in . The half V•I Chip package is compatible with standard pick-and-place and surface mount assembly processes with a planar thermal interface area and superior thermal conductivity. In a Factorized Power Architecture™ system, the PRM48BH480T200A00 and downstream VTM™ transformer minimize distribution and conversion losses in a high power solution. TYPICAL APPLICATIONS • • • • • • An external control loop and current sensor maintain regulation and enable flexibility both in the design of voltage and current compensation loops to control of output voltages and currents. High Efficiency Server Processor and Memory Power High Density ATE system DC-DC power Telecom NPU and ASIC core power LED drivers High Density Power Supply DC-DC rail outputs Non-isolated power converters 48 V to 1.2 V, 130A Voltage Regulator Voltage Control Feedback Enable/ Disable Voltage Reference PC PR IM TM +OUT +IN 38 to 55 Vdc Input IF RE TM +OUT1 +OUT2 VTM PRM -IN PC +IN -IN -OUT SG VC VC Load -OUT1 -OUT2 Current Sense V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 1 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 1.0 ABSOLUTE MAXIMUM RATINGS The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions. All voltages are specified relative to SG unless otherwise noted. Positive pin current represents current flowing out of the pin. PR ……………………………………………………………………….. PC ……………………………………………………………………….. TM ……………………………………………………………………….. +IN to –IN …………………………………………………………………………… VS ……………………………………………………………………….. SG …………………………………………………………………………… IF …………………………………………………………………………… RE …………………………………………………………………………… VC to –OUT +OUT to –OUT Output Current Operating Analog IC Junction Temperature Storage Temperature ……………………………………………………………………….. …………………………………………………………………………… …………………………………………………………………………… …………………………………………………………………………… …………………………………………………………………………… Min -0.3 -0.3 -0.3 -1 -0.5 -0.5 -0.3 -0.5 -1 -40 -40 Max 10.5 ±10 5.7 ±10 5.7 ±1 62 10.5 ±100 ±100 5.7 5 18 ±1.8 62 ±5.5 125 125 Unit V mA V mA V mA V V mA mA V V V A V A ºC ºC 2.0 ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and output voltage from 20 V to 55 V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade). Attribute Symbol Conditions / Notes Min Typ Max Unit 38 0.001 45 55 1000 4 8.5 5.7 V V/ms W mA A µF mΩ 55 4.17 200 ±10 V A W µs ms % See sec 10.6 % POWER INPUT SPECIFICATION Input Voltage range VIN Slew Rate No Load Power Dissipation Input Quiescent current Input Current Input Capacitance (Internal) Input Capacitance (Internal) ESR VIN dVIN /dt PNL IQC IIN DC CIN_INT RCin 0 < VIN < 18 V PC High, VIN = 45 V PC Low, VIN = 45 V IOUT = 4.17 A, VIN = 38 V, VOUT = 48 V Effective value, VIN = 45 V (see Fig. 20) 2.6 4.5 5.5 2 3 POWER OUTPUT SPECIFICATION Output Voltage range Output Current Output Power Output Turn-ON Delay Current Sharing accuracy Efficiency Output Output Output Output Output Discharge current Voltage Ripple Inductance (Parasitic) Capacitance (Internal) Capacitance (Internal) ESR VOUT IOUT POUT TON TOFF + TON IOUT_PS η IOD VOUT_PP LOUT PAR COUT_INT RCout See Fig.16, SOA See Fig.16, SOA From PC pin release to VOUT, VIN pre-applied and TOFF already expired From VIN applied to VOUT, PC floating Equal input, output and PR voltage at full load; VIN = 45 V, VOUT = 48 V, exclusive of current limit Equal input, output and PR voltage at full load; Over line, trim, and temperature; exclusive of current limit Nominal line, full load, VOUT = 48V 50% load and VOUT = 48 V; over temperature 50% load; over temperature Section 4.0 COUT EXT = 0 F, IOUT = 4.17 A, VIN = 45 V, VOUT = 48 V, 20 MHz BW Frequency @ 1 MHz, Simulated J-Lead model Effective value, VOUT = 48 V (see Fig. 20) 5 48 20 18.02 95.7 94.5 88.5 96.9 13 1020 2.5 2 3 1500 % % % mA mV nH µF mΩ POWERTRAIN PROTECTIONS Input Undervoltage Turn-ON Input Undervoltage Turn-OFF Input Overvoltage Turn-ON Input Overvoltage Turn-OFF Overcurrent (IF) and Input Over/Undervoltage Blanking Time Output Overvoltage Threshold Thermal Shutdown Setpoint Overtemperature, Output Overvoltage and PC Shutdown Response Time Short Circuit Vout Threshold Short Circuit Vout Recovery Threshold Short Circuit Vpr Threshold Short Circuit Vpr Recovery Threshold Short Circuit Timeout Short Circuit Fault Recovery Time Output Power Limit VIN_UVLO+ VIN UVLOVIN_OVLO+ VIN OVLO- Instantanous powertrain shutdown, latched after TBLANK Instantanous powertrain shutdown, latched after TBLANK TBLANK VOUT_OVLO+ TJ OTP Instantaneous, latched shutdown Instantaneous, latched shutdown; guaranteed by design, not production tested; V TM = 4.03V 31.97 55.91 35.75 33.56 57.24 58.44 37.13 59.91 V V V V 50 120 150 µs 55.25 130 56.57 59.04 V ºC TPROT 2 µs VSC_VOUT VSC VOUTR VSC_VPR VSC VPRR TSC TSCR PPROT 3.0 4.0 7.2 7.1 20 0.1 V V V V ms ms W Short Circuit fault latched after VSC VOUT and VSC VPR thresholds persist for this time 200 V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 2 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 3.0 SIGNAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and Output Voltage from 20 V to 55 V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade). Primary Control PC • The PC pin enables and disables the PRM • In PRM array configurations, PC pins should be connected in order to synchronize startup. • It is a weak pull-down during any fault mode excluding short circuit. PC is a strong pull-down to SG if a Short Circuit fault is latched. Signal Type State Attribute Symbol Conditions / Notes Regular PC Voltage VPC Operation PC Available Current IPC_OP Analog Output PC Source Current IPC_EN After TOFF Startup Minimum Time to Start TOFF Section 5.0 Startup PC Enable Threshold VPC_EN Digital Input / Output PC Disable Threshold VPC_DIS Standby PC Resistance to disable RPC_EXT Max Resistance to SG required to disable the PRM Digital Output [Short Circuit Fault] Fault PC Sink Current to SG IPC_SC Short circuit, PC Voltage 1 V or above Digital Output [All other Faults] Fault PC Sink Current to ~1V IPC_FAULT Temperature, Over- and Under-Voltage, Overcurrent Voltage Source VS • Intended to power feedback components and/or auxiliary circuits. Signal Type State Attribute VS Voltage Regular VS Available Current Operation VS Voltage Ripple Analog Output Transition VS Capacitance (External) VS Fault Response Time Symbol VVS IVS VVS_PP CVS_EXT TFR_VS Conditions / Notes Min 4.7 Typ Max 5.3 1.8 mA 90 10.0 1.75 18.0 2.50 2.40 µA 30.0 3.20 300 25 10 Min 8.55 5 Iout = 0A, Cvs_ext=0. Maximum specification includes powertrain operation in burst mode. Typ 9.00 100 From fault recognition to VS = 1.5 V Unit V ms V V Ω mA µΑ Max 9.45 Unit V mA 400 mV 0.04 µF µs Unit 30 Reference Enable RE • RE signals successful startup and powertrain ready to operate • Regulated, delayed voltage source intended to power the feedback circuit voltage reference and current monitor Signal Type State Attribute Min Typ Max VRE 3.0 3.3 3.6 V RE Available Current RE Regulation RE Voltage Ripple PC to RE Delay RE Capacitance (External) IRE %RE VRE_PP TPC_RE CRE_EXT 8.0 across load and temperature includes powertrain in burst mode Fault detected 0.1 mA % mV µs µF VS to RE Delay TVS_RE VS = 8.1 V to RE high, VIN > VIN_UVLO- RE Voltage Regular Operation Analog Output Transition Control Node PR • Modulator control node input • Sinks constant current when externally driven • Sources current when pulled below active range Signal Type State Analog Input Regular Operation Attribute PR Voltage Active Range PR Source Current PR Sink Current PR Resistance to SG (Internal) Symbol Conditions / Notes Symbol VPR Conditions / Notes IPR VPR ≤ 0.79V IPR_Low VPR > 0.79V ±2.5 100 100 ms 1 Min 0.79 Typ Max 7.40 Unit V 2 mA 250 500 750 RPR µA kΩ 93.3 Current Feedback IF • A voltage proportional to the PRM output current must be supplied externally to the IF pin in order for the device to properly protect overcurrent events and to enable output current limit (clamp) • Overcurrent protection trip will cause instantaneous powertrain disable, latched after TBLANK Signal Type Analog Input State Regular Operation Attribute Current Limit (clamp) Threshold Symbol VIF_IL Overcurrent Protection Threshold VIF_OC IF Input Impedance Current Limit Bandwidth RIF BW IL Conditions / Notes VIN = 45 V; TJ = 25 °C Not Production Tested; Guaranteed by Design; TJ = 25 °C Min 1.90 Typ 2.00 Max 2.10 2.58 2.69 2.80 2.11 2.13 2 2.15 V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Unit V kΩ kHz Rev. 1.3 10 / 2012 Page 3 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) Temperature Monitor TM • The TM pin monitors the internal temperature of the PRM analog control IC. • "Power Good" flag to verify that the PRM is operating Signal Type Analog Output State Regular Operation Attribute Symbol VTM Conditions / Notes Full temperature range Min 2.12 Typ TM Voltage Max 4.04 TM Voltage reference VTM_AMB TJ = 27 °C 2.94 3.00 3.06 TM Voltage Ripple TM Available Current VVS_PP ITM TM Gain Digital Output [Fault Flag] Fault or Standby TM Disabled Current ITM_DIS Symbol I SG VTM Control VC • Pulsed voltage source used to power and synchronize start up of downstream VTM • If not used, must be resistively terminated to -OUT Signal Type State Attribute VC Voltage Symbol VVC Startup VC Current Limit VC duration VC Slew Rate IVC TVC dVC/dt DC state with TM Voltage +/- 0.5V. This is a high impedance state. mV µA 10 mV/°C 0.0 mA Conditions / Notes Min -100 Typ Max 100 Unit mA Conditions / Notes Min 13 Typ Max Unit V 200 7 500 10 16 RVC = 68Ω VC = 14 V, VIN > 20 V RVC = 1kΩ V 350 100 ATM Signal Ground SG • All control signals must be referenced to this pin, with the exception of VC • SG is internally connected to -IN and -OUT Signal Type State Attribute Analog Input / Output Any Maximum Allowable Current Analog Output powertrain in burst mode Unit V 20 V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 mA ms V/µs Rev. 1.3 10 / 2012 Page 4 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 4.0 FUNCTIONAL BLOCK DIAGRAM +Vin +Vout Vcc PC Vcc 3.3V Linear Regulator Internal Vcc Regulator -Vin 16V PR Vout Cin 3.3V uC 8051 RE L -Vout +Vout 9V Q4 Q2 Output Discharge (OD) 8.2V PR Cout Q3 Q1 Modulator PR 93.3kΩ Enable Var. Vclamp 2.5mA Min VTM Vc Start up pulse 0.5mA 14V VC 10ms Vcc 100uA Q Q SET CLR Fault Logic TOFF delay S Instant latch R R Vout (OV) 5V 2mA max 3V RE RE 3.3V Latch after 120us Vin (OV, UV) Vs 9V 0.01uF Enable PC 10uA PC VPC_EN TM 3 V @ 27°C SG Current Limit Overtemperature Protection VIF_IL Overcurrent Protection Temperature dependent voltage source IF 2130Ω Vref (130°C) VIF_OC V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 5 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 5.0 HIGH LEVEL FUNCTIONAL STATE DIAGRAM Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles. Application of Vin PC HIGH and Toff expiry STARTUP SEQUENCE PC: 1.8mA to HIGH STANDBY SEQUENCE PC: 10uA to LOW Overtemp or Output OVP Toff Timeout PC: 90uA to HIGH Powertrain Stopped Fault removed TBLNK expiry BLANKING PC: 1.8mA to HIGH TBLNK Timeout Powertrain Paused PC falling edge Input OVP, Input UVP, or OverCurrent Prot SUSTAINED OPERATION PC: 1.8mA to HIGH Powertrain Active Short Removed: Vout > VSC_VOUTR or Vpr < VSC_VPR_R Vout < 1 V And TSCR expiry OUTPUT DISCHARGE PC: pulsed 25mA drive LOW PC HIGH and Ton expiry Ton timeout; VC Pulse; Powertrain Active Delayed RE Short Circuit: Vout < VSC_Vout and Vpr > VSC_Vpr SHORT CIRCUIT PC: 1.8mA to HIGH TSC Timeout Powertrain Active TSC expiry PC falling edge TSCR Timeout Powertrain Stopped IOD Output Discharge V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 6 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 6.0 TIMING DIAGRAMS Module Inputs are shown in blue; Module Outputs are shown in brown; Timing diagrams assumes the following: Single PRM (no array) VS powers error amplifier RE powers voltage reference and output current transducer IOUT is sensed, scaled, and fed back to IF pin such that IF = 2.00 V at full load 1 Start up with 1.2V/ms < dVIN/dt < maximum VIN OV TOFF 2 3 4 Quick OC Input OV (t<TBLNK) Input OV recovery 5 PC disable 6 PC release 7 8 Full load Load release and applied Output OV (slow f/b) TON UV 18 V Input Vpr_max PR TBLNK Vpr_min t < TBLNK VIF_OC IFVIF_IL Input / Output TOFF PC TOFF TON TPROT TBLNK Vpc Vpc_en VC Vvc TVC VOUT TPROT OV 1V Output RE TVS_RE TPC_RE TPC_RE TPC_RE Vre_amb Vvs_amb TBLNK VS TM OT Vtm_amb V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 7 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 9 Start up with minimum < dVIN/dt < 1.2V/ms TOFF VIN OV 10 Output short (Output Short fault circuit conditions satisfied) (Output Short fault timer expired) 11 Output Power limit Protection 12 Current limit event 13 Input UV UV 18 V TBLNK Input Vpr_max PR Vpr_min VIF_OC IFVIF_IL TSC Output TSCR+TOFF PC Vpc Vpc_en VC Vvc Input / Output VOUT OV <TBLNK Vsc_vpr 1V RE Vre_amb Vvs_amb VS TM OT Vtm_amb V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 8 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 7.0 APPLICATIONS CHARACTERISTICS The following figures present typical performance at TC = 25º C, unless otherwise noted. See associated figures for general trend data. No Load Power Dissipation vs. Line Module Enabled - Nominal VOUT 1 Power Dissipation [W] Power Dissipation [W] 6 No Load Power Dissipation vs. Line Module Disabled, PC=Low 5 4 3 2 1 0 0.8 0.6 0.4 0.2 0 38 40 42 44 46 48 50 52 54 38 40 42 44 Input Voltage [V] -40 ºC TCASE: 25 ºC 46 48 50 52 54 Input Voltage [V] 100 ºC -40 ºC TCASE: 25 ºC 100 ºC Figure 2 - No load power dissipation vs. VIN, module disabled Efficiency & Power Dissipation VOUT = 20 V TCASE = -40 ºC Efficiency & Power Dissipation VOUT = 48 V TCASE = -40 ºC 12 10 8 6 4 2 0.5 38 1 1.5 2 2.5 3 Load Current [A] 45 55 38 3.5 4 45 Efficiency [%] 14 0 VIN: 16 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 4.5 55 Figure 3 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 20 V, TCASE = -40ºC 14 12 10 8 6 4 2 0 VIN: 16 Power Dissipation [W] 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 Power Dissipation [W] Efficiency [%] Figure 1 - No load power dissipation vs. VIN, module enabled 0.5 38 1 1.5 2 2.5 3 Load Current [A] 45 55 38 3.5 4 45 4.5 55 Figure 4 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 48 V, TCASE = -40ºC V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 9 of 22 Not Recommended for New Designs 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 16 12 10 8 6 4 Efficiency [%] 14 2 0 0.5 1 38 VIN: 1.5 2 2.5 3 Load Current [A] 45 55 3.5 38 4 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 4.5 16 14 12 10 8 6 4 2 0 55 45 Efficiency & Power Dissipation VOUT = 20 V TCASE = 25 ºC Power Dissipation [W] Efficiency & Power Dissipation VOUT = 55 V TCASE = -40 ºC Power Dissipation [W] Efficiency [%] PRM48BH480T200A00 (Formerly VIP0100THJ) 0.5 1 38 VIN: 1.5 2 2.5 3 Load Current [A] 55 45 3.5 38 4 4.5 55 45 Figure 6 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 20 V, TCASE = 25ºC Efficiency & Power Dissipation VOUT = 48 V TCASE = 25 ºC Efficiency & Power Dissipation VOUT = 55 V TCASE = 25 ºC 16 12 10 8 6 4 Efficiency [%] 14 2 0 0.5 1 38 VIN: 1.5 2 2.5 3 Load Current [A] 45 55 3.5 38 4 45 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 4.5 14 12 10 8 6 4 2 0 55 16 Power Dissipation [W] 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 Power Dissipation [W] Efficiency [%] Figure 5 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 55 V, TCASE = -40ºC 0.5 1 38 VIN: 1.5 2 2.5 3 Load Current [A] 45 55 3.5 38 4 45 4.5 55 Figure 8 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 55 V, TCASE = 25ºC Efficiency & Power Dissipation VOUT = 20 V TCASE = 100 ºC Efficiency & Power Dissipation VOUT = 48 V TCASE = 100 ºC 12 10 8 6 4 2 0.5 38 1 1.5 2 2.5 3 Load Current [A] 45 55 38 3.5 4 45 Efficiency [%] 14 0 VIN: 16 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 4.5 55 Figure 9 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 20 V, TCASE = 100ºC 14 12 10 8 6 4 2 0 VIN: 16 Power Dissipation [W] 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 Power Dissipation [W] Efficiency [%] Figure 7 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 48 V, TCASE = 25ºC 0.5 38 1 1.5 2 2.5 3 Load Current [A] 45 55 38 3.5 4 45 4.5 55 Figure 10 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 48 V, TCASE = 100ºC V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 10 of 22 Not Recommended for New Designs 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 16 6.5 14 6 12 10 8 6 4 VPR [V] Efficiency & Power Dissipation VOUT = 55 V TCASE = 100 ºC Power Dissipation [W] Efficiency [%] PRM48BH480T200A00 (Formerly VIP0100THJ) 0.5 1 1.5 38 VIN: 2 2.5 3 3.5 Load Current [A] 45 55 38 4 6.12 6.04 5 4.5 4.62 4.57 4.47 4 -40 4.5 -20 0 20 Figure 11 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 55 V, TCASE = 100ºC 40 60 Temperature [ºC] IOUT: 55 45 6.21 5.5 2 0 VPR vs. Case Temperature VIN = 45 V; VOUT = 48 V 80 2.08 100 4.17 Figure 12 – Typical control node voltage vs. TCASE, IOUT; VIN = 45 V, VOUT = 48 V Powertrain switching frequency and periodic output charge vs. input voltage - Full load fSW [kHz] 18 fsw 1000 16 975 14 950 12 925 10 900 8 875 6 µC 850 4 825 2 800 0 38 Figure 13 – Typical output voltage ripple waveform, TCASE = 30ºC, VIN = 45 V, VOUT = 48 V, IOUT = 4.17 A, no external capacitance. 950 12 925 10 900 8 875 6 µC 4 2 825 38 VOUT 40 55 42 44 46 48 50 Input Voltage [V] 20 48 55 52 54 20 48 50 52 Input Voltage [V] 20 48 54 55 56 20 48 5.21 200 4.17 160 3.13 120 2.08 80 1.04 40 0.00 0 800 46 0 5 56 Output Power [W] 14 Output Current [A] 16 975 850 55 44 DC Safe Operating Area Total input charge per switching cycle [µC] fSW [kHz] 1000 42 Figure 14 – Powertrain switching frequency and periodic output charge vs. VIN, VOUT; IOUT = 4.17 A 18 fsw 40 VOUT Powertrain switching frequency and periodic input charge vs. input voltage - Full load 1025 Total output charge per switching cycle [µC] 1025 10 15 20 25 30 35 40 45 50 55 60 Output Voltage [V] 48 Figure 15 – Powertrain switching frequency and periodic input charge vs. VIN, VOUT; IOUT = 4.17 A Current Power Figure 16 – DC Output Safe Operating Area V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 11 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 4 Gpr 490 8 420 6 350 -2 280 -4 210 -6 140 -2 70 -4 0 -6 r eq_out -8 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 49 42 Gpr 4 G PR [dB] 0 req_out [Ω ] G PR [dB] 2 DC modulator gain and powertrain equivalent output resistance vs. output current - VOUT = 20V 2 28 0 21 45 7 0 4.5 0 0.5 1 1.5 38 45 55 Figure 17 – Powertrain characteristics vs. IOUT; Resistive load, VOUT = 55 V, various VIN 180 2 150 Gpr 120 -2 90 -4 60 r eq_out -6 30 -8 0 1.5 2 2.5 3 3.5 4 4.5 Effective capacitance [µF] 4 req_out [Ω ] G PR [dB] 210 1 45 38 45 55 38 38 45 55 3 2 1.5 1 0.5 0 4.5 5 10 15 20 45 25 30 35 40 45 50 55 Voltage [V] 55 Figure 20 – Effective internal input and output capacitance vs. voltage – ceramic type Powertrain equivalent input resistance vs. output current - VOUT = 55V 32 28 24 Typical max 120 rIN [Ω] Output Power [W] 55 2.5 Nominal 140 4.5 4 Typical min 160 4 3.5 Output Power vs. VPR VIN = 45V, VOUT = 48V, TC=25ºC 180 3.5 0 Figure 19 – Powertrain characteristics vs. IOUT; Resistive load, VOUT = 48 V, various VIN 200 3 Effective internal input (CIN_INT) and output (COUT_INT) capacitance vs. applied voltage Output Current [A] VIN: 2.5 Figure 18 – Powertrain characteristics vs. IOUT; Resistive load, VOUT = 20 V, various VIN 6 0.5 38 VIN: DC modulator gain and powertrain equivalent output resistance vs. output current - VOUT = 48V 0 2 Output Current [A] 55 0 14 r eq_out Output Current [A] 38 VIN: 35 req_out [Ω ] DC modulator gain and powertrain equivalent output resistance vs. output current - VOUT = 55V 100 80 60 20 16 12 8 40 4 20 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0 0.5 1 PR Voltage [V] VIN: Figure 21 – Output Power vs. VPR; VIN = 45 V, VOUT = 48 V, TCASE = 25ºC 38 1.5 2 2.5 3 3.5 4 4.5 Output Current [A] 45 55 Figure 22 – Magnitude of powertrain dynamic input impedance vs. VIN, IOUT; VOUT = 55 V V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 12 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) Powertrain equivalent input resistance vs. output current - VOUT = 20V Powertrain equivalent input resistance vs. output current - VOUT = 48V 180 40 160 35 140 30 100 rIN [Ω] rIN [Ω] 120 80 60 25 20 15 40 10 20 5 0 0 0 0.5 VIN: 1 1.5 38 2 2.5 3 3.5 4 4.5 0 Output Current [A] 45 VIN: 55 Figure 23 – Magnitude of powertrain dynamic input impedance vs. VIN, IOUT; VOUT = 20 V 0.5 1 38 1.5 2 2.5 3 3.5 4 4.5 Output Current [A] 45 55 Figure 24 – Magnitude of powertrain dynamic input impedance vs. VIN, IOUT; VOUT = 48 V 8.0 GENERAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and Output Voltage from 20 V to 55 V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade). Attribute MECHANICAL Length Width Symbol 22.0 / [0.87] 22.3 / [0.88] mm / [in] 16.5 / [0.65] 16.8 / [0.66] mm / [in] Weight W 6.48 / [0.255] 6.73 / [0.265] 6.98 / [0.275] mm / [in] No Heatsink Nickel Palladium Gold Lead Finish TJ Any operating condition TC TST 0.51 0.02 0.003 -40 -40 7 5 ESDHBM 1000 ESDCDM Charged Device Model, "JEDEC JESD 22-C101D" 400 2.03 0.15 0.050 125 100 3 5.33 125 -40 MSL 6, four hours out of bag maximum MSL 5 Human Body Model, "JEDEC JESD 22-A114C.01" g µm ºC ºC Ws/ºC lbs lbs / in 2 ºC V Under MSL 6 conditions above Under MSL 5 conditions above Maximum Time Above [217] ºC Peak Heating Rate During Reflow Peak Cooling Rate Post Reflow 3 cm / [in3] 2.44 / [0.15] Supported by J-Lead only Moisture Sensitivity Level Peak Temperature During Reflow Unit 21.8 / [0.86] H SOLDERING Max 16.3 / [0.64] Vol ESD Rating Typ L Volume ASSEMBLY Peak Compressive Force Applied to Case (Z-axis) Storage Temperature Min W Height THERMAL Operating and Storage Junction Temperature Operating Case Temperature Thermal Capacity Conditions / Notes 1.5 2.5 245 225 150 2 3 ºC ºC s ºC / s ºC / s SAFETY and RELIABILITY MTBF Agency Approvals / Standards Telcordia Issue 2 - Method I Case 1; Ground Benign, Controlled 2.51 MHrs MIL-HDBK-217Plus Parts Count - 25C Ground Benign, Stationary, Indoors / Computer Profile 4.93 MHrs C TUV US CE Mark ROHS 6 of 6 V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 13 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 9.0 PRODUCT OUTLINE DRAWING AND RECOMMENDED PCB FOOTPRINT V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 14 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 10.0 PRODUCT DETAILS AND DESIGN GUIDELINES 10.1 Control pins description and characteristics Control node (PR) is the input to the control node which determines the powertrain timing and ultimately the module output power (Figure 21). An internal 0.5mA current sink is always active. The bi-directional buffer between PR and the control node has two states. In normal operation, PR will be above the 0.79 V switching threshold, and will drive the control node through the buffer. An internal 7.4 V clamp determines the maximum output power that can be requested of the modulator. When PR falls below 0.79 V, the converter will stop switching. An internal circuit clamps the modulator input control node to 0.79 V, and a buffer will source up to 2.5 mA out of the pin at that clamp level. For this reason, the output impedance of the amplifier driving PR must be taken into account. A rail-to-rail operational amplifier with low output impedance is always recommended. The powertrain small signal (plant) response consists of a single pole determined by the load resistance, the powertrain equivalent output resistance, and the total output capacitance (internal and external to the module). Both the modulator gain and the equivalent output resistance vary as a function of line, load and output voltage, as shown in Figures 17, 18 and 19. As the load increases, the powertrain pole moves to higher frequency. As a result, the closed loop crossover frequency will be the highest at full load and lowest at minimum load. Figure 25 shows a reference AC small-signal model. Current feedback (IF) is the input for the module output overcurrent protection and current limit features (see functional block diagram in section 4.0). A voltage proportional to the powertrain output current must be applied to IF in order for overcurrent protection to operate properly. If the IF voltage exceeds the IF pin’s overcurrent protection threshold, the powertrain will stop switching. If the IF voltage falls below the overcurrent protection threshold within TBLANK time, then the powertrain will immediately resumes switching. Otherwise a fault is latched. The current limit threshold for the IF pin is set lower than the protection threshold. When the IF pin average voltage exceeds the current limit threshold, an internal integrator will activate a clamp amplifier which overrides the modulator input maximum level. This causes the powertrain to maintain a constant output current. The bandwidth of this current limit integrator is significantly slower than that of the PR control node input. Therefore this current limit can not be used in lieu of properly compensating the (external) PR control loop to avoid exceeding maximum current or power ratings for the device. If the IF pin is not driven, it must be resistively terminated to SG. A 1 kΩ resistor to SG is recommended in this case. + VIN CIN_INT rEQ_IN + + VPR ∙ GPR VPR RPR IPR_Low COUT_INT rEQ_OUT - Figure 25 – PRM48BH480T200A00 AC small signal model V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 15 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) VTM Control (VC) pin supplies an initial VCC voltage to downstream VTMs, enabling them and synchronizing their startup with the PRM. The VCC voltage is a pulse, typically 10 ms duration at 14 V. If VC is not loaded by a VTM, it must be terminated with a 1 kΩ resistor to –VOUT. Primary Control (PC) is both an input and an output. It can provide the following features: • Delayed start: upon application of voltage (>UVLO) to the module power input and after TOFF, the PC pin will source a constant 90 μA current. • Output disable: PC may be pulled down externally in order to disable the module. Pull down resistance should be less than 300 Ω to SG. • Fault detection flag: The PC 5 V voltage source is internally turned off when a fault condition is latched. Note that aside from the Short Circuit fault condition, PC does not have significant current sinking capability. Therefore in the case of an array of PRMs with interconnected PC pins, PC does not in general reflect the fault state of all PRMs. The common PC line will not disable neighboring modules when a fault is detected except for a latched Output Short Circuit fault. Conversely any unit in the array latching a Short Circuit fault will disable the array for TSCR. Signal Ground (SG) pin provides a Kelvin connection to the PRM’s internal signal ground. It should be used as the reference for PR, TM, IF, and should return all PC, VS and RE pin currents. In array configurations with common ground control circuits, a series resistor (~1 Ω) is recommended in order to decouple power and signal current returns. 10.2 Control circuit requirements and design procedure The PRM48BH480T200A00 is an intelligent powertrain module designed to fully exploit external output voltage feedback and current sensing sub-circuits. These two external circuits are illustrated in Figure 26, which shows an example of the PRM in a standalone application with local voltage feedback and high side current sensing. In general, these circuits include a precision voltage reference, an operational amplifier which provides closed loop feedback compensation, and a high side current sense circuit which includes a shunt and current sense IC. The following design procedures refer to the circuit shown in Figure 26. 10.2.1 Setting the output voltage level Temperature Monitor (TM) pin outputs a voltage proportional to the absolute temperature of the converter analog control IC. It can be used to accomplish the following functions: • Monitor the control IC temperature: The gain and setpoint of TM are such that the temperature, in Kelvin, of the PRM controller IC is equal to the voltage on the TM pin scaled by 100. (i.e. 3.0 V = 300 K = 27 ºC). • Closed loop thermal management at the system level (e.g. variable speed fans or coolant flow) • Fault detection flag: The TM voltage source is turned off as soon as a fault is detected. For system monitoring purposes (microcontroller interface) faults are detected on falling edges of TM. The output voltage setpoint is a function of the voltage reference and the output voltage sense ratio. With reference to Fig. 26, R1 and R2 form the output voltage sensing divider which provides the scaled output voltage to the negative input of the error amplifier; a dedicated reference IC provides the reference voltage to the positive input of the error amplifier. Under normal operation, the error amplifier will keep the voltages at the inverting and non-inverting inputs equal, and therefore the output voltage is defined by: Reference Enable (RE) pin outputs a regulated 3.3 V, 8 mA voltage source. It is enabled only after successful startup of the PRM powertrain (see chapters 5.0 and 6.0.) RE is intended to power the output current transducer and also the voltage reference for the control loop. Powering the reference generator with RE helps provide a controlled startup, since the output voltage of the system is able to track the reference level as it comes up. Note that the component R1 will also factor into the compensation as described in a later section. Voltage Source (VS) pin outputs a gated (e.g. mirrors PC status), non-isolated, regulated 9 V, 5 mA voltage source. It can be used to power external control circuitry; it always leads RE. VOUT = Vref ⋅ R1 + R 2 R2 It is important to apply proper slew rate to the reference voltage rise when the control loop is initially enabled. The recommended range for reference rise time is 1 ms to 9 ms. The lower rise time limit will ensure optimized modulator timing performance during startup, and to allow the current limit feature (through IF pin) to fully protect the device during power-up. The upper rise time limit is needed to guarantee a sufficient factorized bus voltage is provided to any downstream VTM input before the end of the VC pulse. V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 16 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 10.2.2 Setting the output current limit and overcurrent protection level The current limit and overcurrent protection set points are linked, and scale together against the current sense shunt, and the gain of the current sense amplifier. The output of the current sense IC provides the IF voltage which has VIF_IL and VIF_OC thresholds for the two functions respectively. The set points are therefore defined by: I IL = and I OC = VIF _ IL RS ⋅ GCS Powertrain equivalent resistance rEQ: See Figures 17, 18, 19 Internal output capacitance: see Figure 20 External output capacitance value In the case of ceramic capacitors, the ESR can be considered low enough to push the associated zero well above the frequency of interest. Applications with high ESR capacitor may require a different type of compensation, or cascade control. The system poles and zeros of the closed loop can then be defined as follows: VIF _ OC Powertrain pole, assuming the external capacitor ESR can be neglected: RCOUT _ EXT << RS ⋅ GCS where GCS is the gain of the current sense amplifier. 10.2.3 Control loop compensation requirements In order to properly compensate the control loop, all components which contribute to the closed loop frequency response should be identified and understood. Figure 25 shows the AC small signal model for the module. Modulator DC transconductance gain (GPR) and powertrain These equivalent resistance (rEQ_OUT) are shown. modeling parameters will support a design cut-off frequency up to 50 kHz. Standard Bode analysis should be used for calculating the error amplifier compensation and analyzing the closed loop stability. The recommended stability criteria are as follows: 1) Phase Margin > 45º : for the closed loop response, the phase should be greater than 45º where the gain crosses 0dB. 2) Gain Margin > 10dB : The closed loop gain should be lower than -10dB where the phase crosses 0º. 3) Gain Slope = -20dB / decade : The closed loop gain should have a slope of -20dB / decade at the crossover frequency. The compensation characteristics must be selected to meet these stability criteria. Refer to Figure 27 for a local sense, voltage-mode control example based on the configuration in Figure 26. In this example, it is assumed that the maximum crossover frequency (FCMAX) has been selected to occur between B and C. Type-2 compensation (Curve IJKL) is sufficient in this case. The following data must be gathered in order to proceed: Modulator Gain GPR: See Figures 17, 18, 19 rEQ _ OUT + RLOAD Main pole frequency: FP ≈ rEQ _ OUT ⋅ RLOAD 2 π⋅ rEQ _ OUT ⋅ RLOAD rEQ _ OUT + RLOAD R3 R1 [1] Compensation Zero: FZ1 = ⋅ (COUT _ INT + COUT _ EXT ) Compensation Mid-Band Gain: G MB = 20 log 1 1 2 π⋅ R 3 ⋅ C1 [2] Compensation Pole: FP 2 = 1 R ⋅C ⋅C 2 π⋅ 3 1 2 C1 + C2 and for FP2>>FZ1 (C1 + C2 ≈ C1): FP 2 ≈ 1 2π ⋅ R3 ⋅ C2 [3] V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 17 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 10.2.4 Midband Gain Design (R1,R3): 10.2.5 Compensation Zero Design (C1): With reference to Figure 27: curve ABC is the: minimum output voltage in the application maximum input voltage expected in the application maximum load PRM open loop response, and is where the maximum crossover frequency occurs. In order for the maximum crossover frequency to occur at the design choice FCMAX, the compensation gain must be equal and opposite of the powertrain gain at this frequency. For stability purposes, the compensation should be in the Mid-band (J-K) at the crossover. Using Equation [1], the mid-band gain can be selected appropriately. With reference to Figure 27: curve EFG is the: maximum output voltage in the application minimum input voltage expected in the application minimum load in the application PRM open loop response, and is where the minimum crossover frequency FCMIN occurs. Based on stability criteria, the compensation must be in the mid-band at the minimum crossover frequency, therefore FCMIN will occur where EFG is equal and opposite of GMB. C1 can be selected using Equation [2] so that FZ1 occurs prior to FCMIN. C2 C1 R3 + Vref R2 R1 F1 +IN CIN_EXT CIN_INT -IN Vref Vref IC VS IF RE PR RS +OUT PRM COUT_EXT COUT_INT SG -OUT I sense IC Figure 26 – Control circuit example V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 18 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) Open Loop Gain vs. Frequency 80 60 Gain (dB) 40 20 I Application's op-amp G·BW Compensation Gain F E PRM Open Loop Min Load B A PRM Open Loop Max Load J K FCMIN 0 L FCMAX -20 C G -40 Frequency, Log scale (y-intercept is application specific) Figure 27 – Reference asymptotic Bode plot for the considered system 10.2.6 High Frequency Pole Design (C2): Using Equation [3], C2 should be selected so that FP2 is at least one decade above FCMAX and prior to the gain bandwidth product of the operational amplifier (10 MHz for this example). For applications with a higher desired crossover frequency the use of a high gain bandwidth product amplifier may be necessary to ensure that the real pole can be set at least one decade above the maximum crossover frequency. based on the ratio of the “kick” to “droop” (as defined in Fig. 28). k Vout d 10.2.7 Verifying Stability: The preferred method for verifying stability is to use a network analyzer, measuring the closed loop response across various lines and load conditions. In the absence of a network analyzer, a load step transient response can be used in order to estimate stability. Figure 28 illustrates an example of a load step response. Equation [4] can be used to predict the phase margin time Iout time Figure 28 – load step response example and “droop” vs. “kick” definition V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 19 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 2 k ln d Φ m ≈ 100 2 k 2 ln + π d 10.3 [4] Figure 20 provides the effective internal capacitance of the module. A conservative estimate of input and output peakpeak voltage ripple at nominal line and trim is provided by equation [5]: ∆V = Burst Mode Operation: At light loads, the PRM will operate in a burst mode due to minimum timing constraints. An example burst operation waveform is illustrated in Figure 29. For very light loads, and also for higher input voltages, the minimum time power switching cycle from the powertrain will exceed the power required by the load. In this case the external error amplifier will periodically drive PR below the switching threshold in order to maintain regulation. Switching will cease momentarily until the error amplifier once again drives PR voltage above the threshold. QTOT − C INT I FL ⋅ 0.4 f SW + C EXT [5] QTOT is the total input (Fig. 15) or output (Fig. 14) charge per switching cycle at full load, while CINT is the module internal effective capacitance at the considered voltage (Fig. 20) and CEXT is the external effective capacitance at the considered voltage. 10.5 Input filter stability The PRM can provide very high dynamic transients. It is therefore very important to verify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. For this purpose, the converter dynamic input impedance magnitude rEQ _ IN is provided in Figures 22, 23, 24. It is recommended to provide adequate design margin with respect to the stability conditions illustrated in 10.5.1 and 10.5.2. 10.5.1 Inductive source and local, external input decoupling capacitance with negligible ESR (i.e.: ceramic type) Figure 29 – light load burst mode of operation Note that during the bursts of switching, the powertrain frequency is constant, but the number of pulses as well as the time between bursts is variable. The variability depends on many factors including input voltage, output voltages, load impedance, and external error amplifier output impedance. In burst mode, the gain of the PR input to the plant which is modeled in the previous sections is time varying. Therefore the small signal analysis can not be directly applied to burst mode operation. 10.4 Input and Output filter design Figures 14 and 15 provide the total input and output charge per cycle, as well as switching frequency, of the PRM at full load under various input and output voltages conditions. The voltage source impedance can be modeled as a series RlineLline circuit. The high performance ceramic decoupling capacitors will not significantly damp the network because of their low ESR; therefore in order to guarantee stability the following conditions must be verified: Rline > (C IN _ INT Lline + C IN _ EXT ) ⋅ rEQ _ IN Rline << rEQ _ IN [6] [7] It is critical that the line source impedance be at least an octave lower than the converter’s dynamic input resistance, [7]. However, Rline cannot be made arbitrarily low otherwise equation [6] is violated and the system will show instability, due to under-damped RLC input network. V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 20 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) 10.5.2 Inductive source and local, external input decoupling capacitance with significant RCIN_EXT ESR (i.e.: electrolytic type) In order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor Lline. Notice that, the high performance ceramic capacitors CIN_INT within the PRM should be included in the external electrolytic capacitance value for this purpose. The stability criteria will be rEQ _ IN > RC IN _ EXT [8] Lline < rEQ _ IN C IN _ EXT ⋅ RC IN _ EXT [9] Equation [9] shows that if the aggregate ESR is too small – for example by using very high quality input capacitors (CIN_EXT) – the system will be under-damped and may even become destabilized. Again, an octave of design margin in satisfying [8] should be considered the minimum. 10.6 Arrays Up to ten PRMs of the same type may be placed in parallel to expand the power capacity of the system. The following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. –IN pins of all PRMs must be connected together. Both inductance and resistance from the common power source to each PRM should be minimized, and matched. Input voltage to all PRMs must be the same. Independent fuses for each PRM are recommended. PC pins must be connected together for synchronization and proper fault response. Reference supply to the control loop voltage reference and current sense circuitry must be enabled when all modules’ RE pins have reached their operational voltage levels. There must be one single external voltage control loop. The control loop must drive each PR pin relative to each module’s SG pin, and the local PR voltage must be the same across all modules. Each PRM must have its own local current shunt and current sense circuitry to drive its IF pin. The number of PRMs required to achieve a given array capacity must consider all sources of mismatch to avoid overstress of any PRM in the array. Imbalances in sharing are not only due to current sharing accuracy specifications, but also temperature differences among PRMs, Vin variations, and error terms in the buffering of the error amplifier output to the PR pins. Control loop compensation procedures above will hold for an array, in general, although many parameters must be scaled against the number of PRMs in the system. Please contact Vicor Applications for assistance. 10.7 Input Fuse Recommendations A fuse should be incorporated at the input to each PRM, in series with the +IN pin. A 10 A or smaller input fuse ® 2® 451/453 Series, or equivalent) is (Littelfuse NANO required to safety agency conditions of acceptability. Always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. 10.8 Layout considerations Application Note AN:005 details board layout using V•I Chip components. Additional consideration must be given to the external control circuit components. The current sense shunt signal voltage is highly sensitive to noise. As such, current sensing circuitry should be located close to the shunt to minimize the length of the sense signals. A Kelvined connection at the shunt is recommended for best results. The control signal from a remote voltage sense circuit to the PRM should be shielded. Avoid routing this, or other control signals directly underneath the PRM, if possible. Components that tie directly to the PRM should be located close to their respective pins. It is also critical that all control components be referenced to SG, and that SG not be tied to any other ground in the system, including –IN or –OUT of the PRM. V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 21 of 22 Not Recommended for New Designs PRM48BH480T200A00 (Formerly VIP0100THJ) Warranty Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages. Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. Intellectual Property Notice Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965. Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Customer Service: [email protected] Technical Support: [email protected] V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Rev. 1.3 10 / 2012 Page 22 of 22