C8051F066 25 MIPS, 32 kB Flash, 16-Bit ADC, 100-Pin Mixed-Signal MCU Analog Peripherals High-Speed 8051 µC Core - Two 16-Bit ADCs - ±0.75 LSB INL; no missing codes Programmable throughput up to 1 Msps (each ADC) 1 external input each; programmable as two single-ended or one differential ADC DMA to XRAM or external memory interface Data-dependent windowed interrupt generator Three Comparators - - - 4352 bytes data RAM 32 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved) External parallel data memory interface Digital Peripherals - On-Chip JTAG Debug & Boundary Scan - Memory - 16 programmable hysteresis values Configurable to generate interrupts or reset Internal Voltage Reference Precision VDD Monitor/Brown-out Detector - - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan - 59 port I/O; all are 5 V tolerant Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial ports available concurrently Programmable 16-bit counter/timer array with six capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using timers or PCA Clock Sources - Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation External oscillator: Crystal, RC, C, or Clock Can switch between clock sources on-the-fly Supply Voltage: 2.7 to 3.6 V - Typical operating current: 18 mA at 25 MHz Multiple power saving sleep and shutdown modes 100-Pin TQFP Temperature Range: –40 to +85 °C VDD VDD VDD DGND DGND DGND AV+ AGND TCK TMS TDI TDO Digital Power Analog Power Boundary Scan JTAG Logic Debug HW Reset /RST MONEN XTAL1 XTAL2 8 0 5 1 VDD Monitor UART1 SMBus SPI Bus PCA External Oscillator Circuit VREF AVDD ADGND AV+ AGND VREF0 VRGND0 ADC0 1 Msps (16-Bit) AIN0 AIN0G VBGAP0 CNVSTR0 AVDD ADGND AIN1G VBGAP1 CNVSTR1 Precision Mixed Signal ADC1 1 Msps (16-Bit) 256 Byte RAM R E S U L T 1 CP0 4 kB RAM CP1 Σ - D I F F DMA Bus Control EMIF Cntrl Address Bus + - + - P4 Latch Ctrl Latch P5 Latch Addr15-8 P6 Latch Addr7-0 Data Bus Copyright © 2004 by Silicon Laboratories P0 Drv P0.0 P1 Drv P1.0/AIN2.0 P2 Drv P2.0 P3 Drv P3.0 P0.7 P1.7/AIN2.7 P2.7 P3.7 P2.6 P2.7 P2.2 P2.3 + CP2 External Data Memory Bus + C R O S S B A R 32 kB FLASH R E S U L T 0 AV+ AGND VREF1 VRGND1 AIN1 P0, P1, P2, P3 Latches C o r e System Clock Timers 0, 1, 2,3,4 SFR Bus WDT 25 MHz 2% Internal Oscillator VREF UART0 P7 Latch Data Latch P2.4 P2.5 P4 DRV P4.5 P4.6 P4.7 P5 DRV P5.0 P6 DRV P6.0 P7 DRV P7.0 P5.7 P6.7 P7.7 7.28.04 C8051F066 25 MIPS, 32 kB Flash, 16-Bit ADC, 100-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current Clock = 25 MHz (CPU active) Clock = 1 MHz Clock = 32 kHz; VDD Monitor Enabled Supply Current Oscillator not running; VDD Monitor (shutdown) Disabled Clock Frequency Range 16-BIT A/D CONVERTERS Resolution Integral Nonlinearity Single-ended Mode Differential Mode Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Fin = 10 kHz, Single-ended Distortion Fin = 10 kHz, Differential Total Harmonic Distortion Fin = 10 kHz, Single-ended Fin = 10 kHz, Differential Spurious-Free Dynamic Fin = 10 kHz, Single-ended Range Fin = 10 kHz, Differential Throughput Rate Input Voltage Range Single-ended (AINn–AINnG) Differential (AIN0–AIN1) Power Supply Current Operating Mode, 1 Msps (each ADC) (AVDD + AV+) Shutdown Mode MIN TYP 2.7 MAX UNITS 3.6 V mA mA µA µA 25 MHz 18 0.7 20 0.1 DC 16 ±0.75 ±0.50 ±0.5 86 89 96 103 97 104 ±2 ±1 ±1 1 VREF VREF 0 –VREF bits LSB LSB LSB dB dB dB dB dB dB Msps V V 5.5 1 mA µA C8051F060DK Development Kit Package Information D MIN NOM MAX (mm) (mm) (mm) D1 A - A1 0.05 - 1.20 - 0.15 A2 0.95 1.00 1.05 b E1 E 0.17 0.22 0.27 D - 16.00 - D1 - 14.00 - e - 0.50 - E - 16.00 - E1 - 14.00 - 100 PIN 1 DESIGNATOR A2 1 e A b Precision Mixed Signal A1 Copyright © 2004 by Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 7.28.04