Si8450/51/52/55 L O W P O W E R F I V E - C H A N N E L D I G I TA L I S O L A T O R Features High-speed operation DC Up to 2500 VRMS isolation to 150 Mbps 60-year life at rated working No start-up initialization required voltage Wide Operating Supply Voltage: Precise timing (typical) 2.70–5.5 V <10 ns worst case Ultra-low-power (typical) 1.5 ns pulse width distortion 5 V Operation: 0.5 ns channel-channel skew < < N ot fo R r N ec e w om m D e e s nd ig e ns d 2 1.6 mA per channel at 1 Mbps 6 mA per channel at 100 Mbps 2.70 V Operation: 6 ns propagation delay skew ns minimum pulse width Transient Immunity 25 kV/µs 1.4 mA per channel at 1 Mbps Wide temperature range < 4 mA per channel at 100 Mbps –40 to 125 °C at 150 Mbps < High electromagnetic immunity Ordering Information: See page 29. RoHS-compliant packages SOIC-16 narrow body Applications Industrial automation systems Hybrid electric vehicles Isolated switch mode supplies Isolated ADC, DAC Motor control Power inverters Communications systems Safety Regulatory Approvals UL 1577 recognized Up to 2500 VRMS for 1 minute CSA component notice 5A approval IEC VDE certification conformity IEC 60747-5-2 (VDE0884 Part 2) 60950-1, 61010-1 (reinforced insulation) Description Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages when compared to legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges throughout their service life. For ease of design, only VDD bypass capacitors are required. Data rates up to 150 Mbps are supported, and all devices achieve worst-case propagation delays of less than 10 ns. All products are safety certified by UL, CSA, and VDE and support withstand voltages of up to 2.5 kVrms. These devices are available in a 16-pin narrowbody SOIC package. Rev. 1.5 9/13 Copyright © 2013 by Silicon Laboratories Si8450/51/52/55 N ot fo R r N ec e w om m D e e s nd ig e ns d Si8450/51/52/55 2 Rev. 1.5 Si8450/51/52/55 TABLE O F C ONTENTS Section Page N ot fo R r N ec e w om m D e e s nd ig e ns d 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1. Enable Pin Causes Outputs to Go Low (Revision A Only) . . . . . . . . . . . . . . . . . . . . 26 3.2. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . . 26 3.3. Latch Up Immunity (Revision A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4. Pin Descriptions (Si8450/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5. Pin Descriptions (Si8455) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Rev. 1.5 3 Si8450/51/52/55 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit TA 150 Mbps, 15 pF, 5 V –40 25 125 °C VDD1 2.70 — 5.5 V VDD2 2.70 — 5.5 V Ambient Operating Temperature* Supply Voltage N ot fo R r N ec e w om m D e e s nd ig e ns d *Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 2. Absolute Maximum Ratings1 Parameter Storage Temperature Symbol Min Typ Max Unit TSTG –65 — 150 °C 2 Ambient Temperature Under Bias TA –40 — 125 °C 3 VDD1, VDD2 –0.5 — 5.75 V Supply Voltage (Revision B)3 VDD1, VDD2 –0.5 — 6.0 V Input Voltage VI –0.5 — VDD + 0.5 V Output Voltage VO –0.5 — VDD + 0.5 V Output Current Drive Channel IO — — 10 mA Lead Solder Temperature (10 s) — — 260 °C Maximum Isolation Voltage (1 s) — — 3600 VRMS Supply Voltage (Revision A) Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. VDE certifies storage temperature from –40 to 150 °C. 3. See "6. Ordering Guide" on page 29 for more information. 4 Rev. 1.5 Si8450/51/52/55 Table 3. Electrical Characteristics (VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 4.8 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V IL — — ±10 µA ZO — 85 — Input Leakage Current 1 N ot fo R r N ec e w om m D e e s nd ig e ns d Output Impedance Enable Input High Current IENH VENx = VIH — 2.0 — µA Enable Input Low Current IENL VENx = VIL — 2.0 — µA DC Supply Current (All inputs 0 V or at Supply) Si8450Ax, Bx, Si8455Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 Si8451Ax, Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 2.0 3.0 6.0 4.1 3.0 4.5 9.0 6.2 Si8452Ax, Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 2.3 2.7 5.4 4.7 3.5 4.1 8.1 7.1 mA mA mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8450Ax, Bx, Si8455Bx VDD1 VDD2 — — 4.3 3.5 6.5 5.3 mA Si8451Ax, Bx VDD1 VDD2 — — 4.1 4.0 6.2 6.0 mA Si8452Ax, Bx VDD1 VDD2 — — 4.1 4.0 6.2 6.0 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 26 for more details. 4. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.5 5 Si8450/51/52/55 Table 3. Electrical Characteristics (Continued) (VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) — — 4.3 4.8 6.5 6.7 mA Si8451Bx VDD1 VDD2 — — 4.4 5.0 6.2 7.0 mA 6.4 6.7 mA Si8452Bx VDD1 VDD2 N ot fo R r N ec e w om m D e e s nd ig e ns d Si8450Bx, Si8455Bx VDD1 VDD2 — — 4.6 4.8 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8450Bx, Si8455Bx VDD1 VDD2 — — 4.6 24 6.9 30 mA Si8451Bx VDD1 VDD2 — — 8.6 20.4 10.8 25.5 mA — — 12.6 16.5 15.8 20.6 mA Maximum Data Rate 0 — 1.0 Mbps Minimum Pulse Width — — 250 ns Si8452Bx VDD1 VDD2 Timing Characteristics Si845xAx Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 2 — — 35 ns PWD See Figure 2 — — 25 ns tPSK(P-P) — — 40 ns tPSK — — 35 ns Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 26 for more details. 4. Start-up time is the time period from the application of power to valid data at the output. 6 Rev. 1.5 Si8450/51/52/55 Table 3. Electrical Characteristics (Continued) (VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.0 ns Si845xBx Propagation Delay Channel-Channel Skew All Models See Figure 2 3.0 6.0 9.5 ns PWD See Figure 2 — 1.5 2.5 ns tPSK(P-P) — 2.0 3.0 ns tPSK — 0.5 1.8 ns N ot fo R r N ec e w om m D e e s nd ig e ns d Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 tPHL, tPLH Output Rise Time tr CL = 15 pF See Figure 2 — 3.8 5.0 ns Output Fall Time tf CL = 15 pF See Figure 2 — 2.8 3.7 ns CMTI VI = VDD or 0 V — 25 — kV/µs ten1 See Figure 1 — 5.0 8.0 ns ten2 See Figure 1 — 7.0 9.2 ns — 15 40 µs Common Mode Transient Immunity Enable to Data Valid3 3 Enable to Data Tri-State 3,4 Start-up Time tSU Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 26 for more details. 4. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.5 7 Si8450/51/52/55 ENABLE N ot fo R r N ec e w om m D e e s nd ig e ns d OUTPUTS ten1 ten2 Figure 1. ENABLE Timing Diagram 1.4 V Typical Input tPLH tPHL 90% 90% 10% 10% 1.4 V Typical Output tr tf Figure 2. Propagation Delay Timing 8 Rev. 1.5 Si8450/51/52/55 Table 4. Electrical Characteristics (VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 3.1 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V IL — — ±10 µA ZO — 85 — Input Leakage Current N ot fo R r N ec e w om m D e e s nd ig e ns d Output Impedance 1 Enable Input High Current IENH VENx = VIH — 2.0 — µA Enable Input Low Current IENL VENx = VIL — 2.0 — µA DC Supply Current (All inputs 0 V or at supply) Si8450Ax, Bx, Si8455Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 dc All inputs 0 dc All inputs 1 dc All inputs 1 dc — — — — 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 Si8451Ax, Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 dc All inputs 0 dc All inputs 1 dc All inputs 1 dc — — — — 2.0 3.0 6.0 4.1 3.0 4.5 9.0 6.2 Si8452Ax, Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 2.3 2.7 5.4 4.7 3.5 4.1 8.1 7.1 mA mA mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8450Ax, Bx, Si8455Bx VDD1 VDD2 — — 4.3 3.5 6.5 5.3 mA Si8451Ax, Bx VDD1 VDD2 — — 4.1 4.0 6.2 6.0 mA Si8452Ax, Bx VDD1 VDD2 — — 4.1 4.0 6.2 6.0 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 26 for more details. 4. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.5 9 Si8450/51/52/55 Table 4. Electrical Characteristics (Continued) (VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) — — 4.3 4.8 6.5 6.7 mA Si8451Bx VDD1 VDD2 — — 4.4 5.0 6.2 7.0 mA 6.4 6.7 mA Si8452Bx VDD1 VDD2 N ot fo R r N ec e w om m D e e s nd ig e ns d Si8450Bx, Si8455Bx VDD1 VDD2 — — 4.6 4.8 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8450Bx, Si8455Bx VDD1 VDD2 — — 4.4 16.8 6.6 21 mA Si8451Bx VDD1 VDD2 — — 6.9 14.5 8.6 18.1 mA — — 9.5 12 11.9 15 mA Maximum Data Rate 0 — 1.0 Mbps Minimum Pulse Width — — 250 ns Si8452Bx VDD1 VDD2 Timing Characteristics Si845xAx Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL,tPLH See Figure 2 — — 35 ns PWD See Figure 2 — — 25 ns tPSK(P-P) — — 40 ns tPSK — — 35 ns Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 26 for more details. 4. Start-up time is the time period from the application of power to valid data at the output. 10 Rev. 1.5 Si8450/51/52/55 Table 4. Electrical Characteristics (Continued) (VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.0 ns Si845xBx Propagation Delay Channel-Channel Skew All Models See Figure 2 3.0 6.0 9.5 ns PWD See Figure 2 — 1.5 2.5 ns tPSK(P-P) — 2.0 3.0 ns tPSK — 0.5 1.8 ns N ot fo R r N ec e w om m D e e s nd ig e ns d Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 tPHL, tPLH Output Rise Time tr CL = 15 pF See Figure 2 — 4.3 6.1 ns Output Fall Time tf CL = 15 pF See Figure 2 — 3.0 4.3 ns CMTI VI = VDD or 0 V — 25 — kV/µs ten1 See Figure 1 — 5.0 8.0 ns ten2 See Figure 1 — 7.0 9.2 ns — 15 40 µs Common Mode Transient Immunity Enable to Data Valid3 Enable to Data Tri-State Start-up Time 3,4 3 tSU Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 26 for more details. 4. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.5 11 Si8450/51/52/55 Table 5. Electrical Characteristics1 (VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH lOH = –4 mA VDD1,VDD2 – 0.4 2.3 — V Low Level Output Voltage VOL IOL = 4 mA — 0.2 0.4 V IL — — ±10 µA ZO — 85 — Input Leakage Current N ot fo R r N ec e w om m D e e s nd ig e ns d Output Impedance 2 Enable Input High Current IENH VENx = VIH — 2.0 — µA Enable Input Low Current IENL VENx = VIL — 2.0 — µA DC Supply Current (All inputs 0 V or at supply) Si8450Ax, Bx, Si8455Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 Si8451Ax, Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 2.0 3.0 6.0 4.1 3.0 4.5 9.0 6.2 Si8452Ax, Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 2.3 2.7 5.4 4.7 3.5 4.1 8.1 7.1 mA mA mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8450Ax, Bx, Si8455Bx VDD1 VDD2 — — 4.3 3.5 6.5 5.3 mA Si8451Ax, Bx VDD1 VDD2 — — 4.1 4.0 6.2 6.0 mA Si8452Ax, Bx VDD1 VDD2 — — 4.1 4.0 6.2 6.0 mA Notes: 1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is constrained to TA = 0 to 85 °C. 2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. See "3. Errata and Design Migration Guidelines" on page 26 for more details. 5. Start-up time is the time period from the application of power to valid data at the output. 12 Rev. 1.5 Si8450/51/52/55 Table 5. Electrical Characteristics1 (Continued) (VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) — — 4.3 4.8 6.5 6.7 mA Si8451Bx VDD1 VDD2 — — 4.4 5.0 6.2 7.0 mA 6.4 6.7 mA Si8452Bx VDD1 VDD2 N ot fo R r N ec e w om m D e e s nd ig e ns d Si8450Bx, Si8455Bx VDD1 VDD2 — — 4.6 4.8 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8450Bx, Si8455Bx VDD1 VDD2 — — 4.3 13.3 6.5 16.6 mA Si8451Bx VDD1 VDD2 — — 6.2 11.7 7.8 14.6 mA — — 8.0 9.9 10 12.4 mA Maximum Data Rate 0 — 1.0 Mbps Minimum Pulse Width — — 250 ns Si8452Bx VDD1 VDD2 Timing Characteristics Si845xAx Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew3 Channel-Channel Skew tPHL,tPLH See Figure 2 — — 35 ns PWD See Figure 2 — — 25 ns tPSK(P-P) — — 40 ns tPSK — — 35 ns Notes: 1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is constrained to TA = 0 to 85 °C. 2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. See "3. Errata and Design Migration Guidelines" on page 26 for more details. 5. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.5 13 Si8450/51/52/55 Table 5. Electrical Characteristics1 (Continued) (VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.0 ns Si845xBx Propagation Delay Channel-Channel Skew All Models See Figure 2 3.0 6.0 9.5 ns PWD See Figure 2 — 1.5 2.5 ns tPSK(P-P) — 2.0 3.0 ns tPSK — 0.5 1.8 ns N ot fo R r N ec e w om m D e e s nd ig e ns d Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew3 tPHL, tPLH Output Rise Time tr CL = 15 pF See Figure 2 — 4.8 6.5 ns Output Fall Time tf CL = 15 pF See Figure 2 — 3.2 4.6 ns CMTI VI = VDD or 0 V — 25 — kV/µs ten1 See Figure 1 — 5.0 8.0 ns ten2 See Figure 1 — 7.0 9.2 ns — 15 40 µs Common Mode Transient Immunity Enable to Data Valid4 Enable to Data Tri-State Start-up Time4,5 4 tSU Notes: 1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is constrained to TA = 0 to 85 °C. 2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. See "3. Errata and Design Migration Guidelines" on page 26 for more details. 5. Start-up time is the time period from the application of power to valid data at the output. 14 Rev. 1.5 Si8450/51/52/55 Table 6. Regulatory Information* CSA The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. 60950-1: Up to 130 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. VDE The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. UL N ot fo R r N ec e w om m D e e s nd ig e ns d 60747-5-2: Up to 560 Vpeak for basic insulation working voltage. The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 2500 VRMS isolation voltage for basic insulation. *Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. For more information, see "6. Ordering Guide" on page 29. Table 7. Insulation and Safety-Related Specifications Parameter Symbol Test Condition Value NB SOIC-16 Unit Nominal Air Gap (Clearance)1 L(IO1) 4.9 mm Nominal External Tracking (Creepage)1 L(IO2) 4.01 mm 0.008 mm 600 VRMS 0.019 mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Proof Tracking Index) PTI ED Erosion Depth 2 Resistance (Input-Output) RIO Capacitance (Input-Output)2 CIO Input Capacitance IEC60112 3 CI f = 1 MHz 10 12 2.0 pF 4.0 pF Notes: 1. The values in this table correspond to the nominal creepage and clearance values as detailed in "7. Package Outline: 16-Pin Narrow Body SOIC" on page 31. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16 package. 2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 are shorted together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground. Rev. 1.5 15 Si8450/51/52/55 Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings Parameter Test Condition Basic Isolation Group Specification Material Group Rated Mains Voltages < 150 VRMS I-IV Rated Mains Voltages < 300 VRMS I-III Rated Mains Voltages < 400 VRMS I-II Rated Mains Voltages < 600 VRMS I-II N ot fo R r N ec e w om m D e e s nd ig e ns d Installation Classification I Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB* Parameter Symbol Test Condition VIORM Maximum Working Insulation Voltage Input to Output Test Voltage Transient Overvoltage Unit 560 V peak V peak VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 1050 VIOTM t = 60 sec 4000 Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V Characteristic RS V peak 2 >109 *Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of 40/125/21. Table 10. IEC Safety Limiting Values1 Parameter Symbol Case Temperature TS Safety input, output, or supply current IS Device Power Dissipation2 PD Test Condition JA = 105 °C/W (NB SOIC-16), VI = 5.5 V, TJ = 150 °C, TA = 25 °C Max Unit Min Typ — — 150 °C — — 215 mA — — 415 mW NB SOIC-16 Notes: 1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 3. 2. The Si845x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave. 16 Rev. 1.5 Si8450/51/52/55 Table 11. Thermal Characteristics Parameter Typ Symbol NB SOIC-16 JA IC Junction-to-Air Thermal Resistance 105 Unit °C/W 430 VDD1, VDD2 = 2.70 V 400 360 N ot fo R r N ec e w om m D e e s nd ig e ns d Safety-Limiting Current (mA) 500 VDD1, VDD2 = 3.6 V 300 215 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 3. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Rev. 1.5 17 Si8450/51/52/55 2. Functional Description 2.1. Theory of Operation The operation of an Si845x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si845x channel is shown in Figure 4. Transmitter Receiver A N ot fo R r N ec e w om m D e e s nd ig e ns d RF OSCILLATOR MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR B Figure 4. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See Figure 5 for more details. Input Signal Modulation Signal Output Signal Figure 5. Modulation Scheme 18 Rev. 1.5 Si8450/51/52/55 2.2. Eye Diagram N ot fo R r N ec e w om m D e e s nd ig e ns d Figure 6 illustrates an eye-diagram taken on an Si8450. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8450 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited. Figure 6. Eye Diagram Rev. 1.5 19 Si8450/51/52/55 2.3. Device Operation Device behavior during start-up, normal operation, and shutdown is shown in Table 12. Table 13 provides an overview of the output states when the Enable pins are active. Table 12. Si845x Logic Operation Table VI EN 1,2,3,4 1,2 Input Input VDDI State1,5,6 VDDO State1,5,6 VO Output1,2 H H or NC P P H L H or NC P P L L P P Hi-Z or L8 X7 H or NC UP P L X7 L UP P Hi-Z or L8 P UP X 7 Enabled, normal operation. N ot fo R r N ec e w om m D e e s nd ig e ns d X7 Comments X 7 Disabled. Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs. Disabled. Undetermined Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within 1 µs, if EN is in either the H or NC state. Upon transition of VDDO from unpowered to powered, VO returns to Hi-Z within 1 µs if EN is L. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the enable control input located on the same output side. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si845x is operating in noisy environments. 4. No Connect (NC) replaces EN1 on Si8450. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND. 5. “Powered” state (P) is defined as 2.70 V < VDD < 5.5 V. 6. “Unpowered” state (UP) is defined as VDD = 0 V. 7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. 8. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled (EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See "3. Errata and Design Migration Guidelines" on page 26 for more details. 20 Rev. 1.5 Si8450/51/52/55 Table 13. Enable Input Truth Table1 Si8450 Si8451 Si8452 Si8455 Operation EN11,2 EN21,2 — H Outputs B1, B2, B3, B4, B5 are enabled and follow input state. — L Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance state.3 H X Output A5 enabled and follow input state. L X Output A5 disabled and Logic Low or in high impedance state.3 X H Outputs B1, B2, B3, B4 are enabled and follow input state. X L Outputs B1, B2, B3, B4 are disabled and Logic Low or in high impedance state.3 H X Outputs A4 and A5 are enabled and follow input state. L X Outputs A4 and A5 are disabled and Logic Low or in high impedance state.3 X H Outputs B1, B2, B3 are enabled and follow input state. X L Outputs B1, B2, B3 are disabled and Logic Low or in high impedance state.3 — — Outputs B1, B2, B3, B4, B5 are enabled and follow input state. N ot fo R r N ec e w om m D e e s nd ig e ns d P/N Notes: 1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are internally pulled-up to local VDD by a 3 µA current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si845x is operating in a noisy environment. 2. X = not applicable; H = Logic High; L = Logic Low. 3. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled (EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See "3. Errata and Design Migration Guidelines" on page 26 for more details. Rev. 1.5 21 Si8450/51/52/55 2.4. Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 6 on page 15 and Table 7 on page 15 detail the working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, etc.) requirements before starting any design that uses a digital isolator. N ot fo R r N ec e w om m D e e s nd ig e ns d The following sections detail the recommended bypass and decoupling components necessary to ensure robust overall performance and reliability for systems using the Si84xx digital isolators. 2.4.1. Supply Bypass Digital integrated circuit components typically require 0.1 µF (100 nF) bypass capacitors when used in electrically quiet environments. However, digital isolators are commonly used in hazardous environments with excessively noisy power supplies. To counteract these harsh conditions, it is recommended that an additional 1 µF bypass capacitor be added between VDD and GND on both sides of the package. The capacitors should be placed as close as possible to the package to minimize stray inductance. If the system is excessively noisy, it is recommended that the designer add 50 to 100 resistors in series with the VDD supply voltage source and 50 to 300 resistors in series with the digital inputs/outputs (see Figure 7). For more details, see "3. Errata and Design Migration Guidelines" on page 26. All components upstream or downstream of the isolator should be properly decoupled as well. If these components are not properly decoupled, their supply noise can couple to the isolator inputs and outputs, potentially causing damage if spikes exceed the maximum ratings of the isolator (6 V). In this case, the 50 to 300 resistors protect the isolator's inputs/outputs (note that permanent device damage may occur if the absolute maximum ratings are exceeded). Functional operation should be restricted to the conditions specified in Table 1, “Recommended Operating Conditions,” on page 4. 2.4.2. Pin Connections No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND. 2.4.3. Output Pin Termination The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. The series termination resistor values should be scaled appropriately while keeping in mind the recommendations described in “2.4.1. Supply Bypass” above. V Source 1 R1 (50 – 100 ) V Source 2 R2 (50 – 100 ) VDD1 C1 VDD2 50 – 300 0.1 F A1 0.1 F B1 C2 1 F C4 50 – 300 C3 Input/Output Input/Output 1 F Bx Ax 50 – 300 50 – 300 GND1 GND2 Figure 7. Recommended Bypass Components for the Si84xx Digital Isolator Family 22 Rev. 1.5 Si8450/51/52/55 2.5. Typical Performance Characteristics The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Tables 3, 4, and 5 for actual specification limits. 35 35 30 Current (mA) Current (mA) 30 5V 25 20 3.3V 15 2.70V 10 5V 25 3.3V 20 15 2.70V 10 5 N ot fo R r N ec e w om m D e e s nd ig e ns d 5 0 0 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Figure 11. Si8450/55 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) Figure 8. Si8450/55 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation 35 35 25 Current (mA) 30 30 Current (mA) 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Data Rate (Mbps) 5V 20 3.3V 15 10 20 15 5V 3.3V 2.70V 10 5 2.70V 5 25 0 0 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Data Rate (Mbps) Figure 9. Si8451 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) Figure 12. Si8451 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) 35 35 Current (mA) Current (mA) 30 30 25 5V 20 15 3.3V 10 2.70V 25 20 5V 3.3V 15 2.70V 10 5 5 0 0 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Data Rate (Mbps) Figure 10. Si8452 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) Figure 13. Si8452 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) Rev. 1.5 23 Si8450/51/52/55 10 Falling Edge Delay (ns) 9 8 7 Rising Edge 6 5 -40 -20 0 20 40 60 80 100 120 N ot fo R r N ec e w om m D e e s nd ig e ns d Temperature (Degrees C) Figure 14. Propagation Delay vs. Temperature 24 Rev. 1.5 N ot fo R r N ec e w om m D e e s nd ig e ns d Si8450/51/52/55 Figure 15. Si84xx Time-Dependent Dielectric Breakdown Rev. 1.5 25 Si8450/51/52/55 3. Errata and Design Migration Guidelines The following errata apply to Revision A devices only. See "6. Ordering Guide" on page 29 for more details. No errata exist for Revision B devices. 3.1. Enable Pin Causes Outputs to Go Low (Revision A Only) When using the enable pin (EN1, EN2) function on the 5-channel (Si8450/1/2) isolators, the corresponding output pin states (pin = An, Bn, where n can be 1…5) are driven to a logic low (to ground) when the enable pin is disabled (EN1 or EN2 = 0). This functionality is different from the legacy 3-channel (Si8430/1) and 4-channel (Si8440/1/2) isolators. On those devices, the isolator outputs go into a high-impedance state (Hi-Z) when the enable pin is disabled (EN1 = 0 or EN2 = 0). N ot fo R r N ec e w om m D e e s nd ig e ns d 3.1.1. Resolution The enable pin functionality causing the outputs to go low is supported in production for Revision A of the Si845x devices. Revision B corrects the enable pin functionality (i.e., the outputs will go into the high-impedance state to match the legacy isolator products). Refer to the Ordering Guide sections of the data sheet(s) for more information. 3.2. Power Supply Bypass Capacitors (Revision A and Revision B) When using the Si845x isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V supply). Although rise time is power supply dependent, > 1 µF capacitors are required on both power supply pins (VDD1, VDD2) of the isolator device. 3.2.1. Resolution For recommendations on resolving this issue, see "2.4.1. Supply Bypass" on page 22. Additionally, refer to "6. Ordering Guide" on page 29 for current ordering information. 3.3. Latch Up Immunity (Revision A Only) Latch up immunity generally exceeds ± 200 mA per pin. Exceptions: Certain pins provide < 100 mA of latch-up immunity. To increase latch-up immunity on these pins, 100 of equivalent resistance must be included in series with all of the pins listed in Table 14. The 100 equivalent resistance can be comprised of the source driver's output resistance and a series termination resistor. 3.3.1. Resolution This issue has been corrected with Revision B of the device. Refer to the Ordering Guide for more information. Table 14. Affected Ordering Part Numbers (Revision A Only) Affected Ordering Part Numbers* SI8450SV-A-IS/IS1, SI8451SV-A-IS/IS1, SI8452SV-A-IS/IS1 SI8455SV-A-IS/IS1 Device Revision A A *Note: SV = Speed Grade/Isolation Rating (AA, AB, BA, BB). 26 Rev. 1.5 Pin# Name Pin Type 2 A1 Input 6 A5 Input or Output 10 EN2 Input 14 B2 Output 2 A1 Input 6 A5 Input 14 B2 Output Si8450/51/52/55 4. Pin Descriptions (Si8450/51/52) VDD1 VDD2 RF XMITR A1 A3 RF XMITR A4 RF XMITR A5 RF XMITR RF RCVR B1 RF RCVR B2 RF RCVR B3 GND1 RF XMITR A1 A2 RF XMITR A3 RF XMITR RF RCVR B4 A4 RF XMITR RF RCVR B5 A5 RF RCVR EN2/NC NC VDD2 I s o l a t i o n RF RCVR RF RCVR RF RCVR VDD1 B1 A1 B2 B3 GND2 Si8450 A2 A3 RF XMITR RF RCVR B4 A4 RF RCVR RF XMITR B5 A5 RF RCVR EN2 EN1 GND1 Si8451 GND2 GND1 Type VDD1 1 Supply A1 2 Digital Input Side 1 digital input. 3 Digital Input Side 1 digital input. 4 Digital Input Side 1 digital input. 5 Digital I/O Side 1 digital input or output. 6 Digital I/O Side 1 digital input or output. EN1/NC* 7 Digital Input GND1 8 Ground Side 1 ground. GND2 9 Ground Side 2 ground. EN2 10 Digital Input 11 Digital I/O Side 2 digital input or output. 12 Digital I/O Side 2 digital input or output. 13 Digital Output Side 2 digital output. 14 Digital Output Side 2 digital output. B1 15 Digital Output Side 2 digital output. VDD2 16 Supply Side 2 power supply. A4 A5 B5 B4 B3 B2 I s o l a t i o n RF RCVR B1 RF RCVR B2 RF RCVR B3 RF RF XMITR RCVR B4 RF XMITR B5 EN1 SOIC-16 Pin# A3 RF XMITR RF XMITR Name A2 VDD2 N ot fo R r N ec e w om m D e e s nd ig e ns d A2 RF XMITR I s o l a t i o n VDD1 Si8452 EN2 GND2 Description Side 1 power supply. Side 1 active high enable. NC on Si8450. Side 2 active high enable. *Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND. Rev. 1.5 27 Si8450/51/52/55 5. Pin Descriptions (Si8455) VDD1 VDD2 GND1 GND2 RF XMITR A2 RF XMITR A3 RF XMITR A4 RF XMITR RF RCVR B1 RF RCVR B2 RF RCVR B3 RF RCVR B4 RF RCVR B5 N ot fo R r N ec e w om m D e e s nd ig e ns d A1 I s o l a t i o n A5 RF XMITR GND1 Si8455 GND2 Name SOIC-16 Pin# Type VDD1 1 Supply Side 1 power supply. GND1 2 Ground Side 1 ground. A1 3 Digital Input Side 1 digital input. 4 Digital Input Side 1 digital input. 5 Digital Input Side 1 digital input. 6 Digital Input Side 1 digital input. 7 Digital Input Side 1 digital input. GND1 8 Ground Side 1 ground. GND2 9 Ground Side 2 ground. B5 10 Digital Output Side 2 digital output. 11 Digital Output Side 2 digital output. 12 Digital Output Side 2 digital output. 13 Digital Output Side 2 digital output. B1 14 Digital Output Side 2 digital output. GND2 15 Ground Side 2 ground. VDD2 16 Supply Side 2 power supply. A2 A3 A4 A5 B4 B3 B2 Description* *Note: For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be connected to external ground. 28 Rev. 1.5 Si8450/51/52/55 6. Ordering Guide These devices are not recommended for new designs. Please see the Si865x data sheet for replacement options. Table 15. Ordering Guide for Valid OPNs1 Ordering Part Number (OPN) Alternative Part Number of Number of Number Inputs VDD1 Inputs VDD2 (APN) Side Side Maximum Data Rate (Mbps) Isolation Package Type Rating Revision B Devices2 Si8650AB-B-IS1 5 0 1 N ot fo R r N ec e w om m D e e s nd ig e ns d Si8450AA-B-IS1 Si8450BA-B-IS1 Si8650BB-B-IS1 5 0 150 Si8451AA-B-IS1 Si8651AB-B-IS1 4 1 1 Si8451BA-B-IS1 Si8651BB-B-IS1 4 1 150 Si8452AA-B-IS1 Si8652AB-B-IS1 3 2 1 Si8452BA-B-IS1 Si8652BB-B-IS1 3 2 150 Si8455BA-B-IS1 Si8655BB-B-IS1 5 0 150 Si8450AB-B-IS1 Si8650AB-B-IS1 5 0 1 Si8450BB-B-IS1 Si8650BB-B-IS1 5 0 150 Si8451AB-B-IS1 Si8651AB-B-IS1 4 1 1 Si8451BB-B-IS1 Si8651BB-B-IS1 4 1 150 Si8452AB-B-IS1 Si8652AB-B-IS1 3 2 1 Si8452BB-B-IS1 Si8652BB-B-IS1 3 2 150 Si8455BB-B-IS1 Si8655BB-B-IS1 5 0 150 1 kVrms NB SOIC-16 2.5 kVrms NB SOIC-16 Notes: 1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications and peak solder temperature. 2. Revision A and Revision B devices are supported for existing designs. Rev. 1.5 29 Si8450/51/52/55 Table 15. Ordering Guide for Valid OPNs1 (Continued) Ordering Part Number (OPN) Alternative Part Number of Number of Number Inputs VDD1 Inputs VDD2 (APN) Side Side Maximum Data Rate (Mbps) Isolation Package Type Rating Revision A Devices2 Si8650AB-B-IS1 5 0 1 Si8450BA-A-IS1 Si8650BB-B-IS1 5 0 150 Si8451AA-A-IS1 Si8651AB-B-IS1 4 1 1 Si8451BA-A-IS1 Si8651BB-B-IS1 4 1 150 1 kVrms N ot fo R r N ec e w om m D e e s nd ig e ns d Si8450AA-A-IS1 Si8452AA-A-IS1 Si8652AB-B-IS1 3 2 1 Si8452BA-A-IS1 Si8652BB-B-IS1 3 2 150 Si8455BA-A-IS1 Si8655BB-B-IS1 5 0 150 Si8450AB-A-IS1 Si8650AB-B-IS1 5 0 1 Si8450BB-A-IS1 Si8650BB-B-IS1 5 0 150 Si8451AB-A-IS1 Si8651AB-B-IS1 4 1 1 Si8451BB-A-IS1 Si8651BB-B-IS1 4 1 150 Si8452AB-A-IS1 Si8652AB-B-IS1 3 2 1 Si8452BB-A-IS1 Si8652BB-B-IS1 3 2 150 Si8455BB-A-IS1 Si8655BB-B-IS1 5 0 150 2.5 kVrms NB SOIC-16 NB SOIC-16 Notes: 1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications and peak solder temperature. 2. Revision A and Revision B devices are supported for existing designs. 30 Rev. 1.5 Si8450/51/52/55 7. Package Outline: 16-Pin Narrow Body SOIC N ot fo R r N ec e w om m D e e s nd ig e ns d Figure 16 illustrates the package details for the Si845x in a 16-pin narrow-body SOIC (SO-16). Table 16 lists the values for the dimensions shown in the illustration. Figure 16. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 16. Package Diagram Dimensions Dimension Min Max A — 1.75 A1 0.10 0.25 A2 1.25 — b 0.31 0.51 c 0.17 0.25 D 9.90 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC L 0.40 L2 1.27 0.25 BSC Rev. 1.5 31 Si8450/51/52/55 Table 16. Package Diagram Dimensions (Continued) Dimension Min Max h 0.25 0.50 θ 0° 8° 0.10 bbb 0.20 ccc 0.10 ddd 0.25 N ot fo R r N ec e w om m D e e s nd ig e ns d aaa Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 32 Rev. 1.5 Si8450/51/52/55 8. Land Pattern: 16-Pin Narrow Body SOIC N ot fo R r N ec e w om m D e e s nd ig e ns d Figure 17 illustrates the recommended land pattern details for the Si845x in a 16-pin narrow-body SOIC. Table 17 lists the values for the dimensions shown in the illustration. Figure 17. 16-Pin Narrow Body SOIC PCB Land Pattern Table 17. 16-Pin Narrow Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. Rev. 1.5 33 Si8450/51/52/55 9. Top Marking: 16-Pin Narrow Body SOIC 9.1. 16-Pin Narrow Body SOIC Top Marking e3 Si84XYSV YYWWTTTTTT N ot fo R r N ec e w om m D e e s nd ig e ns d 9.2. Top Marking Explanation Table 18. 16-Pin Narrow Body SOIC Top Marking Table Base Part Number Ordering Options Line 1 Marking: (See Ordering Guide for more information). Line 2 Marking: Si84 = Isolator product series XY = Channel Configuration X = # of data channels (5, 4, 3, 2, 1) Y = # of reverse channels (2, 1, 0)* S = Speed Grade A = 1 Mbps; B = 150 Mbps V = Insulation rating A = 1 kV; B = 2.5 kV Circle = 1.2 mm Diameter “e3” Pb-Free Symbol YY = Year WW = Work Week Assigned by the Assembly House. Corresponds to the year and work week of the mold date. TTTTTT = Mfg code Manufacturing Code from Assembly Purchase Order form. Circle = 1.2 mm diameter “e3” Pb-Free Symbol. *Note: Si8455 has 0 reverse channels. 34 Rev. 1.5 Si8450/51/52/55 DOCUMENT CHANGE LIST Revision 1.3 to Revision 1.4 Revision 0.1 to Revision 0.2 Updated all specs to reflect latest silicon. Added "3. Errata and Design Migration Guidelines" on page 26. Added "9. Top Marking: 16-Pin Narrow Body SOIC" on page 34. Revision 0.2 to Revision 1.0 Updated all supply currents and channel-channel skew. absolute maximum supply voltage. clearance and creepage dimensions. Updated Table 12. Updated Updated "6. Ordering Guide" on page 29 to include new title note and “ Alternative Part Number (APN)” column. Updated Table 7. Updated Updated Table 2. Updated Revision 1.4 to Revision 1.5 N ot fo R r N ec e w om m D e e s nd ig e ns d Updated document to reflect availability of Revision B silicon. Updated Tables 3,4, and 5. Removed wide-body SOIC-16 package information and references throughout document. Updated "2.4.1. Supply Bypass" on page 22. Added Figure 7, “Recommended Bypass Components for the Si84xx Digital Isolator Family,” on page 22. Updated "3.2. Power Supply Bypass Capacitors (Revision A and Revision B)" on page 26. Note 7. Updated Table 13. Updated Note 3. Updated "3. Errata and Design Migration Guidelines" on page 26. Updated "6. Ordering Guide" on page 29. Revision 1.0 to Revision 1.1 Updated Tables 3, 4, and 5. Updated notes in both tables to reflect output impedance of 85 . Updated rise and fall time specifications. Updated CMTI value. Revision 1.1 to Revision 1.2 Updated document throughout to include MSL improvements to MSL2A. Updated "6. Ordering Guide" on page 29. Updated Note 1 in ordering guide table to reflect improvement and compliance to MSL2A moisture sensitivity level. Revision 1.2 to Revision 1.3 Updated " Features" on page 1. Moved Tables 1 and 2 to page 4. Updated Tables 6, 7, 8, and 9. Updated Table 12 footnotes. Added Figure 15, “Si84xx Time-Dependent Dielectric Breakdown,” on page 25. Rev. 1.5 35 Si8450/51/52/55 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 N ot fo R r N ec e w om m D e e s nd ig e ns d Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. 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