Si8660/61/62/63 L O W P O W E R S I X - C HANNEL D IGITA L I SOLATOR Features High-speed operation DC to 150 Mbps No start-up initialization required Wide Operating Supply Voltage 2.5–5.5 V Up to 5000 VRMS isolation 60-year life at rated working voltage High electromagnetic immunity Ultra low power (typical) 5 V Operation 1.6 mA per channel at 1 Mbps 5.5 mA per channel at 100 Mbps 2.5 V Operation 1.5 mA per channel at 1 Mbps 3.5 mA per channel at 100 Mbps Schmitt trigger inputs Selectable fail-safe mode Default high or low output (ordering option) Precise timing (typical) 10 ns propagation delay 1.5 ns pulse width distortion 0.5 ns channel-channel skew 2 ns propagation delay skew 5 ns minimum pulse width Transient Immunity 50 kV/µs AEC-Q100 qualification Wide temperature range –40 to 125 °C RoHS-compliant packages SOIC-16 wide body SOIC-16 narrow body Applications Industrial automation systems Medical electronics Hybrid electric vehicles Isolated switch mode supplies Isolated ADC, DAC Motor control Power inverters Communication systems VDE certification conformity IEC 60747-5-2 (VDE0884 Part 2) EN60950-1 (reinforced insulation) CQC certification approval Ordering Information: See page 30. Safety Regulatory Approvals UL 1577 recognized Up to 5000 VRMS for 1 minute CSA component notice 5A approval IEC 60950-1, 61010-1, 60601-1 (reinforced insulation) GB4943.1 Description Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages over legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges and throughout device service life for ease of design and highly uniform performance. All device versions have Schmitt trigger inputs for high noise immunity and only require VDD bypass capacitors. Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of less than 10 ns. Ordering options include a choice of isolation ratings (2.5, 3.75 and 5 kV) and a selectable fail-safe operating mode to control the default output state during power loss. All products >1 kVRMS are safety certified by UL, CSA, VDE, and CQC, and products in wide-body packages support reinforced insulation withstanding up to 5 kVRMS. Rev. 1.6 6/15 Copyright © 2015 by Silicon Laboratories Si8660/61/62/63 Si8660/61/62/63 2 Rev. 1.6 Si8660/61/62/63 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.1. Si866x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 37 10.3. Si866x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 38 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Rev. 1.6 3 Si8660/61/62/63 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Operating Temperature* Supply Voltage Symbol Min Typ Max Unit TA –40 25 125 °C VDD1 2.5 — 5.5 V VDD2 2.5 — 5.5 V *Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 2. Electrical Characteristics (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 4.8 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V Input Leakage Current IL — — ±10 µA ZO — 50 — 1 Output Impedance Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 4 Rev. 1.6 Si8660/61/62/63 Table 2. Electrical Characteristics (Continued) (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit DC Supply Current (All inputs 0 V or at Supply) Si8660Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 1.2 3.5 8.8 3.7 1.9 5.3 12.3 5.6 Si8661Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 1.7 3.4 7.9 4.8 2.7 5.1 11.1 7.2 Si8662Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 2.2 3.0 7.5 5.6 3.3 4.5 10.5 8.4 Si8663Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 2.6 2.6 6.5 6.5 3.9 3.9 9.1 9.1 mA mA mA mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8660Bx, Ex VDD1 VDD2 — — 5.0 4.2 7.0 5.9 mA Si8661Bx, Ex VDD1 VDD2 — — 4.9 4.6 6.9 6.4 mA Si8662Bx, Ex VDD1 VDD2 — — 5.1 4.7 7.1 6.6 mA Si8663Bx, Ex VDD1 VDD2 — — 4.9 4.9 6.8 6.8 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.6 5 Si8660/61/62/63 Table 2. Electrical Characteristics (Continued) (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8660Bx, Ex VDD1 VDD2 — — 5.0 5.9 7.0 8.3 mA Si8661Bx, Ex VDD1 VDD2 — — 5.2 6.1 7.3 8.5 mA Si8662Bx, Ex VDD1 VDD2 — — 5.6 5.9 7.9 8.2 mA Si8663Bx, Ex VDD1 VDD2 — — 5.7 5.7 8.0 8.0 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8660Bx, Ex VDD1 VDD2 — — 5.0 26.2 7.0 34.1 mA Si8661Bx, Ex VDD1 VDD2 — — 8.8 23 11.8 29.8 mA Si8662Bx, Ex VDD1 VDD2 — — 12.8 19.4 16.6 25.2 mA Si8663Bx, Ex VDD1 VDD2 — — 16.4 16.4 21.3 21.3 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 6 Rev. 1.6 Si8660/61/62/63 Table 2. Electrical Characteristics (Continued) (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 5.0 ns Timing Characteristics Si866xBx, Ex Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 1 5.0 8.0 13 ns PWD See Figure 1 — 0.2 4.5 ns tPSK(P-P) — 2.0 4.5 ns tPSK — 0.4 2.5 ns 2.5 4.0 2.5 4.0 All Models Output Rise Time tr CL = 15 pF (See Figure 1) — Output Fall Time tf CL = 15 pF (See Figure 1) — Peak Eye Diagram Jitter tJIT(PK) See Figure 7 — 350 — ps Common Mode Transient Immunity CMTI VI = VDD or 0 V VCM = 1500 V (See Figure 2) 35 50 — kV/µs — 15 40 µs Startup Time3 tSU ns ns Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 1.4 V Typical Input tPLH tPHL 90% 90% 10% 10% 1.4 V Typical Output tr tf Figure 1. Propagation Delay Timing Rev. 1.6 7 Si8660/61/62/63 3 to 5 V Supply Si86xx Input Signal Switch 3 to 5 V Isolated Supply VDD1 VDD2 INPUT OUTPUT Oscilloscope GND1 GND2 Isolated Ground Input High Voltage Differential Probe Output Vcm Surge Output High Voltage Surge Generator Figure 2. Common Mode Transient Immunity Test Circuit 8 Rev. 1.6 Si8660/61/62/63 Table 3. Electrical Characteristics (VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 3.1 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V IL — — ±10 µA ZO — 50 — Input Leakage Current 1 Output Impedance Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.6 9 Si8660/61/62/63 Table 3. Electrical Characteristics (Continued) (VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit DC Supply Current (All inputs 0 V or at supply) Si8660Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 1.2 3.5 8.8 3.7 1.9 5.3 12.3 5.6 Si8661Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 1.7 3.4 7.9 4.8 2.7 5.1 11.1 7.2 Si8662Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 2.2 3.0 7.5 5.6 3.3 4.5 10.5 8.4 Si8663Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 2.6 2.6 6.5 6.5 3.9 3.9 9.1 9.1 mA mA mA mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 10 Rev. 1.6 Si8660/61/62/63 Table 3. Electrical Characteristics (Continued) (VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8660Bx, Ex VDD1 VDD2 — — 5.0 4.2 7.0 5.9 mA Si8661Bx, Ex VDD1 VDD2 — — 4.9 4.6 6.9 6.4 mA Si8662Bx, Ex VDD1 VDD2 — — 5.1 4.7 7.1 6.6 mA Si8663Bx, Ex VDD1 VDD2 — — 4.9 4.9 6.8 6.8 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8660Bx, Ex VDD1 VDD2 — — 5.0 5.0 7.0 7.0 mA Si8661Bx, Ex VDD1 VDD2 — — 5.0 5.3 7.0 7.4 mA Si8662Bx, Ex VDD1 VDD2 — — 5.3 5.2 7.4 7.3 mA Si8663Bx, Ex VDD1 VDD2 — — 5.2 5.2 7.3 7.3 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.6 11 Si8660/61/62/63 Table 3. Electrical Characteristics (Continued) (VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8660Bx, Ex VDD1 VDD2 — — 5.0 18.3 7.0 23.8 mA Si8661Bx, Ex VDD1 VDD2 — — 7.4 16.4 9.9 21.3 mA Si8662Bx, Ex VDD1 VDD2 — — 10 14.1 13 18.3 mA Si8663Bx, Ex VDD1 VDD2 — — 12.3 12.3 15.9 15.9 mA Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 5.0 ns Timing Characteristics Si866xBx, Ex Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 1 5.0 8.0 13 ns PWD See Figure 1 — 0.2 4.5 ns tPSK(P-P) — 2.0 4.5 ns tPSK — 0.4 2.5 ns 2.5 4.0 2.5 4.0 All Models Output Rise Time tr CL = 15 pF See Figure 1 — Output Fall Time tf CL = 15 pF See Figure 1 — Peak Eye Diagram Jitter tJIT(PK) See Figure 7 — 350 — ps Common Mode Transient Immunity CMTI VI = VDD or 0 V VCM = 1500 V (see Figure 2) 35 50 — kV/µs — 15 40 µs Startup Time3 tSU ns ns Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 12 Rev. 1.6 Si8660/61/62/63 Table 4. Electrical Characteristics (VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 2.3 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V IL — — ±10 µA ZO — 50 — Input Leakage Current 1 Output Impedance Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.6 13 Si8660/61/62/63 Table 4. Electrical Characteristics (Continued) (VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit DC Supply Current (All inputs 0 V or at supply) Si8660Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 1.2 3.5 8.8 3.7 1.9 5.3 12.3 5.6 Si8661Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 1.7 3.4 7.9 4.8 2.7 5.1 11.1 7.2 Si8662Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 2.2 3.0 7.5 5.6 3.3 4.5 10.5 8.4 Si8663Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 2.6 2.6 6.5 6.5 3.9 3.9 9.1 9.1 mA mA mA mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 14 Rev. 1.6 Si8660/61/62/63 Table 4. Electrical Characteristics (Continued) (VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8660Bx, Ex VDD1 VDD2 — — 5.0 4.2 7.0 5.9 mA Si8661Bx, Ex VDD1 VDD2 — — 4.9 4.6 6.9 6.4 mA Si8662Bx, Ex VDD1 VDD2 — — 5.1 4.7 7.1 6.6 mA Si8663Bx, Ex VDD1 VDD2 — — 4.9 4.9 6.8 6.8 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8660Bx, Ex VDD1 VDD2 — — 5.0 4.6 7.0 6.4 mA Si8661Bx, Ex VDD1 VDD2 — — 5.0 4.9 6.9 6.9 mA Si8662Bx, Ex VDD1 VDD2 — — 5.2 4.9 7.2 6.9 mA Si8663Bx, Ex VDD1 VDD2 — — 5.0 5.0 7.0 7.0 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.6 15 Si8660/61/62/63 Table 4. Electrical Characteristics (Continued) (VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8660Bx, Ex VDD1 VDD2 — — 5.0 14.7 7.0 19.1 mA Si8661Bx, Ex VDD1 VDD2 — — 6.7 13.4 9.1 17.4 mA Si8662Bx, Ex VDD1 VDD2 — — 8.7 11.7 11.3 15.2 mA Si8663Bx, Ex VDD1 VDD2 — — 10.3 10.3 13.4 13.4 mA Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 5.0 ns Timing Characteristics Si866xBx, Ex Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 1 5.0 8.0 14 ns PWD See Figure 1 — 0.2 5.0 ns tPSK(P-P) — 2.0 5.0 ns tPSK — 0.4 2.5 ns 2.5 4.0 2.5 4.0 All Models Output Rise Time tr CL = 15 pF See Figure 1 — Output Fall Time tf CL = 15 pF See Figure 1 — Peak Eye Diagram Jitter tJIT(PK) See Figure 7 — 350 — ps Common Mode Transient Immunity CMTI VI = VDD or 0 V\ VCM = 1500 V (see Figure 2) 35 50 — kV/µs — 15 40 µs Startup Time3 tSU ns ns Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 16 Rev. 1.6 Si8660/61/62/63 Table 5. Regulatory Information* CSA The Si866x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. 60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage. VDE The Si866x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. 60747-5-2: Up to 1200 Vpeak for basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. UL The Si866x is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. CQC The Si866x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239. Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. *Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec. For more information, see "5. Ordering Guide" on page 30. Rev. 1.6 17 Si8660/61/62/63 Table 6. Insulation and Safety-Related Specifications Parameter Nominal Air Gap (Clearance)1 Nominal External Tracking (Creepage)1 Minimum Internal Gap (Internal Clearance) Tracking Resistance (Proof Tracking Index) Erosion Depth Resistance (Input-Output)2 Capacitance (Input-Output)2 Input Capacitance3 Symbol Test Condition L(IO1) L(IO2) PTI ED RIO CIO CI IEC60112 f = 1 MHz Value Unit WB SOIC-16 8.0 8.0 NB SOIC-16 4.9 4.01 0.014 0.014 600 600 VRMS 0.019 1012 2.0 4.0 0.019 1012 2.0 4.0 mm pF pF mm mm mm Notes: 1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16 package and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16 package and 7.6 mm minimum for the WB SOIC-16 package. 2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground. 18 Rev. 1.6 Si8660/61/62/63 Table 7. IEC 60664-1 (VDE 0844 Part 2) Ratings Parameter Specification Test Conditions Basic Isolation Group NB SOIC-16 WB SOIC-16 I I Rated Mains Voltages < 150 VRMS I-IV I-IV Rated Mains Voltages < 300 VRMS I-III I-IV Rated Mains Voltages < 400 VRMS I-II I-III Rated Mains Voltages < 600 VRMS I-II I-III Material Group Installation Classification Table 8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx* Characteristic Parameter Symbol Maximum Working Insulation Voltage Test Condition WB SOIC-16 NB SOIC-16 1200 630 VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 2250 1182 VIOTM t = 60 sec 6000 6000 2 2 >109 >109 VIORM Input to Output Test Voltage Transient Overvoltage Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V RS Unit Vpeak Vpeak *Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21. Table 9. IEC Safety Limiting Values1 Parameter Symbol Case Temperature TS Safety Input, Output, or Supply Current IS Device Power Dissipation2 PD Test Condition JA = 105 °C/W (NB SOIC-16), VI = 5.5 V, TJ = 150 °C, TA = 25 °C Max WB SOIC-16 NB SOIC-16 150 150 Unit °C mA 220 215 415 415 mW Notes: 1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 3 and 4. 2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave. Rev. 1.6 19 Si8660/61/62/63 Table 10. Thermal Characteristics Parameter Symbol WB SOIC-16 NB SOIC-16 Unit JA 100 105 °C/W IC Junction-to-Air Thermal Resistance Safety-Limiting Current (mA) 500 450 VDD1, VDD2 = 2.70 V 400 370 VDD1, VDD2 = 3.6 V 300 220 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Safety-Limiting Current (mA) 500 430 VDD1, VDD2 = 2.70 V 400 360 VDD1, VDD2 = 3.6 V 300 215 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 4. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 20 Rev. 1.6 Si8660/61/62/63 Table 11. Absolute Maximum Ratings1 Parameter Symbol Min Max Unit TSTG –65 150 °C Ambient Temperature Under Bias TA –40 125 °C Junction Temperature TJ — 150 °C VDD1, VDD2 –0.5 7.0 V Input Voltage VI –0.5 VDD + 0.5 V Output Voltage VO –0.5 VDD + 0.5 V Output Current Drive Channel IO — 10 mA Lead Solder Temperature (10 s) — 260 °C Maximum Isolation (Input to Output) (1 sec) NB SOIC-16 — 4500 VRMS Maximum Isolation (Input to Output) (1 sec) WB SOIC-16 — 6500 VRMS Storage Temperature2 Supply Voltage Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. VDE certifies storage temperature from –40 to 150 °C. Rev. 1.6 21 Si8660/61/62/63 2. Functional Description 2.1. Theory of Operation The operation of an Si866x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si866x channel is shown in Figure 5. Transmitter Receiver RF OSCILLATOR A MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR B Figure 5. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See Figure 6 for more details. Input Signal Modulation Signal Output Signal Figure 6. Modulation Scheme 22 Rev. 1.6 Si8660/61/62/63 2.2. Eye Diagram Figure 7 illustrates an eye-diagram taken on an Si8660. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8660 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited. Figure 7. Eye Diagram Rev. 1.6 23 Si8660/61/62/63 3. Device Operation Device behavior during start-up, normal operation, and shutdown is shown in Figure 8, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when power supply (VDD) is not present. Table 12. Si866x Logic Operation VI Input1,2 VDDI State1,3,4 VDDO State1,3,4 VO Output1,2 H P P H L P P L X5 UP P L6 H6 Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs. X5 P UP Undetermined Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within 1 µs. Comments Normal operation. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V. 4. “Unpowered” state (UP) is defined as VDD = 0 V. 5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. 6. See "5. Ordering Guide" on page 30 for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default output state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/outputs. 24 Rev. 1.6 Si8660/61/62/63 3.1. Device Startup Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs. 3.2. Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply. UVLO+ UVLO- VDD1 UVLO+ UVLO- VDD2 INPUT tSTART tSD tSTART tSTART tPHL tPLH OUTPUT Figure 8. Device Behavior during Normal Operation Rev. 1.6 25 Si8660/61/62/63 3.3. Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 5 on page 17 and Table 6 on page 18 detail the working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 3.3.1. Supply Bypass The Si866x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 ) in series with the inputs and outputs if the system is excessively noisy. 3.3.2. Output Pin Termination The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3.4. Fail-Safe Operating Mode Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 12 on page 24 and "5. Ordering Guide" on page 30 for more information. 26 Rev. 1.6 Si8660/61/62/63 3.5. Typical Performance Characteristics The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Tables 2, 3, and 4 for actual specification limits. 30.0 40.0 35.0 25.0 15.0 Current (mA) Current (mA) 30.0 20.0 5V 3.3V 10.0 2.5V 25.0 20.0 5V 15.0 3.3V 2.5V 10.0 5.0 5.0 0.0 0.0 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Data Rate (Mbps) Figure 9. Si8660 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation Figure 12. Si8660 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) 40.0 30.0 35.0 30.0 Current (mA) Current (mA) 25.0 20.0 15.0 5V 3.3V 10.0 25.0 20.0 5V 15.0 3.3V 2.5V 10.0 2.5V 5.0 5.0 0.0 0 0.0 0 10 20 30 40 50 60 70 80 10 20 30 40 50 90 100 110 120 130 140 150 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Data Rate (Mbps) Figure 10. Si8661 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) Figure 13. Si8661 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) 30.0 30.0 25.0 Current (mA) Current (mA) 25.0 20.0 15.0 5V 3.3V 10.0 2.5V 20.0 15.0 5V 3.3V 10.0 2.5V 5.0 5.0 0.0 0.0 0 10 20 30 40 50 60 70 80 0 90 100 110 120 130 140 150 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Data Rate (Mbps) Figure 11. Si8662 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) Figure 14. Si8662 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) Rev. 1.6 27 Si8660/61/62/63 30.0 Current (mA) 25.0 20.0 15.0 5V 3.3V 10.0 2.5V 5.0 0.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Figure 15. Si8663 Typical VDD1 or VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) 10.0 Delay (ns) 9.0 8.0 7.0 6.0 5.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120 Temperature (Degrees C) Figure 16. Propagation Delay vs. Temperature 28 Rev. 1.6 Si8660/61/62/63 4. Pin Descriptions VDD1 VDD1 VDD2 A1 RF XMITR A2 RF XMITR A3 RF XMITR A4 RF XMITR A5 RF XMITR A6 RF XMITR GND1 I s o l a t i o n VDD2 RF RCVR B1 A1 RF XMITR RF RCVR B2 A2 RF XMITR RF RCVR B3 A3 RF XMITR RF RCVR B4 A4 RF XMITR RF RCVR B5 A5 RF XMITR RF RCVR B6 A6 RF RCVR Si8660 GND2 GND1 I s o l a t i o n VDD1 B1 A1 RF XMITR RF RCVR B2 A2 RF XMITR RF RCVR B3 A3 RF XMITR RF RCVR B4 A4 RF XMITR RF RCVR B5 A5 RF RCVR RF XMITR B6 A6 RF RCVR GND2 Si8661 GND1 VDD1 VDD2 RF RCVR I s o l a t i o n VDD2 RF RCVR B1 A1 RF XMITR RF RCVR B2 A2 RF XMITR RF RCVR B3 A3 RF XMITR RF RCVR B4 A4 RF RCVR RF XMITR B5 A5 RF RCVR RF RF XMITR RCVR B6 A6 RF RCVR Si8662 GND2 GND1 Name SOIC-16 Pin# Type VDD1 1 Supply A1 2 Digital Input Side 1 digital input. A2 3 Digital Input Side 1 digital input. A3 4 Digital Input Side 1 digital input. A4 5 Digital I/O Side 1 digital input or output. A5 6 Digital I/O Side 1 digital input or output. A6 7 Digital I/O Side 1 digital input or output. GND1 8 Ground Side 1 ground. GND2 9 Ground Side 2 ground. B6 10 Digital I/O Side 2 digital input or output. B5 11 Digital I/O Side 2 digital input or output. B4 12 Digital I/O Side 2 digital input or output. B3 13 Digital Output Side 2 digital output. B2 14 Digital Output Side 2 digital output. B1 15 Digital Output Side 2 digital output. VDD2 16 Supply Side 2 power supply. I s o l a t i o n RF RCVR B1 RF RCVR B2 RF RCVR B3 RF XMITR B4 RF XMITR B5 RF RF XMITR RCVR B6 Si8663 GND2 Description Side 1 power supply. Rev. 1.6 29 Si8660/61/62/63 5. Ordering Guide Table 13. Ordering Guide for Valid OPNs1,2 Temp (°C) Package 1.0 –40 to 125 °C NB SOIC-16 Low 2.5 –40 to 125 °C NB SOIC-16 150 Low 3.75 –40 to 125 °C NB SOIC-16 0 150 High 3.75 –40 to 125 °C NB SOIC-16 6 0 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8660ED-B-IS 6 0 150 High 5.0 –40 to 125 °C WB SOIC-16 Si8661BB-B-IS1 5 1 150 Low 2.5 –40 to 125 °C NB SOIC-16 Si8661BC-B-IS1 5 1 150 Low 3.75 –40 to 125 °C NB SOIC-16 Si8661EC-B-IS1 5 1 150 High 3.75 –40 to 125 °C NB SOIC-16 Si8661BD-B-IS 5 1 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8661ED-B-IS 5 1 150 High 5.0 –40 to 125 °C WB SOIC-16 Si8662BB-B-IS1 4 2 150 Low 2.5 –40 to 125 °C NB SOIC-16 Si8662BC-B-IS1 4 2 150 Low 3.75 –40 to 125 °C NB SOIC-16 Si8662EC-B-IS1 4 2 150 High 3.75 –40 to 125 °C NB SOIC-16 Si8662BD-B-IS 4 2 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8662ED-B-IS 4 2 150 High 5.0 –40 to 125 °C WB SOIC-16 Si8663BB-B-IS1 3 3 150 Low 2.5 –40 to 125 °C NB SOIC-16 Si8663BC-B-IS1 3 3 150 Low 3.75 –40 to 125 °C NB SOIC-16 Si8663EC-B-IS1 3 3 150 High 3.75 –40 to 125 °C NB SOIC-16 Si8663BD-B-IS 3 3 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8663ED-B-IS 3 3 150 High 5.0 –40 to 125 °C WB SOIC-16 Number of Max Data Default Isolation Output rating Rate Inputs (kV) State VDD2 Side (Mbps) Ordering Part Number (OPN) Number of Inputs VDD1 Side Si8660BA-B-IS1 6 0 150 Low Si8660BB-B-IS1 6 0 150 Si8660BC-B-IS1 6 0 Si8660EC-B-IS1 6 Si8660BD-B-IS Notes: 1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. 2. “Si” and “SI” are used interchangeably. 30 Rev. 1.6 Si8660/61/62/63 6. Package Outline: 16-Pin Wide Body SOIC Figure 17 illustrates the package details for the Si866x Digital Isolator. Table 14 lists the values for the dimensions shown in the illustration. Figure 17. 16-Pin Wide Body SOIC Rev. 1.6 31 Si8660/61/62/63 Table 14. Package Diagram Dimensions Dimension Min Max A — 2.65 A1 0.10 0.30 A2 2.05 — b 0.31 0.51 c 0.20 0.33 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75 0° 8° aaa — 0.10 bbb — 0.33 ccc — 0.10 ddd — 0.25 eee — 0.10 fff — 0.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AA. 4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components. 32 Rev. 1.6 Si8660/61/62/63 7. Land Pattern: 16-Pin Wide-Body SOIC Figure 18 illustrates the recommended land pattern details for the Si866x in a 16-pin wide-body SOIC. Table 15 lists the values for the dimensions shown in the illustration. Figure 18. 16-Pin SOIC Land Pattern Table 15. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 9.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.90 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. Rev. 1.6 33 Si8660/61/62/63 8. Package Outline: 16-Pin Narrow Body SOIC Figure 19 illustrates the package details for the Si866x in a 16-pin narrow-body SOIC (SO-16). Table 16 lists the values for the dimensions shown in the illustration. Figure 19. 16-pin Small Outline Integrated Circuit (SOIC) Package 34 Rev. 1.6 Si8660/61/62/63 Table 16. Package Diagram Dimensions Dimension Min Max A — 1.75 A1 0.10 0.25 A2 1.25 — b 0.31 0.51 c 0.17 0.25 D 9.90 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC L 0.40 L2 1.27 0.25 BSC h 0.25 0.50 θ 0° 8° aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.6 35 Si8660/61/62/63 9. Land Pattern: 16-Pin Narrow Body SOIC Figure 20 illustrates the recommended land pattern details for the Si866x in a 16-pin narrow-body SOIC. Table 17 lists the values for the dimensions shown in the illustration. Figure 20. 16-Pin Narrow Body SOIC PCB Land Pattern Table 17. 16-Pin Narrow Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 36 Rev. 1.6 Si8660/61/62/63 10. Top Markings 10.1. Si866x Top Marking (16-Pin Wide Body SOIC) Si86XYSV YYWWRTTTTT TW e4 10.2. Top Marking Explanation (16-Pin Wide Body SOIC) Si86 = Isolator product series XY = Channel Configuration X = # of data channels (6, 5, 4, 3, 2, 1) Y = # of reverse channels (3, 2, 1, 0) (See Ordering Guide for more information). S = Speed Grade A = 1 Mbps; B = 150 Mbps (default output = low); E = 150 Mbps (default output = high) V = Insulation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV Line 1 Marking: Base Part Number Ordering Options Line 2 Marking: YY = Year WW = Workweek Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date. RTTTTT = Mfg Code Manufacturing code from assembly house “R” indicates revision Circle = 1.7 mm Diameter (Center-Justified) “e4” Pb-Free Symbol Country of Origin ISO Code Abbreviation TW = Taiwan Line 3 Marking: Rev. 1.6 37 Si8660/61/62/63 10.3. Si866x Top Marking (16-Pin Narrow Body SOIC) e3 Si86XYSV YYWWRTTTTT 10.4. Top Marking Explanation (16-Pin Narrow Body SOIC) Line 1 Marking: Base Part Number Ordering Options (See Ordering Guide for more information). Line 2 Marking: 38 Si86 = Isolator product series XY = Channel Configuration X = # of data channels (6, 5, 4, 3, 2, 1) Y = # of reverse channels (3, 2, 1, 0) S = Speed Grade A = 1 Mbps; B = 150 Mbps (default output = low); E = 150 Mbps (default output = high) V = Insulation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV Circle = 1.2 mm Diameter “e3” Pb-Free Symbol YY = Year WW = Work Week Assigned by the Assembly House. Corresponds to the year and work week of the mold date. RTTTTT = Mfg Code Manufacturing code from assembly house “R” indicates revision Circle = 1.2 mm diameter “e3” Pb-Free Symbol. Rev. 1.6 Si8660/61/62/63 DOCUMENT CHANGE LIST Revision 1.4 to Revision 1.5 Added Figure 2, “Common Mode Transient Immunity Test Circuit,” on page 8. Added references to CQC throughout. Added references to 2.5 kVRMS devices throughout. Revision 0.1 to Revision 1.0 Added chip graphics on page 1. Updated " Features" on page 1. Moved Tables 1 and 11 to page 21. Updated Tables 2, 3, and 4. Updated Table 6, “Insulation and Safety-Related Specifications,” on page 18. Updated Table 8, “IEC 60747-5-2 Insulation Characteristics for Si86xxxx*,” on page 19. Moved Table 12 to page 24. Moved “Typical Performance Characteristics” to page 27. Updated "3.5. Typical Performance Characteristics" on page 27. Updated Table 4, “Pin Descriptions,” on page 29. Updated "5. Ordering Guide" on page 30. Removed references to QSOP-16 package. Updated "5. Ordering Guide" on page 30. Updated "10.1. Si866x Top Marking (16-Pin Wide Body SOIC)" on page 37. Revision 1.5 to Revision 1.6 Updated Table 5 on page 17. Added CQC certificate numbers. Updated "5. Ordering Guide" on page 30. Removed Removed references to moisture sensitivity levels. note 2. Revision 1.0 to Revision 1.1 Reordered spec tables to conform to new convention. Removed “pending” throughout document. Revision 1.1 to Revision 1.2 Updated High Level Output Voltage VOH to 3.1 V in Table 3, “Electrical Characteristics,” on page 9. Updated High Level Output Voltage VOH to 2.3 V in Table 4, “Electrical Characteristics,” on page 13. Revision 1.2 to Revision 1.3 Updated "5. Ordering Guide" on page 30 to include MSL2A. Revision 1.3 to Revision 1.4 Updated Table 11 on page 21. Added junction temperature spec. Updated "3.3.1. Supply Bypass" on page 26. Removed “3.3.2. Pin Connections” on page 22. Updated "5. Ordering Guide" on page 30. Removed Rev A devices. Updated "6. Package Outline: 16-Pin Wide Body SOIC" on page 31. Updated Top Marks. Added revision description. Rev. 1.6 39 Si8660/61/62/63 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 40 Rev. 1.6