SL28EB717 EProClock® Generator for Intel Tunnel Creek & Top Cliff Features • 14.318MHz output • Buffered Reference Clock 25MHz • Compliant Intel CK505 Clock spec • Low power push-pull type differential output buffers • Integrated resistors on differential clocks • 25MHz Crystal Input or Clock input • Support Wake-On-LAN (WOL) • EProClock® Programmable Technology • Wireless friendly 3-bits slew rate control on single-ended clocks. • I2C support with readback capabilities • Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Differential CPU clocks with selectable frequency • 100MHz Differential SRC clocks • Industrial Temperature -40oC to 85oC • 75MHz Differential SATA clocks • 3.3V Power supply • 96MHz Differential DOT clock • 48-pin QFN package • 48MHz USB clock • Selectable 12 or 48MHz output CPU SRC SATA75 DOT96 48M x2/x3 x3/5 x1/2 x0/x1 Block Diagram CLKPWRGD/ PD# GND_SUSPEND 25MHz VDD_SUSPEND CKPWRGD / WOL_STP# / PD# GND_14 Logic Core VR DOC#: SP-AP-0755 (Rev. AA) 400 West Cesar Chavez, Austin, TX 78701 VDD_14 CLKREQ#1** 25 26 27 28 29 30 31 32 33 34 35 36 VDD_SATA 14.318M OTP CPU2 / SRC6 SEL_12_48 CPU2# / SRC6# 12 / 48M Divider VDD_SRC PLL 2 (non-SSC) x1 48 XIN / CLKIN 47 XOUT 46 PCI/SRC_STP#* 45 CPU_STP#* 44 SDATA 43 SCLK 42 GND_CPU 41 CPU0 40 CPU0# 39 VDD_CPU 38 CPU1 37 CPU1# GND_SRC 48M SEL_SATA75 14.318M x1 6 5 4 3 2 1 SRC3# CLKREQ[3:1] 7 SRC3 DOT96 Divider 8 SRC2# PLL 3 (non-SSC) 25M x2 13 14 15 16 17 18 19 20 21 22 23 24 SRC2 PCI/SRC_STP# PCIF / ITP_EN** CLKREQ#3** 12M_48M / SEL12_48* VDD_48 48M / FSA** GND_48 DOT96 DOT96# FSB** GND_SATA SATA75M / SRC0 SATA75M# / SRC0# SRC1# SATA75M / SRC0 ITP_EN CLKREQ#2** Divider GND_PCI PCI PLL 4 (non-SSC) CPU_STP# 12 11 10 9 VDD_PCI SRC FS [ C:A] 14M / FSC** CPU Divider PCI0 / SEL_SATA75** REF [1:0] PLL 1 (SSC) SCLK SDATA x1 VDD_SRC Crystal/ CLKIN 48M/12M 33M Pin Configuration SRC1 XIN XOUT x1 * Internal 100K-ohm pull-up resistor ** Internal 100K-ohm pull down resistor 1+(512) 416-8500 1+(512) 416-9669 Page 1 of 22 www.silabs.com SL28EB717 32-QFN Pin Definitions Pin No. 1 Name GND_SUSPEND 2 25MHz 3 VDD_SUSPEND 4 CKPWRGD/WOL_STP#/PD# 5 VDD_14 6 14.318M / FSC** 7 GND_14 GND Ground for 14.318MHz clock 8 CLKREQ#1** I, PD 3.3V clock request input (internal 100K-ohm pull-down) 9 CLKREQ#2** I, PD 3.3V clock request input (internal 100K-ohm pull-down) 10 PCI0 / SEL_SATA75** 11 GND_PCI 12 VDD_PCI 13 PCIF / ITP_EN** 14 CLKREQ#3** 15 12_48M / SEL12_48* 16 VDD_48 17 48M / FSA** Type GND O PWR I PWR Description Ground for REF clock and WOL support 25MHz reference output clock 3.3V Power Supply for REF clock and power to support WOL 3.3V LVTTL input. This pin is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled / Asynchronous active low input pin that stops all outputs except free running 25MHz when WOL_EN = “1” (Byte 1 bit 1) This pin becomes a real-time active low input for asserting power down (PD#) when WOL_EN = “0” (Byte 1 bit 1). 3.3V Power supply for 14.318MHz clock I/O, PD Fixed 14.318MHz clock output/3.3V-tolerant input for CPU frequency selection (internal 100K-ohm pull-down) Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. I/O, SE 33MHz clock output/3.3V LVTTL input to enable 75MHz SATA (internal 100K-ohm PD pull-down) 0 = SATA75/SRC0 = 100MHz, 1 = SATA75/SRC0 = 75MHz GND Ground for PCI clocks PWR 3.3V Power supply for PCI clocks I/O, SE, 33 MHz free running clock output/3.3V LVTTL input to enable SRC6 or CPU2_ITP PD (sampled on the CKPWRGD assertion) 0= SRC6, 1= CPU2 I, PD 3.3V clock request input (internal 100K-ohm pull-down) I/O, SE 12 MHz/ 48MHz Clock output/3.3V-tolerance input for 12MHz or 48MHz selection PU (Sampled at CKPWRGD assertion) (internal 100K-ohm pull-up) 0 = 48M, 1 = 12M PWR I/O PD GND 3.3V Power supply for 48MHz clocks Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection (internal 100K-ohm pull-down) Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 18 GND_48 19 DOT96 O, DIF Fixed true 96MHz clock output 20 DOT96# O, DIF Fixed complement 96MHz clock output 21 FSB** I, PD 3.3V-tolerant input for CPU frequency selection (internal 100K-ohm pull-down) Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 22 GND_SATA GND Ground for SATA clock 23 SATA75M / SRC0 O, DIF 75MHz or 100MHz True differential serial reference clock 24 SATA75M# / SRC0# O, DIF 75MHz or 100MHz Complement differential serial reference clock 25 VDD_SATA 26 SRC1 O, DIF 100MHz True differential serial reference clock 27 SRC1# O, DIF 100MHz Complement differential serial reference clock 28 SRC2 O, DIF 100MHz True differential serial reference clock 29 SRC2# O, DIF 100MHz Complement differential serial reference clock 30 SRC3 O, DIF 100MHz True differential serial reference clock 31 SRC3# O, DIF 100MHz Complement differential serial reference clock DOC#: SP-AP-0755 (Rev. AA) PWR Ground for 48MHz clocks 3.3V Power supply for SATA clock Page 2 of 22 SL28EB717 Pin No. 32 Name GND_SRC Type GND Description Ground for SRC clocks 33 VDD_SRC PWR 3.3V Power supply for SRC clocks PWR 3.3V Power supply for SRC clocks 34 VDD_SRC 35 SRC6# / CPU2#_ITP O, DIF Selectable complementary differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD assertion = SRC6 ITP_EN = 1 @ CK_PWRGD assertion = CPU2 36 SRC6 / CPU2_ITP, O, DIF Selectable True differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD assertion = SRC6 ITP_EN = 1 @ CK_PWRGD assertion = CPU2 37 CPU1# O, DIF Complement differential CPU clock output 38 CPU1 O, DIF True differential CPU clock output 39 VDD_CPU PWR 3.3V Power supply for CPU clocks 40 CPU0# O, DIF Complement differential CPU clock output 41 CPU0 O, DIF True differential CPU clock output 42 GND_CPU 43 SCLK GND I I/O Ground for clocks SMBus compatible SCLOCK 44 SDATA 45 CPU_STP#* I, PU SMBus compatible SDATA 46 PCI/SRC_STP#* I, PU 47 XOUT O 25.00MHz Crystal output, Float XOUT if using only CLKIN (Clock input) 48 XIN / CLKIN I 25.00MHz Crystal input or 3.3V, 25MHz Clock Input 3.3V-tolerant input for stopping CPU outputs (internal 100K-ohm pull-up) 3.3V-tolerant input for stopping PCI and SRC outputs (internal 100K-ohm pull-up) EProClock® Programmable Technology EProClock® is the world’s first non-volatile programmable clock. The EProClock® technology allows board designer to promptly achieve optimum compliance and clock signal integrity; historically, attainable typically through device and/or board redesigns. - Custom frequency sets EProClock® technology can be configured through SMBus or hard coded. - Differential and single-ended slew rate control - Differential skew control on true or compliment or both - Differential duty cycle control on true or compliment or both - Differential amplitude control Features: - Program Internal or External series resistor on single-ended clocks - > 4000 bits of configurations - Program different spread profiles - Can be configured through SMBus or hard coded - Program different spread modulation rate Frequency Select Pin (FS) SEL_SATA FSC FSB FSA CPU SRC SATA75/SRC0 PCI 0 0 0 0 100.00 100.00 100.00 33.33 0 0 0 1 100.00 100.00 100.00 33.33 0 0 1 0 83.33 100.00 100.00 33.33 0 0 1 1 83.33 100.00 100.00 33.33 0 1 0 0 133.33 100.00 100.00 33.33 0 1 0 1 133.33 100.00 100.00 33.33 0 1 1 0 166.67 100.00 100.00 33.33 0 1 1 1 166.67 100.00 100.00 33.33 1 0 0 0 100.00 100.00 75.00 33.33 1 0 0 1 100.00 100.00 75.00 33.33 DOC#: SP-AP-0755 (Rev. AA) Page 3 of 22 SL28EB717 Frequency Select Pin (FS) 1 0 1 0 83.33 100.00 75.00 33.33 1 0 1 1 1 0 1 83.33 100.00 75.00 33.33 0 133.33 100.00 75.00 33.33 1 1 0 1 133.33 100.00 75.00 33.33 1 1 1 0 166.67 100.00 75.00 33.33 1 1 1 1 166.67 100.00 75.00 33.33 Frequency Select Pin FS Serial Data Interface Apply the appropriate logic levels to FS inputs before CKPWRGD assertion to achieve host clock frequency selection. When the clock chip sampled HIGH on CKPWRGD and indicates that VTT voltage is stable then FS input values are sampled. This process employs a one-shot functionality and once the CKPWRGD sampled a valid HIGH, all other FS, and CKPWRGD transitions are ignored except in test mode. To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. The interface cannot be used during system operation for power management functions. Wake-On-LAN (WOL) Support When power is applied to the VDD_SUSPEND pin, the 25MHz reference clock output will be enabled under all conditions, unless the WOL_EN bit, Byte 1 bit 1, is set to “0”. When the WOL_EN bit Byte 1 bit 1, is set to “0”, the WOL_STP# pin will function as a PD# pin. By default, the WOL_EN bit is enabled and set to a “1”. The clock device will support “out-of-the-box” WOL or after a power outage by enabling the 25MHz reference clock output when the clock device powers up for the very first time with only power applied to the VDD_SUSPEND pin and all other VDD pins power have not been applied. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address–7 bits Block Read Protocol Bit 1 8:2 Description Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Byte Count–8 bits 20 Repeat start DOC#: SP-AP-0755 (Rev. AA) Page 4 of 22 SL28EB717 Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 28 36:29 37 45:38 46 Block Read Protocol Description Bit Acknowledge from slave 27:21 Description Slave address–7 bits Data byte 1–8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2–8 bits 37:30 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N–8 bits 38 46:39 47 .... Acknowledge from slave .... Stop 55:48 Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave–8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Byte Read Protocol Description Bit Start 1 Slave address–7 bits 8:2 Description Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits 18:11 Acknowledge from slave 19 Data byte–8 bits 20 28 Acknowledge from slave 29 Stop 27:21 Command Code–8 bits Acknowledge from slave Repeated start Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave–8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0: Control Register 0 Bit @Pup Name 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 Spread Enable 4 HW SEL_SATA See Table 1 for SATA/SRC selection. 3 0 RESERVED RESERVED 2 HW FSC 1 HW FSB 0 HW FSA DOC#: SP-AP-0755 (Rev. AA) Description Enable spread for CPU/SRC/PCI outputs 0=Disable, 1= -0.5% See Table 1 for CPU Frequency selection Table Page 5 of 22 SL28EB717 Byte 1: Control Register 1 Bit @Pup Name 7 1 DOT96_OE Output enable for DOT96 0 = Output Disabled, 1 = Output Enabled Description 6 1 SATA75/SRC0_OE Output enable for SATA75/SRC0 0 = Output Disabled, 1 = Output Enabled 5 1 CPU2/SRC6_OE Output enable for CPU2/SRC6 0 = Output Disabled, 1 = Output Enabled 4 1 SRC2 Output enable for SRC2 0 = Output Disabled, 1 = Output Enabled 3 1 SRC1 Output enable for SRC1 0 = Output Disabled, 1 = Output Enabled 2 1 RESERVED 1 1 WOL_EN 0 0 RESERVED RESERVED Wake-On-LAN Enable bit 25MHz free running during VDD Suspend (S-states). If this bit is set to 0, the XTAL OSC will also be powered down in the Suspend States) RESERVED Byte 2: Control Register 2 Bit @Pup Name 7 1 48M_OE Description 6 0 RESERVED 5 1 14M_OE Output enable for 14M 0 = Output Disabled, 1 = Output Enabled 4 1 25M_OE Output enable for 25M 0 = Output Disabled, 1 = Output Enabled 3 1 12_48M_OE Output enable for 12_48M 0 = Output Disabled, 1 = Output Enabled 2 1 PCI0_OE Output enable for PCI0 0 = Output Disabled, 1 = Output Enabled 1 1 PCIF_OE Output enable for PCIF 0 = Output Disabled, 1 = Output Enabled 0 0 RESERVED Output enable for 48M 0 = Output Disabled, 1 = Output Enabled RESERVED RESERVED Byte 3: Control Register 3 Bit @Pup Name 7 1 CPU1_OE Output enable for CPU1 0 = Output Disabled, 1 = Output Enabled 6 1 CPU0_OE Output enable for CPU0 0 = Output Disabled, 1 = Output Enabled 5 0 CLKREQ#_3 Clock request for SRC2 0=Not controlled, 1= Controlled 4 0 CLKREQ#_3 Clock request for SRC6 (does not apply to CPU clock) 0=Not controlled, 1= Controlled 3 0 CLKREQ#_2 Clock request for SRC2 0=Not controlled, 1= Controlled 2 0 CLKREQ#_2 Clock request for SATA75M/SRC0 0=Not controlled, 1= Controlled DOC#: SP-AP-0755 (Rev. AA) Description Page 6 of 22 SL28EB717 Byte 3: Control Register 3 1 0 CLKREQ#_1 Clock request for SRC1 0=Not controlled, 1= Controlled 0 0 CLKREQ#_1 Clock request for SATA75M/SRC0 0=Not controlled, 1= Controlled Byte 4: Control Register 4 Bit @Pup Name 7 0 RESERVED 6 0 CPU1 5 HW 12_48M 4 0 CPU2 3 HW ITP_EN 2 0 RESERVED 1 0 CPU0 0 0 RESERVED Description RESERVED CPU1 Free Run Control 0= Free Running, 1= Stoppable Selectable 12_48M status 0= 48M, 1=12M CPU2 Free Run Control 0= Free Running, 1= Stoppable SelectableCPUe_ITP/ SRC6 status 0= SRC6, 1=CPU2 RESERVED CPU0 Free Run Control 0= Free Running, 1= Stoppable RESERVED Byte 5: Control Register 5 Bit @Pup Name 7 0 RESERVED RESERVED Description 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 1 SATA75/SRC0 SATA75/SRC0 Free Run Control 0= Free Running, 1= Stoppable 3 0 SRC6 SRC6 Free Run Control 0= Free Running, 1= Stoppable 2 0 SRC2 SRC2 Free Run Control 0= Free Running, 1= Stoppable 1 0 SRC1 SRC1 Free Run Control 0= Free Running, 1= Stoppable 0 0 RESERVED RESERVED Byte 6: Control Register 6 Bit @Pup Name 7 0 CPU_AMP 6 1 CPU_AMP 5 0 SRC_AMP 4 1 SRC_AMP 3 0 DOT96_AMP 2 1 DOT96_AMP 1 0 SATA_AMP 0 1 SATA_AMP DOC#: SP-AP-0755 (Rev. AA) Description CPU amplitude adjustment 00= 700mV, 01=800mV, 10=900mV, 11= 1000mV SRC amplitude adjustment 00= 700mV, 01=800mV, 10=900mV, 11= 1000mV DOT96 amplitude adjustment 00= 700mV, 01=800mV, 10=900mV, 11= 1000mV SATA75/SRC0 amplitude adjustment 00= 700mV, 01=800mV, 10=900mV, 11= 1000mV Page 7 of 22 SL28EB717 Byte 7: Vendor ID Bit @Pup Name Description 7 0 Rev Code Bit 3 Revision Code Bit 3 6 0 Rev Code Bit 2 Revision Code Bit 2 5 0 Rev Code Bit 1 Revision Code Bit 1 4 1 Rev Code Bit 0 Revision Code Bit 0 3 1 Vendor ID bit 3 Vendor ID Bit 3 2 0 Vendor ID bit 2 Vendor ID Bit 2 1 0 Vendor ID bit 1 Vendor ID Bit 1 0 0 Vendor ID bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name 7 0 BC7 6 0 BC6 5 0 BC5 4 0 BC4 3 1 BC3 2 1 BC2 1 1 BC1 0 1 BC0 Description Byte count register for block read operation. The default value for Byte count is 15 In order to read beyond Byte 15, the user should change the byte count limit.to or beyond the byte that is desired to be read. Byte 9: Control Register 9 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 RESERVED RESERVED 5 1 SRC3 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 SRC3 SRC3 Free Run Control 0= Free Running, 1= Stoppable 1 0 PCI0 PCI0 Free Run Control 0= Free Running, 1= Stoppable 0 1 PCIF PCIF Free Run Control 0= Free Running, 1= Stoppable Output enable for SRC3 0 = Output Disabled, 1 = Output Enabled Byte 10: Control Register 10 Bit @Pup Name 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED DOC#: SP-AP-0755 (Rev. AA) Description Page 8 of 22 SL28EB717 Byte 11: Control Register 11 Bit @Pup Name 7 1 14M_Bit2 6 0 14M_Bit1 5 1 14M_Bit0 4 1 25M_Bit2 3 0 25M_Bit1 2 1 25M_Bit0 1 1 12_48M_Bit2 0 1 12_48M_Bit0 Description Drive Strength Control - Bit[2:0] Normal mode default ‘101’ Wireless Friendly Mode default to ‘111’ Byte 12: Control Register 12 Bit @Pup Name 7 1 48M_Bit2 6 0 48M_Bit1 5 1 48M_Bit0 4 1 PCI0_Bit2 3 0 PCI0_Bit1 2 1 PCI0_Bit0 1 0 RESERVED 0 0 12_48M_Bit1 Description Drive Strength Control - Bit[2:0] Normal mode default ‘101’ Wireless Friendly Mode default to ‘111’ Byte 13: Control Register 13 Bit @Pup Name 7 1 PCIF_Bit2 6 0 PCIF_Bit1 5 1 PCIF_Bit0 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED 0 0 Wireless Friendly mode DOC#: SP-AP-0755 (Rev. AA) Description Drive Strength Control - Bit[2:0] Normal mode default ‘101’ Wireless Friendly Mode default to ‘111’ RESERVED Wireless Friendly Mode 0 = Disabled, Default all single-ended clocks slew rate config bits to ‘101’ 1 = Enabled, Default all single-ended clocks slew rate config bits to ‘111’ Page 9 of 22 SL28EB717 Byte 14: Control Register 14 Bit @Pup Name 7 1 RESERVED RESERVED Description 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED 4 0 OTP_4 3 0 OTP_3 2 0 OTP_2 1 0 OTP_1 0 0 OTP_0 OTP_ID Idenification for programmed device . Table 4. Output Driver Status during CPU_STP# & PCIS_STP# CPU_STP# Asserted Single-ended Clocks Stoppable Differential Clocks PCI_STP# Asserted CLKREQ# Asserted Running Driven Low Running Non stoppable Running Running Running Stoppable Clock driven high Clock driven high Clock driven low Clock# driven low Clock# driven low Clock# driven low Running Running Running Non stoppable SMBus OE Disabled Driven low Clock driven low Table 5. Output Driver Status All Single-ended Clocks PD# = 0 (Power down) All Differential Clocks w/o Strap w/ Strap Clock Clock# Low Hi-z Low Low PD# (Power down) Clarification The CKPWRGD/PD# pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Once CKPWRGD has been sampled HIGH by the clock chip, the pin assumes PD# functionality. The PD# pin is an asynchronous active LOW input used to shut off all clocks cleanly before shutting off power to the device. This signal is synchronized internally to the device before powering down the clock synthesizer. PD# is also an asynchronous input for powering up the system. When PD# is asserted LOW, clocks are driven to a LOW value and held before turning off the VCOs and the crystal oscillator. PD# (Power down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their DOC#: SP-AP-0755 (Rev. AA) next HIGH-to-LOW transition and differential clocks must held LOW. When PD mode is desired as the initial power on state, PD must be asserted HIGH in less than 10 s after asserting CKPWRGD. PD# Deassertion The power up latency is less than 1.8 ms. This is the time from the deassertion of the PD# pin or the ramping of the power supply until the time that stable clocks are generated from the clock chip. All differential outputs stopped in a three-state condition, resulting from power down are driven high in less than 300 s of PD# deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of each clock. Figure 2 is an example showing the relationship of clocks coming up. Page 10 of 22 SL28EB717 PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 1. Power down Assertion Timing Waveform Ts ta b le < 1 .8 m s PD# C P U T , 1 3 3 MH z C P U C , 1 3 3 MH z S R C T 1 0 0 MH z S R C C 1 0 0 MH z U S B , 4 8 MH z D OT 9 6 T D OT 9 6 C P C I, 3 3 MH z Td r iv e _ PW R D N # <300 s , >2 00m V REF Figure 2. Power down Deassertion Timing Waveform FS _A, FS _B ,FS_C ,FS _D CKPWRGD P W R G D _V R M 0.2-0.3 m s D elay V D D C lock G en C lock S tate C lock O utputs C lock V C O S tate 0 W ait for V TT_PW R G D # S tate 1 State 2 O ff O ff D evice is not affected, V TT_P W R G D # is ignored S am ple S els State 3 On On Figure 3. CKPWRGD Timing Diagram DOC#: SP-AP-0755 (Rev. AA) Page 11 of 22 SL28EB717 CPU_STP# Assertion CPU_STP# Deassertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable are stopped within two to six CPU clock periods after sampled by two rising edges of the internal CPUC clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. The deassertion of the CPU_STP# signal causes all stopped CPU outputs to resume normal operation in a synchronous manner. No short or stretched clock pulses are produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. CPU_STP# CPUT CPUC Figure 4. CPU_STP# Assertion Waveform CPU_STP# CPUT CPUC CPUT Internal CPUC Internal Tdrive_CPU_STP#,10 ns>200 mV Figure 5. CPU_STP# Deassertion Waveform PCI/SRC_STP# Assertion . The PCI/SRC_STP# signal is an active LOW input used for synchronously stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI/SRC_STP# going LOW is 10 ns (tSU). (See Figure 6.) The PCIF and SRC clocks are affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. For SRC clocks assertion description, please refer to CPU_STP# description. T su PC I_STP# PC I_F PC I SR C 100M H z Figure 6. PCI_STP# Assertion Waveform DOC#: SP-AP-0755 (Rev. AA) Page 12 of 22 SL28EB717 PCI/SRC_STP# Deassertion . The deassertion of the PCI/SRC_STP# signal causes all PCI and stoppable PCIF to resume running in a synchronous manner within two PCI clock periods, after PCI/SRC_STP# transitions to a HIGH level. Simlarly, PCI/SRC_STP# deassertion will cause stoppable SRC clocks to resume running. For SRC clocks deassertion description, please refer to CPU_STP# description. T su T drive_ S R C P C I_S T P # P C I_F PCI SR C 100 M H z Figure 7. PCI_STP# Deassertion Waveform . . Clock Off to M 1 3.3V Vcc 2.0V FSC T_delay t CPU_STP# FSB FSA PCI_STP# CKPWRGD/PD# Off CK505 SMBUS CK505 State Off Latches Open M1 BSEL[0..2] CK505 Core Logic Off PLL1 Locked CPU1 PLL2 & PLL3 All Other Clocks REF Oscillator T_delay2 T_delay3 Figure 8. BSEL Serial Latching DOC#: SP-AP-0755 (Rev. AA) Page 13 of 22 SL28EB717 Absolute Maximum Conditions Parameter Description Condition VDD_3.3V Main Supply Voltage Functional VIN Input Voltage Relative to VSS TS Temperature, Storage Non-functional TA Temperature, Operating Ambient Functional Min. Max. Unit – 4.6 V –0.5 4.6 VDC –65 150 °C –40 85 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case JEDEC (JESD 51) – 20 °C/ W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/ W ESDHBM ESD Protection (Human Body Model) JEDEC (JESD 22 - A114) 2000 – V UL-94 Flammability Rating UL (Class) Max. Unit 3.135 3.465 V 2.0 VDD + 0.3 V VSS – 0.3 0.8 V 2.2 – V V–0 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Condition VDD core 3.3V Operating Voltage VIH 3.3V Input High Voltage (SE) 3.3 ± 5% VIL 3.3V Input Low Voltage (SE) VIHI2C Input High Voltage SDATA, SCLK VILI2C Input Low Voltage SDATA, SCLK VIH_FS FS Input High Voltage VIL_FS FS Input Low Voltage IIH Input High Leakage Current Except internal pull-down resistors, 0 < VIN < VDD IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD VOH 3.3V Output High Voltage (SE) IOH = –1 mA VOL 3.3V Output Low Voltage (SE) IOZ Min. – 1.0 V 0.7 VDD+0.3 V VSS – 0.3 0.35 V – 5 A –5 – A 2.4 – V – 0.4 V High-impedance Output Current –10 10 A CIN Input Pin Capacitance 1.5 COUT Output Pin Capacitance LIN Pin Inductance – 7 nH IDD_PD Power Down Current – 1 mA IDD_3.3V Dynamic Supply Current – 100 mA DOC#: SP-AP-0755 (Rev. AA) IOL = 1 mA All outputs enabled. SE clocks with 5” traces. Differential clocks with 5” traces. Loading per CK505 spec. 5 pF 6 pF Page 14 of 22 SL28EB717 AC Electrical Specifications Parameter Description Condition Min. Max. Unit – 250 ppm Crystal LACC Long-term Accuracy Measured at VDD/2 differential Clock Input TDC CLKIN Duty Cycle Measured at VDD/2 47 53 % TR/TF CLKIN Rise and Fall Times Measured between 0.2VDD and 0.8VDD 0.5 4.0 V/ns TCCJ CLKIN Cycle to Cycle Jitter Measured at VDD/2 – 250 ps TLTJ CLKIN Long Term Jitter Measured at VDD/2 – 350 ps VIH Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V VIL Input Low Voltage XIN / CLKIN pin – 0.8 V IIH Input HighCurrent XIN / CLKIN pin, VIN = VDD – 35 uA IIL Input LowCurrent XIN / CLKIN pin, 0 < VIN <0.8 –35 – uA TDC CPU Duty Cycle Measured at 0V differential TPERIOD 83.33 MHz CPU Period TPERIODSS 83.33 MHz CPU Period, SSC TPERIODAbs 83.33 MHz CPU Absolute Period CPU at 0.7V 45 55 % Measured at 0V differential at 0.1s 11.99880 12.00120 ns Measured at 0V differential at 0.1s 12.028872 12.03128 ns Measured at 0V differential at 1clock 11.18969 12.16344 ns TPERIODSSAbs 83.33 MHz CPU Absolute Period, SSC Measured at 0V differential at 1 clock 11.89687 12.16344 ns TPERIOD 100 MHz CPU Period Measured at 0V differential at 0.1s 9.99900 10.0010 ns TPERIODSS 100 MHz CPU Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODAbs 100 MHz CPU Absolute Period 10.1260 ns Measured at 0V differential at 1clock 9.87400 TPERIODSSAbs 100 MHz CPU Absolute Period, SSC Measured at 0V differential at 1 clock 9.87406 10.1762 ns TPERIOD 133 MHz CPU Period Measured at 0V differential at 0.1s 7.49925 7.50075 ns TPERIODSS 133 MHz CPU Period, SSC Measured at 0V differential at 0.1s 7.51804 7.51955 ns TPERIODAbs 133 MHz CPU Absolute period 7.58575 ns Measured at 0V differential at 1 clock 7.41425 TPERIODSSAbs 133 MHz CPU Absolute period, SSC Measured at 0V differential at1 clock 7.41430 7.62340 ns TPERIOD 166 MHz CPU Period Measured at 0V differential at 0.1s 5.99940 6.00060 ns TPERIODSS 166 MHz CPU Period, SSC Measured at 0V differential at 0.1s 6.01444 6.01564 ns TPERIODAbs 166 MHz CPU Absolute period 6.08560 ns 6.11572 ns Measured at 0V differential at 1 clock 5.91440 TPERIODSSAbs 166 MHz CPU Absolute period, SSC Measured at 0V differential at 1 clock 5.91444 TCCJ CPU Cycle to Cycle Jitter Measured at 0V differential – 85 ps TCCJ (CPU2) CPU Cycle to Cycle Jitter for CPU 2 Measured at 0V differential – 125 ps Skew CPU0 to CPU1 skew Measured at 0V differential – 100 ps LACC Long-term Accuracy Measured at 0V differential – 100 ppm T R / TF CPU Rising/Falling Slew rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV SRC at 0.7V TDC SRC Duty Cycle Measured at 0V differential 45 55 % TPERIOD 100 MHz SRC Period Measured at 0V differential at 0.1s 9.99900 10.0010 ns TPERIODSS 100 MHz SRC Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODAbs 100 MHz SRC Absolute Period Measured at 0V differential at 1 clock 9.87400 10.1260 ns Measured at 0V differential at 1 clock 9.87406 10.1762 ns TPERIODSSAbs 100 MHz SRC Absolute Period, SSC DOC#: SP-AP-0755 (Rev. AA) Page 15 of 22 SL28EB717 AC Electrical Specifications (continued) Parameter Description Condition TSKEW(window) Any SRC Clock Skew from the earliest Measured at 0V differential bank to the latest bank Min. Max. Unit – 3.0 ns – 125 ps TCCJ SRC Cycle to Cycle Jitter Measured at 0V differential LACC SRC Long Term Accuracy Measured at 0V differential – 100 ppm T R / TF SRC Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV DOT96 at 0.7V TDC DOT96 Duty Cycle Measured at 0V differential 45 55 % 10.4177 ns ns TPERIOD DOT96 Period Measured at 0V differential at 0.1s 10.4156 TPERIODAbs DOT96 Absolute Period Measured at 0V differential at 0.1s 10.1656 10.6677 TCCJ DOT96 Cycle to Cycle Jitter Measured at 0V differential at 1 clock – 250 ps LACC DOT96 Long Term Accuracy Measured at 0V differential at 1 clock – 100 ppm T R / TF DOT96 Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV SATA75M at 0.7V TDC SATA75M Duty Cycle Measured at 0V differential 45 55 % TCCJ SATA75M Cycle to Cycle Jitter Measured at 0V differential at 1 clock – 125 ps LACC SATA75M Long Term Accuracy Measured at 0V differential at 1 clock – 100 ppm T R / TF SATA75M Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV PCI/PCIF at 3.3V TDC PCI Duty Cycle Measurement at 1.5V 45 55 % 30.00300 ns TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99700 TPERIODSS Spread Enabled PCIF/PCI Period Measurement at 1.5V 30.08421 30.23459 ns TPERIODAbs Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.49700 30.50300 ns TPERIODSSAbs Spread Enabled PCIF/PCI Period Measurement at 1.5V 29.56617 30.58421 ns THIGH Spread Enabled PCIF and PCI high time Measurement at 2V 12.27095 16.27995 ns TLOW Spread Enabled PCIF and PCI low time Measurement at 0.8V 11.87095 16.07995 ns THIGH Spread Disabled PCIF and PCI high time 12.27365 16.27665 ns TLOW Spread Disabled PCIF and PCI low time Measurement at 0.8V 11.87365 16.07665 ns T R / TF PCIF/PCI Rising/Falling Slew Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 1000 ps TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 300 ps LACC PCIF/PCI Long Term Accuracy Measurement at 1.5V – 100 ppm DOC#: SP-AP-0755 (Rev. AA) Measurement at 2.V Page 16 of 22 SL28EB717 AC Electrical Specifications (continued) Parameter Description Condition Min. Max. Unit 48M, 12_48M at 3.3V TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD 48MHz Period Measurement at 1.5V 20.83125 20.83542 ns TPERIODAbs 48MHz Absolute Period Measurement at 1.5V 20.48125 21.18542 ns THIGH 48MHz High time Measurement at 2V 8.216563 11.15198 ns TLOW 48MHz Low time Measurement at 0.8V 7.816563 10.95198 ns TR / TF (48M) Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 2.0 V/ns T R / TF (12_48M) Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 2.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 300 ps LACC Long Term Accuracy Measurement at 1.5V – 100 ppm TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 39.996 40.004 ns TPERIODAbs Absolute Period Measurement at 1.5V 39.32360 40.67640 ns T R / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 300 ps LACC Long Term Accuracy Measured at 1.5V – 100 ppm 25M at 3.3V 14.318M, at 3.3V TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 69.82033 69.86224 ns TPERIODAbs Absolute Period Measurement at 1.5V 68.83429 70.84826 ns THIGH High time Measurement at 2V 29.97543 38.46654 ns TLOW Low time Measurement at 0.8V 29.57543 38.26654 ns T R / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 500 ps LACC Long Term Accuracy Measurement at 1.5V – 100 ppm – 1.8 ms 10.0 – ns ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS Stopclock Set-up Time DOC#: SP-AP-0755 (Rev. AA) Page 17 of 22 SL28EB717 Test and Measurement Set-up For Single Ended Clocks The following diagram shows the test load configurations for the single-ended output signals. Figure 9. Single-ended clocks Single Load Configuration Figure 10. Single-ended clocks Double Load Configuration Figure 11. Single-ended Output Signals (for AC Parameters Measurement) DOC#: SP-AP-0755 (Rev. AA) Page 18 of 22 SL28EB717 For Differential Clock Signals This diagram shows the test load configuration for the differential clock signals Figure 12. 0.7V Differential Load Configuration Figure 13. Differential Measurement for Differential Output Signals (for AC Parameters Measurement) DOC#: SP-AP-0755 (Rev. AA) Page 19 of 22 SL28EB717 Figure 14. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) DOC#: SP-AP-0755 (Rev. AA) Page 20 of 22 SL28EB717 Ordering Information Part Number Package Type Product Flow Lead-free SL28EB717ALI 48-pin QFN Industrial, -40 to 85C SL28EB717ALIT 48-pin QFN – Tape and Reel Industrial, -40 to 85C Package Diagrams 48-Lead QFN 6 x 6mm DOC#: SP-AP-0755 (Rev. AA) Page 21 of 22 SL28EB717 Document History Page Document Title: SL28EB717 PC EProClock® Generator for Intel Tunnel Creek & Top Cliff DOC#: SP-AP-0755 (Rev. AA) Issue Date Orig. of Change 0.3 11/30/09 JMA Initial Release 0.4 12/15/09 JMA Updated Table in Feature section to add PCI clocks Updated pin naming in pin diagram Added PCI_STP# state in Table 4 Updated Figure 3 to show trace length Edited ordering information REV. ECR# Description of Change AA 1431 01/04/09 JMA 1. Added WOL Support and description 2. Changed VDD_REF pin to VDD_SUSPEND pin 3. Changed PD# pin to WOL_STP# pin 4. Updated Table 4 to show CLKREQ# status 5. Showed Byte 8bit [7:0] to be byte count 6. Added note to Byte 3 bit 4 to indicate bit will not affect CPU clock 7. Added SRC0 to Byte 3 [bit 2 & bit 0] to indicate bit will disable SATA75 and SRC0 8.Updated 12M_48M slew rate to be 2V/ns max 9. Updated Test condition circuit for single-ended clocks from triple loads to double load 10. Updated all differential clocks to be 8V/ns max instead of 4V/ns max AA 1638 06/23/10 JMA 1. Added CLKIN feature 2. Added Period Spec for CPU, SRC, and DOT96 3. Added Cycle-to-cycle jitter spec for CPU2/SRC5 (ITP clock) 4. Removed REF wording from 14.318MHz 5. Reduced IDD to 130mA from 200mA 6. Reduced PCI clocks cycle-to-cycle jitter to 300ps from 500ps 7. Reduced 25MHzclock cycle-to-cycle jitter to 300ps from 500ps 8. Reduced 48/12MHz clocks cycle-to-cycle jitter to 300ps from 350ps 9. Reduced 14.318MHz clock cycle-to-cycle jitter to 500ps from 1000ps 10. Reduced SATA75 clock cycle-to-cycle jitter to 125ps from 250ps 11. Removed skew for 14MHz 12. Updated CPU2 Cycle-to-cycle jitter to be 125ps from 85ps 13. Updated Package information 14. Added PD# label to pin configuration on page 1 15. Updated MIL-STD to JEDEC 16. Removed Prliminary wording 17. Added period spec for 83.33, 133, and 166MHz 18. Updated block diagram 19. Updated MSL Level from 1 to 2 AA 11/10/10 JMA Updated Rev. ID Byte 7 AA 11/17/10 TRP 1. Updated revision to AA 2. Renamed byte 12 as ‘Control Register’ from ‘Byte count’ The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. DOC#: SP-AP-0755 (Rev. AA) Page 22 of 22