Si 5 50 REVISION D VO L TAG E - C ONTR OLLED C RYSTAL O S C I L L A T O R (VCXO) 10 MH Z TO 1.4 G H Z Features Available with any frequency from 10 to 945 MHz and select frequencies to 1.4 GHz 3rd generation DSPLL® with superior jitter performance (0.5 ps) 3x better temperature stability than SAW-based oscillators Excellent PSRR performance Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant Si5602 Ordering Information: Applications See page 10. SONET/SDH xDSL 10 GbE LAN/WAN Low-jitter clock generation Optical modules Clock and data recovery Pin Assignments: See page 9. Description The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low-jitter clock at high frequencies. The Si550 supports any frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike traditional VCXOs, where a different crystal is required for each output frequency, the Si550 uses one fixed crystal to provide a wide range of output frequencies. This IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. The Si550 IC-based VCXO is factory-configurable for a wide variety of user specifications, including frequency, supply voltage, output format, tuning slope, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating the long lead times associated with custom oscillators. (Top View) VC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Functional Block Diagram V DD Any-Frequency 10 MHz–1.4 GHz DSPLL ® Clock Synthesis Fixed Frequency XO Vc CLK– ADC OE Rev. 1.1 4/13 CLK+ GND Copyright © 2013 by Silicon Laboratories Si550 Si5 50 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Symbol Test Condition Min Typ Max Units VDD 3.3 V option 2.97 3.3 3.63 V 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 V Output enabled LVPECL CML LVDS CMOS — — — — 120 108 99 90 130 117 108 98 tristate mode — 60 75 mA VIH 0.75 x VDD — — V VIL — — 0.5 V –40 — 85 °C Supply Current Output Enable IDD (OE)2 Operating Temperature Range TA mA Notes: 1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 10 for further details. 2. OE pin includes a 17 k resistor to VDD. Table 2. VC Control Voltage Input Parameter Control Voltage Tuning Slope 1,2,3 Control Voltage Linearity4 Symbol Test Condition Min Typ Max Units KV 10 to 90% of VDD — — — — — — 33 45 90 135 180 356 — — — — — — ppm/V BSL –5 ±1 +5 % Incremental –10 ±5 +10 % LVC Modulation Bandwidth BW 9.3 10.0 10.7 kHz VC Input Impedance ZVC 500 — — k — VDD/2 — V VDD V Nominal Control Voltage Control Voltage Tuning Range VCNOM @ fO VC 0 Notes: 1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 10. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. KV variation is ±10% of typical values. 4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope determined with VC ranging from 10 to 90% of VDD. 2 Rev. 1.1 Si550 Table 3. CLK± Output Frequency Characteristics Parameter Symbol Test Condition Min Typ Max Units fO LVDS/CML/LVPECL 10 — 945 MHz CMOS 10 — 160 MHz TA = –40 to +85 ºC –20 –50 –100 — — — +20 +50 +100 ppm ±12 — ±375 ppm Frequency drift over first year. — — ±3 Frequency drift over 15 year life. — — ±10 — — 10 Nominal Frequency1,2,3 Temperature Stability1,4 Absolute Pull Range1,4 APR Aging Power up Time5 tOSC ppm ms Notes: 1. See Section 3. "Ordering Information" on page 10 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Nominal output frequency set by VCNOM = VDD/2. 4. Selectable parameter specified by part number. 5. Time from power up or tristate mode to fO. Table 4. CLK± Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Units VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP 2.5/3.3 V option mid-level — VDD – 1.30 — V 1.8 V option mid-level — VDD – 0.36 — V 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP 1.8 V option swing (diff) 0.35 0.425 0.50 VPP VOH IOH = 32 mA 0.8 x VDD — VDD V VOL IOL = 32 mA — — 0.4 V tR, tF LVPECL/LVDS/CML — — 350 ps CMOS with CL = 15 pF — 1 — ns 45 — 55 % LVPECL Output Option1 LVDS Output Option 2 VO CML Output Option2 VOD CMOS Output Option 3 Rise/Fall time (20/80%) Symmetry (duty cycle) SYM LVPECL: LVDS: CMOS: VDD – 1.3 V (diff) 1.25 V (diff) VDD/2 Notes: 1. 50 to VDD – 2.0 V. 2. Rterm = 100 (differential). 3. CL = 15 pF Rev. 1.1 3 Si5 50 Table 5. CLK± Output Phase Jitter Parameter 1,2,3 Phase Jitter (RMS) for FOUT > 500 MHz Symbol Test Condition Min Typ Max Units J Kv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.26 0.26 — — ps Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.27 0.26 — — ps Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.32 0.26 — — ps Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.40 0.27 — — ps Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.49 0.28 — — ps Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.87 0.33 — — ps Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions. 4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz. 5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz, 2 MHz for 10 MHz < FOUT <50 MHz. 4 Rev. 1.1 Si550 Table 5. CLK± Output Phase Jitter (Continued) Parameter Phase Jitter (RMS)1,2,3,4,5 for FOUT of 125 to 500 MHz Symbol Test Condition Min Typ Max Units J Kv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.37 0.33 — — ps Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.37 0.33 0.4 — ps Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.43 0.34 — — ps Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.50 0.34 — — ps Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.59 0.35 — — ps Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 1.00 0.39 — — ps Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions. 4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz. 5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz, 2 MHz for 10 MHz < FOUT <50 MHz. Rev. 1.1 5 Si5 50 Table 5. CLK± Output Phase Jitter (Continued) Parameter Phase Jitter (RMS)1,2,5 for FOUT 10 to 160 MHz CMOS Output Only Symbol Test Condition Min Typ Max Units J Kv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 0.63 0.62 — — ps Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 0.63 0.62 — — ps Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 0.67 0.66 — — ps Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 0.74 0.72 — — ps Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 0.83 0.8 — — ps Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 1.26 1.2 — — ps Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions. 4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz. 5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz, 2 MHz for 10 MHz < FOUT <50 MHz. Table 6. CLK± Output Period Jitter Parameter Period Jitter* Symbol Test Condition Min Typ Max Units JPER RMS — 2 — ps Peak-to-Peak — 14 — *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. 6 Rev. 1.1 Si550 Table 7. CLK± Output Phase Noise (Typical) Offset Frequency 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 74.25 MHz 155.52 MHz 491.52 MHz 622.08 MHz 90 ppm/V 45 ppm/V 45 ppm/V 135 ppm/V LVPECL LVPECL LVPECL LVPECL –87 –114 –132 –142 –148 –150 n/a –86 –111 –128 –133 –144 –147 n/a –75 –100 –116 –124 –135 –146 –147 –65 –90 –109 –121 –134 –146 –147 Units dBc/Hz Table 8. Environmental Compliance The Si550 meets the following qualification test requirements. Parameter Conditions/Test Method Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 203 Gross & Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Moisture Sensitivity Level J-STD-020, MSL 1 Contact Pads J-STD-020, MSL 1 Table 9. Thermal Characteristics (Typical values TA = 25 ºC, VDD = 3.3 V) Parameter Symbol Test Condition Min Typ Max Unit Thermal Resistance Junction to Ambient JA Still Air — 84.6 — °C/W Thermal Resistance Junction to Case JC Still Air — 38.8 — °C/W Ambient Temperature TA –40 — 85 °C Junction Temperature TJ — — 125 °C Rev. 1.1 7 Si5 50 Table 10. Absolute Maximum Ratings1 Parameter Symbol Rating Units TAMAX 85 ºC Supply Voltage, 1.8 V Option VDD –0.5 to +1.9 V Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V Input Voltage VI –0.5 to VDD + 0.3 V Storage Temperature TS –55 to +125 ºC ESD 2500 V TPEAK 260 ºC tP 20–40 seconds Maximum Operating Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile) 2 Soldering Temperature Time @ TPEAK (Pb-free profile)2 Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from www.silabs.com/VCXO for further information, including soldering profiles. 8 Rev. 1.1 Si550 2. Pin Descriptions (Top View) VC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Table 11. Si550 Pin Descriptions Pin Name Type 1 VC Analog Input Function Control Voltage Output Enable (Polarity = High): 0 = clock output disabled (outputs tri-stated) 1 = clock output enabled Output Enable (Polarity = Low): 0 = clock output enabled 1 = clock output disabled (outputs tri-stated) 2 OE* Input 3 GND Ground Electrical and Case Ground 4 CLK+ Output Oscillator Output 5 CLK– (N/A for CMOS) Output Complementary Output (N/C for CMOS, make no external connection) 6 VDD Power Power Supply Voltage *Note: OE includes 17 k pullup resistor to VDD. See Section 3. "Ordering Information" on page 10 for details on OE polarity ordering options. Rev. 1.1 9 Si5 50 3. Ordering Information The Si550 supports a variety of options including frequency, temperature stability, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si550 at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si550 VCXO series is available in an industry-standard, RoHS compliant, lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option. 550 X X XXXMXXX D G R R = Tape & Reel Blank = Trays 550 VCXO Product Family Operating Temp Range (°C) G –40 to +85 °C Device Revision Letter Frequency (e.g. 622M080 is 622.080 MHz) Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213 to 1417 MHz. The position of “M” shifts to denote higher or lower frequencies. If the frequency of interest requires greater than 6 digit resolution, a six digit code will be assigned for the specific frequency. 1st Option Code A B C D E F G H J K M N P Q R S T U V W VDD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 2nd Option Code Output Format Output Enable Polarity LVPECL High LVDS High CMOS High CML High LVPECL High LVDS High CMOS High CML High CMOS High CML High LVPECL Low LVDS Low CMOS Low CML Low LVPECL Low LVDS Low CMOS Low CML Low CMOS Low CML Low Note: CMOS available to 160 MHz. Temperature Stability ± ppm (max) 100 100 50 50 20 50 20 20 20 100 20 Tuning Slope Kv ppm/V (typ) 180 90 180 90 45 135 356 180 135 356 33 Minimum APR (±ppm) for VDD @ 2.5 V 1.8 V 75 25 Note 6 Note 6 125 75 30 25 Note 6 Note 6 75 50 300 235 145 105 104 70 220 155 Note 6 Note 6 3.3 V Code A 100 B 30 C 150 D 80 E 25 F 100 G 375 H 185 J 130 K 295 M 12 Notes: 1. For best jitter and phase noise performance, always choose the smallest Kv that meets the application’s minimum APR requirements. Unlike SAW-based solutions which require higher higher Kv values to account for their higher temperature dependence, the Si55x series provides lower Kv options to minimize noise coupling and jitter in realworld PLL designs. See AN255 and AN266 for more information. 2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all operating conditions. 3. Nominal Pull range (±) = 0.5 x VDD x tuning slope. 4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging = 0.5 x VDD x tuning slope – stability – 10 ppm 5. Minimum APR values noted above include worst case values for all parameters. 6. Combination not available. Example Part Number: 550AF622M080DGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 622.080 MHz, with a 3.3 V supply, LVPECL output, and Output Enable active high polarity. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format. Figure 1. Part Number Convention 10 Rev. 1.1 Si550 4. Package Outline and Suggested Pad Layout Figure 2 illustrates the package details for the Si550. Table 12 lists the values for the dimensions shown in the illustration. Figure 2. Si550 Outline Diagram Table 12. Package Diagram Dimensions (mm) Dimension A b c D D1 e E E1 H L p R aaa bbb ccc ddd eee Min 1.50 1.30 0.50 4.30 6.10 0.55 1.17 1.80 Nom 1.65 1.40 0.60 5.00 BSC 4.40 2.54 BSC. 7.00 BSC. 6.20 0.65 1.27 — 0.70 REF 0.15 0.15 0.10 0.10 0.50 Rev. 1.1 Max 1.80 1.50 0.70 4.50 6.30 0.75 1.37 2.60 11 Si5 50 5. 6-Pin PCB Land Pattern Figure 3 illustrates the 6-pin PCB land pattern for the Si550. Table 13 lists the values for the dimensions shown in the illustration. Figure 3. Si550 PCB Land Pattern Table 13. PCB Land Pattern Dimensions (mm) Dimension Min Max D2 5.08 REF e 2.54 BSC E2 4.15 REF GD 0.84 — GE 2.00 — VD 8.20 REF VE 7.30 REF X 1.70 TYP Y 2.15 REF ZD — 6.78 ZE — 6.30 Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). 12 Rev. 1.1 Si550 6. Top Marking 6.1. Si550 Top Marking 6.2. Top Marking Explanation Line Position 1 1–10 “SiLabs”+ Part Family Number, 550 (First 3 characters in part number) 2 1–10 Si550: Option1+Option2+Freq(6007)+Temp 3 Description Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2010 = 0) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Position 10 “+” to indicate Pb-Free and RoHS-compliant Rev. 1.1 13 Si5 50 DOCUMENT CHANGE LIST Revision 0.6 to Revision 1.0 Updated Table 4 on page 3. Updated 2.5 V/3.3 V and 1.8 V CML output level specifications. Updated Table 5 on page 4. Removed the words “Differential Modes: LVPECL/LVDS/CML” in the footnote referring to AN256. Added footnotes clarifying max offset frequency test conditions. Added CMOS phase jitter specs. Updated Table 10 on page 8. Separated 1.8 V, 2.5 V/3.3 V supply voltage specifications. Updated and clarified Table 8 on page 7 Added “Moisture Sensitivity Level” and “Contact Pads” rows. Updated 6. "Top Marking" on page 13 to reflect specific marking information (previously, figure was generic). Updated 4. "Package Outline and Suggested Pad Layout" on page 11. Added cyrstal impedance pin in Figure 2 on page 11 and Table 12 on page 11. Reordered spec tables and back matter to conform to data sheet quality conventions. Revision 1.0 to Revision 1.1 14 Added Table 9, “Thermal Characteristics,” on page 7. Rev. 1.1 Si550 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. Rev. 1.1 15