Si596

Si 5 96
D U A L F REQUENCY VOLTAGE - C ON TROLLED C R Y S TA L
O SCILLATOR ( V C X O ) 1 0 TO 810 MH Z
Features


Available with any-rate output
frequencies from 10 to 810 MHz
 Two selectable output frequencies
 3rd generation DSPLL® with
superior jitter performance
 Internal fixed fundamental mode
crystal frequency ensures high
reliability and low aging




Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating range
Si5602
Ordering Information:
Applications
See page 7.



SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video



FTTx
Clock recovery and jitter cleanup PLLs
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
Description
The Si596 dual-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL® circuitry to provide a low-jitter clock at high frequencies. The Si596
is available with any-rate output frequency from 10 to 810 MHz. Unlike
traditional VCXOs, where a different crystal is required for each output
frequency, the Si596 uses one fixed crystal to provide a wide range of output
frequencies. This IC-based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides supply noise rejection, simplifying the task of generating
low-jitter clocks in noisy environments. The Si596 IC-based VCXO is
factory-configurable for a wide variety of user specifications including
frequency, supply voltage, output format, tuning slope, and absolute pull
range (APR). Specific configurations are factory programmed at time of
shipment, thereby eliminating the long lead times associated with custom
oscillators.
(Top View)
VC
1
6
VDD
FS
2
5
CLK–
GND
3
4
CLK+
Functional Block Diagram
CLK–
V DD
CLK+
Any-rate
10–810 MHz
DSPLL ®
Clock Synthesis
Fixed
Frequency
XO
ADC
Vc
Rev. 1.0 6/16
FS
GND
Copyright © 2016 by Silicon Laboratories
Si596
Si5 96
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage1
Symbol
Test Condition
Min
Typ
Max
VDD
3.3 V option
2.97
3.3
3.63
2.5 V option
2.25
2.5
2.75
1.8 V option
1.71
1.8
1.89
LVPECL
CML
LVDS
CMOS
—
—
—
—
120
110
100
90
135
120
110
100
VIH
0.75 x VDD
—
—
VIL
—
—
0.5
–40
—
85
Supply Current
IDD
Frequency Select (FS)2
Operating Temperature Range
TA
Units
V
mA
V
°C
Notes:
1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 7 for further details.
2. FS pin includes an internal 17 k pullup resistor to VDD. When the FS is left floating, the pullup causes
FS = 1 = second frequency selected.
Table 2. VC Control Voltage Input
Parameter
Control Voltage Tuning Slope
1,2,3
Control Voltage Linearity4
Symbol
Test Condition
Min
Typ
Max
Units
KV
10 to 90% of VDD
—
45
95
125
185
380
—
ppm/V
LVC
BSL
–5
±1
+5
Incremental
–10
±5
+10
%
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
VC Input Impedance
ZVC
500
—
—
k
VC Input Capacitance
CVC
—
50
—
pF
—
VDD/2
—
V
VDD
V
Nominal Control Voltage
Control Voltage Tuning Range
VCNOM
@ fO
VC
0
Notes:
1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 7.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
2
Rev. 1.0
Si596
Table 3. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
fO
LVDS/CML/LVPECL
10
—
810
CMOS
10
—
160
TA = –40 to +85 ºC
–20
–50
—
—
+20
+50
ppm
Nominal Frequency1,2,3
Temperature Stability1,4
Units
MHz
Absolute Pull Range1,4
APR
±10
—
±370
ppm
Power up Time5
tOSC
—
—
10
ms
Settling Time After FS Change
TFRQ
—
—
10
ms
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number.
3. Nominal output frequency set by VCNOM = VDD/2.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to fO.
Table 4. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
LVDS Output Option
1
2
Symbol
Test Condition
Min
Typ
Max
Units
VO
mid-level
VDD – 1.42
—
VDD – 1.25
V
VOD
swing (diff)
1.1
—
1.9
VPP
VSE
swing (single-ended)
0.55
—
0.95
VPP
VO
mid-level
1.125
1.20
1.275
V
VOD
swing (diff)
0.5
0.7
0.9
VPP
2.5/3.3 V option mid-level
—
VDD – 1.30
—
1.8 V option mid-level
—
VDD – 0.36
—
2.5/3.3 V option swing (diff)
1.10
1.50
1.90
1.8 V option swing (diff)
0.35
0.425
0.50
VOH
0.8 x VDD
—
VDD
VOL
—
—
0.4
LVPECL/LVDS/CML
—
—
350
ps
CMOS with CL = 15 pF
—
2
—
ns
45
—
55
%
VO
CML Output Option2
VOD
CMOS Output Option3
Rise/Fall time (20/80%)
Symmetry (duty cycle)
tR, tF
SYM
LVPECL:
LVDS:
CMOS:
VDD – 1.3 V (diff)
1.25 V (diff)
VDD/2
V
VPP
V
Notes:
1. 50  to VDD – 2.0 V.
2. Rterm = 100  (differential).
3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V.
Rev. 1.0
3
Si5 96
Table 5. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)1,2
for FOUT of 50 MHz < FOUT
810 MHz
Symbol
J
Test Condition
Min
Typ
Max
Kv = 45 ppm/V
12 kHz to 20 MHz
—
0.5
—
Kv = 95 ppm/V
12 kHz to 20 MHz
—
0.5
—
Kv = 125 ppm/V
12 kHz to 20 MHz
—
0.5
—
Kv = 185 ppm/V
12 kHz to 20 MHz
—
0.5
—
Kv = 380 ppm/V
12 kHz to 20 MHz
—
0.7
—
Units
ps
Notes:
1. Refer to AN256 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
Table 6. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
Test Condition
Min
Typ
Max
Units
JPER
RMS
—
3
—
ps
Peak-to-Peak
—
35
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 7. CLK± Output Phase Noise (Typical)
Offset Frequency
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
4
74.25 MHz
148.5 MHz
155.52 MHz
185 ppm/V
185 ppm/V
95 ppm/V
LVPECL
LVPECL
LVPECL
–77
–101
–121
–134
–149
–151
–150
–68
–95
–116
–128
–144
–147
–148
–77
–101
–119
–127
–144
–147
–148
Rev. 1.0
Units
dBc/Hz
Si596
Table 8. Environmental Compliance and Package Information
Parameter
Conditions/Test Method
Mechanical Shock
MIL-STD-883, Method 2002
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 2003
Gross and Fine Leak
MIL-STD-883, Method 1014
Resistance to Solder Heat
MIL-STD-883, Method 2036
Contact Pads
Gold over Nickel
Table 9. Thermal Characteristics
(Typical values TA = 25 ºC, VDD = 3.3 V)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Thermal Resistance Junction to Ambient
JA
Still Air
—
84.6
—
°C/W
Thermal Resistance Junction to Case
JC
Still Air
—
38.8
—
°C/W
Ambient Temperature
TA
–40
—
85
°C
Junction Temperature
TJ
—
—
125
°C
Table 10. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Units
TAMAX
85
ºC
VDD
–0.5 to +3.8
V
Input Voltage
VI
–0.5 to VDD + 0.3
Storage Temperature
TS
–55 to +125
ºC
ESD
2500
V
TPEAK
260
ºC
tP
20–40
seconds
Maximum Operating Temperature
Supply Voltage
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)
2
Soldering Temperature Time @ TPEAK (Pb-free profile)2
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from
www.silabs.com/VCXO for further information, including soldering profiles.
Rev. 1.0
5
Si5 96
2. Pin Descriptions
(Top View)
VC
1
6
VDD
FS
2
5
CLK–
GND
3
4
CLK+
Table 11. Si596 Pin Descriptions
Pin
Name
Type
Function
1
VC
Analog Input
2
FS*
Input
3
GND
Ground
Electrical and Case Ground
4
CLK+
Output
Oscillator Output
5
CLK–
(N/C for CMOS)
Output
Complementary Output
(N/C for CMOS, do not make external connection)
6
VDD
Power
Power Supply Voltage
Control Voltage
Frequency Select:
0 = first frequency selected
1 = second frequency selected
*Note: FS pin includes a 17 k resistor to VDD. When the FS is left floating, the pullup causes FS = 1 = second frequency
selected. See 3. "Ordering Information" on page 7 for details on frequency select ordering options.
6
Rev. 1.0
Si596
3. Ordering Information
The Si596 supports a variety of options including frequency, temperature stability, tuning slope, output format, and
VDD. Specific device configurations are programmed into the Si596 at time of shipment. Configurations are
specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool
and for further ordering instructions. The Si596 VCXO series is supplied in an industry-standard, RoHS compliant,
lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
596
X
X
D
XXXXXX
G
R
R = Tape & Reel
Blank = Trays
596 Dual VCXO
Product Family
Operating Temp Range (°C)
G
–40 to +85 °C
Device Revision Letter
6-digit Frequency Designator Code
Two unique frequencies can be specified within the following
frequency range: 10 to 810 MHz. A six digit code will be assigned for
the specified combination of frequencies. Codes > 000100 refer to
dual XOs programmed with the lower frequency value selected when
FS = 0, and the higher value when FS = 1. Six digit codes < 000100
refer to dual XOs programmed with the higher frequency value
selected when FS = 0, and the lower value when FS = 1.
1st Option Code
A
B
C
D
E
F
G
H
J
K
VDD
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
1.8
1.8
Output Format
LVPECL
LVDS
CMOS
CML
LVPECL
LVDS
CMOS
CML
CMOS
CML
Note:
CMOS available to 160 MHz.
2nd Option Code
Code
A
B
C
D
E
F
G
H
Temperature
Stability
± ppm (max)
20
20
50
20
20
50
50
20
Tuning Slope
Kv
ppm/V (typ)
380
185
185
125
95
125
95
45
3.3 V
370
160
130
100
65
70
35
15
Minimum APR
(±ppm) for VDD @
2.5 V
1.8 V
275
200
110
80
80
50
75
40
50
25
45
10
20
N/A
N/A
N/A
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Lower Kv options minimize noise
coupling and jitter in real-world PLL designs. See AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±100 ppm is able to lock to a clock with a ±100 ppm stability over 15 years over
all operating conditions.
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.
4. Minimum APR values noted above include worst case values for all parameters.
Figure 1. Part Number Convention
Rev. 1.0
7
Si5 96
4. Outline Diagram and Suggested Pad Layout
Figure 2 illustrates the package details for the Si596. Table 12 lists the values for the dimensions shown in the
illustration.
Figure 2. Si596 Outline Diagram
Table 12. Package Diagram Dimensions (mm)
Dimension
A
b
c
D
D1
e
E
E1
H
L
p
R
aaa
bbb
ccc
ddd
eee
8
Min
1.50
1.30
0.50
4.30
6.10
0.55
1.17
1.80
Nom
1.65
1.40
0.60
5.00 BSC
4.40
2.54 BSC.
7.00 BSC.
6.20
0.65
1.27
—
0.70 REF
0.15
0.15
0.10
0.10
0.50
Rev. 1.0
Max
1.80
1.50
0.70
4.50
6.30
0.75
1.37
2.60
Si596
5. Si5xx Mark Specification
Figure 3 illustrates the mark specification for the Si596. Table 13 lists the line information.
Figure 3. Mark Specification
Table 13. Si596 Top Mark Description
Line
Position
1
1–10
“SiLabs”+ Part Family Number, 596 (First 3 characters in part number)
2
1–10
Si596: Option1+Option2+Freq(6)+Temp
3
Description
Trace Code
Position 1
Pin 1 orientation mark (dot)
Position 2
Product Revision (D)
Position 3–6
Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Position 7
Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9)
Position 8–9
Calendar Work Week number (1–53), to be assigned by assembly site
Position 10
“+” to indicate Pb-Free and RoHS-compliant
Rev. 1.0
9
Si5 96
6. 6-Pin PCB Land Pattern
Figure 4 illustrates the 6-pin PCB land pattern for the Si596. Table 14 lists the values for the dimensions shown in
the illustration.
Figure 4. Si596 PCB Land Pattern
Table 14. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
5.08 REF
e
2.54 BSC
E2
4.15 REF
GD
0.84
—
GE
2.00
—
VD
8.20 REF
VE
7.30 REF
X
1.70 TYP
Y
2.15 REF
ZD
—
6.78
ZE
—
6.30
Notes:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.
2. Land pattern design based on IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition (MMC).
4. Controlling dimension is in millimeters (mm).
10
Rev. 1.0
Si596
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Revision 1.0
June 10, 2016
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Rev. 1.0
11
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