SL2309 Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB) Key Features • • • • • • • • • • • • Description 10 to 140 MHz operating frequency range Low output clock jitter: 140 ps-max cycle-to-cycle jitter Low output-to-output skew: 150 ps-max Low product-to-product skew: 400 ps-max 3.3 V power supply range Low power dissipation: 26 mA-max at 66 MHz 44 mA –max at 133 MHz One input drives 9 outputs organized as 4+4+1 Select mode to bypass PLL or tri-state outputs SpreadThru™ PLL that allows use of SSCG Standard and High-Drive options Available in 16-pin SOIC and TSSOP packages Available in Commercial and Industrial grades The SL2309 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL2309 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tristated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Fanout Buffer (NZDB). The high-drive (-1H) version operates up to 140MHz and low drive (-1) version operates up to 100MHz at 3.3V. Applications • • • • • • Benefits Printers and MFPs Digital Copiers PCs and Work Stations DTV Routers, Switchers and Servers Digital Embeded Systems • • • • Up to nine (9) distribution of input clock Standard and High-Drive levels to control impedance level, frequency range and EMI Low power dissipation, jitter and skew Low cost Block Diagram Low Power and Low Jitter PLL MUX CLKOUT CLKIN CLKA1 CLKA2 CLKA3 CLKA4 S2 Input Selection Decoding Logic S1 CLKB1 CLKB2 CLKB3 2 2 CLKB4 VDD GND Rev 1.3, July 31, 2007 400 West Cesar Chavez, Austin, TX 78701 Page 1 of 12 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL2309 Pin Configuration CLKIN CLKA1 1 16 CLKOUT 2 15 CLKA2 3 14 CLKA4 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 11 CLKB2 7 10 CLKB4 CLKB3 S2 8 9 S1 16-Pin SOIC and TSSOP Pin Description Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input 2 CLKA1 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 3 CLKA2 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 4 VDD Power 3.3V Power Supply. 5 GND Power Power Ground. 6 CLKB1 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 7 CLKB2 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 8 S2 Input Select Input, select pin S2. Weak pull-up (250kΩ). 9 S1 Input Select Input, select pin S1. Weak pull-up (250kΩ). 10 CLKB3 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 11 CLKB4 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 12 GND Power Power Ground. 13 VDD Power 3.3V Power Supply. 14 CLKA3 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 15 CLKA4 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 16 CLKOUT Output Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250kΩ). Rev 1.3, July 31, 2007 Reference Frequency Clock Input. Weak pull-down (250kΩ). Page 2 of 12 SL2309 General Description Select Input Control (S2, S1) The SL2309 is a low skew, low jitter Zero Delay Buffer with very low operating current. The SL2309 provides two (2) input select control pins called S1 (Pin-9) and S2 (Pin-8). This feature enables users to select various states of output clock banks-A and bank-B, output source and PLL shutdown features as shown in the Table 2. The product includes an on-chip high performance PLL that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. In addition to CLKOUT that is used for internal PLL feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). Input and Output Frequency Range The input and output frequency range is the same. But, it depends on the drive and output load (CL) levels as given in the below Table 1. Drive CL(pF) Min(MHz) Max(MHz) HIGH 15 10 140 HIGH 30 10 100 LOW 15 10 100 LOW 30 10 66 Table 1. Input/Output Frequency Range If the input clock is DC (GND to VDD) or floating, this is detected by an input frequency detection circuitry and all nine (9) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12μA-max supply current. In PLL by-pass mode (S2=1 and S1=0), the detection circuit is disabled and input frequency range is 10 to 100MHz for standard (-1) drive and 10 to 140MHz for high (-1H) drive. SpreadThru™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL2309 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency Rev 1.3, July 31, 2007 The S1 (Pin-9) and S2 (Pin-8) inputs include 250 kΩ weak pull-up resistors to VDD. PLL Bypass Mode If the S1 and S2 pins are logic Low(0) and High(1) respectively, the on-chip PLL is shutdown and bypassed, and all the nine output clocks; bank A, bank B and CLKOUT clocks are driven by directly from the reference input clock. In this operation mode SL2309 works like a non-ZDB fanout buffer. In this operation mode the input power-down detection circuit is disabled and outputs follow the input clock from DC to rated frequencies based on drive levels and load specifications. High and Low-Drive Product Options The SL2309 is offered with High Drive “-1H” and Standard Drive “-1” options. These drive options enable the users to control load levels, frequency range and EMI. Refer to the switching electrical tables for the details. Skew and Zero Delay All outputs should drive the similar load to achieve the output-to-output skew and input-to-output specifications given in the switching electrical tables. However, Zero Delay between input and outputs can be adjusted by changing the loading at CLKOUT relative to the banks A and B clocks since CLKOUT is the feedback to the PLL. Power Supply Range (VDD) The SL2309 is designed to operate at VDD=3.3V (+/10%). An internal on-chip voltage regulator is used to provide PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. SL23EP09 Refer to SL23EP09 for extended frequency operation from 10 to 220MHz and 2.5V to 3.3V power supply operation range. Page 3 of 12 SL2309 S2 S1 Clock A1-A4 Clock B1-4 CLKOUT Output Source PLL Status 0 0 Tri-state Tri-state Driven PLL On 0 1 Driven Tri-state Driven PLL On 1 0 Driven Driven Driven Reference Off 1 1 Driven Driven Driven PLL On Table 2. Select Input Decoding CLKIN Input to CLKA or CLKB Delay (ps) 1500 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: FBK Load – CLKA or CLKB Load (pF) Figure 1. CLKIN Input to CLK A and B Delay (In terms of load difference between CLKOUT and CLK A and B) Rev 1.3, July 31, 2007 Page 4 of 12 SL2309 Absolute Maximum Ratings Description Condition Min Max Unit Supply voltage, VDD – 0.5 4.6 V All Inputs and Outputs – 0.5 VDD+0.5 V Ambient Operating Temperature In operation, C-Grade 0 70 °C Ambient Operating Temperature In operation, I-Grade – 40 85 °C Storage Temperature No power is applied – 65 150 °C Junction Temperature In operation, power is applied – 125 °C – 260 °C Soldering Temperature ESD Rating (Human Body Model) JEDEC22-A114D -4,000 4,000 V ESD Rating (Charge Device Model) JEDEC22-C101C -1,500 1,500 V ESD Rating (Machine Model) JEDEC22-A115D -250 250 V Latch-up 125°C -200 200 mA Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition VDD 3.3V Supply Voltage 3.3V+/-10% TA Operating Temperature(Ambient) Commercial Industrial CLOAD Load Capacitance 10 to 140 MHz, -1H high drive All active PLL modes 10 to 100 MHz, -1H high drive All active PLL modes 10 to 100MHz, -1 standard drive All active PLL modes 10 to 66MHz, -1 standard drive All active PLL modes Min Max Unit 3.0 3.6 V 0 70 °C – 40 85 °C – 15 pF – 30 pF – 15 pF – 30 pF CIN Input Capacitance S1, S2 and CLKIN pins tpu Power-up Time Power-up time for all VDDs to reach minimum VDD voltage (VDD=3.0V). CLBW Closed-loop bandwidth 3.3V, (typical) 1.2 MHz ZOUT Output Impedance 3.3V, (typical), -1H high drive 22 Ω 3.3V, (typical), -1 standard drive 32 Ω Rev 1.3, July 31, 2007 – 7 pF 0.05 100 ms Page 5 of 12 SL2309 DC Electrical Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition Min Max Unit 3.0 3.6 V VDD Supply Voltage VIL Input LOW Voltage CLKIN, S2 and S1 Pins – 0.8 V VIH Input HIGH Voltage CLKIN, S2 and S1 pins 2.0 VDD+0.3 V IIL Input LOW Current CLKIN, S2 and S1 Pins, 0 < VIN < 0.8V – 25 µA IIH Input HIGH Current CLKIN, S2 and S1 Pins, VIN = VDD – 50 µA Output LOW Voltage (All outputs) IOL = 8 mA (standard drive) – 0.4 V VOL IOL = 12 mA (high drive) – 0.4 V Output HIGH Voltage (All outputs) IOH = –8 mA (standard drive) 2.4 – V IOH = –12 mA (high drive) 2.4 – V 12 µA 25 µA – 14 mA – 26 mA – 36 mA – 44 mA 175 325 kΩ VOH IDDPD IDD1 IDD2 IDD3 IDD4 RPU/D Power Down Supply Current C-Grade CLKIN=0 to VDD or floating (input will be pulled-down by 250kΩ I-Grade weak pull-down on-chip resistor) All Outputs CL=0, 33MHz CLKIN Power Supply Current S2=S1=1 (High) All Outputs CL=0, 66MHz CLKIN Power Supply Current S2=S1=1 (High) All Outputs CL=0, 100MHz CLKIN Power Supply Current S2=S1=1 (High) All Outputs CL=0, 133MHz CLKIN Power Supply Current S2=S1=1 (High) Pins-1/2/3/6/7/8/9/10/11/14/15/16 Pull-up and Pull-down Resistors 250kΩ-typ Rev 1.3, July 31, 2007 – – Page 6 of 12 SL2309 Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol FMAX1 FMAX2 INDC Description Condition Maximum Frequency (Input=Output ) All Active PLL Modes Maximum Frequency (Input=Output ) PLL Bypass Mode (S2=1 and S1=0) [1] [1] Input Duty Cycle [2] OUTDC1 Output Duty Cycle [2] OUTDC2 Output Duty Cycle [2] tr/f Rise, Fall Time (3.3V) (Measured at: 0.8 to 2.0V) [2] Min Typ Max High drive (-1H). All outputs CL=15pF 10 – 140 MHz High drive (-1H), All outputs CL=30pF 10 – 100 MHz Standard drive, (-1), All outputs CL=15pf 10 – 100 MHz Standard drive, (-1), All outputs CL=30pf 10 – 66 MHz High drive (-1H). All outputs CL=15pF 0 – 140 MHz High drive (-1H), All outputs CL=30pF 0 – 100 MHz Standard drive, (-1), All outputs CL=15pf 0 – 100 MHz Standard drive, (-1), All outputs CL=30pf 0 – 66 MHz Measured at 1.4V, Fout=66MHz, CL=15pF 30 50 70 % Measured at 1.4V, Fout=66MHz, CL=15pF 40 50 60 % Measured at 1.4V, Fout=66MHz, CL=15pF 40 50 60 % High drive (-1H), CL=15pF – – 1.5 ns High drive (-1H), CL=30pF – – 1.8 ns Standard drive (-1), CL=15pF – – 2.2 ns Standard drive (-1), CL=30pF – – 2.5 ns All outputs CL=0 or equally loaded, -1 or -1H drives – 70 150 ps – 180 400 ps 1.5 5 8.7 ns –220 – 220 ps Time from 90% of VDD to valid clocks on all the output clocks – – 1.0 ms Fin=Fout=66 MHz, <CL=15pF, -1H drive – 70 140 ps Fin=Fout=66 MHz, <CL=15pF, -1 drive – 75 150 ps Fin=Fout=66 MHz, <CL=30pF, -1H drive – 80 160 ps Fin=Fout=66 MHz, <CL=30pF, -1 drive – 85 170 ps t1 Output-to-Output Skew (Measured at VDD/2) t2 Product-to-Product Skew (Measured at VDD/2) All outputs CL=0 or equally loaded, -1 or -1H drives t3 Delay Time, CLKIN Rising Edge to CLKOUT Rising [2] Edge (Measured at VDD/2) PLL Bypass mode Only when S2=1 and S1=0 [2] [2] tPLOCK PLL Lock Time CCJ Cycle-to-cycle Jitter [2] PLL enabled All active PLL modes Unit Notes: 1. For the given maximum loading conditions. See CL in Operating Conditions Table. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. Rev 1.3, July 31, 2007 Page 7 of 12 SL2309 External Components & Design Considerations Typical Application Schematic 1 CLKIN 16 CLKOUT CL 2 4 VDD 0.1μF CLKA1 CL SL2309 13 VDD 0.1μF S1 11 CLKB4 9 CL VDD S2 8 5 12 GND GND Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the capacitor s on the component side of the PCB as close to the VDD pins as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and the load is over 1 ½ inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination resistors as close to the clock outputs as possible. Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay” between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL, and sees an additional 2 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and CLKIN. For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same. Rev 1.3, July 31, 2007 Page 8 of 12 SL2309 Switching Waveforms VDD/2 OUTPUT VDD/2 OUTPUT t1 Figure 2. Output to Output Skew VDD/2 INPUT VDD/2 CLKOUT t2 Figure 3. Input-to-Output Skew VDD/2 Any Output Part 1 or 2 VDD/2 Any Output Part 2 or 1 t3 Figure 4. Part-to-Part Skew Rev 1.3, July 31, 2007 Page 9 of 12 SL2309 Package Drawing and Dimensions 16-Lead TSSOP (4.4-mm) 9 16 6.250(0.246) 6.500(0.256) 4.300(0.169) 4.500(0.177) Dimensions are in milimeters(inches). Top line: (MIN) and Bottom line: (Max) Pin-1 ID 1 8 4.900(0.193) 5.100(0.200) 1.100(0.043) MAX 0.650(0.025) BSC 0.050(0.002) 0.150(0.006) 0.850(0.033) 0.950(0.037) 0.076(0.003) 0.190(0.007) 0.300(0.012) 0.650(0.025) BSC 0.090(0.003) 0.200(0.008) Gauge Plane 0 to 8° Seating Plane 0.500(0.020) 0.700(0.027) Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Rev 1.3, July 31, 2007 Symbol Condition Min Typ Max Unit θ JA Still air - 80 - °C/W θ JA 1m/s air flow - 70 - °C/W θ JA 3m/s air flow - 68 - °C/W θ JC Independent of air flow - 36 - °C/W Page 10 of 12 SL2309 Package Drawing and Dimensions (Cont.) 16-Lead SOIC (150-Mil) 9 16 Dimensions are in inches(milimeters). Top line: (MIN) and Bottom line: (Max) 0.150(3.810) 0.157(3.987 Pin-1 ID 0.230(5.842) 0.244(6.197) 8 1 0.386(9.804) 0.393(9.982) 0.010(0.2540) X 45° 0.016(0.406) 0.0075(0.190) 0.0098(0.249) 0.061(1.549) 0.068(1.727) 0.004(0.102) 0.050(1.270) BSC 0.004(0.102) 0.0098(0.249) Seating plane 0.016(0.406) 0.035(0.889) 0° to 8° 0.0138(0.350) 0.0192(0.487) Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Rev 1.3, July 31, 2007 Symbol Condition Min Typ Max Unit θ JA Still air - 120 - °C/W θ JA 1m/s air flow - 115 - °C/W θ JA 3m/s air flow - 105 - °C/W θ JC Independent of air flow - 60 - °C/W Page 11 of 12 SL2309 Ordering Information[3] Ordering Number Marking Shipping Package Package Temperature SL2309ZC-1 SL2309ZC-1T SL2309ZC-1 Tube 16-pin TSSOP 0 to 70°C SL2309ZC-1 Tape and Reel 16-pin TSSOP 0 to 70°C SL2309ZC-1H SL2309ZC-1H Tube 16-pin TSSOP 0 to 70°C SL2309ZC-1HT SL2309ZC-1H Tape and Reel 16-pin TSSOP 0 to 70°C SL2309ZI-1 SL2309ZI-1 Tube 16-pin TSSOP -40 to 85°C SL2309ZI-1T SL2309ZI-1 Tape and Reel 16-pin TSSOP -40 to 85°C SL2309ZI-1H SL2309ZI-1H Tube 16-pin TSSOP -40 to 85°C SL2309ZI-1HT SL2309ZI-1H Tape and Reel 16-pin TSSOP -40 to 85°C SL2309SC-1 SL2309SC-1 Tube 16-pin SOIC 0 to 70°C SL2309SC-1T SL2309SC-1 Tape and Reel 16-pin SOIC 0 to 70°C SL2309SC-1H SL2309SC-1H Tube 16-pin SOIC 0 to 70°C SL2309SC-1HT SL2309SC-1H Tape and Reel 16-pin SOIC 0 to 70°C SL2309SI-1 SL2309SI-1 Tube 16-pin SOIC -40 to 85°C SL2309SI-1T SL2309SI-1 Tape and Reel 16-pin SOIC -40 to 85°C SL2309SI-1H SL2309SI-1H Tube 16-pin SOIC -40 to 85°C SL2309SI-1HT SL2309SI-1H Tape and Reel 16-pin SOIC -40 to 85°C Notes: 3. The SL2309 products are RoHS compliant. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Rev 1.3, July 31, 2007 Page 12 of 12