SL23EP08

SL23EP08
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
•
•
•
•
•
•
•
•
•
•
•
•
Description
10 to 220 MHz operating frequency range
Low output clock skew: 45ps-typ
Low output clock jitter:
 25 ps-typ cycle-to-cycle jitter
 15 ps-typ period jitter
Low part-to-part output skew: 90 ps-typ
Wide 2.5 V to 3.3 V power supply range
Low power dissipation:
 20 mA-max at 66 MHz and VDD=3.3 V
 18 mA-max at 66 MHz and VDD=2.5V
One input drives 8 outputs
Multiple configurations and drive options
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
The SL23EP08 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9) clock
outputs from one (1) reference input clock, for high speed
clock distribution applications.
The product has an on-chip PLL and a feedback pin (FBK)
which can be used to obtain feedback from any one of the
output clocks. The SL23EP08 has two (2) clock driver banks
each with four (4) clock outputs. These outputs are controlled
by two (2) select input pins S1 and S2. When only four (4)
outputs are needed, four (4) bank-B output clock buffers can
be tri-stated to reduce power dissipation and jitter. The select
inputs can also be used to tri-state both banks A and B or
drive them directly from the input bypassing the PLL and
making the product behave like a Non-Zero Delay Buffer
(NZDB). The product also offers various 1X, 2X and 4X
frequency options at the output clocks. Refer to the “Product
Configuration Table” for the details.
The high-drive version operates up to 220MHz and 200MHz at
3.3V and 2.5V power supplies respectively.
Applications
•
•
•
•
•
Benefits
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Datacom and Telecom
High-SpeedDigital Embeded Systems
•
•
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Up to eight (8) distribution of input clock
Standard and High-Dirive levels to control impedance
level, frequency range and EMI
Low power dissipation, jitter and skew
Low cost
Block Diagram
/2
CLKIN
(Divider for -3 and -4 only)
Low Power and
Low Jitter
/2
PLL
MUX
FBK
(Divider for -5H only)
CLKA1
CLKA2
CLKA3
CLKA4
S2
Input Selection
Decoding Logic
S1
/2
(Divider for -2 and -3 only)
CLKB1
CLKB2
CLKB3
2
2
CLKB4
VDD
GND
Rev 1.0, May 18, 2006
2400 West Cesar Chavez, Austin, TX 78701
Page 1 of 15
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL23EP08
Pin Configuration
CLKIN
1
16
FBK
CLKA1
2
15
CLKA2
3
14
CLKA4
CLKA3
VDD
4
13
VDD
GND
5
12
GND
CLKB1
6
11
CLKB2
7
10
CLKB4
CLKB3
S2
8
9
S1
16-Pin SOIC and TSSOP
Pin Description
Pin
Number
Pin Name
Pin Type
Pin Description
1
CLKIN
Input
2
CLKA1
Output
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
3
CLKA2
Output
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
3.3V or 2.5V Power Supply.
4
Reference Frequency Clock Input. 5V tolerant input. Weak pull-down (250kΩ).
VDD
Power
5
GND
Power
Power Ground.
6
CLKB1
Output
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
7
CLKB2
Output
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
8
S2
Input
Select Input, select pin S2. Weak pull-up (250kΩ).
S1
Input
Select Input, select pin S1. Weak pull-up (250kΩ).
9
10
CLKB3
Output
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
11
CLKB4
Output
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
12
GND
Power
Power Ground.
VDD
Power
3.3V or 2.5V Power Supply.
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
13
14
CLKA3
Output
15
CLKA4
Output
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
16
FBK
Output
PLL Feedback input.
Rev 1.0, May 18, 2006
Page 2 of 15
SL23EP08
General Description-
Select Input Control-
The SL23EP08 is a low skew, low jitter Zero Delay Buffer
with very low operating current.
The SL23EP08 provides two (2) input select control pins
called S1 and S2. This feature enables users to selects
various states of output clock banks-A and bank-B, output
source and PLL shutdown features as shown in the Table 2.
The product includes an on-chip high performance PLL that
locks into the input reference clock and produces nine (9)
output clock drivers tracking the input reference clock for
systems requiring clock distribution.
in addition to CLKOUT that is used for internal PLL
feedback, there are two (2) banks with four (4) outputs in
each bank, bringing the number of total available output
clocks to nine (9).
Input and output Frequency RangeThe input and output frequency range is the same. But, the
frequency range depends on VDD and drive levels as given
in the below Table 1.
VDD(V)
Drive
Min(MHz) Max(MHz)
3.3
HIGH
10
220
3.3
STD
10
167
2.5
HIGH
10
200
2.5
STD
10
133
The S1 (Pin-9) and S2 (Pin-8) inputs include 250 kΩ weak
pull-down resistors to GND.
PLL Bypass Mode
If the S1 and S2 pins are logic Low(0) and High(1)
respectively, the on-chip PLL is shutdown and bypassed,
and all the nine output clocks bank A, bank B and CLKOUT
clocks are driven by directly from the reference input clock.
In this operation mode SL23EP08 works like a non-ZDB
product.
High and Low-Drive Product Options The SL23EP08 is offered with High-Drive “-1H” and
Standard-Drive “-1” options. These drive options enable the
users to control load levels, frequency range and EMI
control. Refer to the AC electrical tables for the details.
Table 1. Input/Output Frequency Range
Skew and Zero Delay If the input clock frequency is less than 2 MHz or floating,
this is detected by an input frequency detection circuitry and
all eight (8) clock outputs are forced to Hi-Z. The PLL is
shutdown to save power. In this shutdown state, the product
draws less than 25 μA supply current.
All outputs should drive the similar load to achieve output-tooutput skew and input-to-output specifications given in the
AC electrical tables. However, Zero delay between input and
outputs can be adjusted by changing the loading of CLKOUT
relative to the banks A and B clocks since CLKOUT is the
feedback to the PLL.
SpreadThru™ FeatureIf a Spread Spectrum Clock (SSC) were to be used as an
input clock, the SL23EP08 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from its
reference input to the output clocks. The same spread
characteristics at the input are passed through the PLL and
drivers without any degradation in spread percent (%),
spread profile and modulation frequency
S2
S1
0
Power Supply Range (VDD)The SL23EP08 is designed to operate in a wide power
supply range from 2.3V (Min) to 3.3V (Max). An internal onchip voltage regulator is used to supply PLL constant power
supply of 1.8V, leading to a consistent and stable PLL
electrical performance in terms of skew, jitter and power
dissipation. Contact SLI for 1.8V power supply version ZDB
called SL23EPL08.
Clock A1-A4 Clock B1-B4 CLKOUT
0
0
1
1
0
1
1
Tri-state
Tri-state
Driven
Tri-state
Driven
[1]
Driven
Driven
[1]
Driven
Output Source
Driven
PLL
PLL Shutdown and
Bypass
Yes
Driven
PLL
No
Driven (4)
Reference
Yes
Driven
PLL
No
Table 2. Select Input Decoding
Rev 1.0, May 18, 2006
Page 3 of 15
SL23EP08
Device
SL23EP08-1
SL23EP08-1H
SL23EP08-2
SL23EP08-2
SL23EP08-3
SL23EP08-3
SL23EP08-4
SL23EP08-5H
Feedback From
Bank-A or Bank-B
Bank-A or Bank-B
Bank-A
Bank-B
Bank-A
Bank-B
Bank-A or Bank-B
Bank-A or Bank-B
Bank-A Frequency
Reference
Reference
Reference
2x Reference
2X Reference
4X Reference
2X Reference
Reference /2
Bank-B Frequency
Reference
Reference
Reference/2
Reference
[2]
Reference
2X Reference
2X Reference
Reference /2
Table 3. Available SL23EP08 Configurations
Notes:
1. Outputs are inverted on SL23EP08-2 and SL23EP08-3 in PLL bypass mode when S2=1 and S1=0.
2. Output phase is either 0° or 180° with respect to CLKIN input. If phase integrity is required, use the SL23EP08-2.
1500
1000
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
Output Load Difference: FBK Load – CLKA or CLKB Load (pF)
Figure 1. CLKIN Input to CLKA and CLKB Delay
Rev 1.0, May 18, 2006
Page 4 of 15
SL23EP08
Absolute Maximum Ratings
Description
Condition
Min.
Max.
Unit
Supply voltage, VDD
– 0.5
4.6
V
All Inputs and Outputs
– 0.5
VDD+0.5
V
Ambient Operating Temperature
In operation, C-Grade
0
70
°C
Ambient Operating Temperature
In operation, I-Grade
– 40
85
°C
Storage Temperature
No power is applied
– 65
150
°C
Junction Temperature
In operation, power is applied
–
125
°C
–
260
°C
2000
–
V
Soldering Temperature
ESD Rating (Human Body Model)
MIL-STD-883, Method 3015
Operating Conditions: Unless otherwise stated VDD=2.5V to 3.3V and for both C and I Grades
Symbol Description
Condition
Min.
Max.
Unit
VDD3.3
3.3V Supply Voltage
3.3V+/-10%
3.0
3.6
V
VDD2.5
2.5V Supply Voltage
2.5V+/-10%
2.3
2.7
V
TA
Operating Temperature(Ambient)
Commercial
0
70
°C
–40
85
°C
<100 MHz, 3.3V with Standard or High
drive
–
30
pF
<100 MHz, 2.5V with High drive
–
30
pF
<133.3 MHz, 3.3V with Standard or
High drive
–
22
pF
<133.3 MHz, 2.5V with High drive
–
22
pF
<133.3 MHz, 2.5V with Standard drive
–
15
pF
>133.3 MHz, 3.3V with Standard or
High drive
–
15
pF
>133.3 MHz, 2.5V with High drive
–
15
pF
–
5
pF
Industrial
CLOAD
Load Capacitance
CIN
Input Capacitance
S1, S2 and CLKIN pins
CLBW
Closed-loop bandwidth
3.3V, (typical)
1.2
MHz
2.5V, (typical)
0.8
MHz
3.3V, (typical), High drive
29
Ω
3.3V, (typical), Standard drive
41
Ω
2.5V, (typical), High drive
37
Ω
2.5V, (typical), Standard drive
41
Ω
ZOUT
Output Impedance
Rev 1.0, May 18, 2006
Page 5 of 15
SL23EP08
DC Electrical Specifications (VDD=3.3V): Unless otherwise stated for both C and I Grades
Symbol
Condition
Min.
Max.
Description
Unit
2.970
3.630
V
Input LOW Voltage
–
0.8
V
VIH
Input HIGH Voltage
2.0
VDD+0.3
V
IIL
Input Leakage Current
0 < VIN < 0.8V
–
±10
µA
IIH
Input HIGH Current
VIN = VDD
–
100
µA
VOL
Output LOW Voltage
IOL = 8 mA (standard drive)
–
0.4
V
IOL = 12 mA (high drive)
–
0.4
V
IOH = –8 mA (standard drive)
2.4
–
V
IOH = –12 mA (high drive)
2.4
–
V
CLKIN = 0 MHz (C-Grade)
–
12
µA
CLKIN = 0 MHz (I-Grade)
–
25
µA
All Outputs CL=0, 66-MHz CLKIN
–
20
mA
VDD
Supply Voltage
VIL
VOH
IDDPD
IDD
Output HIGH Voltage
Power Down Supply Current
CLKIN<2MHz
Power Supply Current
DC Electrical Specifications (VDD=2.5V): Unless otherwise stated for both C and I Grades
Symbol
Condition
Min.
Max.
Description
Unit.
2.3
2.7
V
Input LOW Voltage
–
0.7
V
VIH
Input HIGH Voltage
1.7
VDD+ 0.3
V
IIL
Input Leakage Current
0<VIN < 0.8V
–
10
µA
IIH
Input HIGH Current
VIN = VDD
–
100
µA
VOL
Output LOW Voltage
IOL = 8 mA (standard drive)
–
0.5
V
IOL = 12 mA (high drive)
–
0.5
V
IOH = –8 mA (standard drive)
VDD – 0.6
–
V
IOH = –12 mA (high drive)
VDD – 0.6
–
V
VDD
Supply Voltage
VIL
VOH
IDDPD
IDD
Output HIGH Voltage
Power Down Supply Current
CLKIN<2MHz
Power Supply Current
Rev 1.0, May 18, 2006
CLKIN = 0 MHz (C-Grade)
–
12
µA
CLKIN = 0 MHz (I-Grade)
–
25
µA
All Outputs CL=0, 66-MHz CLKIN
–
18
Page 6 of 15
mA
SL23EP08
AC Electrical Specifications: VDD=3.3V+/-10% and 0°C to +70°C Operation (Commercial Grade)
Symbol Description
Condition
Min
Typ
Max
Unit
FOUT-1
Output Frequency
CL=30pf, All devices
10
-
160
MHz
FOUT-2
Output Frequency
CL=20pF, -1H and -5H versions
10
-
220
MHz
FOUT-2
Output Frequency
CL=15pF, -1,-2,-3 and -4 versions
10
-
200
MHz
DC-1
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=30pF, FOUT=66.6MHz and Measured
at VDD/2
40.0
60.0
%
DC-2
Duty Cycle, -1, -2, -3,-4,-1H
and -5H versions
CL=15pF, FOUT<66.6MHz and Measured
at VDD/2
45.0
55.0
%
DC-1
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=30pF, FOUT=120MHz and Measured
at VDD/2
TBD
TBD
%
DC-2
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=15pF, FOUT=120MHz and Measured
at VDD/2
TBD
TBD
%
tr/f-1
Rise and Fall Times. -1, -2, - Measured between 0.8V and 2.0V
3, and -4 versions
CL=30pF
-
1.6
ns
tr/f-2
Rise and Fall Times. -1, -2, - Measured between 0.8V and 2.0V
3, and -4 versions
CL=15pF
-
1.2
ns
tr/f-3
Rise and Fall Times. -1,1H
and -5H versions
Measured between 0.8V and 2.0V
CL=30pF
-
1.2
ns
tr/f-3
Rise and Fall Times. -1H and Measured between 0.8V and 2.0V
-5H versions
CL=15pF
-
1.0
ns
50.0
50.0
TBD
TBD
-
Output-to-Output on same
bank A or B. All versions
All outputs are equally loaded. Measured
at VDD/2
-
60
All outputs are equally loaded. Measured
at VDD/2
-
60
All outputs are equally loaded. Measured
at VDD/2
-
130
SKW-4
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Device-to-Device Skew.
All versions
All outputs are equally loaded. Measured
at VDD/2 and FBK pin
-
180
tCFD
CLKIN to FBK Rising Edge
Delay
All outputs are equally loaded. Measured
at VDD/2
-200
-
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
[2]
Edge
(Measured at VDD/2)
PLL Bypass mode
1.5
–
4.4
ns
PLL enabled @ 3.3V
–100
–
100
ps
PLL enabled @2.5V
–200
–
200
ps
Measured at VDD/2. Any output to any
output, 3.3V supply
–
–
±150
ps
Measured at VDD/2. Any output to any
output, 2.5V supply
–
–
±300
ps
Valid on all clock pins from VDD=2.97V
-
-
1.0
ms
SKW-1
SKW-2
SKW-3
t2
t3
tLOCK
[2]
Part-to-Part Skew
(Measured at VDD/2)
PLL Lock Time
Rev 1.0, May 18, 2006
150
ps
150
ps
300
ps
500
200
ps
ps
Page 7 of 15
SL23EP08
AC Electrical Specifications: VDD=3.3V+/-10% and -40°C to +85°C Operation (Industrial Grade)
Symbol Description
Condition
Min
Typ
Max
Unit
FOUT-1
Output Frequency
CL=30pf, All devices
10
-
160
MHz
FOUT-2
Output Frequency
CL=20pF, -1H and -5H versions
10
-
220
MHz
FOUT-2
Output Frequency
CL=15pF, -1,-2,-3 and -4 versions
10
-
200
MHz
DC-1
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=30pF, FOUT=66.6MHz and Measured
at VD/2
40.0
60.0
%
DC-2
Duty Cycle, -1, -2, -3,-4,-1H
and -5H versions
CL=15pF, FOUT<66.6MHz and Measured
at VDD/2
45.0
55.0
%
DC-1
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=30pF, FOUT=120MHz and Measured
at VDD/2
TBD
TBD
%
DC-2
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=15pF, FOUT=120MHz and Measured
at VDD/2
TBD
TBD
%
tr/f-1
Rise and Fall Times. -1, -2, - Measured between 0.8V and 2.0V
3, and -4 versions
CL=30pF
-
1.6
ns
tr/f-2
Rise and Fall Times. -1, -2, - Measured between 0.8V and 2.0V
3, and -4 versions
CL=15pF
-
1.2
ns
tr/f-3
Rise and Fall Times. -1,1H
and -5H versions
Measured between 0.8V and 2.0V
CL=30pF
-
1.2
ns
tr/f-3
Rise and Fall Times. -1H and Measured between 0.8V and 2.0V
-5H versions
CL=15pF
-
1.0
ns
50.0
50.0
TBD
TBD
-
Output-to-Output on same
bank A or B. All versions
All outputs are equally loaded. Measured
at VDD/2
-
60
All outputs are equally loaded. Measured
at VDD/2
-
60
All outputs are equally loaded. Measured
at VDD/2
-
130
SKW-4
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Device-to-Device Skew.
All versions
All outputs are equally loaded. Measured
at VDD/2 and FBK pin
-
180
tCFD
CLKIN to FBK Rising Edge
Delay
All outputs are equally loaded. Measured
at VDD/2
-200
-
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
[2]
Edge
(Measured at VDD/2)
PLL Bypass mode
1.5
–
4.4
ns
PLL enabled @ 3.3V
–100
–
100
ps
PLL enabled @2.5V
–200
–
200
ps
Measured at VDD/2. Any output to any
output, 3.3V supply
–
–
±150
ps
Measured at VDD/2. Any output to any
output, 2.5V supply
–
–
±300
ps
Valid on all clock pins from VDD=2.97V
-
-
1.0
ms
SKW-1
SKW-2
SKW-3
t2
t3
tLOCK
[2]
Part-to-Part Skew
(Measured at VDD/2)
PLL Lock Time
Rev 1.0, May 18, 2006
150
ps
150
ps
300
ps
500
200
ps
ps
Page 8 of 15
SL23EP08
AC Electrical Specifications: VDD=2.5V+/-10% and 0°C to +70°C Operation (Commercial Grade)
Symbol Description
Condition
Min
Typ
Max
Unit
FOUT-1
Output Frequency
CL=30pf, All devices
10
-
160
MHz
FOUT-2
Output Frequency
CL=20pF, -1H and -5H versions
10
-
220
MHz
FOUT-2
Output Frequency
CL=15pF, -1,-2,-3 and -4 versions
10
-
200
MHz
DC-1
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=30pF, FOUT=66.6MHz and Measured
at VDD/2
40.0
60.0
%
DC-2
Duty Cycle, -1, -2, -3,-4,-1H CL=15pF, FOUT<66.6MHz and Measured at
and -5H versions
VDD/2
45.0
55.0
%
DC-1
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=30pF, FOUT=120MHz and Measured
at VDD/2
TBD
TBD
%
DC-2
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=15pF, FOUT=120MHz and Measured
at VDD/2
TBD
TBD
%
tr/f-1
Rise and Fall Times. -1, -2, - Measured between 0.8V and 2.0V
3, and -4 versions
CL=30pF
-
1.6
ns
tr/f-2
Rise and Fall Times. -1, -2, - Measured between 0.8V and 2.0V
3, and -4 versions
CL=15pF
-
1.2
ns
tr/f-3
Rise and Fall Times. -1,1H
and -5H versions
Measured between 0.8V and 2.0V
CL=30pF
-
1.2
ns
tr/f-3
Rise and Fall Times. -1H and Measured between 0.8V and 2.0V
-5H versions
CL=15pF
-
1.0
ns
50.0
50.0
TBD
TBD
-
Output-to-Output on same
bank A or B. All versions
All outputs are equally loaded. Measured
at VDD/2
-
60
All outputs are equally loaded. Measured
at VDD/2
-
60
All outputs are equally loaded. Measured
at VDD/2
-
130
SKW-4
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Device-to-Device Skew.
All versions
All outputs are equally loaded. Measured
at VDD/2 and FBK pin
-
180
tCFD
CLKIN to FBK Rising Edge
Delay
All outputs are equally loaded. Measured
at VDD/2
-200
-
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
[2]
Edge
(Measured at VDD/2)
PLL Bypass mode
1.5
–
4.4
ns
PLL enabled @ 3.3V
–100
–
100
ps
PLL enabled @2.5V
–200
–
200
ps
Measured at VDD/2. Any output to any
output, 3.3V supply
–
–
±150
ps
Measured at VDD/2. Any output to any
output, 2.5V supply
–
–
±300
ps
Valid on all clock pins from VDD=2.97V
-
-
1.0
ms
SKW-1
SKW-2
SKW-3
t2
t3
tLOCK
[2]
Part-to-Part Skew
(Measured at VDD/2)
PLL Lock Time
Rev 1.0, May 18, 2006
150
ps
150
ps
300
ps
500
200
ps
ps
Page 9 of 15
SL23EP08
AC Electrical Specifications: VDD=2.5V+/-10% and -40°C to +85°C Operation (Industrial Grade)
Symbol Description
Condition
Min
Typ
Max
Unit
FOUT-1
Output Frequency
CL=30pf, All devices
10
-
160
MHz
FOUT-2
Output Frequency
CL=20pF, -1H and -5H versions
10
-
220
MHz
FOUT-2
Output Frequency
CL=15pF, -1,-2,-3 and -4 versions
10
-
200
MHz
DC-1
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=30pF, FOUT=66.6MHz and Measured
at VDD/2
40.0
60.0
%
DC-2
Duty Cycle, -1, -2, -3,-4,-1H
and -5H versions
CL=15pF, FOUT<66.6MHz and Measured
at VDD/2
45.0
55.0
%
DC-1
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=30pF, FOUT=120MHz and Measured
at VDD/2
TBD
TBD
%
DC-2
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=15pF, FOUT=120MHz and Measured
at VDD/2
TBD
TBD
%
tr/f-1
Rise and Fall Times. -1, -2, - Measured between 0.8V and 2.0V
3, and -4 versions
CL=30pF
-
1.6
ns
tr/f-2
Rise and Fall Times. -1, -2, - Measured between 0.8V and 2.0V
3, and -4 versions
CL=15pF
-
1.2
ns
tr/f-3
Rise and Fall Times. -1,1H
and -5H versions
Measured between 0.8V and 2.0V
CL=30pF
-
1.2
ns
tr/f-3
Rise and Fall Times. -1H and Measured between 0.8V and 2.0V
-5H versions
CL=15pF
-
1.0
ns
50.0
50.0
TBD
TBD
-
Output-to-Output on same
bank A or B. All versions
All outputs are equally loaded. Measured
at VDD/2
-
60
All outputs are equally loaded. Measured
at VDD/2
-
60
All outputs are equally loaded. Measured
at VDD/2
-
130
SKW-4
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Device-to-Device Skew.
All versions
All outputs are equally loaded. Measured
at VDD/2
-
180
tCFD
CLKIN to FBK Rising Edge
Delay
All outputs are equally loaded. Measured
at VDD/2
-200
-
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
[2]
Edge
(Measured at VDD/2)
PLL Bypass mode
1.5
–
4.4
ns
PLL enabled @ 3.3V
–100
–
100
ps
PLL enabled @2.5V
–200
–
200
ps
Part-to-Part Skew
(Measured at VDD/2)
Measured at VDD/2. Any output to any
output, 3.3V supply
–
–
±150
ps
Measured at VDD/2. Any output to any
output, 2.5V supply
–
–
±300
ps
Valid on all clock pins from VDD=2.97V
-
-
1.0
ms
SKW-1
SKW-2
SKW-3
t2
t3
tLOCK
PLL Lock Time
Rev 1.0, May 18, 2006
150
ps
150
ps
300
ps
500
200
ps
ps
Page 10 of 15
SL23EP08
External Components & Design Considerations
Typical Application Schematic
1
CLKIN
16
FBK
CL-4pF
2
4
VDD
0.1μF
CLKA1
CL
SL23EP08
13
VDD
3
CLKA2
11
CLKB4
0.1μF
S1
9
VDD
S2
8
5
12
GND
CL
GND
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the capacitor on
the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via
should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and
the load is over 1 ½ inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination
resistors as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay”
between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL, and
sees an additional 4 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the load
at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the
CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and CLKIN.
For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.
Rev 1.0, May 18, 2006
Page 11 of 15
SL23EP08
Switching Waveforms
VDD/2
OUTPUT
VDD/2
OUTPUT
t1
Figure 2. Output to Output Skew
VDD/2
INPUT
VDD/2
CLKOUT
t2
Figure 3. Input to Output Skew
VDD/2
Any Output
Part 1 or 2
VDD/2
Any Output
Part 2 or 1
t3
Figure 4. Part-to-Part Skew
Rev 1.0, May 18, 2006
Page 12 of 15
SL23EP08
Package Drawing and Dimensions
16-Lead TSSOP (4.4mm)
9
16
6.250(0.246)
6.500(0.256)
4.300(0.169)
4.500(0.177)
Dimensions are in milimeters(inches).
Top line: (MIN) and Bottom line: (Max)
Pin-1 ID
1
8
2.900(0.114)
3.100(0.122)
1.100(0.043) MAX
0.190(0.007)
0.300(0.012)
Thermal Characteristics
Parameter
Thermal Resistance
Junction to Ambient
Thermal Resistance
Junction to Case
Rev 1.0, May 18, 2006
0.650(0.025)
BSC
0.050(0.002)
0.150(0.006)
0.850(0.033)
0.950(0.037)
0.076(0.003)
0.650(0.025)
BSC
Symbol
θ JA
0.090(0.003)
0.200(0.008)
Gauge
Plane
Seating Plane
Condition
0 to 8°
0.500(0.020)
0.700(0.027)
Min
Typ
Max
Unit
Still air
-
80
-
°C/W
θ JA
1m/s air flow
-
70
-
°C/W
θ JA
3m/s air flow
-
68
-
°C/W
θ JC
Independent of air flow
-
36
-
°C/W
Page 13 of 15
SL23EP08
Package Drawing and Dimensions (Cont.)
16-Lead SOIC (150 Mil)
16
9
Dimensions are in milimeters(inches).
Top line: (MIN) and Bottom line: (Max)
0.150(3.810)
0.157(3.987
Pin-1 ID
0.230(5.842)
0.244(6.197)
1
8
0.189(4.800)
0.196(4.978)
0.010(0.2540)
X 45°
0.016(0.406)
0.0075(0.190)
0.0098(0.249)
0.061(1.549)
0.068(1.727)
0.004(0.102)
0.050(1.270)
BSC
0.004(0.102)
0.0098(0.249)
Seating plane
0.016(0.406)
0.035(0.889)
0° to 8°
0.0138(0.350)
0.0192(0.487)
Thermal Characteristics
Parameter
Thermal Resistance
Junction to Ambient
Thermal Resistance
Junction to Case
Rev 1.0, May 18, 2006
Symbol
Condition
Min
Typ
Max
Unit
θ JA
Still air
-
120
-
°C/W
θ JA
1m/s air flow
-
115
-
°C/W
θ JA
3m/s air flow
-
105
-
°C/W
θ JC
Independent of air flow
-
60
-
°C/W
Page 14 of 15
SL23EP08
Ordering Information
[3]
Ordering Number
Marking
Shipping Package
Package
Temperature
SL23EP08SC-1
SL23EP08SC-1
Tube
16-pin SOIC
0 to 70°C
SL23EP08SC-1T
SL23EP08SC-1
Tape and Reel
16-pin SOIC
0 to 70°C
SL23EP08SI-1
SL23EP08SI-1
Tube
16-pin SOIC
-40 to 85°C
SL23EP08SI-1T
SL23EP08SI-1
Tape and Reel
16-pin SOIC
-40 to 85°C
SL23EP08SC-1H
SL23EP08SC-1H
Tube
16-pin SOIC
0 to 70°C
SL23EP08SC-1HT
SL23EP08SC-1H
Tape and Reel
16-pin SOIC
0 to 70°C
SL23EP08SI-1H
SL23EP08SI-1H
Tube
16-pin SOIC
-40 to 85°C
SL23EP08SI-1HT
SL23EP08SI-1H
Tape and Reel
16-pin SOIC
-40 to 85°C
SL23EP08ZC-1H
SL23EP08ZC-1H
Tube
16-pin TSSOP
0 to 70°C
SL23EP08ZC-1HT
SL23EP08ZC-1H
Tape and Reel
16-pin TSSOP
0 to 70°C
SL23EP08ZI-1H
SL23EP08ZI-1H
Tube
16-pin TSSOP
-40 to 85°C
SL23EP08ZI-1HT
SL23EP08ZI-1H
Tape and Reel
16-pin TSSOP
-40 to 85°C
SL23EP08SC-2
SL23EP08SC-2
Tube
16-pin SOIC
0 to 70°C
SL23EP08SC-2T
SL23EP08SC-2
Tape and Reel
16-pin SOIC
0 to 70°C
SL23EP08SI-2
SL23EP08SI-2
Tube
16-pin SOIC
-40 to 85°C
SL23EP08SI-2T
SL23EP08SI-2
Tape and Reel
16-pin SOIC
-40 to 85°C
SL23EP08SC-3
SL23EP08SC-3
Tube
16-pin SOIC
0 to 70°C
SL23EP08SC-3T
SL23EP08SC-3
Tape and Reel
16-pin SOIC
0 to 70°C
SL23EP08SI-3
SL23EP08SI-3
Tube
16-pin SOIC
-40 to 85°C
SL23EP08SI-3T
SL23EP08SI-3
Tape and Reel
16-pin SOIC
-40 to 85°C
SL23EP08SC-4
SL23EP08SC-4
Tube
16-pin SOIC
0 to 70°C
SL23EP08SC-4T
SL23EP08SC-4
Tape and Reel
16-pin SOIC
0 to 70°C
SL23EP08SI-4
SL23EP08SI-4
Tube
16-pin SOIC
-40 to 85°C
SL23EP08SI-4T
SL23EP08SI-4
Tape and Reel
16-pin SOIC
-40 to 85°C
SL23EP08SC-5H
SL23EP08SC-5H
Tube
16-pin SOIC
0 to 70°C
SL23EP08SC-5HT
SL23EP08SC-5H
Tape and Reel
16-pin SOIC
0 to 70°C
Notes:
3. The SL23EP08 products are RoHS compliant.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed
features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories
assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in
applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Rev 1.0, May 18, 2006
Page 15 of 15