Si8239x Data Sheet

Si8239x Data Sheet
4.0 ISODrivers with 2.5 V VDDI and Safety Features
KEY FEATURES
The Si8239x combines two isolated drivers with either an independent input control or a
single input into a single package for high power applications. All drivers operate with a
2.5 V input VDD and a maximum drive supply voltage of 24 V.
• Two isolated drivers in one package
• Up to 5 kVRMS isolation
The Si8239x isolators are ideal for driving power MOSFETs and IGBTs used in a wide
variety of switched power and motor control applications. These drivers utilize Silicon
Laboratories' proprietary silicon isolation technology, supporting up to 5 kVRMS withstand voltage. This technology enables high CMTI (100 kV/µs), lower prop delays and
skew, reduced variation with temperature and age and tighter part-to-part matching.
• Enhanced output UVLO safety
• Status feedback to controller
• Up to 1500 VDC peak driver-to-driver
differential voltage
• Both outputs drive low on UVLO
• EN pin for enhanced safety
It also offers some unique features such as an output UVLO fault detection and feedback, and automatic shutdown for both drivers, an EN (active high) instead of a DIS (active low) pin, a safe delayed start-up time of 1 ms, fail-safe drivers with default low in
case of VDDI power-down, and dead time programmability. The Si8239x family offers
longer service life and dramatically higher reliability compared to opto-coupled gate drivers.
• Extended VDDI: 2.5 V – 5.5 V
Applications
• Power Delivery Systems
• Motor Control Systems
• Isolated dc-dc Power Supplies
• Lighting Control Systems
• Solar and Industrial Inverters
• 30 ns propagation delay
Safety Approvals (Pending)
• UL 1577 recognized
• Up to 5000 Vrms for 1 minute
• CSA component notice 5A approval
• IEC 60950-1
• VDE certification conformity
• VDE 0884-10
• EN 60950-1 (reinforced insulation)
• CQC certification approval
• GB4943.1
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• PWM and dual driver versions
• 4.0 A peak output
• High electromagnetic immunity
• Extended start-up time (1ms) for safe
initialization sequence
• Transient immunity: 100 kV/µs
• Programmable dead time
• 10–200 ns
• 40–400 ns
• Deglitch option for filtering noise
• Wide operating range
• –40 to +125 °C
• RoHS-compliant packages
• SOIC-16 wide body
• SOIC-16 narrow body
• AEC-Q100 qualified
Rev. 0.9
Si8239x Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si8239x Ordering Guide
Configuration
Output
UVLO
Enhanced
UVLO
UVLO
Status
Pin
Delayed
Startup
Time
Dead-Time
Setting
Deglitch
Package
Type
Isolation
Rating
Si82390AD-IS
Dual, VIA, VIB
6V
Yes
Yes
Yes
N/A
No
SOIC-16 WB
5 kVrms
Si82390BD-IS
Dual, VIA, VIB
8V
Yes
Yes
Yes
N/A
No
SOIC-16 WB
5 kVrms
Si82390CD-IS
Dual, VIA, VIB
12 V
Yes
Yes
Yes
N/A
No
SOIC-16 WB
5 kVrms
Si82395AD-IS
Dual, VIA, VIB
6V
No
Yes
Yes
N/A
No
SOIC-16 WB
5 kVrms
Si82395BD-IS
Dual, VIA, VIB
8V
No
Yes
Yes
N/A
No
SOIC-16 WB
5 kVrms
Si82395CD-IS
Dual, VIA, VIB
12 V
No
Yes
Yes
N/A
No
SOIC-16 WB
5 kVrms
Si82397AD-IS
Dual, VIA, VIB
6V
No
No
Yes
N/A
No
SOIC-16 WB
5 kVrms
Si82397BD-IS
Dual, VIA, VIB
8V
No
No
Yes
N/A
No
SOIC-16 WB
5 kVrms
Si82397CD-IS
Dual, VIA, VIB
12 V
No
No
Yes
N/A
No
SOIC-16 WB
5 kVrms
Si82391AD-IS
Dual, VIA, VIB
6V
Yes
Yes
No
N/A
No
SOIC-16 WB
5 kVrms
Si82391BD-IS
Dual, VIA, VIB
8V
Yes
Yes
No
N/A
No
SOIC-16 WB
5 kVrms
Si82391CD-IS
Dual, VIA, VIB
12 V
Yes
Yes
No
N/A
No
SOIC-16 WB
5 kVrms
Si82396AD-IS
Dual, VIA, VIB
6V
No
Yes
No
N/A
No
SOIC-16 WB
5 kVrms
Si82396BD-IS
Dual, VIA, VIB
8V
No
Yes
No
N/A
No
SOIC-16 WB
5 kVrms
Si82396CD-IS
Dual, VIA, VIB
12 V
No
Yes
No
N/A
No
SOIC-16 WB
5 kVrms
Si82394AD-IS
HS/LS, PWM
6V
No
Yes
Yes
10–200 ns
No
SOIC-16 WB
5 kVrms
Si82394BD-IS
HS/LS, PWM
8V
No
Yes
Yes
10–200 ns
No
SOIC-16 WB
5 kVrms
Si82394CD-IS
HS/LS, PWM
12 V
No
Yes
Yes
10–200 ns
No
SOIC-16 WB
5 kVrms
Si82398AD-IS
HS/LS, PWM
6V
No
Yes
No
10–200 ns
No
SOIC-16 WB
5 kVrms
Si82398BD-IS
HS/LS, PWM
8V
No
Yes
No
10–200 ns
No
SOIC-16 WB
5 kVrms
Si82398CD-IS
HS/LS, PWM
12 V
No
Yes
No
10–200 ns
No
SOIC-16 WB
5 kVrms
Ordering Part
Number
Available Now
Contact Silicon Labs to Order the Following Product Options
Si82390AB-IS1
Dual, VIA, VIB
6V
Yes
Yes
Yes
N/A
No
SOIC-16 NB
2.5
kVrms
Si82390BB-IS1
Dual, VIA, VIB
8V
Yes
Yes
Yes
N/A
No
SOIC-16 NB
2.5
kVrms
Si82390CB-IS1
Dual, VIA, VIB
12 V
Yes
Yes
Yes
N/A
No
SOIC-16 NB
2.5
kVrms
Si82395AB-IS1
Dual, VIA, VIB
6V
No
Yes
Yes
N/A
No
SOIC-16 NB
2.5
kVrms
Si82395BB-IS1
Dual, VIA, VIB
8V
No
Yes
Yes
N/A
No
SOIC-16 NB
2.5
kVrms
Si82395CB-IS1
Dual, VIA, VIB
12 V
No
Yes
Yes
N/A
No
SOIC-16 NB
2.5
kVrms
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Si8239x Data Sheet
Ordering Guide
Ordering Part
Number
Configuration
Output
UVLO
Enhanced
UVLO
UVLO
Status
Pin
Delayed
Startup
Time
Dead-Time
Setting
Deglitch
Package
Type
Isolation
Rating
Si82394AB4-IS1
HS/LS, PWM
6V
No
Yes
Yes
40–400 ns
Yes
SOIC-16 NB
2.5
kVrms
Si82394BB4-IS1
HS/LS, PWM
8V
No
Yes
Yes
40–400 ns
Yes
SOIC-16 NB
2.5
kVrms
Si82394CB4-IS1
HS/LS, PWM
12 V
No
Yes
Yes
40–400 ns
Yes
SOIC-16 NB
2.5
kVrms
Si82394AD4-IS
HS/LS, PWM
6V
No
Yes
Yes
40–400 ns
Yes
SOIC-16 WB
5 kVrms
Si82394BD4-IS
HS/LS, PWM
8V
No
Yes
Yes
40–400 ns
Yes
SOIC-16 WB
5 kVrms
Si82394CD4-IS
HS/LS, PWM
12 V
No
Yes
Yes
40–400 ns
Yes
SOIC-16 WB
5 kVrms
Si82391AB-IS1
Dual, VIA, VIB
6V
Yes
Yes
No
N/A
No
SOIC-16 NB
2.5
kVrms
Si82391BB-IS1
Dual, VIA, VIB
8V
Yes
Yes
No
N/A
No
SOIC-16 NB
2.5
kVrms
Si82391CB-IS1
Dual, VIA, VIB
12 V
Yes
Yes
No
N/A
No
SOIC-16 NB
2.5
kVrms
Si82396AB-IS1
Dual, VIA, VIB
6V
No
Yes
No
N/A
No
SOIC-16 NB
2.5
kVrms
Si82396BB-IS1
Dual, VIA, VIB
8V
No
Yes
No
N/A
No
SOIC-16 NB
2.5
kVrms
Si82396CB-IS1
Dual, VIA, VIB
12 V
No
Yes
No
N/A
No
SOIC-16 NB
2.5
kVrms
Si82398AB4-IS1
HS/LS, PWM
6V
No
Yes
No
40–400 ns
Yes
SOIC-16 NB
2.5
kVrms
Si82398BB4-IS1
HS/LS, PWM
8V
No
Yes
No
40–400 ns
Yes
SOIC-16 NB
2.5
kVrms
Si82398CB4-IS1
HS/LS, PWM
12 V
No
Yes
No
40–400 ns
Yes
SOIC-16 NB
2.5
kVrms
Si82398AD4-IS
HS/LS, PWM
6V
No
Yes
No
40–400 ns
Yes
SOIC-16 WB
5 kVrms
Si82398BD4-IS
HS/LS, PWM
8V
No
Yes
No
40–400 ns
Yes
SOIC-16 WB
5 kVrms
Si82398CD4-IS
HS/LS, PWM
12 V
No
Yes
No
40–400 ns
Yes
SOIC-16 WB
5 kVrms
Note:
1. All products are rated at 4 A output drive current max, VDDI = 2.5 V – 5.5 V, EN (active high)
2. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures.
3. “Si” and “SI” are used interchangeably.
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Rev. 0.9 | 2
Si8239x Data Sheet
System Overview
2. System Overview
The operation of an Si8239x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead
of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up.
A simplified block diagram for a single Si8239x channel is shown in the following figure.
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the following figure for more details.
Figure 2.2. Modulation Scheme
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Si8239x Data Sheet
System Overview
2.1 Typical Performance Characteristics (4.0 Amp)
The typical performance characteristics depicted in the following figures are for information purposes only. Refer to the Electrical Characteristics table for actual specification limits.
Figure 2.3. Rise/Fall Time vs. Supply Voltage
Figure 2.4. Propagation Delay vs. Supply Voltage
Figure 2.5. Rise/Fall Time vs. Load
Figure 2.6. Propagation Delay vs. Load
Figure 2.7. Propagation Delay vs. Temperature
Figure 2.8. Supply Current vs. Supply Voltage
Figure 2.9. Supply Current vs. Supply Voltage
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Figure 2.10. Supply Current vs. Temperature
Rev. 0.9 | 4
Si8239x Data Sheet
System Overview
Figure 2.11. Output Sink Current vs. Supply Voltage
Figure 2.13. Output Sink Current vs. Temperature
Figure 2.12. Output Source Current vs. Supply Voltage
Figure 2.14. Output Source Current vs. Temperature
2.2 Family Overview and Logic Operation During Startup
The Si8239x family of isolated drivers consists of high-side/low-side and dual driver configurations.
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Si8239x Data Sheet
System Overview
2.2.1 Device Behavior
The following are truth tables for the Si8239x families.
Table 2.1. Si82390/1 Dual Drivers Enhanced UVLO and Status
VIA
VIB
EN1
VDDI
VDDA
VDDB
VOA
VOB
RDY
Notes
H
L
H
P2
P
P
H
L
H
L
H
H
P
P
P
L
H
H
H
H
H
P
P
P
H
H
H
L
L
H
P
P
P
L
L
H
X
X
L/NC
P
P
P
L
L
H
X
X
X
UP2
P
P
L
L
UD3
Fail-safe output when
VDDI unpowered
X
X
H
P
P
UP
L
UD
L
X
X
H
P
UP
P
UD
L
L
VOA, VOB are actively
driven low if either
VDDA or VDDB is UP
Device disabled
Note:
1. The EN pin needs to be pulled down with a 100 kΩ resistor externally to GND.
2. The chip can be powered through the VIA,VIB input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered. The EN pin has a special ESD circuit that prevents the IC from powering up through the
EN pin.
3. UD = undetermined if same side power is UP.
Table 2.2. Si82395/6 Dual Drivers with UVLO Status
VIA
VIB
EN1
VDDI
VDDA
VDDB
VOA
VOB
RDY
H
L
H
P
P
P
H
L
H
L
H
H
P
P
P
L
H
H
H
H
H
P
P
P
H
H
H
L
L
H
P
P
P
L
L
H
X
X
L/NC
P
P
P
L
L
H
X
X
X
UP2
P
P
L
L
UD3
H
X
H
P
P
UP
H
UD
L
L
X
H
P
P
UP
L
UD
L
X
H
H
P
UP
P
UD
H
L
X
L
H
P
UP
P
UD
L
L
Notes
Device disabled
Fail-safe output when
VDDI unpowered
VOA depends on
VDDA state
VOB depends on
VDDB state
Note:
1. The EN pin needs to be pulled down with a 100 kΩ resistor externally to GND.
2. The chip can be powered through the VIA,VIB input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered. The EN pin has a special ESD circuit that prevents the IC from powering up through the
EN pin.
3. UD = undetermined if same side power is UP.
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Si8239x Data Sheet
System Overview
Table 2.3. Si82397 Dual Drivers with No UVLO Status
VIA
VIB
EN1
VDDI
VDDA
VDDB
VOA
VOB
Notes
H
L
H
P
P
P
H
L
L
H
H
P
P
P
L
H
H
H
H
P
P
P
H
H
L
L
H
P
P
P
L
L
X
X
L/NC
P
P
P
L
L
Device disabled
X
X
X
UP2
P
P
L
L
Fail-safe output when
VDDI is unpowered
H
X
H
P
P
UP
H
UD3
L
X
H
P
P
UP
L
UD
X
H
H
P
UP
P
UD
H
X
L
H
P
UP
P
UD
L
VOA depends on VDDA
state
VOB depends on VDDB
state
Note:
1. The EN pin needs to be pulled down with a 100 kΩ resistor externally to GND.
2. The chip can be powered through the VIA,VIB input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered. The EN pin has a special ESD circuit that prevents the IC from powering up through the
EN pin.
3. UD = undetermined if same side power is UP.
Table 2.4. Si82394/8 PWM Input HS/LS Drivers with UVLO Status
PWM
EN1
VDDI
VDDA
VDDB
VOA
VOB
RDY
Notes
H
H
P
P
P
H
L
H
See Dead-time note and
Figure 2.18 Dead Time
Waveforms for HighSide/Low-Side Drivers on
page 12 for timing
L
H
P
P
P
L
H
H
X
L/NC
P
P
P
L
L
H
X
X
UP2
P
P
L
L
UD3
H
H
P
P
UP
H
UD
L
L
H
P
P
UP
L
UD
L
H
H
P
UP
P
UD
L
L
L
H
P
UP
P
UD
H
L
Device disabled
Fail-safe output when
VDDI unpowered
VOA depends on VDDA
state
VOB depends on VDDB
state
Note:
1. The EN pin needs to be pulled down with a 100 kΩ resistor externally to GND.
2. The chip can be powered through the PWM input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered. The EN pin has a special ESD circuit that prevents the IC from powering up through the
EN pin.
3. UD = undetermined if same side power is UP.
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Si8239x Data Sheet
System Overview
2.3 Power Supply Connections
Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these supplies must be
placed as close to the VDD and GND pins of the Si8239x as possible. The optimum values for these capacitors depend on load current
and the distance between the chip and the regulator that powers it. Low effective series resistance (ESR) capacitors, such as Tantalum,
are recommended.
2.4 Power Dissipation Considerations
Proper system design must assure that the Si8239x operates within safe thermal limits across the entire load range. The Si8239x total
power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by
the series gate resistor and load. Equation 1 shows Si8239x power dissipation.
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Si8239x Data Sheet
System Overview
Substituting values for PDmax Tjmax, TA, and θja into Equation 2 results in a maximum allowable total power dissipation of 1.19 W.
Maximum allowable load is found by substituting this limit and the appropriate data sheet values from Table 4.1 Electrical Characteristics1,2 on page 15 into Equation 1 and simplifying. The result is Equation 3 (4.0 A driver), which assumes VDDI = 5 V and VDDA =
VDDB = 18 V.
Equation 3 is graphed in the following figure where the points along the load line represent the package dissipation-limited value of CL
for the corresponding switching frequency.
Figure 2.15. Max Load vs. Switching Frequency
2.5 Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si8239x VDD lines. Care must be taken to minimize parasitic
inductance in these paths by locating the Si8239x as close to the device it is driving as possible. In addition, the VDD supply and
ground trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground
plane system having separate ground and VDD planes for power devices and small signal components provides the best overall noise
performance.
2.6 Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 2.16 Si82391/6/8 Device Behavior during Normal
Operation and Shutdown on page 10, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively.
Note that outputs VOA and VOB default low when input side power supply (VDDI) is not present.
2.6.1 Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this,
the outputs follow the states of inputs VIA and VIB.
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Si8239x Data Sheet
System Overview
2.6.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. The input (control) side, Driver A and Driver B, each have their own undervoltage lockout monitors.
The Si8239x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver outputs, VOA and
VOB, remain low when the input side of the Si8239x is in UVLO and their respective VDD supply (VDDA, VDDB) is within tolerance.
Each driver output can enter or exit UVLO independently for the Si82394/5/6/7/8 products. For example, VOA unconditionally enters
UVLO when VDDA falls below VDDAUV– and exits UVLO when VDDA rises above VDDAUV+. For the Si82390/1 products, when either VDDA or VDDB falls under VDDxUV–, this information is fed back through the isolation barrier to the input side logic which forces
VOB or VOA to be driven low respectively under these conditions. If the application is driving a transformer for an isolated power converter, for example, this behavior is useful to prevent flux imbalances in the transformer. Please note that this feature implies that it can
only be implemented when the VDDA and VDDB power supplies are independent from each other. If a bootstrap circuit is used for
Si82390/1, it will prevent the IC from powering up. Please do not use the Si82390/1 in conjunction with a bootstrap circuit for driver
power.
Figure 2.16. Si82391/6/8 Device Behavior during Normal Operation and Shutdown
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Si8239x Data Sheet
System Overview
Figure 2.17. Si82390/4/5/7 Device Behavior during Normal Operation and Shutdown
2.6.3 Control Inputs
VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB causes the corresponding
output to go high. For PWM input versions (Si82394/8), VOA is high and VOB is low when the PWM input is high, and VOA is low and
VOB is high when the PWM input is low.
2.6.4 Enable Input
When brought low, the EN input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. Device operation
terminates within tSD after EN = VIL and resumes within tRESTART after EN = VIH. The EN input has no effect if VDDI is below its
UVLO level (i.e., VOA, VOB remain low). The EN pin should be connected to GNDI through a 100 kΩ pull-down resistor.
2.6.5 Delayed Startup Time
Product options Si82390/4/5/7 have a safe startup time (tSTARTUP_SAFE) of 1ms typical from input power valid to output showing
valid data. This feature allows users to proceed through a safe initialization sequence with a monotonic output behavior.
2.6.6 RDY Pin
This is a digital output pin available on all options except the Si82397. The RDY pin is “H” if all the UVLO circuits monitoring VDDI,
VDDA, and VDDB are above UVLO threshold. It indicates that device is ready for operation. An “L” status indicates that one of the
power supplies (VDDI, VDDA, or VDDB) is in an unpowered state.
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Si8239x Data Sheet
System Overview
2.7 Programmable Dead Time and Overlap Protection
All high-side/low-side drivers (Si82394/8) include programmable dead time, which adds a user-programmable delay between transitions
of VOA and VOB. When enabled, dead time is present on all transitions. The amount of dead time delay (DT) is programmed by a
single resistor (RDT) connected from the DT input to ground per the equation below. Note that the dead time pin should be connected
to GND1 through a resistor between the values of 6 kΩ and 100 kΩ and a filter capacitor of 100 pF in parallel as shown in Figure
3.1 Si82394/8 in Half-Bridge Application on page 13. It is highly recommended it not be tied to VDDI. See Figure 2.18 Dead Time
Waveforms for High-Side/Low-Side Drivers on page 12 below.
Figure 2.18. Dead Time Waveforms for High-Side/Low-Side Drivers
2.8 De-glitch Feature
A de-glitch feature is provided on some options, as defined in the Ordering Guide. The de-glitch basically provides an internal time delay during which any noise is ignored and will not pass through the IC. It is about 30 ns; so, for these product options, the prop delay will
be extended by 30 ns.
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Si8239x Data Sheet
Applications
3. Applications
The following examples illustrate typical circuit configurations using the Si8239x.
3.1 High-Side/Low-Side Driver
The following figure shows the Si82394/8 controlled by a single PWM signal.
Figure 3.1. Si82394/8 in Half-Bridge Application
In the above figure, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has
a maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note that the input side of the Si8239x requires VDDI in the range of 2.5 to 5.5 V, while the VDDA and VDDB output side supplies must be between 6.5 and 24 V with respect to
their respective grounds. The boot-strap start up time will depend on the CB cap chosen. Also note that the bypass capacitors on the
Si8239x should be located as close to the chip as possible.
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Si8239x Data Sheet
Applications
3.2 Dual Driver
The following figure shows the Si82390/1/5/6/7 configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be referenced to a common ground or to different grounds with as much as 1500 Vdc between them.
Figure 3.2. Si82390/1/5/6/7 in a Dual Driver Application
Because each output driver resides on its own die, the relative voltage polarities of VOA and VOB can reverse without damaging the
driver. A dual driver can operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity
changes.
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Si8239x Data Sheet
Electrical Characteristics
4. Electrical Characteristics
Table 4.1. Electrical Characteristics1,2
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
2.5
3.3
5.5
V
DC Specifications
Input-side Power Supply Voltage
VDDI
Driver Supply Voltage
VDDA, VDDB
Voltage between VDDA and
GNDA, and VDDB and GNDB
6.5
—
24
V
IDDI(Q)
Si82390/1/4/5/6/8
—
2.8
3.8
mA
Si82397
—
1.5
2.1
mA
Si82390/1/4/5/6/8
—
4.2
6.5
mA
Si82397
—
1.5
2.5
mA
Si82390/1/5/6 VIA, VIB freq =
1 MHz
—
5.0
7.2
mA
Si82394/8: PWM freq = 1
MHz
—
5.2
7.3
Si82397: VIA, VIB freq = 1
MHz
—
3.7
5.6
Si82390/1/4/5/6/8: Input freq
= 1 MHz, no load
—
7.1
16.0
Si82397: Input freq = 1 MHz,
no load
—
4.4
12.4
IVIA, IVIB, IPWM
–10
—
+10
µA
IENABLE
–10
—
+10
µA
Input Supply Quiescent Current EN = 0
Output Supply Quiescent Current, per
channel EN = 0
IDDA(Q),
IDDB(Q)
Input Supply Active Current
IDDI
Output Supply Active Current, per
channel
Input Pin Leakage Current, VIA, VIB,
PWM
IDDA/B
Input Pin Leakage Current, EN
mA
Logic High Input Threshold
VIH
TTL Levels
2.0
—
—
V
Logic Low Input Threshold
VIL
TTL Levels
—
—
0.8
V
400
450
—
mV
Input Hysteresis
VIHYST
Logic High Output Voltage
VOAH, VOBH
IOA, IOB = –1 mA
VDDA,
VDDB –
0.04
—
—
V
Logic Low Output Voltage
VOAL, VOBL
IOA, IOB = 1 mA
—
—
0.04
V
Output Short-Circuit Pulsed Source
Current
IOA(SCL),
IOB(SCL)
See Figure 4.1 IOL Sink Current Test on page 18
—
4.0
—
A
Output Short-Circuit Pulsed Source
Current
IOA(SCH),
IOB(SCH)
See Figure 4.2 IOH Source
Current Test on page 18
—
2.0
—
A
Output Sink Resistance
RON(SINK)
—
1.0
—
Ω
RON(SOURCE)
—
2.7
—
Ω
Output Source Resistance
VDDI Undervoltage Threshold
VDDIUV+
VDDI rising
2.15
2.3
2.5
V
VDDI Undervoltage Threshold
VDDIUV–
VDDI falling
2.1
2.2
2.4
V
VDDI Lockout Hysteresis
VDDIHYS
80
100
—
mV
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Si8239x Data Sheet
Electrical Characteristics
Parameter
VDDA, VDDB Undervoltage Threshold
Symbol
Test Condition
VDDAUV+,
VDDBUV+
VDDA, VDDB rising
Min
Typ
Max
V
6V
5.0
6.0
7.0
8V
7.2
8.6
10.0
12 V
9.2
11.1
12.8
VDDA, VDDB Undervoltage Threshold
VDDAUV–,
VDDBUV–
Unit
VDDA, VDDB falling
V
6V
4.7
5.8
6.7
8V
6.6
8.0
9.3
12 V
8.7
10.1
11.6
UVLO = 6 V
200
280
—
UVLO = 8 V
450
600
—
UVLO = 12 V
600
1000
—
VDDAUV– to VOB low
—
120
—
ns
—
500
—
ns
—
92
—
ns
—
30
—
ns
VDDA, VDDB Lockout Hysteresis
VDDAHYS,
VDDBHYS
UVLO Fault Shutdown Time Enhanced
Mode
mV
VDDBUV– to VOA low
Si82390/1 only
UVLO Fault Shutdown Time
VDDAUV– to VOA low
VDDBUV– to VOB low
UVLO fault to RDY
t_FLT
AC Specifications
Minimum Pulse Width
Propagation Delay
tpHL, tpLH
Si82390/1/5/6/7
20
30
40
ns
VDDA/B = 12 V
tpHL
Si82394/8
20
30
40
ns
CL = 0 pF
tpLH
Si82394/8 (measured with 6
kΩ RDT resistor; includes
minimum dead time.)
35
45
55
ns
Pulse Width Distortion |tPLH – tPHL|
PWD
VDDA/B = 12 V
—
2.7
5.60
ns
RDT = 6 kΩ
9
14
19
ns
RDT = 15 kΩ
23
33
43
RDT = 100 kΩ
150
200
250
CL = 200 pF
—
—
12
ns
CL = 0 pF
Programmed Dead Time for product
options with 10–200 ns dead time setting range
DT
Output Rise and Fall Time
tR,tF
Shutdown Time from Enable False
tSD
—
—
60
ns
tRESTART
—
—
60
ns
Restart Time from Enable True
Device Start-up Time Input
Si82390/4/5/7
Si82391/6/8
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Time from VDDI_ = VDDI_UV
+ to VOA, VOB = VIA, VIB
—
—
tSTART_SAFE
1
ms
tSTART
40
µs
Rev. 0.9 | 16
Si8239x Data Sheet
Electrical Characteristics
Parameter
Device Start-up Time
Symbol
Test Condition
Min
Typ
Max
Unit
tSTART_OUT
Time from VDDA/B = VDDA/
B_UV+ to VOA, VOB = VIA,
VIB
—
60
—
µs
CMTI
VIA, VIB, PWM = VDDI or 0 V
35
100
—
kV/µs
Output
Common Mode Transient Immunity
VCM = 1500 V
Note:
1. 2.5 V < VDDI < 5.5 V; 6.5 V < VDDA, VDDB < 24 V; TA = –40 to +125 °C.
2. Typical specs at 25 °C, VDDA = VDDB = 12 V for 5 V and 8 V UVLO devices, otherwise 15 V.
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Si8239x Data Sheet
Electrical Characteristics
The following figures depict sink current, source current, and common-mode transient immunity test circuits, respectively.
Figure 4.1. IOL Sink Current Test
Figure 4.2. IOH Source Current Test
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Si8239x Data Sheet
Electrical Characteristics
Figure 4.3. CMTI Test Circuit
Table 4.2. Regulatory Information1,2,3
CSA
The Si8239x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
VDE
The Si8239x is certified according to VDE 0884-10. For more details, see File 5006301-4880-0001.
VDE 0884-10: Up to 891 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si8239x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si8239x is certified under GB4943.1-2011. For more details, see certificates CQCxxx (TBD).
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
2. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
3. For more information, see Ordering Guide.
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Si8239x Data Sheet
Electrical Characteristics
Table 4.3. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
Unit
WBSOIC-16
NBSOIC-16
Nominal Air Gap
(Clearance)1
L(1O1)
8.0
4.01
mm
Nominal External
Tracking (Creepage)
L(1O2)
8.0
4.01
mm
0.014
0.014
mm
600
600
V
Minimum Internal
Gap (Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
IEC60112
Erosion Depth
ED
0.019
0.019
mm
Resistance (InputOutput)2
RIO
1012
1012
Ω
Capacitance (InputOutput)2
CIO
1.4
1.4
pF
Input Capacitance3
CI
4.0
4.0
pF
f = 1 MHz
Note:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in 7. Package Outline: 16-Pin Wide
Body SOIC and 9. Package Outline: 16-Pin Narrow Body SOIC. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16 and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage
minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC16 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si8239x is converted into a 2-terminal device. Pins 1–8 are shorted together to
form the first terminal,and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 4.4. IEC 60664-1 (VDE 0884) Ratings
Parameter
Test Condition
WB SOIC-16
NB SOIC-16
Material Group
I
I
Rated Mains Voltages < 150 VRMS
I-IV
I-IV
Rated Mains Voltages < 300 VRMS
I-IV
I-III
Rated Mains Voltages < 400 VRMS
I-III
I-II
Rated Mains Voltages < 600 VRMS
I-III
I-II
Basic Isolation Group
Installation Classification
Specification
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Si8239x Data Sheet
Electrical Characteristics
Table 4.5. IEC 60747-5-5 Insulation Characteristics
Parameter
Symbol
Test Condition
Characteristic
Unit
WB SOIC-16
NB SOIC-16
891
560
V peak
Maximum Working
Insulation Voltage
VIORM
Input to Output Test
Voltage
VPR
Method b1 (VIORM x
1.875 = VPR, 100%
Production Test, tm
= 1 sec, Partial Discharge < 5 pC)
1671
1050
V peak
Transient Overvoltage
VIOTM
t = 60 sec
6000
4000
V peak
2
2
>109
>109
Pollution Degree
(DIN VDE 0110, See
Table 4.1 Electrical
Characteristics1,2 on
page 15)
Insulation Resistance at TS, VIO =
500 V
RS
Ω
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si8239x provides a climate classification of 40/125/21.
Table 4.6. IEC Safety Limiting Values1
Parameter
Symbol
Case Temperature
TS
Safety Input Current
IS
Test Condition
θJA = 100 °C/W (WB
SOIC-16), 105 °C/W
(NB SOIC-16)
WB SOIC-16
NB SOIC-16
Unit
150
150
°C
50
50
mA
1.2
1.2
W
VDDI = 5.5 V,
VDDA = VDDB = 24 V,
TJ = 150 °C, TA = 25 °C
Device Power Dissipation2
PD
Note:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 4.4 WB SOIC-16, NB SOIC-16
Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10 on page 23.
2. The Si8239x is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle square
wave.
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Si8239x Data Sheet
Electrical Characteristics
Table 4.7. Thermal Characteristics
Parameter
Symbol
WB SOIC-16
NB SOIC-16
Unit
IC Junction-to-Air Thermal Resistance
θJA
100
105
°C/W
Table 4.8. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Unit
Ambient Temperature
under Bias
TA
–40
+125
°C
Storage Temperature
TSTG
–65
+150
°C
Junction Temperature
TJ
—
+150
°C
Input-side Supply Voltage
VDDI
–0.6
6.0
V
Driver-side Supply Voltage
VDDA, VDDB
–0.6
30
V
Voltage on any Pin with
respect to Ground
VIO
–0.5
VDD + 0.5
V
Peak Output Current
(tPW = 10 µs, duty cycle
= 0.2%)
IOPK
—
4.0
A
—
260
°C
HBM
—
4
kV
CDM
—
2
kV
Maximum Isolation (Input
to Output) (1 s) WB SOIC-16
—
6500
VRMS
Maximum Isolation (Output to Output) (1 s) WB
SOIC-16
—
2500
VRMS
Maximum Isolation (Input
to Output) (1 s) NB SOIC-16
—
4500
VRMS
Maximum Isolation (Output to Output) (1 s) NB
SOIC-16
—
2500
VRMS
Lead Solder Temperature (10 s)
ESD per AEC-Q100
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Si8239x Data Sheet
Electrical Characteristics
Figure 4.4. WB SOIC-16, NB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature
per VDE 0884-10
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Si8239x Data Sheet
Top-Level Block Diagrams
5. Top-Level Block Diagrams
Figure 5.1. Si82390/1 Dual Isolated Drivers with Enhanced UVLO Safety
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Si8239x Data Sheet
Top-Level Block Diagrams
Figure 5.2. Si82394/98 Single-Input High-Side/Low-Side Isolated Drivers
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Si8239x Data Sheet
Top-Level Block Diagrams
Figure 5.3. Si82395/96 Dual Isolated Drivers with RDY Pin
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Si8239x Data Sheet
Top-Level Block Diagrams
Figure 5.4. Si82397 Dual Isolated Drivers
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Si8239x Data Sheet
Pin Descriptions
6. Pin Descriptions
Figure 6.1. Si8239x SOIC-16
Table 6.1. Pin Descriptions
Pin Name
GNDI
Description
Input-side ground terminal.
VIA
Non-inverting logic input terminal for Driver A.
VIB
Non-inverting logic input terminal for Driver B.
VDDI
Input-side power supply terminal; connect to a source of 2.5 to 5.5 V.
EN
Device ENABLE. When low or NC, this input unconditionally drives outputs VOA, VOB LOW. When high, device is enabled to perform in normal operating mode. It is strongly recommended that this input be connected to external logic level
to avoid erroneous operation due to capacitive noise coupling.
DT
Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output
transitions of VOA and VOB.
NC
No connection.
GNDB
VOB
Ground terminal for Driver B.
Driver B output (low-side driver).
VDDB
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
GNDA
Ground terminal for Driver A.
VOA
VDDA
RDY
Driver A output (high-side driver).
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Power ready on secondary side for Driver A and Driver B (both UVLO thresholds for VDDA and VDDB need to be
crossed). High state indicates UVLO thresholds crossed, low state indicates UVLO low condition. No reset is necessary.
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Si8239x Data Sheet
Package Outline: 16-Pin Wide Body SOIC
7. Package Outline: 16-Pin Wide Body SOIC
The following figure illustrates the package details for the Si8239x in a 16-Pin Wide Body SOIC. The table lists the values for the dimensions shown in the illustration.
Figure 7.1. 16-Pin Wide Body SOIC
Table 7.1. Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75
θ
0°
8°
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Si8239x Data Sheet
Package Outline: 16-Pin Wide Body SOIC
Symbol
Millimeters
Min
Max
aaa
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.
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Si8239x Data Sheet
Land Pattern: 16-Pin Wide Body SOIC
8. Land Pattern: 16-Pin Wide Body SOIC
The following figure illustrates the recommended land pattern details for the Si8239x in a 16-Pin Wide-Body SOIC. The table lists the
values for the dimensions shown in the illustration.
Figure 8.1. 16-Pin Wide Body SOIC PCB Land Pattern
Table 8.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.90
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si8239x Data Sheet
Package Outline: 16-Pin Narrow Body SOIC
9. Package Outline: 16-Pin Narrow Body SOIC
The following figure illustrates the package details for the Si8239x in a 16-Pin Narrow-Body SOIC. The table lists the values for the
dimensions shown in the illustration.
Figure 9.1. 16-Pin Narrow Body SOIC
Table 9.1. Package Diagram Dimensions
Dimension
Min
Max
Dimension
Min
Max
A
—
1.75
L
0.40
1.27
A1
0.10
0.25
L2
A2
1.25
—
h
0.25
0.50
b
0.31
0.51
θ
0°
8°
c
0.17
0.25
aaa
0.10
0.25 BSC
D
9.90 BSC
bbb
0.20
E
6.00 BSC
ccc
0.10
E1
3.90 BSC
ddd
0.25
e
1.27 BSC
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si8239x Data Sheet
Land Pattern: 16-Pin Narrow Body SOIC
10. Land Pattern: 16-Pin Narrow Body SOIC
The following figure illustrates the recommended land pattern details for the Si8239x in a 16-Pin Narrow-Body SOIC. The table lists the
values for the dimensions shown in the illustration.
Figure 10.1. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 10.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si8239x Data Sheet
Top Markings
11. Top Markings
11.1 Si8239x Top Marking (16-Pin Wide Body SOIC)
11.2 Top Marking Explanation (16-Pin Wide Body SOIC)
Line 1 Marking:
Base Part Number
Si8239 = ISOdriver product series
Ordering Options
Y = Output configuration: 0, 1, 4, 5, 6, 7, 8
See Ordering Guide for more information.
0, 1, 5, 6, 7 = Dual drivers
4, 8 = PWM input High side/Low side drivers
U = UVLO level: A, B, C
A = 6 V; B = 8 V; C = 12 V
V = Isolation rating: B, D
B = 2.5 kV; D = 5.0 kV
D = Dead time setting range: none, 4
none = 10–200 ns; 4 = 40–400 ns
Line 2 Marking:
YY = Year
WW = Workweek
Line 3 Marking:
Assigned by the Assembly House. Corresponds to the year
and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing Code from Assembly Purchase Order form.
Circle = 1.5 mm Diameter
“e4” Pb-Free Symbol
(Center Justified)
Country of Origin
TW = Taiwan
ISO Code Abbreviation
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Si8239x Data Sheet
Top Markings
11.3 Si8239x Top Marking (16-Pin Narrow Body SOIC)
11.4 Top Marking Explanation (16-Pin Narrow Body SOIC)
Line 1 Marking:
Base Part Number
Si8239 = ISOdriver product series
Ordering Options
Y = Output configuration: 0, 1, 4, 5, 6, 7, 8
See Ordering Guide for more information.
0, 1, 5, 6, 7 = Dual drivers
4, 8 = PWM input High side/Low side drivers
U = UVLO level: A, B, C
A = 6 V; B = 8 V; C = 12 V
V = Isolation rating: B, D
B = 2.5 kV; D = 5.0 kV
D = Dead time setting range: none, 4
none = 10–200; 4 = 40–400
Line 2 Marking:
YY = Year
WW = Workweek
TTTTTT = Mfg Code
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Assigned by the Assembly House. Corresponds to the year
and workweek of the mold date.
Manufacturing Code from Assembly Purchase Order form.
Rev. 0.9 | 35
Table of Contents
1. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Typical Performance Characteristics (4.0 Amp).
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 4
2.2 Family Overview and Logic Operation During Startup
2.2.1 Device Behavior . . . . . . . . . . . .
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.
.
.
.
.
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.
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.
.
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. 6
2.3 Power Supply Connections .
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2.4 Power Dissipation Considerations .
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2.5 Layout Considerations .
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. 9
2.6 Undervoltage Lockout Operation
2.6.1 Device Startup . . . . . .
2.6.2 Undervoltage Lockout . . .
2.6.3 Control Inputs . . . . . .
2.6.4 Enable Input . . . . . . .
2.6.5 Delayed Startup Time . . .
2.6.6 RDY Pin . . . . . . . .
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. 9
. 9
.10
.11
.11
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.11
2.7 Programmable Dead Time and Overlap Protection
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.12
2.8 De-glitch Feature .
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.12
3. Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3.2 Dual Driver .
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.14
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
15
5. Top-Level Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . .
24
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7. Package Outline: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . .
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8. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . .
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9. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . .
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10. Land Pattern: 16-Pin Narrow Body SOIC. . . . . . . . . . . . . . . . . . . .
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11. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11.1 Si8239x Top Marking (16-Pin Wide Body SOIC) .
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.34
11.2 Top Marking Explanation (16-Pin Wide Body SOIC).
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.34
11.3 Si8239x Top Marking (16-Pin Narrow Body SOIC) .
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.35
11.4 Top Marking Explanation (16-Pin Narrow Body SOIC) .
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.35
Table of Contents
36
Smart.
Connected.
Energy-Friendly
Products
Quality
Support and Community
www.silabs.com/products
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