Si824x CLASS D AUDIO DRIVER WI TH P R E C I S I O N D E AD - T I M E G E N E R A T O R Features 0.5 A peak output (Si8241) 4.0 A peak output (Si8244) PWM input High-precision linear programmable dead-time generator 0.4 ns to 1 µs High latchup immunity >100 V/ns Up to 1500 Vrms output-output isolation, supply voltage of ±750 V Input to output isolation for low noise (up to 2500 V) Up to 8 MHz operation Wide operating range –40 to +125 °C Transient immunity >45 kV/µs RoHS-compliant SOIC-16 narrow body Applications Ordering Information: See page 25. Class D audio amplifiers Description The Si824x isolated driver family combines two isolated drivers in a single package. The Si8241/44 are high-side/low-side drivers specifically targeted at high-power (>30 W) audio applications. Versions with peak output currents of 0.5 A (Si8241) and 4.0 A (Si8244) are available. All drivers operate with a maximum supply voltage of 24 V. Based on Silicon Labs' proprietary isolation technology, the Si824x audio drivers incorporate input-to-output and output-to-output isolation, which enables leveltranslation of signals without additional external circuits as well as use of bipolar supply voltage up to ±750 V. The Si824x audio drivers feature an integrated deadtime generator that provides highly precise control for achieving optimal THD. These products also have overlap protection that safeguards against shootthrough current damage. The CMOS-based design also provides robust immunity from latch-up and high-voltage transients. The extremely low propagation delays enable faster modulation frequencies for an enhanced audio experience. The TTL level compatible inputs with >400 mV hysteresis are available in PWM input configuration; other options include UVLO levels of 8 V or 10 V. These products are available in narrow body SOIC packages. Functional Block Diagram Pin Assignments SOIC-16 (Narrow) PWM 1 16 VDDA NC 2 15 VOA VDDI 3 14 GNDA GNDI 4 13 NC DISABLE 5 12 NC DT 6 11 VDDB NC 7 10 VOB VDDI 8 9 Si8241/44 GNDB Patents Pending PWM Isolation VDDA DT VOA GNDA Programmable Dead Time, Control Gating VDDI UVLO Isolation VDDB DISABLE VOB GNDB GNDI Si8241/44 Rev. 1.0 4/14 Copyright © 2014 by Silicon Laboratories Si824x Si824x 2 Rev. 1.0 Si824x TABLE O F C ONTENTS Section Page 1. Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1. Typical Performance Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2. Typical Performance Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3. Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . . . . . . . . . 17 3.4. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.6. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7. Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . . 22 4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1. Class D Digital Audio Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.1. Si824x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 28 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Rev. 1.0 3 Si824x 1. Top-Level Block Diagram VDDI VDDA ISOLATION PWM LPWM VOA UVLO GNDA DT CONTROL & OVERLAP PROTECTION DT VDDI VDDI VDDB ISOLATION VDDI UVLO DISABLE VOB UVLO GNDB LPWM GNDI Si8241/44 Figure 1. Si8241/44 Single-Input High-Side/Low-Side Isolated Drivers 4 Rev. 1.0 Si824x 2. Electrical Specifications Table 1. Electrical Characteristics1 4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C Parameter Symbol Test Conditions Min Typ Max Units 4.5 — 5.5 V 6.5 — 24 V DC Specifications Input-Side Power Supply Voltage Driver Supply Voltage Input Supply Quiescent Current VDDI Voltage between VDDA and VDDA, VDDB GNDA, and VDDB and GNDB (See “6. Ordering Guide” ) IDDI(Q) Si8241/44 — 2 3 mA IDDA(Q), IDDB(Q) Current per channel — — 3.0 mA Input Supply Active Current IDDI PWM freq = 500 kHz — 2.5 — mA Output Supply Active Current IDDO PWM freq = 500 kHz — 3.6 — mA Input Pin Leakage Current IPWM –10 — +10 µA dc Input Pin Leakage Current IDISABLE –10 — +10 µA dc Logic High Input Threshold VIH 2.0 — — V Logic Low Input Threshold VIL — — 0.8 V Input Hysteresis VIHYST 400 450 — mV Logic High Output Voltage VOAH, VOBH IOA, IOB = –1 mA (VDDA /VDDB) — 0.04 — — V Logic Low Output Voltage VOAL, VOBL IOA, IOB = 1 mA — — 0.04 V Output Short-Circuit Pulsed Sink Current IOA(SCL), IOB(SCL) Si8241, Figure 2 — 0.5 — A Si8244, Figure 2 — 4.0 — A Output Short-Circuit Pulsed Source Current IOA(SCH), IOB(SCH) Si8241, Figure 3 — 0.25 — A Si8244, Figure 3 — 2.0 — A Output Sink Resistance RON(SINK) Si8241 — 5.0 — Si8244 — 1.0 — Si8241 — 15 — Si8244 — 2.7 — Output Supply Quiescent Current Output Source Resistance RON(SOURCE) Notes: 1. VDDA = VDDB = 12 V for 8 V UVLO and 10 V UVLO devices. 2. The largest RDT resistor that can be used is 220 k. Rev. 1.0 5 Si824x Table 1. Electrical Characteristics1 (Continued) 4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C Parameter Symbol Test Conditions Min Typ Max Units VDDI Undervoltage Threshold VDDIUV+ VDDI rising 3.60 4.0 4.45 V VDDI Undervoltage Threshold VDDIUV– VDDI falling 3.30 3.70 4.15 V VDDI Lockout Hysteresis VDDIHYS — 250 — mV VDDA, VDDB Undervoltage Threshold VDDAUV+, VDDBUV+ VDDA, VDDB rising 8 V Threshold See Figure 35 on page 21. 7.50 8.60 9.40 V 10 V Threshold See Figure 36 on page 21. 9.60 11.1 12.2 V VDDA, VDDB Undervoltage Threshold VDDAUV–, VDDBUV– VDDA, VDDB falling 8 V Threshold See Figure 35 on page 21. 7.20 8.10 8.70 V 10 V Threshold See Figure 36 on page 21. 9.40 10.1 10.9 V VDDA, VDDB Lockout Hysteresis VDDAHYS, VDDBHYS UVLO voltage = 8 V — 600 — mV VDDA, VDDB Lockout Hysteresis VDDAHYS, VDDBHYS UVLO voltage = 10 V — 1000 — mV — 10 — ns — 25 60 ns — 1.0 5.60 ns See Figures 37 and 38 0.4 — 1000 ns CL = 1 nF (Si8241) — — 20 ns CL = 1 nF (Si8244) — — 12 ns AC Specifications Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| tPHL, tPLH CL = 1 nF PWD Programmed Dead Time2 DT Output Rise and Fall Time tR,tF Shutdown Time from Disable True tSD — — 60 ns tRESTART — — 60 ns Restart Time from Disable False Device Start-up Time tSTART Time from VDD_ = VDD_UV+ to VOA, VOB = VIA, VIB — 5 7 µs Common Mode Transient Immunity CMTI VIA, VIB, PWM = VDDI or 0 V VCM = 1500 V (see Figure 4) 25 45 — kV/µs Notes: 1. VDDA = VDDB = 12 V for 8 V UVLO and 10 V UVLO devices. 2. The largest RDT resistor that can be used is 220 k. 6 Rev. 1.0 Si824x 2.1. Test Circuits Figures 2 and 3 depict sink current and source current test circuits. VDDA = VDDB = 15 V VDDI VDD IN INPUT 10 OUT Si824x SCHOTTKY VSS 1 µF 1 µF CER Measure 100 µF 8V + _ 5.5 V + _ 10 µF EL RSNS 0.1 50 ns VDDI GND 200 ns INPUT WAVEFORM Figure 2. IOL Sink Current Test Circuit VDDA = VDDB = 15 V VDDI IN INPUT VDD Si824x 10 OUT SCHOTTKY VSS 1 µF 1 µF CER Measure 100 µF 10 µF EL RSNS 0.1 50 ns VDDI GND 200 ns INPUT WAVEFORM Figure 3. IOH Source Current Test Circuit Rev. 1.0 7 Si824x 12 V Supply Si824x Input Signal Switch 5V Isolated Supply VDDI VDDA INPUT VOA DISABLE DT GNDA VDDB Oscilloscope VOB 100k GNDI GNDB Isolated Ground Input High Voltage Differential Probe Output Vcm Surge Output High Voltage Surge Generator Figure 4. Common Mode Transient Immunity Test Circuit Table 2. Regulatory Information* CSA The Si824x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. 60950-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. VDE The Si824x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. 60747-5-2: Up to 560 Vpeak for basic insulation working voltage. UL The Si824x is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 2500 VRMS isolation voltage for basic protection. *Note: Regulatory Certifications apply to 2.5 kVRMS rated devices, which are production tested to 3.0 kVRMS for 1 sec. For more information, see "6.Ordering Guide" on page 25. 8 Rev. 1.0 Si824x Table 3. Insulation and Safety-Related Specifications Value Parameter Symbol Test Condition NBSOIC-16 2.5 kVRMS Unit Nominal Air Gap (Clearance)1 L(1O1) 4.01 mm Nominal External Tracking (Creepage)1 L(1O2) 4.01 mm 0.011 mm 600 V Minimum Internal Gap (Internal Clearance) Tracking Resistance (Proof Tracking Index) PTI Erosion Depth ED 0.019 mm Resistance (Input-Output)2 RIO 1012 Capacitance (Input-Output)2 CIO 1.4 pF 4.0 pF Input Capacitance3 IEC60112 f = 1 MHz CI Notes: 1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Package Outline: 16-Pin Narrow Body SOIC” . VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC 16. 2. To determine resistance and capacitance, the Si824x is converted into a 2-terminal device. Pins 1–8 are shorted together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground. Table 4. IEC 60664-1 (VDE 0884 Part 2) Ratings Parameter Basic Isolation Group Installation Classification Test Conditions Material Group Specification NB SOIC-16 I Rated Mains Voltages < 150 VRMS I-IV Rated Mains Voltages < 300 VRMS I-III Rated Mains Voltages < 400 VRMS I-II Rated Mains Voltages < 600 VRMS I-II Rev. 1.0 9 Si824x Table 5. IEC 60747-5-2 Insulation Characteristics* Parameter Symbol Maximum Working Insulation Voltage VIORM Characteristic NB SOIC-16 Unit 560 V peak VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 1050 V peak VIOTM t = 60 sec 4000 V peak Input to Output Test Voltage Transient Overvoltage Test Condition Pollution Degree (DIN VDE 0110, Table 1) 2 Insulation Resistance at TS, VIO = 500 V >109 RS *Note: Maintenance of the safety data is ensured by protective circuits. The Si824x provides a climate classification of 40/125/21. Table 6. IEC Safety Limiting Values1 Parameter Case Temperature Symbol Test Condition TS Safety Input Current IS Device Power Dissipation2 PD JA = 105 °C/W (NB SOIC-16), VDDI = 5.5 V, VDDA = VDDB= 24 V, TJ = 150 °C, TA = 25 °C NB SOIC-16 Unit 150 °C 50 mA 1.2 W Notes: 1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 5. 2. The Si82xx is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle square wave. 10 Rev. 1.0 Si824x Table 7. Thermal Characteristics Parameter Symbol NB SOIC-16 Unit JA 105 °C/W Safety-Limiting Current (mA) IC Junction-to-Air Thermal Resistance 60 50 VDDI = 5.5 V VDDA, VDDB = 24 V 40 30 20 10 0 0 50 100 150 Case Temperature (ºC) 200 Figure 5. NB SOIC-16, Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Table 8. Absolute Maximum Ratings1 Parameter Symbol Min Typ Max Units TSTG –65 — +150 °C TA –40 — +125 °C Input-side Supply Voltage VDDI –0.6 — 6.0 V Driver-side Supply Voltage VDDA, VDDB –0.6 — 30 V VIN –0.5 — VDD + 0.5 V IO — — 10 mA Storage Temperature2 Ambient Temperature under Bias Voltage on any Pin with respect to Ground Output Drive Current per Channel Lead Solder Temperature (10 sec) — — 260 °C 3 — — 100 V/ns Maximum Isolation (Input to Output) — — 2500 VRMS Maximum Isolation (Output to Output) — — 1500 VRMS Latchup Immunity Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. VDE certifies storage temperature from –40 to 150 °C. 3. Latchup immunity specification is for slew rate applied across GNDI and GNDA or GNDB. Rev. 1.0 11 Si824x 3. Functional Description The operation of an Si824x channel is analogous to that of an opto coupler and gate driver, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si824x channel is shown in Figure 6. Transmitter Receiver Driver RF Oscillator VDD A Dead Time Generator Modulator SemiconductorBased Isolation Barrier B Demodulator 0.5 to 4 A peak Gnd Figure 6. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See Figure 7 for more details. Input Signal Modulation Signal Output Signal Figure 7. Modulation Scheme 12 Rev. 1.0 Si824x 3.1. Typical Performance Characteristics (0.5 Amp) The typical performance characteristics depicted in Figures 8 through 19 are for information purposes only. Refer to Table 1 on page 5 for actual specification limits. VDDA Supply Current (mA) 10 Rise/Fall Time (ns) 8 Tfall 6 4 Trise 2 VDD=12V, 25°C CL = 100 pF 7 5 12 15 18 500kHz 3 100kHz 2 1 50 kHz 0 9 21 1MHz 4 0 9 Duty Cycle = 50% CL = 100 pF 1 Channel Switching 6 14 19 24 VDDA Supply Voltage (V) 24 VDDA Supply (V) Figure 11. Supply Current vs. Supply Voltage Figure 8. Rise/Fall Time vs. Supply Voltage 5 Supply Current (mA) Propagation Delay (ns) 30 25 H-L 20 L-H 15 VDD=12V, 25°C CL = 100 pF 12 15 18 3 VDDA = 15V, f = 250kHz, CL = 0 pF Duty Cycle = 50% 2 Channels Switching 2 1 -50 10 9 4 21 0 50 100 Temperature (°C) 24 VDDA Supply (V) Figure 12. Supply Current vs. Temperature Figure 9. Propagation Delay vs. Supply Voltage 40 35 Duty Cycle = 50% CL = 0 pF 1 Channel Switching 3.5 Rise/Fall Time (ns) VDDA Supply Current (mA) 4 1MHz 3 500kHz 2.5 2 100kHz Trise 30 25 20 Tfall 15 10 5 1.5 50 kHz 9 14 19 VDD=12V, 25°C 0 1 24 VDDA Supply Voltage (V) 0.0 0.5 1.0 1.5 2.0 Load (nF) Figure 10. Supply Current vs. Supply Voltage Rev. 1.0 Figure 13. Rise/Fall Time vs. Load 13 Propagation Delay (ns) Si824x 50 4 45 3.75 35 Source Current (A) 40 L-H 30 H-L 25 20 15 3.5 3.25 3 2.75 2.5 2.25 VDD=12V, 25°C 10 0.0 0.5 1.0 VDD=12V, Vout=VDD-5V 2 1.5 2.0 10 15 Load (nF) 20 25 Supply Voltage (V) Figure 17. Output Source Current vs. Supply Voltage Figure 14. Propagation Delay vs. Load 25 L-H 20 Sink Current (A) Propagation Delay (ns) 30 H-L 15 VDD=12V, Load = 200pF 10 -40 -20 0 20 40 60 80 100 120 7 6.75 6.5 6.25 6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 VDD=12V, Vout=5V -40 Temperature (°C) -10 20 50 80 110 Temperature (°C) Figure 15. Propagation Delay vs. Temperature Figure 18. Output Sink Current vs. Temperature 9 3.5 3.25 Source Current (A) Sink Current (A) 8 7 6 5 12 14 16 18 20 22 24 2.5 VDD=12V, Vout=VDD-5V 2 -40 Supply Voltage (V) -10 20 50 80 110 Temperature (°C) Figure 16. Output Sink Current vs. Supply Voltage 14 2.75 2.25 VDD=12V, Vout=5V 4 10 3 Figure 19. Output Source Current vs. Temperature Rev. 1.0 Si824x 3.2. Typical Performance Characteristics (4.0 Amp) The typical performance characteristics depicted in Figures 20 through 31 are for information purposes only. Refer to Table 1 on page 5 for actual specification limits. VDDA Supply Current (mA) 10 Rise/Fall Time (ns) 8 Tfall 6 Trise 4 2 14 Duty Cycle = 50% CL = 100 pF 1 Channel Switching 12 10 500kHz 8 6 100kHz 4 2 50 kHz 0 9 VDD=12V, 25°C CL = 100 pF 12 15 18 14 19 24 VDDA Supply Voltage (V) 0 9 1MHz 21 24 Figure 23. Supply Current vs. Supply Voltage VDDA Supply (V) 10 Supply Current (mA) Figure 20. Rise/Fall Time vs. Supply Voltage Propagation Delay (ns) 30 25 L-H 6 VDDA = 15V, f = 250kHz, CL = 0 pF Duty Cycle = 50% 2 Channels Switching 4 2 0 20 -50 0 50 15 Figure 24. Supply Current vs. Temperature 10 9 12 15 18 21 40 24 35 Rise/Fall Time (ns) VDDA Supply (V) Figure 21. Propagation Delay vs. Supply Voltage 14 Duty Cycle = 50% CL = 0 pF 1 Channel Switching 12 1MHz Trise 30 25 20 Tfall 15 10 5 10 VDD=12V, 25°C 0 8 0 500kHz 6 4 100kHz 14 19 2 3 4 5 6 7 8 9 10 Figure 25. Rise/Fall Time vs. Load 50 kHz 0 1 Load (nF) 2 9 100 Temperature (°C) H-L VDD=12V, 25°C CL = 100 pF VDDA Supply Current (mA) 8 24 VDDA Supply Voltage (V) Figure 22. Supply Current vs. Supply Voltage Rev. 1.0 15 Si824x 4 50 3.75 H-L 40 35 3.5 Source Current (A) Propagation Delay (ns) 45 L-H 30 25 3.25 3 2.75 2.5 20 2.25 15 10 0 1 2 3 4 5 6 7 8 9 10 10 Load (nF) Sink Current (A) Propagation Delay (ns) H-L L-H 20 15 VDD=12V, Load = 200pF -40 -20 0 20 40 60 80 100 120 7 6.75 6.5 6.25 6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 -40 -10 20 50 80 110 Temperature (°C) Figure 27. Propagation Delay vs. Temperature Figure 30. Output Sink Current vs. Temperature 3.5 9 3.25 Source Current (A) 8 Sink Current (A) 25 VDD=12V, Vout=5V Temperature (°C) 7 6 5 3 2.75 2.5 2.25 VDD=12V, Vout=5V 4 10 12 14 16 18 20 22 VDD=12V, Vout=VDD-5V 2 24 -40 Supply Voltage (V) -10 20 50 80 110 Temperature (°C) Figure 28. Output Sink Current vs. Supply Voltage 16 20 Supply Voltage (V) 30 10 15 Figure 29. Output Source Current vs. Supply Voltage Figure 26. Propagation Delay vs. Load 25 VDD=12V, Vout=VDD-5V 2 VDD=12V, 25°C Figure 31. Output Source Current vs. Temperature Rev. 1.0 Si824x 3.3. Family Overview and Logic Operation During Startup The Si824x family of isolated drivers consists of high-side, low-side, and dual driver configurations. 3.3.1. Products Table 9 shows the configuration and functional overview for each product in this family. Table 9. Si824x Family Overview Part Number Configuration UVLO Voltage Programmable Dead Time Inputs Peak Output Current (A) Si8241 High-Side/Low-Side 8 V/10 V PWM 0.5 Si8244 High-Side/Low-Side 8 V/10 V PWM 4.0 3.3.2. Device Behavior Table 10 contains truth tables for the Si8241/4 families. Table 10. Si824x Family Truth Table* Si8241/4 (PWM Input High-Side/Low-Side) Truth Table PWM Input VDDI State Disable Output VOA VOB Notes H Powered L H L Output transition occurs after internal dead time expires. L Powered L L H Output transition occurs after internal dead time expires. X Unpowered X L L Output returns to input state within 7 µs of VDDI power restoration. X Powered H L L Device is disabled. *Note: This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see "3.7.2.Undervoltage Lockout" on page 20 for more information. Rev. 1.0 17 Si824x 3.4. Power Supply Connections Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these supplies must be placed as close to the VDD and GND pins of the Si824x as possible. The optimum values for these capacitors depend on load current and the distance between the chip and the regulator that powers it. Low effective series resistance (ESR) capacitors, such as Tantalum, are recommended. 3.5. Power Dissipation Considerations Proper system design must assure that the Si824x operates within safe thermal limits across the entire load range. The Si824x total power dissipation is the sum of the power dissipated by bias supply current, internal switching losses, and power delivered to the load. Equation 1 shows total Si824x power dissipation. In a non-overlapping system, such as a high-side/low-side driver, n = 1. 2 2 P D = V DDI I DDI + 2 V DDO I QOUT + C int V DDO F + 2n C L V DDO F where: P D is the total Si824x device power dissipation (W) I DDI is the input-side maximum bias current (3 mA) I QOUT is the driver die maximum bias current (2.5 mA) C int is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver) V DDI is the input-side VDD supply voltage (4.5 to 5.5 V) V DDO is the driver-side supply voltage (10 to 24 V) F is the switching frequency (Hz) n is the overlap constant (max value = 2) Equation 1. The maximum power dissipation allowable for the Si824x is a function of the package thermal resistance, ambient temperature, and maximum allowable junction temperature, as shown in Equation 2: T jmax – T A P Dmax --------------------------ja where: P Dmax = Maximum Si824x power dissipation (W) T jmax = Si824x maximum junction temperature (150 °C) T A = Ambient temperature (°C) ja = Si824x junction-to-air thermal resistance (105 °C/W) F = Si824x switching frequency (Hz) Equation 2. Substituting values for PDmax Tjmax, TA, and ja into Equation 2 results in a maximum allowable total power dissipation of 1.19 W. Maximum allowable load is found by substituting this limit and the appropriate datasheet values from Table 1 on page 5 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and Equation 4 (4.0 A driver), both of which assume VDDI = 5 V and VDDA = VDDB = 18 V. –3 10 - – 7.5 10 – 11 C L(MAX) = 1.4 ------------------------F Equation 3. –3 10 - – 3.7 10 – 10 C L(MAX) = 1.4 ------------------------F Equation 4. 18 Rev. 1.0 Si824x Equation 1 and Equation 2 are graphed in Figure 32 where the points along the load line represent the package dissipation-limited value of CL for the corresponding switching frequency. 1 6 ,0 0 0 0 .5 A D r i ve r ( p F ) 4 A D r i ve r ( p F ) 1 4 ,0 0 0 1 2 ,0 0 0 8 ,0 0 0 Ta = 25 °C 6 ,0 0 0 4 ,0 0 0 2 ,0 0 0 0 700 650 600 550 500 450 400 350 300 250 200 150 100 F re q u e n c y (K h z ) Figure 32. Max Load vs. Switching Frequency 20 VDDA Supply Current (mA) Max Load (pF) 1 0 ,0 0 0 CL = 1000pF 15 10 CL = 500pF CL = 200pF 5 VDD=15V, 25°C 0 0 200 400 600 800 1000 Switching Frequency (kHz) Figure 33. Switching Frequency vs. Load Current Rev. 1.0 19 Si824x 3.6. Layout Considerations It is most important to minimize ringing in the drive path and noise on the Si824x VDD lines. Care must be taken to minimize parasitic inductance in these paths by locating the Si824x as close to the device it is driving as possible. In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for power devices and small signal components provides the best overall noise performance. 3.7. Undervoltage Lockout Operation Device behavior during start-up, normal operation and shutdown is shown in Figure 34, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively. Note that outputs VOA and VOB default low when input side power supply (VDDI) is not present. 3.7.1. Device Startup Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs VIA and VIB. 3.7.2. Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating circuits range. The input (control) side, Driver A and Driver B, each have their own undervoltage lockout monitors. The Si824x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver outputs, VOA and VOB, remain low when the input side of the Si824x is in UVLO and their respective VDD supply (VDDA, VDDB) is within tolerance. Each driver output can enter or exit UVLO independently. For example, VOA unconditionally enters UVLO when VDDA falls below VDDAUV– and exits UVLO when VDDA rises above VDDAUV+. UVLO+ UVLO- VDD HYS VDDI UVLO+ UVLO- VDD HYS VDDA PW M DISABLE tSTART tSD tSTART tSTART tSD tRESTART tPHL tPLH VOA Figure 34. Device Behavior during Normal Operation and Shutdown 20 Rev. 1.0 Si824x 3.7.3. Undervoltage Lockout (UVLO) The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 35 and 36, upon power up, the Si824x is maintained in UVLO until VDD rises above VDDUV+. During power down, the Si824x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+ – VDDHYS). V DDUV+ (Typ) Output Voltage (VO) 10.5 Output Voltage (VO) 10.5 V DDUV+ (Typ) 6.0 6.5 7.0 7.5 8.0 8.5 9.0 8.5 9.5 10.0 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 Supply Voltage (V DD - V SS) (V) Supply Voltage (V DD - V SS) (V) Figure 36. Si824x UVLO Response (10 V) Figure 35. Si824x UVLO Response (8 V) 3.7.4. Control Inputs PWM inputs are high-true, TTL level-compatible logic inputs. VOA is high and VOB is low when the PWM input is high, and VOA is low and VOB is high when the PWM input is low. 3.7.5. Disable Input When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of input. Device operation terminates within tSD after DISABLE = VIH and resumes within tRESTART after DISABLE = VIL. The DISABLE input has no effect if VDDI is below its UVLO level (i.e. VOA, VOB remain low). The DISABLE input is typically connected to external protection circuitry to unconditionally halt driver operation in the event of a fault. Rev. 1.0 21 Si824x 3.8. Programmable Dead Time and Overlap Protection All high-side/low-side drivers (Si8241/4) include programmable overlap protection to prevent outputs VOA and VOB from being high at the same time. These devices also include programmable dead time, which adds a userprogrammable delay between transitions of VOA and VOB. When enabled, dead time is present on all transitions, even after overlap recovery. The amount of dead time delay (DT) is programmed by a single resistor (RDT) connected from the DT input to ground per Equation 5. Minimum dead time (approximately 400 ps) can be achieved by connecting the DT pin to VDDI. Note that dead time accuracy is limited by the resistor’s (RDT) tolerance and temperature coefficient. See Figures 37 and 38 for additional information about dead time operation. DT 10 RDT where: DT = dead time (ns) and RDT = dead time programming resistor (k 1000 100 900 90 800 80 700 70 Dead-time (ns) Dead-time (ns) Equation 5. 600 500 400 300 0 0 80 100 RDT = 2k RDT = 1k RDT = 0 -40 Dead-time Resistance (k: :) -20 0 20 40 60 80 100 120 Temperature (°C) Figure 37. Dead Time vs.Resistance (RDT) 22 RDT = 3k 30 10 60 RDT = 4k 40 20 40 RDT = 5k 50 100 20 RDT = 6k 60 200 0 RDT = 10k Figure 38. Dead Time vs.Temperature Rev. 1.0 Si824x 4. Applications The following examples illustrate typical circuit configurations using the Si824x. 4.1. Class D Digital Audio Driver Figures 39 and 40 show the Si8241/4 controlled by a single PWM signal. Supply can be unipolar (0 to 1500 V) or bipolar (± 750 V). VDD2 VDDI D1 C2 1 µF VDDI C1 1uF 1500 V max VDDA GNDI CB PWM PWMOUT GNDA DT RDT CONTROLLER Q1 VOA Si8241/4 VDDB VDDB I/O C3 10uF DISABLE GNDB Q2 VOB Figure 39. Si824x in Half-Bridge Audio Application VDD2 VDDI D1 C2 1 µF VDDI C1 1uF +750 V max VDDA GNDI CB PWM PWMOUT GNDA DT CONTROLLER RDT Q1 VOA Si8241/4 VDDB VDDB I/O C3 10uF DISABLE GNDB VOB Q2 -750 V max Figure 40. Si824x in Half-Bridge Audio Application D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has a maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note that the input side of the Si824x requires VDD in the range of 4.5 to 5.5 V, while the VDDA and VDDB output side supplies must be between 6.5 and 24 V with respect to their respective grounds. The boot-strap start up time will depend on the CB cap chosen. VDD2 is usually the same as VDDB. Also note that the bypass capacitors on the Si824x should be located as close to the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass capacitors be used to reduce high frequency noise and maximize performance. The D1 diode should be a fast-recovery diode; it should be able to withstand the maximum high voltage (e.g. 1500 V) and be low-loss. See “AN486: High-Side Bootstrap Design Using Si823x ISODrivers in Power Delivery Systems” for more details in selecting the bootstrap cap (CB) and diode (D1). Rev. 1.0 23 Si824x 5. Pin Descriptions SOIC-16 (Narrow) PWM 1 16 VDDA NC 2 15 VOA VDDI 3 14 GNDA GNDI 4 13 NC DISABLE 5 12 NC DT 6 11 VDDB NC 7 10 VOB VDDI 8 9 Si8241/44 GNDB Table 11. Si8241/44 PWM Input HS/LS Isolated Driver (SOIC-16) Pin Name 1 PWM 2 NC 3 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. 4 GNDI Input-side ground terminal. 5 24 Description PWM input. No connection. DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 DT Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when connected to VDDI or left open (see "3.8.Programmable Dead Time and Overlap Protection" on page 22). 7 NC No connection. 8 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. 9 GNDB Ground terminal for Driver B. 10 VOB 11 VDDB 12 NC No connection. 13 NC No connection. 14 GNDA 15 VOA 16 VDDA Driver B output (low-side driver). Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. Ground terminal for Driver A. Driver A output (high-side driver). Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Rev. 1.0 Si824x 6. Ordering Guide The currently available OPNs are listed in Table 12. Table 12. Ordering Part Numbers* Ordering Part Number (OPN) Input Type Package Si8241BB-D-IS1 PWM NB SOIC-16 Si8241CB-D-IS1 PWM NB SOIC-16 Si8244BB-D-IS1 PWM NB SOIC-16 Si8244CB-D-IS1 PWM NB SOIC-16 Drive Strength Output Isolation Rating (Input to Output) 8V 0.5 A High-Side/Low-Side 4A UVLO Voltage 10 V 8V 2.5 kVrms 10 V *Note: All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. Tape and reel options are specified by adding an “R” suffix to the ordering part number. “Si” and “SI” are used interchangeably. Rev. 1.0 25 Si824x 7. Package Outline: 16-Pin Narrow Body SOIC Figure 41 illustrates the package details for the Si824x in a 16-pin narrow-body SOIC (SO-16). Table 13 lists the values for the dimensions shown in the illustration. Figure 41. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 13. Package Diagram Dimensions Dimension Min Max Dimension Min Max A — 1.75 L 0.40 1.27 A1 0.10 0.25 L2 A2 1.25 — h 0.25 0.50 b 0.31 0.51 θ 0° 8° c 0.17 0.25 aaa 0.10 0.25 BSC D 9.90 BSC bbb 0.20 E 6.00 BSC ccc 0.10 E1 3.90 BSC ddd 0.25 e 1.27 BSC Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 26 Rev. 1.0 Si824x 8. Land Pattern: 16-Pin Narrow Body SOIC Figure 42 illustrates the recommended land pattern details for the Si824x in a 16-pin narrow-body SOIC. Table 14 lists the values for the dimensions shown in the illustration. Figure 42. 16-Pin Narrow Body SOIC PCB Land Pattern Table 14. 16-Pin Narrow Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. Rev. 1.0 27 Si824x 9. Top Marking: 16-Pin Narrow Body SOIC 9.1. Si824x Top Marking (16-Pin Narrow Body SOIC) e4 Si824YUV YYWWTTTTTT 9.2. Top Marking Explanation (16-Pin Narrow Body SOIC) Base Part Number Ordering Options Line 1 Marking: See Ordering Guide for more information. Line 2 Marking: 28 Si824 = ISOdriver product series Y = Peak output current 1 = 0.5 A 4 = 4.0 A U = UVLO level B = 8 V; C = 10 V V = Isolation rating B = 2.5 kV YY = Year WW = Workweek Assigned by the Assembly House. Corresponds to the year and workweek of the mold date. TTTTTT = Mfg Code Manufacturing Code from Assembly Purchase Order form. Rev. 1.0 Si824x DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Deleted Table 3. Added Tables 2 through 7. Added Figure 5. Updated common-mode transient immunity specification throughout. Revision 0.2 to Revision 0.3 Updated Figures 2 and 3 on page 7. Added Figure 4 on page 8. Updated Table 12 on page 25. Revision 0.3 to Revision 1.0 Updated Table 12, Ordering Part Numbers. Added Revision D Ordering Part Numbers. all Ordering Part Numbers of previous revisions. Removed moisture sensitivity level table notes. Removed Rev. 1.0 29 Smart. Connected. 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