Si 5 3 4 5 / 4 4 /42 10-C HANNEL , A NY - F R E QUE N C Y, A NY - O UTPUT J ITTER A TTENUATOR / C L O C K M ULTIPLIER Features Generates any combination of output frequencies from any input frequency Input frequency range: Differential: 8 kHz to 750 MHz LVCMOS: 8 kHz to 250 MHz Output frequency range: Differential: up to 712.5 MHz LVCMOS: up to 250 MHz Ultra-low jitter: <100 fs typ (12 kHz–20 MHz) Programmable jitter attenuation bandwidth from 0.1 Hz to 4 kHz Meets G.8262 EEC Opt 1, 2 (SyncE) Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude Status monitoring (LOS, OOF, LOL) Hitless input clock switching: automatic or manual Locks to gapped clock inputs Automatic free-run and holdover modes Optional zero delay mode Fastlock feature for low nominal bandwidths Glitchless on the fly output frequency changes DCO mode: as low as 0.001 ppb steps. Core voltage VDD: 1.8 V ±5% VDDA: 3.3 V ±5% Independent output clock supply pins: 3.3 V, 2.5 V, or 1.8 V Output-output skew: 20 ps typ Serial interface: I2C or SPI In-circuit programmable with non-volatile OTP memory ClockBuilder ProTM software simplifies device configuration Si5345: 4 input, 10 output, 64 QFN Si5344: 4 input, 4 output, 44 QFN Si5342: 4 input, 2 output, 44 QFN Temperature range: –40 to +85 °C Pb-free, RoHS-6 compliant Ordering Information: See section 8 Functional Block Diagram XTAL Si5345/44/42 XB XA IN_SEL Device Selector Guide OSC Grade Max Output Frequency Frequency Synthesis Modes Si534fA 712.5 MHz Integer+Fractional Si534fB 350 MHz Integer+Fractional Si534fC 712.5 MHz Integer Si534fD 350 MHz Integer IN0 ÷FRAC IN1 ÷FRAC IN2 ÷FRAC IN3/ FB_IN ÷FRAC DSPLL Optional External Feedback Applications ÷INT OUT0 Multi Synth ÷INT OUT1 Multi Synth ÷INT OUT2 Multi Synth ÷INT OUT3 Multi Synth ÷INT OUT4 ÷INT OUT5 NVM ÷INT OUT6 I2C/SPI ÷INT OUT7 Control/ Status ÷INT OUT8 ÷INT OUT9 Description These jitter attenuating clock multipliers combine fourth-generation DSPLL and MultiSynth™ technologies to enable any-frequency clock generation and jitter attenuation for applications requiring the highest level of jitter performance. These devices are programmable via a serial interface with in-circuit programmable nonvolatile memory (NVM) so they always power up with a known frequency configuration. They support free-run, synchronous, and holdover modes of operation, and offer both automatic and manual input clock switching. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level. Programming the Si5345/44/42 is easy with Silicon Labs’ ClockBuilder Pro software. Factory preprogrammed devices are also available. Rev. 1.0 7/15 Copyright © 2015 by Silicon Laboratories Si5345 Multi Synth Carrier Ethernet switches SONET/SDH Line Cards Broadcast video Test and measurement ITU-T G.8262 (SyncE) Compliant Si5344 OTN Muxponders and Transponders 10/40/100G networking line cards GbE/10GbE/100GbE Synchronous Ethernet (ITU-T G.8262) Si5342 Si5345/44/42 Si5345/44/42 TABLE O F C ON TENTS 1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 5.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.13. Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . 43 6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 9.1. Si5345 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 9.2. Si5344 and Si5342 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . 57 10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2 Rev. 1.0 Si5345/44/42 1. Typical Application Schematic 100 MHz (HCSL) 133.333 MHz (CMOS) Si5345 83.333 MHZ (CMOS) DSPLL 50 MHz (CMOS) 100 MHz 156.25 MHz (LVDS) PCIe 3.0 CPU/NPU FPGA/ASIC/ SWITCH 125 MHz MultiSynth 19.44 MHz 2.048 MHz 156.25 MHz (LVDS) MultiSynth MultiSynth 156.525 MHz (LVDS) 10G PHY MultiSynth MultiSynth 155.52 MHz (LVDS) 125 MHz (LVPECL) 125 MHz (LVPECL) 10G PHY 1G PHY 1G PHY Figure 1. 10G Ethernet Data Center Switch and Compute Blade Schematic Rev. 1.0 3 Si5345/44/42 2. Electrical Specifications Table 1. Recommended Operating Conditions* (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%,TA = –40 to 85 °C) Parameter Symbol Min Typ Max Unit Ambient Temperature TA –40 25 85 °C Junction Temperature TJMAX — — 125 °C Core Supply Voltage VDD 1.71 1.80 1.89 V VDDA 3.14 3.30 3.47 V VDDO 3.14 3.30 3.47 V 2.38 2.50 2.62 V 1.71 1.80 1.89 V 3.14 3.30 3.47 V 1.71 1.80 1.89 V Clock Output Driver Supply Voltage Status Pin Supply Voltage VDDS *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. 4 Rev. 1.0 Si5345/44/42 Table 2. DC Characteristics (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Core Supply Current Symbol Test Condition Min Typ Max Unit IDD Si5345 — 125 185 mA Si5344 — 105 155 mA Si5342 — 105 155 mA Si5345 — 120 125 mA Si5344 — 115 120 mA Si5342 — 115 120 mA LVPECL Output4 @ 156.25 MHz — 21 25 mA LVDS Output4 @ 156.25 MHz — 15 18 mA 3.3 V LVCMOS5 output @ 156.25 MHz — 21 25 mA 2.5 V LVCMOS5 output @ 156.25 MHz — 16 18 mA 1.8 V LVCMOS5 output @ 156.25 MHz — 12 13 mA IDDA Output Buffer Supply Current IDDOx Total Power Dissipation Pd Si5345 Notes 1, 6 — 880 1040 mW Si5344 Notes 2, 6 — 720 850 mW Si5342 Notes 3, 6 — 715 840 mW Notes: 1. Si5345 test configuration: 10x 3.3 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors. 2. Si5344 test configuration: 4x 3.3 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 3. Si5342 test configuration: 2x 3.3 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 4. Differential outputs terminated into an AC coupled 100 load. 5. LVCMOS outputs measured into a 6 inch 50 PCB trace with 5 pF load. Measurements were made in CMOS3 mode. Differential Output Test Configuration IDDO LVCMOS Output Test Configuration IDDO 0.1 uF OUT 50 100 OUT 50 6 inch OUTa OUTb 50 5 pF 0.1 uF 6. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. Rev. 1.0 5 Si5345/44/42 Table 3. Input Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Standard Differential or Single-Ended - AC Coupled (IN0/IN0, IN1/IN1, IN2/IN2, IN3/IN3, FB_IN/FB_IN) Input Frequency Range Differential 0.008 — 750 MHz Single-ended/LVCMOS 0.008 — 250 MHz Differential AC Coupled fin < 250 MHz 100 — 1800 mVpp_se Differential AC Coupled 250 MHz < fin < 750 MHz 225 — 1800 mVpp_se Single-Ended AC Coupled fin < 250 MHz 100 — 3600 mVpp_se fIN_DIFF Voltage Swing1 VIN Slew Rate2, 3 SR 400 — — V/µs Duty Cycle DC 40 — 60 % Capacitance CIN — 2 — pF fIN_PULSED_CMOS4 0.008 — 250 MHz VIL –0.2 — 0.33 V VIH 0.49 — — V Slew Rate2, 3 SR 400 — — V/µs Minimum Pulse Width PW 1.6 — — ns Input Resistance RIN — 8 — k Pulsed CMOS - DC Coupled (IN0, IN1, IN2, IN3) Input Frequency Input Voltage4 Pulse Input REFCLK (applied to XA/XB) Notes: 1. Voltage swing is specified as single-ended mVpp. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx 2. Imposed for jitter performance. 3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 – 0.2) x VIN_Vpp_se) / SR 4. This mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz that must be dc-coupled because they have a duty cycle significantly less than 50%. A typical application example is a low-frequency video frame sync pulse. Since the input thresholds (VIL, VIH) of this buffer are non-standard (0.33 and 0.49 V, respectively) refer to the input attenuator circuit for dc-coupled pulsed LVCMOS in the Family Reference Manual at: www.silabs.com/ Support%20Documents/TechnicalDocs/Si5345-44-42-RM.pdf. Otherwise, for standard LVCMOS input clocks, use the Standard Differential or Single-Ended ac-coupled input mode. 6 Rev. 1.0 Si5345/44/42 Table 3. Input Specifications (Continued) (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter REFCLK Frequency Symbol Test Condition Min Typ Max Unit fIN_REF Frequency range for best output jitter performance 48 — 54 MHz TCXO frequency for SyncE applications. Jitter performance may be reduced — 40 — MHz — 2000 mVpp_se 2500 mVpp_diff Input Single-ended Voltage Swing VIN_SE 365 Input Differential Voltage Swing VIN_DIFF 365 Slew rate2, 3 SR 400 — — V/µs Input Duty Cycle DC 40 — 60 % Notes: 1. Voltage swing is specified as single-ended mVpp. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx 2. Imposed for jitter performance. 3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 – 0.2) x VIN_Vpp_se) / SR 4. This mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz that must be dc-coupled because they have a duty cycle significantly less than 50%. A typical application example is a low-frequency video frame sync pulse. Since the input thresholds (VIL, VIH) of this buffer are non-standard (0.33 and 0.49 V, respectively) refer to the input attenuator circuit for dc-coupled pulsed LVCMOS in the Family Reference Manual at: www.silabs.com/ Support%20Documents/TechnicalDocs/Si5345-44-42-RM.pdf. Otherwise, for standard LVCMOS input clocks, use the Standard Differential or Single-Ended ac-coupled input mode. Rev. 1.0 7 Si5345/44/42 Table 4. Control Input Pin Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Si5345 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, A1, SCLK, A0/CS, FINC, FDEC, SDA/SDIO) VIL — — 0.3 x VDDIO* V VIH 0.7 x VDDIO* — — V Input Capacitance CIN — 2 — pF Input Resistance RIN — 20 — k Minimum Pulse Width PW RST, FINC and FDEC 50 — — ns Update Rate TUR FINC and FDEC 1 — — µs Input Voltage Si5344/42 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, A1, SCLK, A0/CS, SDA/SDIO) VIL — — 0.3 x VDDIO* V VIH 0.7 x VDDIO* — — V Input Capacitance CIN — 2 — pF Input Resistance RIN — 20 — k Minimum Pulse Width PW 50 — — ns Input Voltage RST *Note: VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5345/44/42 Family Reference Manual for more details on the proper register settings. 8 Rev. 1.0 Si5345/44/42 Table 5. Differential Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Frequency fOUT Duty Cycle DC Output-Output Skew Test Condition TSK Min Typ Max Unit 0.0001 — 712.5 MHz fOUT < 400 MHz 48 — 52 % 400 MHz < fOUT < 712.5 MHz 45 — 55 % Outputs on same Multisynth (Normal Mode) — 20 50 ps Outputs on same Multisynth (Low-Power Mode) — 20 100 ps — 0 100 ps OUT-OUT Skew TSK_OUT Measured from the positive to negative output pins Output Voltage Swing1 Normal Mode VOUT VDDO = 3.3 V or 2.5 V or 1.8 V LVDS 350 470 550 mVpp_se VDDO = 3.3 V or 2.5 V LVPECL 660 810 1000 mVpp_se VDDO = 3.3 V or 2.5 V or 1.8 V LVDS 300 420 530 mVpp_se VDDO = 3.3 V or 2.5 V LVPECL 620 820 1060 mVpp_se Low-Power Mode VOUT Note: 1. For normal and low-power modes, the amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode (or low-power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. Also note that the output voltage swing specifications are given in peak-to-peak single-ended swing. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx 2. Not all combinations of voltage swing and common mode voltages settings are possible. See the Si5345/44/42 Family Reference Manual for details. 3. Driver output impedance depends on selected output mode (Normal, Low-Power). 4. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and noise spur amplitude measured. 5. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk. Rev. 1.0 9 Si5345/44/42 Table 5. Differential Clock Output Specifications (Continued) (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Common Mode Voltage1,2 (100 Ω load line-to-line) Rise and Fall Times (20% to 80%) Differential Output Impedance3 Symbol Test Condition Min Typ Max Unit LVDS 1.10 1.25 1.35 V LVPECL 1.90 2.05 2.15 V VDDO = 2.5 V LVPECL LVDS 1.15 1.25 1.35 V VDDO = 1.8 V Sub-LVDS 0.87 0.93 1.0 V Normal Mode — 170 240 ps Low-Power Mode — 300 430 Normal Mode — 100 — Low-Power Mode — 650 — Normal Mode or Low-Power Mode VCM tR/tF ZO VDDO = 3.3 V Note: 1. For normal and low-power modes, the amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode (or low-power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. Also note that the output voltage swing specifications are given in peak-to-peak single-ended swing. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx 2. Not all combinations of voltage swing and common mode voltages settings are possible. See the Si5345/44/42 Family Reference Manual for details. 3. Driver output impedance depends on selected output mode (Normal, Low-Power). 4. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and noise spur amplitude measured. 5. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk. 10 Rev. 1.0 Si5345/44/42 Table 5. Differential Clock Output Specifications (Continued) (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Power Supply Noise Rejection4 Symbol PSRR Test Condition Min Typ Max Unit 10 kHz sinusoidal noise — –93 — dBc 100 kHz sinusoidal noise — –93 — 500 kHz sinusoidal noise — –84 — 1 MHz sinusoidal noise — –79 — 10 kHz sinusoidal noise — –98 — 100 kHz sinusoidal noise — –95 — 500 kHz sinusoidal noise — –84 — 1 MHz sinusoidal noise — –76 — Si5345 Measured spur from adjacent output5 — –75 — dBc Si5342/44 Measured spur from adjacent output5 — –85 — dBc Normal Mode Low Power Mode Output-output Crosstalk XTALK dBc Note: 1. For normal and low-power modes, the amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode (or low-power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. Also note that the output voltage swing specifications are given in peak-to-peak single-ended swing. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx 2. Not all combinations of voltage swing and common mode voltages settings are possible. See the Si5345/44/42 Family Reference Manual for details. 3. Driver output impedance depends on selected output mode (Normal, Low-Power). 4. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and noise spur amplitude measured. 5. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk. Rev. 1.0 11 Si5345/44/42 Table 6. LVCMOS Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Frequency fOUT Duty Cycle DC Output-to-Output Skew TSK Output Voltage High1, 2, 3 VOH Test Condition Min Typ Max Unit 0.0001 — 250 MHz fOUT <100 MHz 47 — 53 % 100 MHz < fOUT < 250 MHz 44 — 55 — — 100 ps VDDO x 0.85 — — V — — — — — — — — — — — — — — VDDO = 3.3 V OUTx_CMOS_DRV = 1 IOH = –10 mA OUTx_CMOS_DRV = 2 IOH = –12 mA OUTx_CMOS_DRV = 3 IOH = –17 mA VDDO = 2.5 V OUTx_CMOS_DRV = 1 IOH = –6 mA OUTx_CMOS_DRV = 2 IOH = –8 mA OUTx_CMOS_DRV = 3 IOH = –11 mA VDDO x 0.85 V VDDO = 1.8 V OUTx_CMOS_DRV = 2 IOH = –4 mA OUTx_CMOS_DRV = 3 IOH = –5 mA VDDO x 0.85 V Notes: 1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the Si5345/44/42 Family Reference Manual for more details on register settings. 2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration. 3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 PCB trace. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3. AC Test Configuration Trace length 5 inches IOL/IOH IDDO 50 OUT Zs VOL/VOH 499 4.7 pF DC Block OUT 499 DC Block 50 probe, scope 50 4.7 pF 12 50 probe, scope 56 Rev. 1.0 56 Si5345/44/42 Table 6. LVCMOS Clock Output Specifications (Continued) (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Voltage Low1, 2, 3 VOL Test Condition Min Typ Max Unit VDDO x 0.15 V VDDO x 0.15 V VDDO x 0.15 V VDDO = 3.3 V OUTx_CMOS_DRV=1 IOL = 10 mA — — OUTx_CMOS_DRV=2 IOL = 12 mA — — OUTx_CMOS_DRV=3 IOL = 17 mA — — VDDO = 2.5 V OUTx_CMOS_DRV=1 IOL = 6 mA — — OUTx_CMOS_DRV=2 IOL = 8 mA — — OUTx_CMOS_DRV=3 IOL = 11 mA — — VDDO = 1.8 V LVCMOS Rise and Fall Times3 (20% to 80%) OUTx_CMOS_DRV=2 IOL = 4 mA — — OUTx_CMOS_DRV=3 IOL = 5 mA — — VDDO = 3.3V — 420 550 ps VDDO = 2.5 V — 475 625 ps VDDO = 1.8 V — 525 705 ps tr/tf Notes: 1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the Si5345/44/42 Family Reference Manual for more details on register settings. 2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration. 3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 PCB trace. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3. AC Test Configuration Trace length 5 inches IOL/IOH IDDO 50 OUT Zs VOL/VOH 499 4.7 pF DC Block 50 probe, scope 56 OUT 499 DC Block 50 probe, scope 50 4.7 pF Rev. 1.0 56 13 Si5345/44/42 Table 7. Output Status Pin Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Si5345 Status Output Pins (LOL, INTR, SDA/SDIO1, SDO) Output Voltage VOH IOH = –2 mA VDDIO x 0.75 — — V VOL IOL = 2 mA — — VDDIO2 x 0.15 V Si5344 Status Output Pins (LOL, INTR, SDA/SDIO1, SDO) Output Voltage VOH IOH = –2 mA VDDIO* x 0.75 — — V VOL IOL = 2 mA — — VDDIO2 x 0.15 V Si5342 Status Output Pins (LOL, LOS0, LOS1, LOS2, LOS3, LOS_XAXB, INTR, SDA/SDIO1, SDO) Output Voltage VOH IOH = –2 mA VDDS x 0.75 — — V VOL IOL = 2 mA — — VDDS x 0.15 V Notes: 1. Note that the VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused with I2C_SEL pulled high. VOL remains valid in all cases. 2. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5345/44/42 Family Reference Manual for more details on the proper register settings. 14 Rev. 1.0 Si5345/44/42 Table 8. Performance Characteristics (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol PLL Loop Bandwidth Programming Range1 fBW Test Condition Min Typ Max Unit 0.1 — 4000 Hz tSTART Time from power-up to when the device generates free-running clocks — 30 45 ms tACQ fIN = 19.44 MHz — 500 600 ms tDELAY_frac fVCO = 14 GHz — 0.28 — ps tDELAY_int — 71.4 — ps tRANGE — ±9.14 — ns POR to Serial Interface Ready3 tRDY — — 15 ms Jitter Peaking JPK Measured with a frequency plan running a 25 MHz input, 25 MHz output, and a Loop Bandwidth of 4 Hz — — 0.1 dB Jitter Tolerance JTOL Compliant with G.8262 Options 1 and 2 Carrier Frequency = 10.3125 GHz Jitter Modulation Frequency = 10 Hz — 3180 — UI pk-pk tSWITCH Only valid for a single switch between two input clocks running at the same frequency — — 2.8 ns P — 500 — ppm tIODELAY — 2 — ns Initial Start-Up Time PLL Lock Time2 Output Delay Adjustment Maximum Phase Transient During a Hitless Switch Pull-in Range Input-to-Output Delay Variation RMS Phase Jitter4 tZDELAY In Zero Delay Mode. Measured as the time delay difference between the reference input and the feedback input, with both clocks running at 10 MHz and having the same slew rate. The rise time of the reference input should not exceed 200 ps in order to meet this spec. — 110 — ps JGEN Integer Mode 12 kHz to 20 MHz — 0.090 0.140 ps RMS Fractional Mode 12 kHz to 20 MHz — 0.130 0.165 ps RMS Notes: 1. Actual loop bandwidth might be lower; please refer to CBPro for actual value for your frequency plan. 2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL tresholds, etc. For this case, lock time was measured with nominal and fastlock bandwidths set to 100 Hz, LOL set/clear thresholds of 6/0.6 ppm respectively, using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first rising edge of the clock reference and the LOL indicator deassertion. 3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands. 4. Jitter generation test conditions: fIN = 19.44 MHz, fOUT = 156.25 MHz LVPECL, loop bandwidth = 100 Hz. Rev. 1.0 15 Si5345/44/42 Table 9. I2C Timing Specifications (SCL,SDA) Parameter Symbol Test Condition Min Max Standard Mode 100 kbps Min Max Unit Fast Mode 400 kbps — 100 — 400 kHz 25 35 25 35 ms tHD:STA 4.0 — 0.6 — µs Low period of the SCL clock tLOW 4.7 — 1.3 — µs HIGH period of the SCL clock tHIGH 4.0 — 0.6 — µs Set-up time for a repeated START condition tSU:STA 4.7 — 0.6 — µs Data hold time tHD:DAT 100 — 100 — ns Data set-up time tSU:DAT 250 — 100 — ns Rise time of both SDA and SCL signals tr — 1000 20 300 ns Fall time of both SDA and SCL signals tf — 300 — 300 ns Set-up time for STOP condition tSU:STO 4.0 — 0.6 — µs tBUF 4.7 — 1.3 — µs Data valid time tVD:DAT — 3.45 — 0.9 µs Data valid acknowledge time tVD:ACK — 3.45 — 0.9 µs SCL Clock Frequency SMBus Timeout Hold time (repeated) START condition Bus free time between a STOP and START condition 16 fSCL — When Timeout is Enabled Rev. 1.0 Si5345/44/42 Figure 2. I2C Serial Port Timing Standard and Fast Modes Rev. 1.0 17 Si5345/44/42 Table 10. SPI Timing Specifications (4-Wire) (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, TA = –40 to 85 °C) Parameter Symbol Min Typ Max Unit SCLK Frequency fSPI — — 20 MHz SCLK Duty Cycle TDC 40 — 60 % SCLK Period TC 50 — — ns Delay Time, SCLK Fall to SDO Active TD1 — 12.5 18 ns Delay Time, SCLK Fall to SDO TD2 — 10 15 ns Delay Time, CS Rise to SDO Tri-State TD3 — 10 15 ns Setup Time, CS to SCLK TSU1 5 — — ns Hold Time, SCLK Fall to CS TH1 5 — — ns Setup Time, SDI to SCLK Rise TSU2 5 — — ns Hold Time, SDI to SCLK Rise TH2 5 — — ns Delay Time Between Chip Selects (CS) TCS 2 — — TC TSU1 TD1 TC SCLK TH1 CS TSU2 TH2 TCS SDI TD2 TD3 SDO Figure 3. 4-Wire SPI Serial Interface Timing 18 Rev. 1.0 Si5345/44/42 Table 11. SPI Timing Specifications (3-Wire) (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, TA = –40 to 85 °C) Parameter Symbol Min Typ Max Unit SCLK Frequency fSPI — — 20 MHz SCLK Duty Cycle TDC 40 — 60 % SCLK Period TC 50 — — ns Delay Time, SCLK Fall to SDIO Turn-on TD1 — 12.5 20 ns Delay Time, SCLK Fall to SDIO Next-bit TD2 — 10 15 ns Delay Time, CS Rise to SDIO Tri-State TD3 — 10 15 ns Setup Time, CS to SCLK TSU1 5 — — ns Hold Time, CS to SCLK Fall TH1 5 — — ns Setup Time, SDI to SCLK Rise TSU2 5 — — ns Hold Time, SDI to SCLK Rise TH2 5 — — ns Delay Time Between Chip Selects (CS) TCS 2 — — TC TSU1 TC SCLK TH1 TD1 TD2 CS TSU2 TH2 TCS SDIO TD3 Figure 4. 3-Wire SPI Serial Interface Timing Rev. 1.0 19 Si5345/44/42 Table 12. Crystal Specifications Parameter Crystal Frequency Range Symbol Test Condition Min Typ Max Unit fXTAL_48-54 Frequency range for best jitter performance 48 — 54 MHz Load Capacitance CL_48-54 — 8 — pF Shunt Capacitance CO_48-54 — — 2 pF Crystal Drive Level dL_48-54 — — 200 µW Equivalent Series Resistance rESR_48-54 Refer to the Si5345/44/42 Family Reference Manual to determine ESR. fXTAL_25 — 25 — MHz Load Capacitance CL_25 — 8 — pF Shunt Capacitance CO_25 — — 3 pF Crystal Drive Level dL_25 — — 200 µW Crystal Frequency Range Equivalent Series Resistance rESR_25 Refer to the Si5345/44/42 Family Reference Manual to determine ESR. Notes: 1. The Si5345/44/42 is designed to work with crystals that meet the specifications in Table 12. 2. Refer to the Si5345/44/42 Family Reference Manual for recommended 48 to 54 MHz crystals. 20 Rev. 1.0 Si5345/44/42 Table 13. Thermal Characteristics Parameter Symbol Test Condition* Value Unit JA Still Air 22 °C/W Air Flow 1 m/s 19.4 Air Flow 2 m/s 18.3 Si5345-64QFN Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case JC 9.5 Thermal Resistance Junction to Board JB 9.4 JB 9.3 JT 0.2 Thermal Resistance Junction to Top Center Si5344, Si5342-44QFN Thermal Resistance Junction to Ambient JA Still Air 22.3 Air Flow 1 m/s 19.4 Air Flow 2 m/s 18.4 Thermal Resistance Junction to Case JC 10.9 Thermal Resistance Junction to Board JB 9.3 JB 9.2 JT 0.23 Thermal Resistance Junction to Top Center °C/W *Note: Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via: 36, Number of Cu Layers: 4. Rev. 1.0 21 Si5345/44/42 Table 14. Absolute Maximum Ratings1,2,3,4 Parameter Symbol Test Condition Value Unit Storage Temperature Range TSTG –55 to +150 °C DC Supply Voltage VDD –0.5 to 3.8 V VDDA –0.5 to 3.8 V VDDO –0.5 to 3.8 V VDDS –0.5 to 3.8 V Input Voltage Range Latch-up Tolerance VI1 IN0 – IN3/FB_IN –0.85 to 3.8 V VI2 IN_SEL1, IN_SEL0, RST, OE, I2C_SEL, FINC, FDEC, SDI, SCLK, A0/CS, A1, SDA/SDIO –0.5 to 3.8 V VI3 XA/XB –0.5 to 2.7 V LU ESD Tolerance HBM Storage Temperature Range JESD78 Compliant 2.0 kV TSTG –55 to 150 °C Junction Temperature TJCT –55 to 150 °C Soldering Temperature (Pb-free profile)4 TPEAK 260 °C TP 20–40 s Soldering Temperature Time at TPEAK (Pb-free profile)4 100 pF, 1.5 k Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. 64-QFN and 44-QFN packages are RoHS-6 compliant. 3. For more packaging information, including MSL rating, go to www.silabs.com/support/quality/pages/ RoHSInformation.aspx. 4. The device is compliant with JEDEC J-STD-020. 22 Rev. 1.0 Si5345/44/42 3. Typical Operating Characteristics The phase noise plots below were taken under the following conditions: VDD = 1.8 V, VDDA = 3.3 V, VDDS = 3.3 V, 1.8 V, and TA = 25 °C. Figure 5. Input = 25 MHz; Output = 625 MHz, 2.5 V LVDS Figure 6. Input = 25 MHz; Output = 156.25 MHz, 2.5 V LVDS Rev. 1.0 23 Si5345/44/42 Figure 7. Input = 25 MHz; Output = 155.52 MHz, 2.5 V LVDS 24 Rev. 1.0 Si5345/44/42 48-54MHz XTAL or REFCLK VDDA VDD 4. Detailed Block Diagrams 3 XA Si5345 XB OSC IN_SEL[1:0] ÷PREF IN0 P ÷ 0n P0d IN0 IN1 IN1 IN2 IN2 IN3/FB_IN IN3/FB_IN ÷ P1n P1d DSPLL ÷ P2n P2d PD ÷ P3n P3d LPF ÷ Optional External Feedback Multi N ÷ 0n Synth N0d t0 Multi N ÷ 1n Synth N1d t1 Multi N ÷ 2n Synth N2d t2 Multi N ÷ 3n Synth N3d t3 Multi N ÷ 4n Synth N4d t4 Mn Md ÷R0 VDDO0 OUT0 OUT0 ÷R1 VDDO1 OUT1 OUT1 ÷R2 VDDO2 OUT2 OUT2 ÷R3 VDDO3 OUT3 OUT3 ÷R4 VDDO4 OUT4 OUT4 ÷R5 VDDO5 OUT5 OUT5 ÷R6 VDDO6 OUT6 OUT6 ÷R7 VDDO7 OUT7 OUT7 ÷R8 VDDO8 OUT8 OUT8 ÷R9 VDDO9 OUT9 OUT9 I2C_SEL A1/SDO SCLK SPI/ I2C NVM A0/CS FINC FDEC LOL Status Monitors RST INTR OE SDA/SDIO Figure 8. Si5345 Block Diagram Rev. 1.0 25 4 48-54MHz XTAL or REFCLK VDDA VDD VDDS Si5345/44/42 2 XA Si5344 XB OSC IN_SEL[1:0] ÷PREF IN0 IN0 IN1 IN1 IN2 IN2 IN3/FB_IN IN3/FB_IN ÷ P0n P0d ÷ P1n P1d DSPLL ÷ P2n P2d PD ÷ P3n P3d LPF ÷ Optional External Feedback Mn Md I2C_SEL SDA/SDIO A1/SDO SCLK SPI/ I2C Multi N ÷ 0n Synth N0d t0 NVM Multi N ÷ 1n Synth N1d t1 Multi N ÷ 2n Synth N2d t2 Multi N ÷ 3n Synth N3d t3 A0/CS ÷R0 VDDO0 OUT0 OUT0 ÷R1 VDDO1 OUT1 OUT1 ÷R2 VDDO2 OUT2 OUT2 ÷R3 VDDO3 OUT3 OUT3 Figure 9. Si5344 Block Diagram 26 Rev. 1.0 OE LOL LOS_XAXB INTR RST Status Monitors 2 4 3 48-54MHz XTAL or REFCLK VDDA VDD VDDS Si5345/44/42 XA Si5342 XB OSC IN_SEL[1:0] ÷PREF IN0 P ÷ 0n P0d IN0 IN1 IN1 IN2 IN2 IN3/FB_IN IN3/FB_IN ÷ P1n P1d DSPLL ÷ P2n P2d PD ÷ P3n P3d LPF ÷ Optional External Feedback Mn Md I2C_SEL t0 Multi N ÷ 1n Synth N1d t1 ÷R0 VDDO0 OUT0 OUT0 ÷R1 VDDO1 OUT1 OUT1 NVM OE LOS3 LOS_XAXB LOS2 LOS1 RST Status Monitors LOL SCLK A0/CS Multi N ÷ 0n Synth N0d LOS0 A1/SDO SPI/ I2C INTR SDA/SDIO Figure 10. Si5342 Block Diagram Rev. 1.0 27 Si5345/44/42 5. Functional Description The Si5345’s internal DSPLL provides jitter attenuation and any-frequency multiplication of the selected input frequency. Fractional input dividers (P) allow the DSPLL to perform hitless switching between input clocks (INx) that are fractionally related. Input switching is controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which determines output frequency stability and accuracy while the device is in free-run or holdover mode. The high-performance MultiSynth dividers (N) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the MultiSynth generated frequencies to any of the outputs. Additional integer division (R) determines the final output frequency. 5.1. Frequency Configuration The frequency configuration of the DSPLL is programmable through the serial interface and can also be stored in non-volatile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/ Md), fractional output MultiSynth division (Nn/Nd), and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro utility. 5.2. DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. 5.2.1. Fastlock Feature Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Loop Bandwidth settings of in the range of 100 Hz to 4 kHz are available for selection. The DSPLL will revert to its normal loop bandwidth once lock acquisition has completed. 5.3. Modes of Operation Once initialization is complete the DSPLL operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 11. The following sections describe each of these modes in greater detail. 5.3.1. Initialization and Reset Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits including the serial interface will be restored to their initial state. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. 28 Rev. 1.0 Si5345/44/42 Power-Up Reset and Initialization No valid input clocks selected Free-run Valid input clock selected An input is qualified and available for selection Phase lock on selected input clock is achieved Holdover Mode No s Ye Is holdover history valid? Lock Acquisition (Fast Lock) Selected input clock fails Locked Mode Figure 11. Modes of Operation 5.3.2. Freerun Mode The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes. 5.3.3. Lock Acquisition Mode The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency. 5.3.4. Locked Mode Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point any XTAL frequency drift will not affect the output frequency. A loss of lock pin (LOL) and status bit indicate when lock is achieved. See section 5.7.4 for more details on the operation of the loss of lock circuit. 5.3.5. Holdover Mode The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for the DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in Figure 12. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data that may be corrupt just before the input clock failure. Rev. 1.0 29 Si5345/44/42 Clock Failure and Entry into Holdover Historical Frequency Data Collected time 120s Programmable historical data window used to determine the final holdover value Programmable delay 30ms, 60ms, 1s,10s, 30s, 60s 0s 1s,10s, 30s, 60s Figure 12. Programmable Holdover Window When entering holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in holdover, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If the clock input becomes valid, the DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is glitchless and its rate is controlled by the DSPLL or the Fastlock bandwidth. 5.4. External Reference (XA/XB) An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in Figure 13. The device includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Refer to Table 12 for crystal specifications. A crystal in the range of 48 MHz to 54 MHz is recommended for best jitter performance. Frequency offsets due to CL mismatch can be adjusted using the frequency adjustment feature which allows frequency adjustments of ±200 ppm. The Si5345/44/42 Family Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. The device can also accommodate an external reference clock (REFCLK) instead of a crystal. Selection between the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in this mode. Refer to Table 3 for REFCLK requirements when using this mode. A PREF divider is available to accommodate external clock frequencies higher than 54 MHz. Frequencies in the range of 48 MHz to 54 MHz will achieve the best output jitter performance. 5.5. Digitally Controlled Oscillator (DCO) Mode The output MultiSynths support a DCO mode where their output frequencies are adjustable in pre-defined steps defined by frequency step words (FSW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increment (FINC) or decrement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. Any number of MultiSynths can be can be updated at once or independently controlled. The DCO mode is available when the DSPLL is operating in either free-run or locked mode. 30 Rev. 1.0 Si5345/44/42 48-54MHz XO 48-54MHz XO 48-54MHz XTAL XA 100 XB 2xCL XA 2xCL 2xCL OSC XA XB 2xCL XB 2xCL 2xCL OSC OSC ÷PREF ÷PREF ÷PREF Si5345/44/42 Si5345/44/42 Crystal Resonator Connection Si5345/44/42 Differential XO Connection Single-ended XO Connection Figure 13. Crystal Resonator and External Reference Clock Connection Options 5.6. Inputs (IN0, IN1, IN2, IN3) There are four inputs that can be used to synchronize the DSPLL. The inputs accept both differential and singleended clocks. Input selection can be manual (pin or register controlled) or automatic with user definable priorities. 5.6.1. Manual Input Switching (IN0, IN1, IN2, IN3) Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal on the selected input, the device will automatically enter free-run or holdover mode. When the zero delay mode is enabled, IN3 becomes the feedback input (FB_IN) and is not available for selection as a clock input. Table 15. Manual Input Selection Using IN_SEL[1:0] Pins Selected Input IN_SEL[1:0] Zero Delay Mode Disabled Zero Delay Mode Enabled 0 0 IN0 IN0 0 1 IN1 IN1 1 0 IN2 IN2 1 1 IN3 Reserved Rev. 1.0 31 Si5345/44/42 5.6.2. Automatic Input Selection (IN0, IN1, IN2, IN3) An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection criteria is based on input clock qualification, input priority, and the revertive option. Only input clocks that are valid can be selected by the automatic clock selection state machine. If there are no valid input clocks available the DSPLL will enter the holdover mode. With revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority becomes valid then an automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority will be initiated. 5.6.3. Hitless Input Switching Hitless switching is a feature that prevents a phase transient from propagating to the output when switching between two clock inputs that have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked meaning that they have to be exactly at the same frequency, or at a fractional frequency relationship to each other. When hitless switching is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during a input switch. When disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature supports clock frequencies down to the minimum input frequency of 8 kHz. 5.6.4. Glitchless Input Switching The DSPLL has the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if enabled. The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output during the transition. 5.6.5. Input Configuration and Terminations Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown in Figure 14. Differential signals must be ac-coupled, while single-ended LVCMOS signals can be ac or dc-coupled. Unused inputs can be disabled and left unconnected when not in use. 32 Rev. 1.0 Si5345/44/42 Standard AC Coupled Differential LVDS 50 100 Si5345/44/42 Standard INx 50 3.3V, 2.5V LVDS or CML INx Pulsed CMOS Standard AC Coupled Differential LVPECL 50 INx Si5345/44/42 Standard 100 INx 50 3.3V, 2.5V LVPECL Pulsed CMOS Standard AC Coupled Single Ended 50 INx 3.3V, 2.5V, 1.8V LVCMOS Si5345/44/42 Standard INx Pulsed CMOS Pulsed CMOS DC Coupled Single Ended R1 Si5345/44/42 50 INx 3.3V, 2.5V, 1.8V LVCMOS VDD 1.8V 2.5V 3.3V R2 R1 () 549 680 750 R2 () 442 324 243 Standard INx Pulsed CMOS Figure 14. Termination of Differential and LVCMOS Input Signals Rev. 1.0 33 Si5345/44/42 5.6.6. Synchronizing to Gapped Input Clocks The DSPLL supports locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is shown in Figure 15. For more information on gapped clocks, see “AN561: Introduction to Gapped Clocks and PLLs”. Gapped Input Clock Periodic Output Clock 100 MHz clock 1 missing period every 10 90 MHz non-gapped clock 100 ns 100 ns DSPLL 1 2 3 4 5 6 7 8 9 1 10 Period Removed 10 ns 2 3 4 5 6 7 8 9 11.11111... ns Figure 15. Generating an Averaged Clock Output Frequency from a Gapped Clock Input A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every 8. Locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification in Table 8 when the switch occurs during a gap in either input clock. 5.7. Fault Monitoring All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in Figure 16. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is also a Loss Of Lock (LOL) indicator which is asserted when the DSPLL loses synchronization. XA XB Si5345/44/42 OSC IN0 IN0 IN1 IN1 IN2 IN2 IN3/FB_IN IN3/FB_IN ÷P0 LOS OOF Precision Fast ÷P1 LOS OOF Precision Fast ÷P2 LOS OOF Precision Fast ÷P3 LOS OOF Precision Fast LOS PD Figure 16. Si5345/44/42 Fault Monitors 34 Rev. 1.0 DSPLL LOL LPF ÷M Si5345/44/42 5.7.1. Input LOS Detection The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS monitors is also available. Monitor Sticky LOS LOS LOS en Live Figure 17. LOS Status Indicators 5.7.2. XA/XB LOS Detection A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is detected. 5.7.3. OOF Detection Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its “0_ppm” reference. This OOF reference can be selected as either: XA/XB pins Any input clock (IN0, IN1, IN2, IN3) The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in Figure 18. An option to disable either monitor is also available. The live OOF register always displays the current OOF state, and its sticky register bit stays asserted until cleared. Monitor OOF Sticky en Precision LOS OOF Fast Live en Figure 18. OOF Status Indicator 5.7.3.1. Precision OOF Monitor The precision OOF monitor circuit measures the frequency of all input clocks to within ±1 ppm accuracy with respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range which is register configurable from ±2 ppm to ±500 ppm in steps of 2 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in Figure 19. In this case the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0 - IN3) as the 0 ppm OOF reference instead of the XA/XB pins is available. This option is register configurable. Rev. 1.0 35 Si5345/44/42 OOF Declared fIN Hysteresis Hysteresis OOF Cleared -6 ppm (Set) -4 ppm (Clear) +4 ppm (Clear) 0 ppm OOF Reference +6 ppm (Set) Figure 19. Example of Precise OOF Monitor Assertion and De-assertion Triggers 5.7.3.2. Fast OOF Monitor Because the precision OOF monitor needs to provide 1 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than ±4000 ppm. 5.7.4. LOL Detection The Loss Of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in Figure 20. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects the current state of the LOL monitor. LOL Monitor Sticky LOL Clear Timer LOS LOL LOL Set Live LOL DSPLL fIN PD LPF Feedback Clock ÷M Si5345/44/42 Figure 20. LOL Status Indicators 36 Rev. 1.0 Si5345/44/42 The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.2 ppm to 20000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indicated when there is less than 0.2 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there’s more than 2 ppm frequency difference is shown in Figure 21. Clear LOL Threshold Set LOL Threshold Lock Acquisition LOL Hysteresis Lost Lock LOCKED 0 0.2 2 20,000 Phase Detector Frequency Difference (ppm) Figure 21. LOL Set and Clear Thresholds Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards. An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilder Pro utility. 5.7.5. Interrupt pin (INTR) An interrupt pin (INTR) indicates a change in state of the status indicators (LOS, OOF, LOL, HOLD). Any of the status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by clearing the status register that caused the interrupt. Rev. 1.0 37 Si5345/44/42 5.8. Outputs Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats. In addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. 5.8.1. Output Crosspoint A crosspoint allows any of the output drivers to connect with any of the MultiSynths as shown in Figure 22. The crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is ready at power up. Multi N ÷ 0n Synth N0d t0 Multi N ÷ 1n Synth N1d t1 Multi N ÷ 2n Synth N2d t2 Multi N ÷ 3n Synth N3d t3 Multi N ÷ 4n Synth N4d t4 ÷R0 VDDO0 OUT0 OUT0 ÷R1 VDDO1 OUT1 OUT1 ÷R2 VDDO2 OUT2 OUT2 ÷R3 VDDO3 OUT3 OUT3 ÷R4 VDDO4 OUT4 OUT4 ÷R5 VDDO5 OUT5 OUT5 ÷R6 VDDO6 OUT6 OUT6 ÷R7 VDDO7 OUT7 OUT7 ÷R8 VDDO8 OUT8 OUT8 ÷R9 VDDO9 OUT9 OUT9 Figure 22. MultiSynth to Output Driver Crosspoint 5.8.2. Output Signal Format The differential output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. 38 Rev. 1.0 Si5345/44/42 5.8.3. Differential Output Terminations Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards. The differential output drivers support both ac coupled and dc coupled terminations as shown in Figure 23. DC Coupled LVDS/LVPECL VDDO = 3.3V, 2.5V, 1.8V 50 OUTx 100 OUTx 50 Si5345/44/42 AC Coupled LVPECL AC Coupled LVDS/LVPECL VDD – 1.3V VDDO = 3.3V, 2.5V, 1.8V VDDO = 3.3V, 2.5V 50 OUTx 50 OUTx 100 OUTx 50 50 OUTx 50 50 Internally self-biased Si5345/44/42 Si5345/44/42 Figure 23. Supported Differential Output Terminations 5.8.4. LVCMOS Output Terminations LVCMOS outputs are dc-coupled as shown in Figure 24. 3.3V, 2.5V, 1.8V LVCMOS VDDO = 3.3V, 2.5V, 1.8V 50 OUTx Rs OUTx 50 Si5345/44/42 Rs Figure 24. LVCMOS Output Terminations Rev. 1.0 39 Si5345/44/42 5.8.5. Differential Output Swing Modes There are two selectable differential output swing modes: Normal and Low-Power. Each output can support a unique mode. Please see the Si5345/44/42 Reference Manual for information on setting the differential output driver to non-standard amplitudes. Differential Normal Swing Mode: When an output driver is configured in normal swing mode, its output swing is selectable as one of 7 settings ranging from 200 mVpp_se to 800 mVpp_se in increments of 100 mV. The output impedance in the Normal Swing Mode is 100differentialAny of the terminations shown in Figure 23 is supported in this mode. Differential Low Power Mode: When an output driver is configured in low power mode, its output swing is configurable as one of 7 settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV. The output driver is in high impedance mode and supports standard 50 PCB traces. Any of the terminations shown in Figure 23 is supported in this mode. 5.8.6. LVCMOS Output Impedance Selection Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances. A source termination resistor is recommended to help match the selected output impedance to the trace impedance, where Rs = Transmission line impedance – ZO. There are three programmable output impedance selections (CMOS1, CMOS2, CMOS3) for each VDDO options as shown in Table 16. Table 16. Typical Output Impedance (ZS) CMOS_DRIVE_Selection VDDO CMOS1 CMOS2 CMOS3 3.3 V 38 30 22 2.5 V 43 35 24 1.8 V — 46 31 5.8.7. LVCMOS Output Signal Swing The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. Each output driver automatically detects the voltage on the VDDO pin to properly determine the correct output voltage. 5.8.8. LVCMOS Output Polarity When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTx). By default the clock on the OUTx pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configurable enabling complementary clock generation and/or inverted polarity with respect to other output drivers. 40 Rev. 1.0 Si5345/44/42 5.8.9. Output Enable/Disable The OE pin provides a convenient method of disabling or enabling the output drivers. When the OE pin is held high all outputs will be disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be individually disabled through register control. 5.8.10. Output Driver State When Disabled The disabled state of an output driver is configurable as: disable low, disable high, or disable high-impedance. 5.8.11. Synchronous Output Disable Feature The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the period to complete. 5.8.12. Output Skew Control (t0 – t4) The Si5345 uses independent MultiSynth dividers (N0 - N4) to generate up to 5 unique frequencies to its 10 outputs through a crosspoint switch. By default all clocks are phase aligned. A delay path (t0 - t4) associated with each of these dividers is available for applications that need a specific output skew configuration. This is useful for PCB trace length mismatch compensation. The resolution of the phase adjustment is approximately 0.28 ps per step definable in a range of ±9.14 ns. Phase adjustments are register configurable. An example of generating two frequencies with unique configurable path delays is shown in Figure 25. ÷N0 t0 ÷R0 VDDO0 OUT0 OUT0 VDDO1 OUT1 OUT1 ÷N1 t1 ÷R1 ÷N2 t2 ÷R2 VDDO2 OUT2 OUT2 ÷N3 t3 ÷R3 VDDO3 OUT3 OUT3 ÷N4 t4 ÷R4 VDDO4 OUT4 OUT4 ÷R5 VDDO5 OUT5 OUT5 ÷R6 VDDO6 OUT6 OUT6 ÷R7 VDDO7 OUT7 OUT7 ÷R8 VDDO8 OUT8 OUT8 ÷R9 VDDO9 OUT9 OUT9 Figure 25. Example of Independently Configurable Path Delays All phase delay values are restored to their default values after power-up, hard reset, or a reset using the RST pin. Phase delay default values can be written to NVM allowing a custom phase offset configuration at power-up or after power-on reset, or after a hardware reset using the RST pin. Rev. 1.0 41 Si5345/44/42 5.8.13. Zero Delay Mode A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally as shown in Figure 26. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize the input-to-output delay. The OUT9 and FB_IN pins are recommended for the external feedback connection. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for best performance. Note that automatic input clock switching and hitless switching features are not available when zero delay mode is enabled. IN0 Si5345/44/42 ÷P0 IN0 IN1 DSPLL ÷P1 IN1 IN2 PD ÷P2 IN2 LPF ÷M IN3/FB_IN 100 ÷P3 ÷R0 VDDO0 OUT0 OUT0 IN3/FB_IN ÷N0 t0 ÷R1 VDDO1 OUT1 OUT1 ÷N1 t1 ÷R2 VDDO2 OUT2 OUT2 ÷N2 t2 ÷N3 t3 ÷R7 VDDO7 OUT7 OUT7 ÷N4 t4 ÷R8 VDDO8 OUT8 OUT8 ÷R9 VDDO9 OUT9 OUT9 External Feedback Path Figure 26. Si5345 Zero Delay Mode Setup 5.8.14. Output Divider (R) Synchronization All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable phase alignment across all output drivers. Resetting the device using the RST pin or asserting the hard reset bit will have the same result. Asserting the sync register bit provides another method of realigning the R dividers without resetting the device. 42 Rev. 1.0 Si5345/44/42 5.9. Power Management Unused inputs and output drivers can be powered down when unused. Consult the Si5345/44/42 Family Reference Manual and ClockBuilder Pro configuration utility for details. 5.10. In-Circuit Programming The Si5345/44/42 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the old configuration is no longer accessible. Refer to the Si5345/44/42 Family Reference Manual for a detailed procedure for writing registers to NVM. 5.11. Serial Interface Configuration and operation of the Si5345/44/42 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or 3-wire. See the Si5345/44/42 Family Reference Manual for details. 5.12. Custom Factory Preprogrammed Parts For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into NVM. A factory pre-programmed part will generate clocks at power-up. Custom, factory-preprogrammed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly and easily request and generate a custom part number for your configuration. In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local Silicon Labs sales representative. Samples of your preprogrammed device will typically ship in about two weeks. 5.13. Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory Preprogrammed Devices As with essentially all modern software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.silabs.com, you will be notified whenever changes are made and what the impact of those changes are. This update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented in this data sheet and the Si5345/44/42 Family Reference Manual. However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register setting, but the feature or register setting is not yet available in CBPro, you must contact a Silicon Labs applications engineer for assistance. One example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock outputs. After careful review of your project file and requirements, the Silicon Labs applications engineer will email back your CBPro project file with your specific features and register settings enabled using what's referred to as the manual "settings override" feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro design report are shown in Table 17. Rev. 1.0 43 Si5345/44/42 Table 17. Setting Overrides Location Customer Name Engineering Name Type Target Dec Value Hex Value 0x0435[0] FORCE_HOLD_PLLA OLA_HO_FORCE No NVM N/A 1 0x1 0x0B48[0:4] OOF_DIV_CLK_DIS OOF_DIV_CLK_DIS User OPN&EVB 0 0x00 Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the NVM file. The flowchart for this process is shown in Figure 27. End: Place sample order Start Do I need a pre‐programmed device with a feature or setting which is unavailable in ClockBuilder Pro? No Configure device using CBPro Generate Custom OPN in CBPro Yes Contact Silicon Labs Technical Support to submit & review your non‐standard configuration request & CBPro project file Receive updated CBPro project file from Silicon Labs with “Settings Override” Yes Load project file into CBPro and test Does the updated CBPro Project file match your requirements? Figure 27. Process for Requesting Non-Standard CBPro Features 44 Rev. 1.0 Si5345/44/42 6. Register Map The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessible registers, such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such as frequency configuration, and general device settings. A high level map of the registers is shown in “6.2. High-Level Register Map” . Refer to the Si5345/44/42 Family Reference Manual for a complete list of register descriptions and settings. Silicon Labs strongly recommends using ClockBuilder Pro to create and manage register settings. 6.1. Addressing Scheme The device registers are accessible using a 16-bit address which consists of an 8-bit page address + 8-bit register address. By default the page address is set to 0x00. Changing to another page is accomplished by writing to the ‘Set Page Address’ byte located at address 0x01 of each page. 6.2. High-Level Register Map Table 18. High-Level Register Map 16-Bit Address Content 8-bit Page Address 8-bit Register Address Range 00 00 Revision IDs 01 Set Page Address 02–0A Device IDs 0B–15 Alarm Status 17–1B INTR Masks 1C Reset controls 1D FINC, FDEC Control Bits 2B SPI (3-Wire vs 4-Wire) 2C–E1 Alarm Configuration E2–E4 NVM Controls FE Device Ready Status 01 Set Page Address 08–3A Output Driver Controls 41–42 Output Driver Disable Masks FE Device Ready Status 01 Set Page Address 02–05 XTAL Frequency Adjust 08–2F Input Divider (P) Settings 30 Input Divider (P) Update Bits 47–6A Output Divider (R) Settings 6B–72 User Scratch Pad Memory FE Device Ready Status 01 02 Rev. 1.0 45 Si5345/44/42 Table 18. High-Level Register Map (Continued) 16-Bit Address 8-bit Page Address 8-bit Register Address Range 03 01 Set Page Address 02–37 MultiSynth Divider (N0–N4) Settings 0C MultiSynth Divider (N0) Update Bit 17 MultiSynth Divider (N1) Update Bit 22 MultiSynth Divider (N2) Update Bit 2D MultiSynth Divider (N3) Update Bit 38 MultiSynth Divider (N4) Update Bit 39–58 FINC/FDEC Settings N0 - N4 59–62 Output Delay (t) Settings FE Device Ready Status 04 87 Zero Delay Mode Set Up 05 0E - 14 Fast Lock Loop Bandwidth 15–1F Feedback Divider (M) Settings 2A Input Select Control 2B Fast Lock Control 2C–35 Holdover Settings 36 Input Clock Switching Mode Select 38–39 Input Priority Settings 3F Holdover History Valid Data 06–08 00–FF Reserved 09 01 Set Page Address 1C Zero Delay Mode Settings 43 Control I/O Voltage Select 49 Input Settings 00–FF Reserved 10–FF 46 Content Rev. 1.0 Si5345/44/42 7. Pin Descriptions IN0 IN3/FB_IN IN3/FB_IN VDD OUT9 OUT9 VDDO9 RSVD RSVD OUT8 OUT8 VDDO8 OUT7 OUT7 VDDO7 63 62 61 60 59 58 57 56 55 53 52 51 50 49 54 IN0 64 Si5345 Top View IN1 1 48 FINC IN1 2 47 LOL IN_SEL0 3 46 VDD IN_SEL1 4 45 OUT6 RSVD 5 44 OUT6 RST 6 43 VDDO6 X1 7 42 OUT5 XA 8 41 OUT5 XB 9 40 VDDO5 X2 10 39 I2C_SEL OE 11 38 OUT4 INTR 12 37 OUT4 VDDA 13 36 VDDO4 IN2 14 35 OUT3 IN2 15 34 OUT3 SCLK 16 33 VDDO3 19 20 21 22 23 24 25 26 27 28 29 30 31 A0/CS RSVD RSVD VDDO0 OUT0 OUT0 FDEC VDDO1 OUT1 OUT1 VDDO2 OUT2 OUT2 LOS3 LOS2 VDDS 36 35 34 37 VDD I2C_SEL IN_SEL1 38 IN3/FB_IN VDD 41 39 IN3/FB_IN 42 40 IN0 43 VDDO3 34 IN0 OUT3 35 44 OUT3 36 37 VDD I2C_SEL IN_SEL1 IN3/FB_IN VDD 38 IN3/FB_IN 41 39 IN0 42 40 IN0 43 32 18 Si5342 44QFN Top View Si5344 44QFN Top View 44 VDD 17 A1/SDO SDA/SDIO GND Pad INTR IN1 1 33 INTR 2 32 31 VDD OUT2 IN1 IN_SEL0 3 31 VDD LOS1 IN1 1 33 IN1 2 32 IN_SEL0 3 X1 4 30 OUT2 X1 4 30 LOS0 XA 5 29 VDDO2 XA 5 29 VDDS XB 6 28 LOS_XAXB XB 6 28 LOS_XAXB X2 VDDA 7 27 LOL 7 27 LOL 8 26 VDDS X2 VDDA 8 26 VDDS VDDA 9 25 OUT1 VDDA 9 25 OUT1 IN2 10 24 OUT1 IN2 10 24 OUT1 IN2 11 23 VDDO1 IN2 11 23 VDDO1 15 16 17 18 19 20 21 22 A1/SDO A0/CS RST VDDO0 OUT0 OUT0 VDD NC NC 14 22 SCLK 21 VDD 13 20 OUT0 12 19 OUT0 GND Pad OE SDA/SDIO 18 16 A0/CS 17 15 A1/SDO RST 14 SCLK VDDO0 13 12 OE SDA/SDIO GND Pad Rev. 1.0 47 Si5345/44/42 Table 19. Si5345/44/42 Pin Descriptions Pin Number Pin Type1 Function 5 I 6 6 I Crystal Input Input pins for external crystal (XTAL). Alternatively these pins can be driven with an external reference clock (REFCLK). An internal register bit selects XTAL or REFCLK mode. Default is XTAL mode. 7 4 4 I X2 10 7 7 I IN0 63 43 43 I IN0 64 44 44 I IN1 1 1 1 I IN1 2 2 2 I IN2 14 10 10 I IN2 15 11 11 I IN3/FB_IN 61 41 41 I IN3/FB_IN 62 42 42 I Pin Name Si5345 Si5344 Si5342 XA 8 5 XB 9 X1 Inputs XTAL Shield Connect these pins directly to the XTAL ground pins. X1, X2 and the XTAL ground pins should be separated from the PCB ground plane. Refer to the Si5345/44/42 Family Reference Manual for layout guidelines. These pins should be left disconnected when connecting XA/XB pins to an external reference clock (REFCLK). Clock Inputs These pins accept an input clock for synchronizing the device. They support both differential and single-ended clock signals. Refer to "5.6.5. Input Configuration and Terminations" on page 32 for input termination options. These pins are high-impedance and must be terminated externally. The negative side of the differential input must be grounded through a capacitor when accepting a single-ended clock. Clock Input 3/External Feedback Input By default these pins are used as the fourth clock input (IN3/IN3). They can also be used as the external feedback input (FB_IN/FB_IN) for the optional zero delay mode. See section "5.8.13. Zero Delay Mode" on page 42 for details on the optional zero delay mode. Notes: 1. I = Input, O = Output, P = Power 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. 4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names. 48 Rev. 1.0 Si5345/44/42 Table 19. Si5345/44/42 Pin Descriptions (Continued) Pin Number Pin Type1 Function 20 O 19 19 O 28 25 25 O OUT1 27 24 24 O OUT2 31 31 — O Output Clocks These output clocks support a programmable signal swing and common mode voltage. Desired output signal format is configurable using register control. Termination recommendations are provided in “5.8.3. Differential Output Terminations” and section “5.8.4. LVCMOS Output Terminations” . Unused outputs should be left unconnected. OUT2 30 30 — O OUT3 35 36 — O OUT3 34 35 — O OUT4 38 — — O OUT4 37 — — O OUT5 42 — — O OUT5 41 — — O OUT6 45 — — O OUT6 44 — — O OUT7 51 — — O OUT7 50 — — O OUT8 54 — — O OUT8 53 — — O OUT9 59 — — O OUT9 58 — — O Pin Name Si5345 Si5344 Si5342 OUT0 24 20 OUT0 23 OUT1 Outputs Notes: 1. I = Input, O = Output, P = Power 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. 4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names. Rev. 1.0 49 Si5345/44/42 Table 19. Si5345/44/42 Pin Descriptions (Continued) Pin Number Pin Name Si5345 Si5344 Si5342 Pin Type1 Function Serial Interface I2C_SEL 39 38 38 I I2C Select2 This pin selects the serial interface mode as I2C (I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally pulled up by a ~ 20 k resistor to the voltage selected by the IO_VDD_SEL register bit. SDA/SDIO 18 13 13 I/O Serial Data Interface2 This is the bidirectional data pin (SDA) for the I2C mode, or the bidirectional data pin (SDIO) in the 3-wire SPI mode, or the input data pin (SDI) in 4-wire SPI mode. When in I2C mode, this pin must be pulled-up using an external resistor of at least 1 k. No pull-up resistor is needed when is SPI mode. Tie low when unused. A1/SDO 17 15 15 I/O Address Select 1/Serial Data Output2 In I2C mode this pin functions as the A1 address input pin and does not have an internal pull-up or pull-down resistor. In 4-wire SPI mode this is the serial data output (SDO) pin and drives high to the voltage selected by the IO_VDD_SEL bit. Leave disconnected when unused. SCLK 16 14 14 I Serial Clock Input2 This pin functions as the serial clock input for both I2C and SPI modes. When in I2C mode, this pin must be pulled-up using an external resistor of at least 1 k. No pull-up resistor is needed when in SPI mode. Tie high or low when unused. A0/CS 19 16 16 I Address Select 0/Chip Select2 This pin functions as the hardware controlled address A0 in I2C mode. In SPI mode, this pin functions as the chip select input (active low). This pin is internally pulled-up by a ~20 k resistor and can be left unconnected when not in use. Notes: 1. I = Input, O = Output, P = Power 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. 4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names. 50 Rev. 1.0 Si5345/44/42 Table 19. Si5345/44/42 Pin Descriptions (Continued) Pin Number Pin Name Si5345 Si5344 Si5342 Pin Type1 Function Control/Status INTR 12 33 33 O Interrupt2 This pin is asserted low when a change in device status has occurred. It should be left unconnected when not in use. RST 6 17 17 I Device Reset2 Active low input that performs power-on reset (POR) of the device. Resets all internal logic to a known state and forces the device registers to their default values. Clock outputs are disabled during reset. This pin is internally pulled-up and can be left unconnected when not in use. OE 11 12 12 I Output Enable2 This pin disables all outputs when held high. This pin is internally pulled low and can be left unconnected when not in use. LOL 47 — — O Loss Of Lock (Si5345)2 This output pin indicates when the DSPLL is locked (high) or out-of-lock (low). It can be left unconnected when not in use. — 27 27 O Loss Of Lock (Si5344/42)3 This output pin indicates when the DSPLL is locked (high) or out-of-lock (low). It can be left unconnected when not in use. LOS0 — — 30 O Loss Of Signal for IN03 This pin indicate a loss of clock at the IN0 pin when low. LOS1 — — 31 O Loss Of Signal for IN13 This pin indicate a loss of clock at the IN1 pin when low. LOS2 — — 35 O Loss Of Signal for IN23 This pin indicate a loss of clock at the IN2 pin when low. LOS3 — — 36 O Loss Of Signal for IN33 This pin indicate a loss of clock at the IN3 pin when low. LOS_XAXB — 28 28 O Loss Of Signal on XA/XB Pins3 This pin indicates a loss of signal at the XA/XB pins when low. Notes: 1. I = Input, O = Output, P = Power 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. 4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names. Rev. 1.0 51 Si5345/44/42 Table 19. Si5345/44/42 Pin Descriptions (Continued) Pin Number Pin Type1 Function — I Frequency Increment Pin2 This pin is used to step-up the output frequency of a selected output. The affected output and its frequency change step size is register configurable. This pin is internally pulled low and can be left unconnected when not in use. — — I Frequency Decrement Pin2 This pin is used to step-down the output frequency of a selected output. The affected output driver and its frequency change step size is register configurable. This pin is internally pulled low and can be left unconnected when not in use. 3 3 3 I IN_SEL1 4 37 37 I Input Reference Select2 The IN_SEL[1:0] pins are used in manual pin controlled mode to select the active clock input as shown in Table 15 on page 31. These pins are internally pulled low. RSVD 5 — — — 20 — — — 21 — — — 55 — — — 56 — — — — 22 22 Pin Name Si5345 Si5344 Si5342 FINC 48 — FDEC 25 IN_SEL0 NC Reserved These pins are connected to the die. Leave disconnected. No Connect These pins are not connected to the die. Leave disconnected. Notes: 1. I = Input, O = Output, P = Power 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. 4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names. 52 Rev. 1.0 Si5345/44/42 Table 19. Si5345/44/42 Pin Descriptions (Continued) Pin Number Pin Type1 Function 21 P 32 32 P 60 39 39 P — 40 40 P Core Supply Voltage The device operates from a 1.8 V supply. A 1.0 µF bypass capacitor should be placed very close to this pin. See the Si5345/44/42 Family Reference Manual for power supply filtering recommendations. 13 8 8 P — 9 9 P — 26 26 P — — 29 P — — 34 P VDDO0 22 18 18 P VDDO1 26 23 23 P VDDO2 29 29 — P VDDO3 33 34 — P VDDO4 36 — — P VDDO5 40 — — P VDDO6 43 — — P VDDO7 49 — — P VDDO8 52 — — P VDDO9 57 — — P GND PAD — — — P Pin Name Si5345 Si5344 Si5342 32 21 46 Power VDD VDDA VDDS Core Supply Voltage 3.3 V This core supply pin requires a 3.3 V power source. A 1 µF bypass capacitor should be placed very close to this pin. See the Si5345/44/42 Family Reference Manual for power supply filtering recommendations. Status Output Voltage The voltage on this pin determines VOL/VOH on the Si5342/44 LOL_A and LOL_B outputs. Connect to either 3.3 V or 1.8 V. A 1.0 µF bypass capacitor should be placed very close to this pin. Output Clock Supply Voltage Supply voltage (3.3 V, 2.5 V, 1.8 V) for OUTn, OUTn outputs. For unused outputs, leave VDDO pins unconnected. An alternative option is to connect the VDDO pin to a power supply and disable the output driver to minimize current consumption. Ground Pad This pad provides connection to ground and must be connected for proper operation. Use as many vias as practical and keep the via length to an internal ground plan as short as possible. Notes: 1. I = Input, O = Output, P = Power 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. 4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names. Rev. 1.0 53 Si5345/44/42 8. Ordering Guide Ordering Part Number (OPN) Number of Input/Output Clocks Output Clock Frequency Range (MHz) Supported Frequency Synthesis Modes Package 4/10 0.001 to 712.5 MHz Integer Fractional 64-Lead 9x9 QFN –40 to 85 °C 44-Lead 7x7 QFN –40 to 85 °C 44-Lead 7x7 QFN –40 to 85 °C Evaluation Board — Temperature Range Si5345 Si5345A-B-GM1,2 Si5345B-B-GM1,2 0.001 to 350 MHz Si5345C-B-GM1,2 0.001 to 712.5 MHz Si5345D-B-GM1,2 0.001 to 350 MHz Integer Only Si5344 Si5344A-B-GM1,2 4/4 1,2 Si5344B-B-GM 0.001 to 712.5 MHz 0.001 to 350 MHz Si5344C-B-GM1,2 0.001 to 712.5 MHz Si5344D-B-GM1,2 0.001 to 350 MHz Integer Fractional Integer Only Si5342 Si5342A-B-GM1,2 4/2 0.001 to 712.5 MHz Si5342B-B-GM1,2 0.001 to 350 MHz Si5342C-B-GM1,2 0.001 to 712.5 MHz Si5342D-B-GM1,2 0.001 to 350 MHz Integer Fractional Integer Only Si5345/44/42-EVB Si5345-EVB — — — Si5344-EVB Si5342-EVB Notes: 1. Add an R at the end of the OPN to denote tape and reel ordering options. 2. Custom, factory preprogrammed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuilder Pro software utility. Custom part number format is “Si5345A-Bxxxxx-GM” where “xxxxx” is a unique numerical sequence representing the preprogrammed configuration. 54 Rev. 1.0 Si5345/44/42 8.1. Ordering Part Number Fields Si534fg-Rxxxxx-GM Timing product family f = Jitter attenuator family member (5, 4, 2) g = Device grade (A, B, C, D) Product Revision* Custom ordering part number (OPN) sequence ID** Package, ambient temperature range (QFN, -40°C to +85°C) *See Ordering Guide table for current product revision ** 5 digits; assigned by ClockBuilder Pro Rev. 1.0 55 Si5345/44/42 9. Package Outlines 9.1. Si5345 9x9 mm 64-QFN Package Diagram Figure 28 illustrates the package details for the Si5345. Table 20 lists the values for the dimensions shown in the illustration. Figure 28. 64-Pin Quad Flat No-Lead (QFN) Table 20. Package Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 9.00 BSC 5.10 5.20 e 0.50 BSC E 9.00 BSC 5.30 E2 5.10 5.20 5.30 L 0.30 0.40 0.50 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 56 Rev. 1.0 Si5345/44/42 9.2. Si5344 and Si5342 7x7 mm 44-QFN Package Diagram Figure 29 illustrates the package details for the Si5344 and Si5342. Table 21 lists the values for the dimensions shown in the illustration. Figure 29. 44-Pin Quad Flat No-Lead (QFN) Table 21. Package Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 7.00 BSC 5.10 5.20 e 0.50 BSC E 7.00 BSC 5.30 E2 5.10 5.20 5.30 L 0.30 0.40 0.50 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 57 Si5345/44/42 10. PCB Land Pattern Figure 30 illustrates the PCB land pattern details for the devices. Table 22 lists the values for the dimensions shown in the illustration. Si5345 Si5344 and Si5342 Figure 30. PCB Land Pattern Table 22. PCB Land Pattern Dimensions Dimension Si5345 (Max) Si5344/42 (Max) C1 8.90 6.90 C2 8.90 6.90 E 0.50 0.50 X1 0.30 0.30 Y1 0.85 0.85 X2 5.30 5.30 Y2 5.30 5.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication Allowance of 0.05 mm. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 8. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad. Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 58 Rev. 1.0 Si5345/44/42 11. Top Marking Si534fgRxxxxx-GM YYWWTTTTTT e4 TW Si534fgRxxxxx-GM YYWWTTTTTT TW e4 64-QFN Line Characters 1 Si534fg- 44-QFN Description Base part number and Device Grade for Any-frequency, Any-output, Jitter Cleaning Clock (single PLL): f = 5: 10-output Si5345: 64-QFN f = 4: 4-output Si5344: 44-QFN f = 2: 2-output Si5342: 44-QFN g = Device Grade (A, B, C, D). See “8. Ordering Guide” for more information. – = Dash character. 2 Rxxxxx-GM 3 YYWWTTTTTT 4 R = Product revision. (Refer to “8. Ordering Guide” for latest revision). xxxxx = Customer specific NVM sequence number. Optional NVM code assigned for custom, factory pre-programmed devices. Characters are not included for standard, factory default configured devices. See Ordering Guide for more information. -GM = Package (QFN) and temperature range (–40 to +85 °C) YYWW = Characters correspond to the year (YY) and work week (WW) of package assembly. TTTTTT = Manufacturing trace code. Circle w/ 1.6 mm Pin 1 indicator; left-justified (64-QFN) or 1.4 mm (44-QFN) diameter e4 TW Pb-free symbol; Center-Justified TW = Taiwan; Country of Origin (ISO Abbreviation) Rev. 1.0 59 Si5345/44/42 12. Device Errata Please log in or register at www.silabs.com to access the device errata document. 60 Rev. 1.0 Si5345/44/42 DOCUMENT CHANGE LIST Revision 0.9 to Revision 0.95 Removed advanced product information revision history. Updated “8. Ordering Guide” and changed references to Revision B. Updated parametric tables 2, 3, 5, 6, 7, and 8 to reflect production characterization. Updated terminology to align with ClockBuilder Pro software. Corrected Table 3 references and specifications from “LVCMOS - DC coupled” to “Pulsed CMOS DC-Coupled”. Corrected Table 9 I2C data hold time specification to 100 ns from 5 µs. Revision 0.95 to Revision 1.0 Corrected minimum input frequency spec from 10 to 0.008 MHz. Corrected XAXB minimum input voltage swing spec from 350 to 365 mV. Corrected FINC and FDEC update rate from 1 ns to 1 μs. Corrected PLL lock time spec to 500 ms typical and 600 ms max. Added common-mode voltage spec for 1.8 V LVDS (Sub-LVDS) in Table 5. Updated spec delay time between chip selects in Tables 10 and 11. Removed SPI Tr/Tf from Table 10. Corrected AC Test Configuration Schematic. Corrected INx voltage swing spec and split into single-ended and different inputs requirements. Added typical crosstalk spec for Si5342 and Si5344. Updated pin descriptions for serial interface. Updated SPI timing diagrams and spec. Updated max IDDOx spec for LVDS output from 17 to 18 mA. Updated max normal mode LVPECL output voltage swing from 950 to 1000 mVpp_se. Updated max VCM specs. Updated output-to-output skew specification. Rev. 1.0 61 Si5345/44/42 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 62 Rev. 1.0