TN-49-03: RLDRAM 2 Clocking Strategies Introduction Technical Note RLDRAM® 2 Clocking Strategies Introduction The Micron® reduced latency DRAM 2 (RLDRAM® 2) addresses the high-bandwidth memory requirements for communication and data storage applications. This is achieved through the use of a flexible clocking strategy that incorporates a series of clock pairs for managing both input and output data. A delay-lock loop (DLL) is utilized to synchronize output data. The RLDRAM 2 device requires a differential input master clock pair, CK and CK#, and differential input data clock pairs, DKx and DKx#. The RLDRAM 2 has output data clock pairs, QKx and QKx#, that are derived from the input master clock pair. For complete details regarding RLDRAM 2, consult Micron’s component data sheets and technical note “TN-49-01: RLDRAM 2 Design Guide,” located on Micron’s Web site: www.micron.com. This technical note addresses the operation of the device outside the specified range of clock periods and the timing changes that occur in this mode of operation. It also addresses the possibility of running the device within the specified range of tCK with the DLL off (although closing timing could become a concern). DLL Considerations The RLDRAM 2 device has an on-chip DLL to generate the edge-aligned data and output data clock signals. This results in a minimum required frequency for stable DLL operation for all configurations on the RLDRAM 2 device. This is shown in the data sheet as t CK (MAX). At frequencies below the minimum clock cycle time, the DLL delay becomes too great, eventually resulting in the DLL being unable to maintain lock. As a result, the DLL is susceptible to noise, can alias, lose lock, re-lock, skip a clock, etc.—potentially causing the RLDRAM 2 device to not output the entire desired data cycle, and certainly causing the data to shift. For these frequencies, using the DLL RESET (disable) function of the mode register would result in more reliable output data. Although this affects the output data clock skew in regard to the master clock, QK to output data times do not change. PDF: 09005aef829d1640/Source: 09005aef829d16c5 TN4903.fm - Rev. A 10/12 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All information discussed herein is provided on an “as is” basis, without warranties of any kind. TN-49-03: RLDRAM 2 Clocking Strategies Operating the DLL Outside the AC Timing Specification Operating the DLL Outside the AC Timing Specification During initial system debug it is common to run the system much more slowly so events can be more easily captured. The RLDRAM 2 device employs a mode register bit that can select between enabling or disabling the DLL (default is disabled). The data sheet shows the safe value of the clock period in which the device can operate with the DLL enabled. Any operation below this range must be done with the DLL disabled. Figure 1 shows the timing relationship between CK and QK for the RLDRAM 2 device during normal operation, while Figure 2 demonstrates the effects on the tCKQK timing with the DLL disabled. No change occurs in the relationship between QK and the output data when the DLL is disabled. Figure 1: Clock-to-Output Data Clock Timing with the DLL Enabled CK# CK tCKQK (MIN) Case 1: tCKQK (MIN) QK# QK Case 1: tCKQK (MAX) tCKQK (MAX) QK# QK Figure 2: Clock-to-Output Data Clock Timing with the DLL Disabled CK# CK Case 1: tCKQK (MIN) tCKQK (MIN) = 0 QK# QK Case 1: tCKQK (MAX) tCKQK (MAX) QK# QK PDF: 09005aef829d1640/Source: 09005aef829d16c5 TN4903.fm - Rev. A 10/12 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. TN-49-03: RLDRAM 2 Clocking Strategies Operating the DLL Outside the AC Timing Specification Table 1 shows the timing parameters for the various speed grades of the RLDRAM 2 device with and without the DLL enabled. Note the tCK (DLL enabled) parameter for all speed grades. The RLDRAM 2 device can be operated in this range while achieving the t CKQK (DLL enabled) parameter. Operation below this frequency range requires the DLL to be disabled due to a dead band of frequencies in which the DLL is unable to retain lock, at which time the tCKQK (DLL disabled) parameter is met. Note also that no other timing parameters change when the DLL is disabled on the RLDRAM 2 device. Table 1: Timing Parameters -1.8 Symbol t CK (DLL enabled) tCK (DLL disabled)1, 2, 3 tCKH tCKL tCKQK (DLL enabled) tCKQK (DLL disabled)3, 4 tQKQ tQKQ0, tQKQ1 tQKVLD tQKH tQKL tQHP tDVW tCKDK tDS Notes: -2.5/-25E -3.3 -5 Min Max Min Max Min Max Min Max Units 1.875 2.7 2.5 5.7 3.3 5.7 5.0 5.7 ns 1.875 488 2.5 488 3.3 488 5.0 488 ns 0.45 0.45 –0.2 0.55 0.55 0.2 0.45 0.45 –0.25 0.55 0.55 0.25 0.45 0.45 –0.3 0.55 0.55 0.3 0.45 0.45 –0.5 0.55 0.55 0.5 tCK 0 3.5 0 3.5 0 3.5 0 3.5 ns –0.22 –0.12 –0.22 0.9 0.9 0.22 0.12 0.22 1.1 1.1 0.4 0.3 0.4 1.1 1.1 ns ns ns tCKH tCKL ns ns ns ns –0.3 0.3 –0.35 0.35 –0.4 –0.2 0.2 –0.25 0.25 –0.3 –0.3 0.3 –0.35 0.35 –0.4 0.9 1.1 0.9 1.1 0.9 0.9 1.1 0.9 1.1 0.9 Minimum for all speed grades: MIN (tQKH, tQKH) Minimum for all speed grades: tQHP - (tQKQx [MAX] + |tQKQx [MIN]|) –0.3 0.3 –0.3 0.5 –0.3 1.0 –0.3 0.17 0.25 0.3 0.4 1.5 tCK ns 1. Although running the device at the minimum tCK with the DLL disabled is possible, closing timing may not be possible at these higher frequencies. 2. tCK MAX is required to ensure data retention of a single address location. 3. These AC timing parameters are for reference only and are not tested. 4. tCKQK (DLL disabled) is independent of the clock frequency. 5. tCKQK (DLL disabled) can vary over its full range due to shifts in process, voltage, and temperature. Figure 3 on page 4 shows an example of the data valid window and output data timing for the DQ signals to their respective QK clocks on the x36 CIO device. As previously discussed, these parameters do not change whether the DLL is enabled or disabled. PDF: 09005aef829d1640/Source: 09005aef829d16c5 TN4903.fm - Rev. A 10/12 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. TN-49-03: RLDRAM 2 Clocking Strategies Operating the DLL Outside the AC Timing Specification Figure 3: Data Valid Window and Output Data Timing QK0# QK0 tQKQ0 (MAX) tQHP tQKQ0 (MAX) tQKQ0 (MIN) tQHP tQKQ0 (MAX) tQKQ0 (MIN) tQHP tQKQ0 (MAX) tQKQ0 (MIN) tQHP tQKQ0 (MIN) Lower Word DQ0 . . . . . . . . . . . . . . . DQ17 DQ (last valid data) DQ (first valid data) All DQ and QKs collectively tDVW tDVW tDVW tDVW QK1# QK1 tQKQ1 (MAX) tQHP tQKQ1 (MAX) tQKQ1 (MIN) tQHP tQKQ1 (MAX) tQKQ1 (MIN) tQHP tQKQ1 (MAX) tQKQ1 (MIN) tQHP tQKQ1(MIN) Upper Word DQ18 . . . . . . . . . . . . . . . DQ35 DQ (last valid data) DQ (first valid data) All DQ and QKs collectively tDVW PDF: 09005aef829d1640/Source: 09005aef829d16c5 TN4903.fm - Rev. A 10/12 EN tDVW 4 tDVW tDVW Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. TN-49-03: RLDRAM 2 Clocking Strategies What Happens in the Dead Band What Happens in the Dead Band This section provides insight into the device’s internal operation and does not constitute guaranteed data timing. Obviously the RLDRAM 2 device needs to have some margin designed in; otherwise, Micron could never guarantee any specifications. Here is what happens in the dead band between DLL locked and unlocked: Using the -5 (200 MHz) device as an example, for a clock period of 5–5.7ns, everything runs in accordance with the AC timing specifications. As the clock period increases above 5.7ns, the DLL cannot achieve a lock on the incoming clock, causing the RLDRAM 2 device to produce larger uncertainty in the output data until a point at which the DLL gain becomes too large to remain stable— potentially causing the RLDRAM 2 device to miss outputting a data cycle. These undesirable frequencies require the DLL to be disabled in the mode register for operation. Disabling the DLL Through the Mode Register DLL reset is selected with bit A7 of the mode register, as shown in Figure 4. The default setting for this option is LOW, whereby the DLL is disabled. If A7 is set HIGH, 1,024 cycles (5µs at 200 MHz) are needed before a READ command can be issued, enabling the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tCKQK parameter. If the DLL is not enabled through the mode register, these extra cycles are not required. Figure 4: Mode Register Bit Map A17 ..... A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A17–A10 9 8 7 6 5 Reserved ODT IM DLL NA AM 4 3 2 1 0 BL Configuration M9 On-Die Termination 0 Off (default) 1 On Mode Register (Mx) M2 M1 M0 Configuration M7 DLL Reset 0 0 0 1 (default) 0 0 1 0 1 0 1 2 0 1 1 3 0 No 1 0 0 1 Yes 1 0 1 4 5 1 1 0 Reserved 1 1 1 Reserved M8 Drive Impedance 0 Internal 50 (default) 1 External (ZQ) M4 M3 PDF: 09005aef829d1640/Source: 09005aef829d16c5 TN4903.fm - Rev. A 10/12 EN Address Bus Burst Length 0 0 2 (default) 0 1 4 1 0 1 1 8 Reserved M5 Address MUX 0 Nonmultiplexed (default) 1 Multiplexed 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. TN-49-03: RLDRAM 2 Clocking Strategies Data Bus Transitions Data Bus Transitions Running the RLDRAM 2 device with the DLL disabled will have little-to-no effect on the WRITE functionality and timing; however, disabling the DLL does change the output timing of the DQ relative to the input clock. So instead of the DQ transitioning near or at the same time as CK, they are now delayed along with the output QK clocks. The READ latency (RL) remains the same, but the change in the tCKQK times causes the data to appear up to 3.5ns after the CK transition. At higher frequencies, this can cause a need for an additional clock cycle when going from a READ command to a WRITE command. Figure 5 demonstrates this READ-to-WRITE transition. Figure 5: READ-to-WRITE Data Bus Transition T0 T1 T2 T3 T4 T5 T6 T7 T8 COMMAND READ NOP WRITE NOP NOP NOP NOP NOP NOP NOP ADDRESS Bank a, Add n CK# CK Bank b, Add n DM tCKQK (DLL-off) QK# QK DK# DK RL = 4 WL = RL + 1 = 5 QVLD Da n DQ Qb n Potential data bus contention depending on clock frequency TRANSITIONING DATA DON’T CARE We can calculate the worst-case turnaround time on the data bus with the following equation: tCT = tCK - tCKQK (DLL off [MAX]) - tQKQ (MAX) t DS (MIN) - |tCKDK (MIN)| (EQ 1) This parameter tCT can be seen in Figure 6 on page 7. If this value is negative, it is obvious that an extra wait cycle is required on the command and address bus when going from a READ command to a WRITE command. However, this does not take into account other system variables, including signal-flight time, data-hold time at the controller, and output times of the controller. If we assume a clock cycle time of 5ns and worst-case parameters for the -5 speed grade, we see the following: t CT = 5ns - 3.5ns - 0.4ns - 0.4ns - 0.3ns (EQ 2) Here we can tell that there is 400ps to turn the data bus around at the RLDRAM 2 device. Again, this does not take into account a number of additional timing penalties, including the flight time for the READ from the RLDRAM 2 device to get to the controller and the WRITE from the controller to get to the RLDRAM 2 device. Including these additional timing penalties will help determine the need for the extra cycle to turn the data bus around. PDF: 09005aef829d1640/Source: 09005aef829d16c5 TN4903.fm - Rev. A 10/12 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. TN-49-03: RLDRAM 2 Clocking Strategies Conclusion Figure 6: READ-to-WRITE Contention at the RLDRAM 2 Device tCKH tCKL tCK CK# CK tCKQK(DLL-off MAX) QK# QK tQKQ(MAX) DQ tDS Da n Qb n tCT DK# DK tCKDK(MIN) TRANSITIONING DATA Conclusion The RLDRAM 2 device is equipped with an on-chip DLL to guarantee proper data and data clock generation and alignment. In order to do this, the RLDRAM has a maximum clock cycle time requirement that is needed to ensure stable DLL operation. Violation of the tCK (MAX) parameter could cause any number of undesirable scenarios, compromising the proper function of the RLDRAM 2 device. However, as discussed in this document, it is possible to operate the RLDRAM 2 device while violating the tCK (MAX) parameter. This requires the disabling of the DLL by way of the mode register. Since the primary reason for including the DLL disable option in the RLDRAM 2 mode resister is to enable system debug and low-frequency testing, only gross functional testing is done in this mode. Full functional testing of the RLDRAM 2 device is performed with the DLL enabled, to which all timing parameters are established, but no timing parameters are tested with the DLL disabled. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. RLDRAM is a trademark of Qimonda AG in various countries and is used by Micron Technology, Inc. under license from Qimonda AG. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef829d1640/Source: 09005aef829d16c5 TN4903.fm - Rev. A 10/12 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved.