1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Features DDR SDRAM RDIMM MT36VDDT12872 – 1GB1 MT36VDDT25672 – 2GB1 MT36VDDT51272 – 4GB For component data sheets, refer to Micron’s Web site: www.micron.com Features Figure 2: • 184-pin, registered dual in-line memory module (RDIMM) • Standard and low profile height PCB modules • Fast data transfer rates: PC2100 or PC2700 • 1GB (128 Meg x 72), 2GB (256 Meg x 72), and 4GB (512 Meg x 72) • Supports ECC error detection and correction • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O (SSTL_2-compatible) • Internal, pipelined double data rate (DDR) 2n-prefetch architecture • Bidirectional data strobe (DQS) transmitted/ received with data—that is, source-synchronous data capture • Differential clock inputs (CK and CK#) • Multiple internal device banks for concurrent operation • Dual rank • Selectable burst lengths (BL): 2, 4, or 8 • Auto precharge option • Auto refresh and self refresh modes: 7.8125µs maximum average periodic refresh interval • Serial presence-detect (SPD) with EEPROM • Selectable CAS latency (CL) for maximum compatibility • Gold edge contacts Low-Profile Layout (MO-206) PCB height: 30.48mm (1.2in) Options Marking • Operating temperature2 – Commercial (0°C ≤ TA ≤ +70°C) None – Industrial (–40°C ≤ TA ≤ +85°C) I • Package – 184-pin DIMM (standard) G – 184-pin DIMM (Pb-free) Y • Memory clock, speed, CAS latency3 – 6.0ns (167 MHz), 333 MT/s, CL = 2.5 -335 – 7.5ns (133 MHz), 266 MT/s, CL = 24 -262 – 7.5ns (133 MHz), 266 MT/s, CL = 24 -26A – 7.5ns (133 MHz), 266 MT/s, CL = 2 -265 Notes: 1. End of life. 2. Contact Micron for industrial temperature module offerings. 3. CL = CAS (READ) latency; registered mode will add one clock cycle to CL. 4. Not recommended for new designs. 184-Pin RDIMM Figures Figure 1: Standard-Height Layout (MO-206) PCB height: 43.18mm (1.7in) PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Features Table 1: Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 2.5 CL = 2 t RCD (ns) t RP (ns) t RC (ns) Notes -335 PC2700 333 266 18 18 60 1 60 -262 PC2100 266 266 15 15 -26A PC2100 266 266 20 20 65 -265 PC2100 266 200 20 20 65 Notes: Table 2: 1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications; actual DDR SDRAM device specifications are 15ns. Addressing Parameter 1GB Refresh count Row address 2GB 4GB 4K 8K 8K 8K (A0–A12) 8K (A0–A12) 16K (A0–A13) Device bank address 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Device configuration 256Mb (64 Meg x 4) 512Mb (128 Meg x 4) 1Gb (256 Meg x 4) 2K (A0–A9, A11) 4K (A0–A09, A11, A12) 4K (A0–A9, A11, A12) 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#) Column address Module rank address Table 3: Part Numbers and Timing Parameters – 1GB Modules Base device: MT46V64M4,1 256Mb DDR SDRAM Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT36VDDT12872G-335__ 1GB 128 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT36VDDT12872Y-335__ 1GB 128 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT36VDDT12872G-26A__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3 Part Number2 MT36VDDT12872G-265__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT36VDDT12872Y-265__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Table 4: Part Numbers and Timing Parameters – 2GB Modules Base device: MT46V128M4,1 512Mb DDR SDRAM Part Number2 MT36VDDT25672G-335__ Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 2GB 256 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT36VDDT25672G-262__ 2GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT36VDDT25672G-26A__ 2GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT36VDDT25672Y-26A__ 2GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT36VDDT25672G-265__ 2GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT36VDDT25672Y-265__ 2GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Notes: PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 1. The data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT36VDDT51272Y-335A2. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Features Table 5: Part Numbers and Timing Parameters – 4GB Modules Base device: MT46V256M4,1 1Gb DDR SDRAM Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT36VDDT51272G-335__ 4GB 512 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT36VDDT51272Y-335__ 4GB 512 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT36VDDT51272G-26A__ 4GB 512 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3 Part Number2 MT36VDDT51272G-265__ 4GB 512 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT36VDDT51272Y-265__ 4GB 512 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Notes: PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 1. The data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT36VDDT51272Y-335A2. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 6: Pin Assignments 184-Pin DDR RDIMM Front 184-Pin DDR RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF 24 DQ17 47 DQS8 70 VDD 93 VSS 116 VSS 139 VSS 162 DQ47 2 DQ0 25 DQS2 48 A0 71 NC 94 DQ4 117 DQ21 140 DQS17 163 NC 3 VSS 26 VSS 49 CB2 72 DQ48 95 DQ5 118 A11 141 A10 164 VDDQ 4 DQ1 27 A9 50 VSS 73 DQ49 96 VDDQ 119 DQS11 142 CB6 165 DQ52 5 DQS0 28 DQ18 51 CB3 74 VSS 97 DQS9 120 VDD 143 VDDQ 166 DQ53 6 DQ2 29 A7 52 BA1 75 NC 98 DQ6 121 DQ22 144 CB7 7 VDD 30 VDDQ 53 DQ32 76 NC 99 DQ7 122 A8 145 VSS 168 VDD 8 DQ3 31 DQ19 54 VDDQ 77 VDDQ 100 VSS 123 DQ23 146 DQ36 169 DQS15 9 NC 32 A5 55 DQ33 78 DQS6 101 NC 124 VSS 147 DQ37 170 DQ54 10 RESET# 33 DQ24 56 DQS4 79 DQ50 102 NC 125 A6 148 VDD 171 DQ55 1671 NC/A13 11 VSS 34 VSS 57 DQ34 80 DQ51 103 NC 126 DQ28 149 DQS14 172 VDDQ 12 DQ8 35 DQ25 58 VSS 81 VSS 104 VDDQ 127 DQ29 150 DQ38 173 NC 13 DQ9 36 DQS3 59 BA0 82 NC 105 DQ12 128 VDDQ 151 DQ39 174 DQ60 14 DQS1 37 A4 60 DQ35 83 DQ56 106 DQ13 129 DQS12 152 VSS 175 DQ61 15 VDDQ 38 VDD 61 DQ40 84 DQ57 107 DQS10 130 A3 153 DQ44 176 VSS 16 NC 39 DQ26 62 VDDQ 85 VDD 108 VDD 131 DQ30 154 RAS# 177 DQS16 17 NC 40 DQ27 63 WE# 86 DQS7 109 DQ14 132 VSS 155 DQ45 178 DQ62 18 VSS 41 A2 64 DQ41 87 DQ58 110 DQ15 133 DQ31 156 VDDQ 179 DQ63 19 DQ10 42 VSS 65 CAS# 88 DQ59 111 CKE1 134 CB4 157 S0# 180 VDDQ 20 DQ11 43 A1 66 VSS 89 VSS 112 VDDQ 135 CB5 158 S1# 181 SA0 21 CKE0 44 CB0 67 DQS5 90 NC 113 NC 136 VDDQ 159 DQS14 182 SA1 22 VDDQ 45 CB1 68 DQ42 91 SDA 114 DQ20 137 CK0 160 VSS 183 SA2 23 DQ16 46 VDD 69 DQ43 92 SCL 115 A12 138 CK0# 161 DQ46 184 VDDSPD Notes: PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 1. Pin 167 is NC for 1GB and 2GB, or A13 for 4GB. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Pin Assignments and Descriptions Table 7: Pin Descriptions Symbol Type Description A0–A13 Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0 and BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. A0–A12 (1GB, 2GB ) or A0–A13 (4GB). BA0, BA1 Input Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. CKE0, CKE1 Input Clock enable: CKE enables (registered HIGH) and CKE disables (registered LOW) the internal clock, input buffers, and output drivers. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z. S0#, S1# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. SA0–SA2 Input Presence-detect address inputs: These pins are used to configure the SPD EEPROM address range on the I2C bus. SCL Input Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect data transfer to and from the module. CB0–CB7 I/O Check bits. DQ0–DQ63 I/O Data input/output: Data bus. DQS0–DQS17 I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. Used to capture data. SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. VDD/VDDQ Supply Power supply: +2.5V ±0.2V. VDDSPD Supply SPD EEPROM power supply: +2.3V to +3.6V. VREF Supply SSTL_2 reference voltage (VDD/2). VSS Supply Ground. NC – No connect: These pins are not connected on the module. NF – No function: These pins are connected within the module, but provide no functionality. PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Functional Block Diagrams Functional Block Diagrams Figure 3: Functional Block Diagram, Standard Height, 43.18mm (1.7in) VSS RS1# RS0# DQS0 DQ0 DQ1 DQ2 DQ3 DQS9 DQS CS# DM DQ DQ U1b DQ DQ DQS CS# DM DQ DQ DQ U1t DQ DQS CS# DM DQ DQ U2b DQ DQ DQS CS# DM DQ DQ U2t DQ DQ DQS CS# DM DQ DQ U3b DQ DQ DQS CS# DM DQ DQ DQ U3t DQ DQS CS# DM DQ DQ U4b DQ DQ DQS CS# DM DQ DQ U4t DQ DQ DQS CS# DM DQ DQ U6b DQ DQ DQS CS# DM DQ DQ U6t DQ DQ DQS CS# DM DQ DQ U7b DQ DQ DQS CS# DM DQ DQ U7t DQ DQ DQS CS# DM DQ DQ U8b DQ DQ DQS CS# DM DQ DQ U8t DQ DQ DQS CS# DM DQ DQ U9b DQ DQ DQS CS# DM DQ DQ U9t DQ DQ DQS CS# DM DQ DQ U5b DQ DQ DQS CS# DM DQ DQ DQ U5t DQ DQ4 DQ5 DQ6 DQ7 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ20 DQ21 DQ22 DQ23 DQ28 DQ29 DQ30 DQ31 DQ36 DQ37 DQ38 DQ39 DQ44 DQ45 DQ46 DQ47 DQ52 DQ53 DQ54 DQ55 DQ60 DQ61 DQ62 DQ63 BA0, BA1 A0–A13/A12 RAS# CAS# CKE0, CKE1 WE# CK CK# PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN R e g i s t e r s DQS CS# DM DQ DQ U17b DQ DQ DQS CS# DM DQ DQ U17t DQ DQ DQS CS# DM DQ DQ U16b DQ DQ DQS CS# DM DQ DQ U16t DQ DQ DQS CS# DM DQ DQ U15b DQ DQ DQS CS# DM DQ DQ U15t DQ DQ DQS CS# DM DQ DQ U14b DQ DQ DQS CS# DM DQ DQ U14t DQ DQ DQS CS# DM DQ DQ U18b DQ DQ DQS CS# DM DQ DQ U18t DQ DQ DQS17 CB4 CB5 CB6 CB7 U10 SPD EEPROM U11, U13 S0#, S1# DQS CS# DM DQ DQ U19t DQ DQ DQS16 DQS8 CB0 CB1 CB2 CB3 DQS CS# DM DQ DQ U19b DQ DQ DQS15 DQS7 DQ56 DQ57 DQ58 DQ59 DQS CS# DM DQ DQ DQ U20t DQ DQS14 DQS6 DQ48 DQ49 DQ50 DQ51 DQS CS# DM DQ DQ U20b DQ DQ DQS13 DQS5 DQ40 DQ41 DQ42 DQ43 DQS CS# DM DQ DQ U21t DQ DQ DQS12 DQS4 DQ32 DQ33 DQ34 DQ35 DQS CS# DM DQ DQ DQ U21b DQ DQS11 DQS3 DQ24 DQ25 DQ26 DQ27 DQS CS# DM DQ DQ DQ U22t DQ DQS10 DQS2 DQ16 DQ17 DQ18 DQ19 DQS CS# DM DQ DQ U22b DQ DQ SCL WP A0 RS0#, RS1#: DDR SDRAM RBA0, RBA1: DDR SDRAM A1 SDA A2 VSS SA0 SA1 SA2 U12 RA0–RA13/RA12 : DDR SDRAM CK0 CK0# RRAS#: DDR SDRAM RCAS#: DDR SDRAM PLL RCKE0, RCKE1: DDR SDRAM RWE#: DDR SDRAM VDDSPD SPD EEPROM VDDQ DDR SDRAM VDD DDR SDRAM RESET# VREF DDR SDRAM VSS DDR SDRAM 6 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 Register x 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Functional Block Diagrams Figure 4: Functional Block Diagram, Low Profile, 43.18mm (1.2in) VSS RS1# RS0# DQS0 DQS9 DQ0 DQ1 DQ2 DQ3 DQS CS# DM DQ DQ U1b DQ DQ DQS CS# DM DQ DQ DQ U1t DQ DQS CS# DM DQ DQ U2b DQ DQ DQS CS# DM DQ DQ U2t DQ DQ DQS CS# DM DQ DQ U3b DQ DQ DQS CS# DM DQ DQ DQ U3t DQ DQS CS# DM DQ DQ U4b DQ DQ DQS CS# DM DQ DQ U4t DQ DQ DQS CS# DM DQ DQ U6b DQ DQ DQS CS# DM DQ DQ U6t DQ DQ DQS CS# DM DQ DQ U7b DQ DQ DQS CS# DM DQ DQ U7t DQ DQ DQS CS# DM DQ DQ U8b DQ DQ DQS CS# DM DQ DQ U8t DQ DQ DQS CS# DM DQ DQ U9b DQ DQ DQS CS# DM DQ DQ U9t DQ DQ DQS CS# DM DQ DQ U5b DQ DQ DQS CS# DM DQ DQ DQ U5t DQ DQ4 DQ5 DQ6 DQ7 DQS1 DQ12 DQ13 DQ14 DQ15 DQS2 DQ20 DQ21 DQ22 DQ23 DQS3 DQ28 DQ29 DQ30 DQ31 DQS4 DQ36 DQ37 DQ38 DQ39 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 U22 SPD EEPROM U19, U20 PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN DQS CS# DM DQ DQ U13b DQ DQ DQS CS# DM DQ DQ U13t DQ DQ DQS CS# DM DQ DQ U12b DQ DQ DQS CS# DM DQ DQ U12t DQ DQ DQS CS# DM DQ DQ U11b DQ DQ DQS CS# DM DQ DQ U11t DQ DQ DQS CS# DM DQ DQ U10b DQ DQ DQS CS# DM DQ DQ U10t DQ DQ DQS CS# DM DQ DQ U14b DQ DQ DQS CS# DM DQ DQ U14t DQ DQ DQS17 DQS8 CK DQS CS# DM DQ DQ U5t DQ DQ DQS16 DQS7 DQ56 DQ57 DQ58 DQ59 CK# DQS CS# DM DQ DQ U15b DQ DQ DQS15 DQS6 WE# DQS CS# DM DQ DQ DQ U16t DQ DQS14 DQS5 DQ40 DQ41 DQ42 DQ43 CKE0, CKE1 DQS CS# DM DQ DQ U16b DQ DQ DQS13 DQ32 DQ33 DQ34 DQ35 RAS# CAS# DQS CS# DM DQ DQ U17t DQ DQ DQS12 DQ24 DQ25 DQ26 DQ27 A0–A13/A12 DQS CS# DM DQ DQ DQ U17b DQ DQS11 DQ16 DQ17 DQ18 DQ19 S0#, S1# DQS CS# DM DQ DQ DQ U18t DQ DQS10 DQ8 DQ9 DQ10 DQ11 BA0, BA1 DQS CS# DM DQ DQ U18b DQ DQ R e g i s t e r s RS0#, RS1#: DDR SDRAM SCL RBA0, RBA1: DDR SDRAM RA0–RA13/RA12: DDR SDRAM WP A0 A1 SDA A2 VSS SA0 SA1 SA2 RRAS#: DDR SDRAM U20 CK0 CK0# RCAS#: DDR SDRAM RCKE0, RCKE1: DDR SDRAM RWE#: DDR SDRAM RESET# VDDSPD SPD EEPROM VDDQ DDR SDRAM VDD DDR SDRAM VREF DDR SDRAM VSS DDR SDRAM 7 PLL DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 DDR SDRAM x 4 Register x 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM General Description General Description The MT36VDDT12872, MT36VDDT25672, and MT36VDDT51272 DDR SDRAM modules are high-speed, CMOS dynamic random access 1GB, 2GB, and 4GB memory modules organized in a x72 configuration. These modules use DDR SDRAM devices with four internal banks. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM device during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs(CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Register and PLL Operation These DDR SDRAM modules operate in registered mode, where the control, command, and address input signals are latched in the registers on the rising clock edge and sent to the DDR SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR SDRAM devices. The register(s) and PLL reduce control, command, address, and clock signals loading by isolating DRAM from the system controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various DDR SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0], which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected to VSS, permanently disabling hardware write protect. PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 8 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device’s data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 8: Symbol Absolute Maximum Ratings Parameter Min Max Units VDD/VDDQ VDD/VDDQ supply voltage relative to VSS –1.0 +3.6 V VIN, VOUT Voltage on any pin relative to VSS –0.5 +3.2 V –5 +5 µA CK, CK# –10 +10 DM –4 +4 –10 +10 II Input leakage current; Any input 0V ≤ VIN ≤ VDD; Address inputs, VREF input 0V ≤ VIN ≤ 1.35V (All other pins not under RAS#, CAS#, WE#, BA, test = 0V) S#, CKE IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are disabled DQ, DQS TA DRAM ambient operating temperature1 Commercial Industrial Notes: PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN µA 0 +70 °C –40 +85 °C 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s Web site. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Electrical Specifications DRAM Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades, as shown in Table 9. Table 9: Module and Component Speed Grades DDR components may exceed the listed module speed grades Module Speed Grade Component Speed Grade -335 -6 -262 -75E -26A -75Z -265 -75 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system’s memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Electrical Specifications IDD Specifications Table 10: IDD Specifications and Conditions – 1GB Values are for the MT46V64M4 DDR SDRAM only and are computed from values specified in the 256Mb (64 Meg x 4) component data sheet Parameter/Condition Symbol -335 -26A -265 Units Operating one bank active-precharge current: RC = RC (MIN); CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles 1 IDD0 2,322 2,232 2,232 mA Operating one bank active-read-precharge current: BL = 2; t RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD11 3,132 2,682 2,682 mA Precharge power-down standby current: All device banks idle; Powerdown mode; tCK = tCK (MIN); CKE = LOW IDD2P2 144 144 144 mA Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DM, and DQS IDD2F2 1,800 1,620 1,620 mA Active power-down standby current: One device bank active; Powerdown mode; tCK = tCK (MIN); CKE = LOW IDD3P2 1,080 900 1,080 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; t RC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N2 2,160 1,800 1,800 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R2 3,222 2,772 2,772 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W2 3,222 2,772 2,772 mA IDD52 9,180 8,460 8,820 mA IDD5A2 216 216 216 mA t t t Auto refresh current tREFC = tRFC (MIN) tREFC = 15.625µs Self refresh current: CKE ≤ 0.2V IDD62 144 144 144 mA Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands IDD71 7,452 6,372 6,642 mA Notes: PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 1. Value calculated as one module rank in this operating condition; all other module ranks in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Electrical Specifications Table 11: IDD Specifications and Conditions – 2GB Values are for the MT46V128M4 DDR SDRAM only and are computed from values specified in the 512Mb (128 Meg x 4) component data sheet -335 -262 -26A/ -265 Units Operating one bank active-precharge current: RC = RC (MIN); CK = CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 1 2,430 2,430 2,160 mA Operating one bank active-read-precharge current: BL = 2; RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD11 2,970 2,970 2,700 mA Precharge power-down standby current: All device banks idle; Powerdown mode; tCK = tCK (MIN); CKE = LOW IDD2P2 180 180 180 mA Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DM, and DQS IDD2F2 1,620 1,620 1,440 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P2 1,260 1,260 1,080 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; RC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N2 1,800 1,800 1,620 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R1 3,060 3,060 2,700 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W1 3,240 2,880 2,520 mA 10,440 10,440 10,080 mA Parameter/Condition Symbol t t t t t t Auto refresh current tREFC = tRFC (MIN) tREFC = 7.8125µs Self refresh current: CKE ≤ 0.2V Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Notes: PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN IDD52 IDD5A2 360 IDD62 IDD71 180 180 180 mA 7,380 7,290 6,390 mA 360 360 mA 1. Value calculated as one module rank in this operating condition; all other module ranks in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Electrical Specifications Table 12: IDD Specifications and Conditions – 4GB Values are for the MT46V256M4 DDR SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) component data sheet -335 -26A/ -265 Units Operating one bank active-precharge current: RC = RC (MIN); CK = CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles 1 IDD0 3,060 2,790 mA Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN); t CK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD11 3,690 3,420 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD2P2 360 360 mA Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DM, and DQS IDD2F2 2,340 2,160 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P2 1,260 1,080 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; t RC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N2 1,800 1,620 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R1 4,140 3,780 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W1 4,320 3,960 mA IDD52 12,240 11,880 mA IDD5A2 360 360 mA Parameter/Condition Symbol t Auto refresh current t t t tREFC = tRFC (MIN) tREFC = 7.8125µs Self refresh current: CKE ≤ 0.2V IDD62 324 324 mA Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands IDD71 9,630 8,910 mA Notes: PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 1. Value calculated as one module rank in this operating condition; all other module ranks in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Register and PLL Specifications Register and PLL Specifications Table 13: Register Specifications SSTV16859 devices or equivalent JESD82-4B Parameter Symbol Pins Condition Min Max Units DC high-level input voltage VIH(DC) Address, control, command SSTL_25 VREF(DC) + 150 – mV DC low-level input voltage VIL(DC) Address, control, command SSTL_25 – VREF(DC) - 150 mV AC high-level input voltage VIH(AC) Address, control, command SSTL_25 VREF(DC) + 310 VDD mV AC low-level input voltage VIL(AC) Address, control, command SSTL_25 – VREF(DC) - 310 mV Output high voltage VOH Parity output LVCMOS VDD - 0.2 – V Output low voltage VOL Parity output LVCMOS – 0.2 V Input current II All pins VI = VDDQ or VSSQ –5.0 +5.0 µA Static standby IDD All pins RESET# = VSSQ (IO = 0) – 100 µA Static operating IDD All pins RESET# = VSSQ; VI = VIH(AC) or VIL(DC) IO = 0 – Varies by manufacturer mA Dynamic operating (clock tree) IDDD n/a RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle – Varies by manufacturer µA Dynamic operating (per each input) IDDD n/a RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle; One data input switching at tCK/2, 50% duty cycle – Varies by manufacturer µA Input capacitance (per device, per pin) CI All inputs except RESET# VI = VREF ±250mV; VDDQ = 1.8V 2.5 3.5 pF Input capacitance (per device, per pin) CI RESET# VI = VDDQ or VSSQ – Varies by manufacturer pF Notes: PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 1. Timing and switching specifications for the register listed are critical for proper operation of the DDR SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Register and PLL Specifications Table 14: PLL Specifications CVF857 device or equivalent JESD82-1A Parameter Symbol Min Max Units VIH 1.7 VDDQ + 0.3 V DC low-level input voltage VIL –0.3 0.7 V Input voltage (limits) VIN –0.3 VDDQ + 0.3 V DC high-level input voltage VIX (VDDQ/2) - 0.2 (VDDQ/2) + 0.2 V Input differential voltage Input differential-pair cross voltage VID(DC) 0.36 VDDQ + 0.6 V Input differential voltage VID(AC) 0.70 VDDQ + 0.6 V II –10 +10 µA Dynamic supply current IDDPD – 200 µA Dynamic supply current IDDQ – 300 µA Dynamic supply current IADD – 12 mA CIN 2.0 3.5 pF Input current Input capacitance Table 15: PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Symbol Min Max tL – 100 µs tslr(i) 1.0 4.0 V/ns SSC modulation frequency – 30 50 kHz SSC clock input frequency deviation – 0 –0.50 % PLL loop bandwidth (–3dB from unity gain) – 2.0 – MHz Stabilization time Input clock slew rate Notes: PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN Units 1. PLL timing and switching specifications are critical for proper operation of the DDR DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information is available in JEDEC Standard JESD82-1A. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Serial Presence-Detect Serial Presence-Detect Table 16: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Symbol Min Max Units VDDSPD 2.3 3.6 V Supply voltage Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V Input low voltage: Logic 0; All inputs VIL –1.0 VDDSPD × 0.3 V Output low voltage: IOUT = 3mA VOL – 0.4 V Input leakage current: VIN = GND to VDD ILI – 10 µA Output leakage current: VOUT = GND to VDD ILO – 10 µA Standby current: SCL = SDA = VDD – 0.3V; All other inputs = VSS or VDD ISB – 30 µA Power supply current: SCL clock frequency = 100 kHz ICC – 2.0 mA Table 17: Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1 Time the bus must be free before a new transition can start tBUF 1.3 – µs Data-out hold time tDH 200 – ns SDA fall time tF – 300 ns 2 SDA rise time tR – 300 ns 2 tHD:DAT 0 – µs Start condition hold time tH:STA 0.6 – µs Clock HIGH period tHIGH 0.6 – µs tI – 50 ns tLOW 1.3 – µs fSCL – 400 kHz Data-in setup time tSU:DAT 100 – ns Start condition setup time tSU:STA 0.6 – µs Stop condition setup time tSU:STO 0.6 – µs tWRC – 10 ms Data-in hold time Noise suppression time constant at SCL, SDA inputs Clock LOW period SCL clock frequency WRITE cycle time Notes: 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron’s SPD page: www.micron.com/SPD. PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Module Dimensions Module Dimensions Figure 5: 184-Pin DDR RDIMM – Standard Height, 43.18mm (1.7in) 6.81 (0.268) MAX Front view 133.5 (5.256) 133.2 (5.244) U1 U2 U3 U4 U5 U6 U7 U8 U9 43.33 (1.706) 43.03 (1.694) 2.0 (0.079) R (4X) U11 U13 U12 2.5 (0.098) D (2X) 10.0 (0.39) TYP 17.8 (0.7) TYP 2.3 (0.091) TYP 0.9 (0.035) R Pin 1 1.27 (0.05) TYP 64.77 (2.55) TYP 2.2 (0.087) TYP 1.02 (0.04) TYP Pin 92 6.35 (0.25) TYP 1.37 (0.054) 1.17 (0.046) 49.53 (1.95) TYP 120.65 (4.75) TYP Back view U14 U15 U16 U17 U18 U19 U20 U21 U22 3.8 (0.15) TYP Pin 184 Pin 93 73.3 (2.88) TYP Notes: PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM Module Dimensions Figure 6: 184-Pin DDR RDIMM – Low Profile, 43.18mm (1.2in) Front view 0.268 (6.81) MAX 133.5 (5.256) 133.2 (5.244) 2.0 (0.079) R (4X) U19 U2 U1 U3 U4 U5 U6 U7 U8 U9 30.63 (1.206) 30.48 (1.194) U20 2.5 (0.098) D (2X) 10.0 (0.39) TYP 17.8 (0.7) TYP 2.3 (0.091) TYP 0.9 (0.035) R Pin 1 1.27 (0.05) TYP 64.77 (2.55) TYP 2.2 (0.087) TYP 1.02 (0.04) TYP Pin 92 1.37 (0.054) 1.17 (0.046) 6.35 (0.25) TYP 49.53 (1.95) TYP 120.65 (4.75) TYP Back view U21 U10 U11 U12 U13 U14 U15 U16 U17 U18 U22 3.8 (0.15) TYP Pin 184 Pin 93 73.3 (2.88) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef809d5451/Source: 09005aef807da325 dd36c128_256_512x72.fm - Rev. F 6/08 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved.