256MB, 512MB: (x72, ECC, PLL, SR) 200

256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Features
DDR SDRAM Small-Outline DIMM
MT9VDDF3272PH(I) – 256MB,
MT9VDDF6472PH(I) – 512MB
For component specifications, refer to Micron’s Web site: www.micron.com/products/ddrsdram
Features
Figure 1:
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Supports ECC error detection and correction
• Fast data transfer rates: PC2100 and PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 256MB (32 Meg x 72) and 512MB (64 Meg x 72)
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Programmable READ CAS latency
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence Detect (SPD) with EEPROM
• Bidirectional data strobe (DQS) transmitted/received with data—i.e., source-synchronous data
capture
• Gold edge contacts
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DDF9C32_64x72PH_1.fm - Rev. A 1/06 EN
200-Pin SODIMM (MO-224)
Height 1.25in (31.75mm)
Options
• Operating Temperature Range
Commercial (0°C ≤ TA ≤ +70°C)
Industrial (-40°C ≤ TA ≤ +85°C)
• Package
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)
• Clock frequency, speed, CAS latency2
6ns (267 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
• PCB Height
1.25in. (31.75mm)
Marking
None
I1
G
Y1
-335
-2621
-26A1
-265
Notes: 1. Consult Micron for product availability.
2. CL = Device CAS (READ) latency.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Features
Table 1:
Address Table
Refresh Count
Row Addressing
DeviceBankAddressing
Base Device Configuration
Column Addressing
Module Rank Addressing
Table 2:
256MB
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
1 (S0#)
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
1K (A0–A9, A11)
1 (S0#
Part Numbers and Timing Parameters
Part Number
MT9VDDF3272PHG-335_
MT9VDDF3272PHY-335_
MT9VDDF3272PHG-262_
MT9VDDF3272PHY-262_
MT9VDDF3272PHG-26A_
MT9VDDF3272PHY-26A_
MT9VDDF3272PH(I)G-265_
MT9VDDF3272PH(I)Y-265_
MT9VDDF6472PHG-335_
MT9VDDF6472PHY-335_
MT9VDDF6472PHG-262_
MT9VDDF6472PHY-262_
MT9VDDF6472PHG-26A_
MT9VDDF6472PHY-26A_
MT9VDDF6472PH(I)G-265_
MT9VDDF6472PH(I)Y-265_
Note:
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DDF9C32_64x72PH_1.fm - Rev. A 1/06 EN
Module
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Latency
(CL - tRCD - tRP)
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
6ns, 333 MT/s
6ns, 333 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
6ns, 333 MT/s
6ns, 333 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT9VDDF3272PHG-265A1.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Serial Presence-Detect Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Serial Presence-Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
SPD Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
SPD Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
SPD Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
SPD Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
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DDF9C32_64x72PHTOC.fm - Rev. A 1/06 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
200-Pin SODIMM (MO-224) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Component Case Temperature vs. Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Definition of Start and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Acknowledge Response from Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SPD EEPROM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
200-Pin SODIMM Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
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DDF9C32_64x72PHLOF.fm - Rev. A 1/06 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Part Numbers and Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
CAS Latency (CL) Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
IDD Specifications and Conditions – 256MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
IDD Specifications and Conditions – 512MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Capacitance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Module and Component Speed Grade Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PLL Clock Driver Timing Requirements and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
EEPROM Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
EEPROM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Serial Presence-Detect EEPROM DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Serial Presence-Detect EEPROM AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Serial Presence-Detect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PDF: 09005aef81eef7d4/Source: 09005aef81eef0df
DDF9C32_64x72PHLOT.fm - Rev. A 1/06 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 3:
Pin Assignment
200-Pin SODIMM Front
200-Pin SODIMM Back
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
VREF
VSS
DQ0
DQ1
Vdd
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
NC
VSS
NC
NC
VDD
NC
NC
A12
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
NC
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
NC
VSS
VSS
VDD
VDD
CKE0
NC
A11
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
NC
NC
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
VDD
NC
NC
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
NC
Figure 2:
Module Layout
Back View
Front View
U1
U2
U4
U3
U5
No components this side of module.
U6
U7
U8
U9
U10
U11
PIN 1
(all odd pins)
PIN 199
PIN 200
Indicates a VDD or VDDQ pin
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
6
(all even pins)
PIN 2
Indicates a VSS pin
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Pin Assignments and Descriptions
Table 4:
Pin Descriptions
Refer to Pin Assignment Tables on page 6 for pin number and symbol correlation.
Pin Numbers
Symbol
Type
118, 119, 120
WE#, CAS#, RAS#
Input
35, 37
CK0, CK0#
96
CKE0,
121
S0#
117, 116
BA0, BA1
99, 100, 101,102, 105,
106, 107, 108, 109, 110,
111, 112, 115
A0–A12
(256MB, 512MB)
11, 25, 47, 61, 77, 133,
147,169, 183
DQS0–DQS8
12, 26, 48, 62, 78, 134,
148, 170, 184
DM0–DM8
71, 72, 73, 74, 79, 80, 83,
84
CB0–CB7
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
Description
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Input Clock: CK and CK# are differential clock inputs distributed
through an on-board PLL to all devices. All address and control
input signals are sampled on the crossing of the positive edge of
CK and negative edge of CK#. Output data (DQ and DQS) is
referenced to the crossings of CK and CK#.
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers.and output drivers. Taking CKE LOW
provides PRECHARGE POWER- DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any device bank). CKE is synchronous for POWERDOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after VDD is applied.
Input Chip Select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All com- mands are masked when
S# is registered HIGH. S# is considered part of the command
code.
Input Bank Address: BA0, BA1 define to which device bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Input Address Inputs: A0-A11/A12 provide the row address for ACTIVE
commands, and the column address, and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of
the memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The
address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Input/ Data Strobe: Output with READ data, input with WRITE data.
Output DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.
Input/ Check Bits.
Output
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Pin Assignments and Descriptions
Table 4:
Pin Descriptions
Refer to Pin Assignment Tables on page 6 for pin number and symbol correlation.
Pin Numbers
Symbol
5, 6, 7, 8, 13, 14, 17, 18,
19, 20, 23, 24, 29, 30, 31,
32, 41, 42, 43, 44, 49, 50,
53, 54, 55, 56, 59, 60, 61,
65, 66, 67, 68, 127, 128,
129, 130, 135, 136, 139,
140, 141, 142, 145, 146,
151, 152, 153, 154, 163,
164, 165, 166, 171, 172,
175, 176, 177, 181, 182,
187, 188, 189, 190
195
DQ0–DQ63
194, 196, 198
SA0–SA2
193
SDA
1, 2
9, 10, 21, 22, 33, 34, 36,
45, 46, 57, 58, 69, 70, 81,
82, 92, 93, 94, 113, 114,
131, 132, 143, 144, 155,
156, 157, 167, 168, 179,
180, 191, 192
3, 4, 15, 16, 27, 28, 38,
39, 40, 51, 52, 63, 64, 75,
76, 87, 88, 90, 103, 104,
125, 126, 137, 138, 149,
150, 159, 161, 162, 173,
174, 185, 186
197
85, 86, 89, 91, 95, 97, 98,
122, 123, 124, 158, 160,
200
VREF
VDD
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Input Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-detect
portion of the module.
Supply SSTL_2 reference voltage.
Supply DQ Power Supply: +2.5V ±0.2V.
VSS
Supply Ground.
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
SCL
VDDSPD
NC
Type
Description
Input/ Data I/Os: Data bus.
Output
Input
Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
–
No Connect: These pins should be left unconnected.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Functional Block Diagram
Functional Block Diagram
All resistor values are 22Ω unless otherwise specified. Per industry standard, Micron
modules utilize various component speed grades, as referenced in the module part
numbering guide at www.micron.com/numberguide.
Standard modules use the following DDR SDRAM devices: MT46V32M8FG (256MB);
MT46V64M8FN (512MB). Lead-free modules use the following DDR SDRAM devices:
MT46V32M8BG (256MB); MT46V64M8BN (512MB). For component specifications, refer
to component data sheets at: www.micron.com/products/ddrsdram.
Figure 3:
Functional Block Diagram
S0#
DQS0
DQS4
DM0
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ
DQ
DQ
DQ U2
DQ
DQ
DQ
DQ
DQS1
DQS5
DM1
DM5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
DQ
DQ
DQ
U6
DQ
DQ
DQ
DQ
DQ
DQS2
DQS6
DM2
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS# DQS
DQ
DQ
DQ
U7
DQ
DQ
DQ
DQ
DQ
DQS3
DQS7
DM3
DM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS
DQ
DQ
DQ
U3
DQ
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS# DQS
DQ
DQ
DQ
U8
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS# DQS
DQ
DQ
DQ
U9
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS# DQS
DQ
DQ
DQ
U4
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS# DQS
DQ
DQ
DQ U10
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ
DQ
DQ
U5
DQ
DQ
DQ
DQ
DQ
DQS8
DM8
U2, U3, U6
PLL
CK0#
A0-A12/A13
SERIAL PD
SCL
WP
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
A0-A12/A13: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#
CAS#: DDR SDRAMs
WE#
WE#: DDR SDRAMs
CKE0
CKE0: DDR SDRAMs
U11
A0
A1
A2
SDA
SA0 SA1 SA2
BA0, BA1: DDR SDRAMs
RAS#
U7 - U9
U4, U5, U10
VDDSPD
BA0, BA1
U1
120
CK0
9
EEPROM/SPD
VDDQ
DDR SDRAMs
VDD
DDR SDRAMs
VREF
DDR SDRAMs
VSS
DDR SDRAMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
General Description
General Description
The Micron MT9VDDF3272PH and MT9VDDF6472PH are high-speed CMOS, dynamic
random-access, 256MB and 512MB memory modules organized in x72 (ECC) configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices.
DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effectively consists of a single 2n-bit
wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding nbit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR
SDRAM device during READs and by the memory controller during WRITEs. DQS is
edge-aligned with data for READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK. A phase-lock loop (PLL) device on the
module is used to redrive the differential clock signals to the DDR SDRAM devices to
minimize system clock loading.
PLL Operation
A phase-lock loop (PLL) on the module is used to redrive the differential clock signals CK
and CK# to the DDR SDRAM devices to minimize system clock loading.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA(2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
Table 5:
CAS Latency (CL) Table
Allowable Operating Clock Frequency (MHz)
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
Speed
CL = 2
CL = 2.5
-335
-262
-26A
-265
N/A
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 100
75 ≤ f ≤ 167
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
10
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©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Electrical Specifications
Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 6:
Absolute Maximum Ratings Table
Parameter
Rating
-1V to +3.6V
-1V to +3.6V
-1V to +3.6V
-0.5V to VDDQ + 0.5V
0°C to +70°C
-40°C to +85°C
-55°C to +150°C
50mA
VDD Supply Voltage Relative to VSS
VDDQ supply voltage relative to VSS
VREF and inputs voltage relative to Vss
I/O pins voltage relative to VSS
Operating temperature
TA (ambient - commercial)
TA (ambient - industrial)
Storage temperature (plastic)
Short circuit output current
Table 7:
DC Electrical Characteristics and Operating Conditions
Notes: 1–5, 13; notes appear on pages 15–17; 0°C ≤ TA ≤ +70°C
Parameter/Condition
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN
≤ 1.35V
(All other pins not under test = 0V)
Command/Address,
RAS#, CAS#, WE#,
CKE, S#
CK, CK#
DM
DQ, DQS
OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)
OUTPUT LEVELS:
High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum
VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
11
Symbol
Min
Max
Units
Notes
VDD
VDDQ
2.3
2.3
2.7
2.7
V
V
VREF
VTT
VIH(DC)
VIL(DC)
II
0.49 x VDDQ
VREF - 0.04
VREF + 0.15
-0.3
-18
0.51 x VDDQ
VREF + 0.04
VDD + 0.3
VREF - 0.15
18
V
V
V
V
µA
19, 35
19, 35,
36
6, 36
7, 36
17
17
II
-5
5
µA
II
-2
2
µA
IOZ
-5
5
µA
41
IOH
IOL
-16.8
16.8
–
–
mA
mA
20, 34
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Electrical Specifications
Table 8:
IDD Specifications and Conditions – 256MB
DDR SDRAM components only;
Notes: 1–5, 8, 10, 12, 42; notes appear on pages 15–17; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
Max
Parameter/Condition
Symbol
-335
-262
-26A/
-265
Units
Notes
IDD0
1,125
1,125
960
mA
14, 37
IDD1
1,530
1,440
1,305
mA
14, 37
IDD2P
35
36
36
mA
15, 18,
39
IDD2F
450
405
405
mA
40
IDD3P
270
225
225
mA
15, 18,
39
IDD3N
540
450
450
mA
IDD4R
1,575
1,350
1,350
mA
14, 37
IDD4W
1,400
1,200
1,200
mA
14
IDD5
2,295
2,115
2,115
mA
14, 39
IDD5A
IDD6
IDD7
54
36
3,645
54
36
3,150
54
36
3,150
mA
mA
mA
16, 39
9
14, 38
OPERATING CURRENT: One device bank; Active-Precharge;
t
RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One device bank; Active-ReadPrecharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN);
IOUT = 0mA; Address and control inputs changing once per
clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
tCK = tCK MIN; CKE = HIGH; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ, DQS, and
DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge; tRC = RAS (MAX); tCK = tCK
(MIN); DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per
clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle; CK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle
tREFC = tRFC(MIN)
AUTO REFRESH CURRENT
tREFC
= 7.8125µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four bank interleaving READs (BL=4)
with auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN);
Address and control inputs change only during Active READ,
or WRITE commands
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
12
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©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Electrical Specifications
Table 9:
IDD Specifications and Conditions – 512MB
DDR SDRAM components only;
Notes: 1–5, 8, 10, 12, 42; notes appear on pages 15–17; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
Max
Parameter/Condition
OPERATING CURRENT: One device bank; Active-Precharge; tRC =
t
RC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing
once per clock cyle; Address and control inputs changing once
every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK
= tCK MIN; CKE = HIGH; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge; tRC = RAS (MAX); tCK = tCK
(MIN); DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle; CK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
t
AUTO REFRESH CURRENT
REFC = tRFC (MIN)
tREFC
= 7.8125µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four bank interleaving READs (BL=4) with
auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN); Address
and control inputs change only during Active READ, or WRITE
commands
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
13
Symbol
-335
-262
-26A/
-265
Units
Notes
IDD0
1,040
1,040
920
mA
14, 37
IDD1
1,280
1,280
1,160
mA
14, 37
IDD2P
40
40
40
mA
IDD2F
360
360
320
mA
15, 18,
39
40
IDD3P
280
280
240
mA
IDD3N
400
400
360
mA
IDD4R
1,320
1,320
1,160
mA
14, 37
IDD4W
1,400
1,240
1,080
mA
14
IDD5
2,320
2,320
2,240
mA
14, 39
IDD5A
IDD6
IDD7
80
40
3,240
80
40
3,200
80
40
2,800
mA
mA
mA
16, 39
9
14, 38
15, 18,
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Electrical Specifications
Table 10:
Capacitance)
Note: 11; notes appear on pages 15–17
Parameter
Input/Output Capacitance: DQ, DQS, DM
Input Capacitance: Command and Address, S#, CKE
Input Capacitance: CK, CK#
Symbol
Min
Typ
Max
Units
CIO
CI1
CI2
5.0
18.0
–
–
–
7.7
6.0
27.0
–
pF
pF
pF
Electrical Characteristics and Recommended AC Operating Conditions
Recommended AC operating conditions are given in the DDR component data sheets,
available at www.micron.com/products/ddrsdram. Module speed grades correlate with
component speed grades as shown in the following table:
Table 11:
Module and Component Speed Grade Table
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
Module Speed Grade
Component Speed Grade
-335
-262
-26A
-265
-6
-75E
-75Z
-75
14
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©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Notes
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load:
VTT
Output
(VOUT)
50Ω
Reference
Point
30pF
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#),
and parameter specifications are guaranteed for the specified AC input levels under
normal use conditions. The minimum slew rate for the input signals used to test the
device is 1V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e.,
the receiver will effectively switch as a result of the signal crossing the AC input level,
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (non-common mode) on Vref may not
exceed ±2 percent of the DC value. Thus, from VDDQ/2, Vref is allowed ±25mV for DC
error and an additional ±25mV for AC noise. This measurement is to be taken at the
nearest VREF bypass capacitor.
7. VTT is not applied directly to the device. VTT is a system supply for signal termination
resistors, is expected to be set equal to VREF and must track variations in the DC level
of VREF.
8. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time at CL = 2 for -26A and -202, CL = 2.5 for -335 and -265 with
the outputs open.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is properly initialized, and is averaged at
the defined cycle rate.
11. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100
MHz, TA = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped
with I/O pins, reflecting the fact that they are matched in loading.
12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must be
derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from
500 mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is
uncertain. For -335, slew rates must be ≥ 0.5 V/ns.
13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period
before VREF stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.
14. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS.
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
15
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©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Notes
15. The refresh period 64ms. This equates to an average refresh rate of 7.8251µs. However,
an AUTO REFRESH command must be asserted at least once every 70.3µs; burst
refreshing or posting by the DRAM controller greater than eight refresh cycles is not
allowed.
16. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
17. To maintain a valid level, the transitioning edge of the input must:
A. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
B. Reach at least the target AC level.
C. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
18. VDD must not vary more than 4 percent if CKE is not active while any bank is active.
19. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and
not exceed either -300mV or 2.2V, whichever is more positive.
20. Normal Output Drive Curves:
A. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I
curve of Figure 4 on page 16.
B. The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 4 on page 16.
C. The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 5 on page 17
D. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 5 on page 17.
E. The full variation in the ratio of the maximum to minimum pull-up and pulldown current should be between 0.71 and 1.4, for device drain-to-source voltages
from 0.1V to 1.0V, and at the same voltage and temperature.
F. The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
Figure 4:
Pull-Down Characteristics
160
um
140
Maxim
120
Nominal
IOUT (mA)
100
high
80
Nominal low
60
Minimum
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
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Notes
Figure 5:
Pull-Up Characteristics
0
-20
Maximum
-40
Nominal high
IOUT (mA)
-60
-80
-100
Nom
-120
inal
-140
Min
low
imu
-160
m
-180
-200
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
34. The voltage levels used are derived from a minimum VDD level and the referenced test
load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values.
35. VDD and VDDQ must track each other.
36. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are
0Vs, provided a minimum of 42Ω of series resistance is used between the VTT supply
and the input pin.
37. Random addressing changing and 50 percent of data changing at every transfer.
38. Random addressing changing and 100 percent of data changing at every transfer.
39. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tREF later.
40. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.
IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
41. Leakage number reflects the worst case leakage possible through the module pin, not
what each memory device contributes.
42. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
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PLL Specifications
PLL Specifications
Table 12:
PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
0°C ≤ TA ≤ +70°C
Vdd = +2.5V ±0.2V
Parameter
Symbol
Operating Clock Frequency
Input Duty Cycle
Stabilization Time
Cycle to Cycle Jitter
Static Phase Offset
Output Clock Skew
Period Jitter
Half-Period Jitter
Input Clock Slew Rate
Output Clock Slew Rate
f
CK
tDC
t
STAB
JITCC
t∅
tSK
O
tJIT
PER
tJIT
HPER
tLS
I
tLS
O
t
Min
Nominal
Max
Units
notes
60
40
-75
-50
-75
-100
1.0
1.0
0
-
170
60
100
75
50
100
75
100
4
2
MHz
%
ms
ps
ps
ps
ps
ps
V/ns
V/ns
2, 3
4
5
6
6
7
Notes: 1. The timing and switching specifications for the PLL listed above are critical for proper
operation of DDR SDRAM modules. These are meant to be a subset of the parameters
for the specific device used on the module. Detailed information for this PLL is available in JEDEC Standard JESD82.
2. The PLL must be able to handle spread spectrum induced skew.
3. Operating clock frequency indicates a range over which the PLL must be able to lock,
but in which it is not required to meet the other timing parameters. (Used for lowspeed system debug.)
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase
lock of its feedback signal to its reference signal after power up.
5. Static Phase Offset does not include Jitter.
6. Period Jitter and Half-Period Jitter specifications are separate specifications that must
be met independently of each other.
7. The output slew rate is determined from the IBIS model:
VDD
CDCV857
VCK
R=60Ω
R=60 Ω
VDD/2
VCK
GND
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Thermal Specifications
Thermal Specifications
Figure 6:
Component Case Temperature vs. Air Flow
100
Ambient Temperature = 25º C
90
Tmax- memory stress software
Degrees Celsius
80
70
Tave- memory stress software
60
50
Tave- 3D gaming software
40
30
Minimum Air Flow
20
2.0
1.0
0.5
0.0
Air Flow (meters/sec)
8. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM)
across all modules.
9. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz
work station, fully loaded, with four comparable registered memory modules. Case temperatures charted represent worst-case component locations on modules installed in the
internal slots of the system.
10. Temperature versus air speed data is obtained by performing experiments with the system
motherboard removed from its case and mounted in a Eiffel-type low air speed wind tunnel. Peripheral devices installed on the system motherboard for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel
test chamber.
11. The memory diagnostic software used for determining worst-case component temperatures is a memory diagnostic software application developed for internal use by Micron
Technology, Inc.
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Serial Presence-Detect
Serial Presence-Detect
SPD Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7 on
page 20, and Figure 8 on page 21).
SPD Start Condition
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
SPD Acknowledge
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Figure 9 on page 21).
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data
transmissions and await the stop condition to return to standby power mode.
Figure 7:
Data Validity
SCL
SDA
DATA STABLE
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
DATA
CHANGE
20
DATA STABLE
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Serial Presence-Detect
Figure 8:
Definition of Start and Stop
SCL
SDA
START
BIT
Figure 9:
STOP
BIT
Acknowledge Response from Receiver
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
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Serial Presence-Detect
Table 13:
EEPROM Device Select Code
Most significant bit (b7) is sent first
Device Type Identifier
Select Code
Memory Area Select Code (two arrays)
Protection Register Select Code
Table 14:
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
EEPROM Operating Modes
Mode
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
Figure 10:
Chip Enable
RW Bit
WC
Bytes
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
VIL
1
1
1
≥1
1
≤ 16
Initial Sequence
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
SPD EEPROM Timing Diagram
tF
t HIGH
tR
t LOW
SCL
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
SDA IN
t DH
t AA
t BUF
SDA OUT
UNDEFINED
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Serial Presence-Detect
Table 15:
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: IOUT = 3mA
INPUT LEAKAGE CURRENT: VIN = GND to VDD
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
STANDBY CURRENT:
SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
Table 16:
Symbol
Min
Max
Units
VDD
VIH
VIL
VOL
ILI
ILO
ISB
2.3
VDD X 0.7
-1
–
–
–
–
3.6
VDD + 0.5
VDD x 0.3
0.4
10
10
30
V
V
V
V
µA
µA
µA
IDD
–
2
mA
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Symbol
Min
Max
Units
Notes
tAA
0.2
1.3
200
0.9
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
1
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
300
0
0.6
0.6
tI
tLOW
50
1.3
tR
0.3
400
fSCL
tSU:DAT
tSU:STA
tSU:STO
t
WRC
100
0.6
0.6
10
2
2
3
4
Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
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Serial Presence-Detect
Table 17:
Serial Presence-Detect Matrix
“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”
Byte
Description
0
1
2
3
4
5
6
7
8
9
Number of SPD Bytes Used by Micron
Total Number of Bytes in SPD Device
Fundamental Memory Type
Number of Row Addresses on Ass’y
Number of Column Addresses on Ass’y
Number of Physical Ranks on DIMM
Module Data Width
Module Data Width (Continued)
Module Voltage Interface Levels
SDRAM Cycle Time, tCK (CAS Latency = 2.5)
(see note 2)
10
SDRAM Access from Clock, tAC (CAS Latency =
2.5) (see note 1)
Module Configuration Type
Refresh Rate/ Type
SDRAM Device Width (Primary DDR SDRAM)
Error-checking DDR SDRAM Data Width
Minimum Clock Delay, Back-to-Back Random
Column Access
Burst Lengths Supported
Number of Banks on DDR SDRAM Device
CAS Latencies Supported
CS Latency
WE Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time, tCK (CL = 2) (See note 2)
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
SDRAM Access from CK, tAC (CL = 2) (See note
2)
SDRAM Cycle Time, tCK (CL = 1.5)
SDRAM Access from CK, tAC (CL = 1.5)
Minimum Row Precharge Time, tRP (see note
5)
28
Minimum Row Active to Row Active, tRRD
29
Minimum RAS# to CAS# Delay, tRCD (see note
5)
30
Minimum RAS# Pulse Width, tRAS (see note 3)
31
32
Module Rank Density
Address and Command Setup Time, tIS (see
note 4)
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DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
Entry (Version)
MT9VDDF3272PH
MT9VDDF6472PH
128
256
DDR SDRAM
13
10 or 11
1
72
0
SSTL 2.5V
6ns (-335)
7ns (-262/-26A)
7.5ns (-265)
0.7ns (-335)
0.75ns (-262/-26A/-265)
ECC
15.6µs or 7.8µs/SELF
8
8
1 clock
80
08
07
0D
0A
01
48
00
04
60
70
75
70
75
02
82
08
08
01
80
08
07
0D
0B
01
48
00
04
60
70
75
70
75
02
82
08
08
01
2, 4, 8
4
2, 2.5
0
1
Unbuff, Diff CLK, PLL
Fast/concurrent AP
7.5ns (-335/-262/-26A)
10ns (-265)
0.7ns (-335)
0.75ns (-265/-26A)
N/A
N/A
18ns (-335)
15ns (-262)
20ns (-26A/-265)
12ns (-335)
15ns (-262/-26A/-265)
18ns (-335)
15ns (-262)
20ns (-26A/-265)
42ns (-335)
45ns (-262/-26A/-265)
256MB, 512MB
0.8ns (-335)
1.0ns (-262/-26A/-265)
0E
04
0C
01
02
24
C0
75
A0
70
75
00
00
48
3C
50
30
3C
48
3C
50
2A
2D
40
80
A0
0E
04
0C
01
02
24
C0
75
A0
70
75
00
00
48
3C
50
30
3C
48
3C
50
2A
2D
80
80
A0
24
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256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Serial Presence-Detect
Table 17:
Serial Presence-Detect Matrix (Continued)
“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”
Byte
33
Description
t
34
Address and Command Hold Time, IH (see
note 4)
Data/Data Mask Input Setup Time, tDS
35
Data/ Data Mask Input Hold Time, tDH
36-40 Reserved
41
Min Active Refresh Time tRC
42
43
44
Minimum Auto Refresh to Active/Auto
Refresh Command Period, tRFC
SDRAM Device Max Cycle Time, tCKMAX
SDRAM Device Max DQS–DQ Skew Time,
tDQSQ
45
SDRAM Device Max Read Data Hold Skew
Factor
46
Reserved
47
DIMM Height
48–61 Reserved
62
SPD Revision
63
Checksum For Bytes 0–62
64
65-71
72
73-90
91
92
93
94
95-98
99-127
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (continued)
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Identification Code (Continued)
Year Of Manufacture in BCD
Week Of Manufacture in BCD
Module Serial Number
Manufacturer-Specific Data ( RSVD)
Entry (Version)
MT9VDDF3272PH
MT9VDDF6472PH
0.8ns (-335)
1.0ns (-262/-26A/-265)
0.45ns (-335
0.5ns (-262/-26A/-265)
0.45ns (-335
0.5ns (-262/-26A/-265)
80
A0
45
50
45
50
00
3C
41
48
4B
30
34
2D
32
55
75
00
01
00
10
33
D0
FD
2D
2C
00
01–0C
Variable Data
01–09
00
Variable Data
Variable Data
Variable Data
–
80
A0
45
50
45
50
00
3C
41
48
4B
30
34
2D
32
55
75
00
01
00
10
74
11
3E
6E
2C
00
01–0C
Variable Data
01–09
00
Variable Data
Variable Data
Variable Data
–
60ns (-335/-262)
65ns (-26A/-265)
72ns (-335)
75ns (-262/-26A/-265)
12ns (-335)
13ns (-262/-26A/-265)
0.45ns (-335)
0.5ns (-262/-26A/-265)
0.55ns (-335)
0.75ns (-262/-26A/-265)
Revision 1.0
-335
-262
-26A
-265
MICRON
01–12
1–9
0
Notes: 1. Device latencies used for SPD values.
2. Value for -262/-26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device
spec. value is 7.5ns.
3. The value of tRAS used for -265 modules is calculated from tRC - tRP. Actual device spec
value is 40ns.
4. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worstcase (slow slew rate) value is represented here. Systems requiring the fast slew rate setup
and hold values are supported, provided the faster minimum slew rate is met.
5. The value of tRP, tRCD, and tRAP for -335 modules indicated as 18ns to align with industry
specifications; actual DDR SDRAM device specification is 15ns.
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256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Package Dimensions
Package Dimensions
All dimensions are in inches (millimeters); MAX or typical where noted.
MIN
Figure 11:
200-Pin SODIMM Dimensions
0.094 (2.40)
MAX
FRONT VIEW
2.667 (67.75)
2.656 (67.45)
U1
U2
0.079 (2.00) R
(2X)
U3
U6
0.071 (1.80)
(2X)
U7
U4
U8
U5
U9
1.244 (31.60)
1.256 (31.90)
U10
0.787 (20.00)
TYP.
U11
0.236 (6.00)
TYP.
PIN 199
PIN 1
0.079 (2.00)
TYP.
0.039 (0.99)
TYP.
0.018 (0.46)
TYP.
2.504 (63.60)
TYP.
0.024 (0.61)
TYP.
0.043 (1.10)
0.035 (0.90)
BACK VIEW
No components this side of module.
0.157 (4.0) TYP.
0.165 (4.20) TYP.
PIN 200
1.867 (47.40)
TYP.
PIN 2
0.448 (11.40)
TYP.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
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