512MB (x72, DR ECC) 184-Pin DDR UDIMM Features DDR SDRAM UDIMM MT18VDDF6472A – 512MB For component data sheets, refer to Micron’s Web site: www.micron.com Features Figure 1: • 184-pin, unbuffered dual in-line memory module (UDIMM) • Fast data transfer rates: PC2100, PC2700, • 512MB (64 Meg x 72) • Supports ECC error detection and correction • VDD = VDDQ = 2.5V • VDDSPD = 2.3–3.6V • 2.5V I/O (SSTL_2-compatible) • Internal, pipelined double data rate (DDR) 2n-prefetch architecture • Bidirectional data strobe (DQS) transmitted/ received with data—that is, source-synchronous data capture • Differential clock inputs (CK and CK#) • Multiple internal device banks for concurrent operation • Dual rank • Selectable burst lengths (BL) 2, 4, or 8 • Auto precharge option • Auto refresh and self refresh modes: 7.8125µs maximum average periodic refresh interval • Serial presence-detect (SPD) with EEPROM • Selectable CAS latency (CL) for maximum compatibility • Gold edge contacts Table 1: 184-Pin UDIMM (MO-206) Module height: 25.4mm (1.0in) Options Marking • Operating temperature1 – Commercial (0°C TA +70°C) None • Package – 184-pin DIMM (lead-free) Y • Memory clock, speed, CAS latency – 6.0ns (167 MHz), 333 MT/s, CL = 2.5 -335 Notes: 1. Contact Micron for industrial temperature module offerings. Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 3 CL = 2.5 CL = 2 (ns) tRP (ns) tRC (ns) -335 -265 PC2700 PC2100 – – 333 266 266 200 18 20 18 20 60 65 Notes: tRCD Notes 1 1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications; actual DDR SDRAM device specifications are 15ns. PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB (x72, DR ECC) 184-Pin DDR UDIMM Features Table 2: Addressing Parameter 512MB 8K 8K A[12:0] 4 BA[1:0] 256Mb (32 Meg x 8) 1K A[9:0] 2 S#[1:0] Refresh count Row address Device bank address Device configuration Column address Module rank address Table 3: Part Numbers and Timing Parameters – 512MB Modules Base device: MT46V32M8,1 256Mb DDR SDRAM Part Number2 MT18VDDF6472AY-335__ Notes: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 512MB 64 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDF6472AY-335M1. PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved. 512MB (x72, DR ECC) 184-Pin DDR UDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 4: Pin Assignments 184-Pin DDR UDIMM Front 184-Pin DDR UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1# VSS DQ10 DQ11 CKE0 VDDQ DQ16 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDD NC DQ48 DQ49 VSS CK2# CK2 VDDQ DQS6 DQ50 DQ51 VSS NF DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 3 VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ NC DQ20 A12 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 CK0# 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 VSS DQS17 A10 CB6 VDDQ CB7 VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VDDQ S0# S1# DM5 VSS DQ46 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 DQ47 NC VDDQ DQ52 DQ53 NF VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved. 512MB (x72, DR ECC) 184-Pin DDR UDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Symbol Type Description A[12:0] Input BA[1:0] Input CK[2:0], CK#[2:0] Input CKE[1:0] Input DM[7:0] (DQS[17:9]) Input S#[1:0] Input SA[2:0]2 Input SCL Input RAS#, CAS#, WE# Input DQ[63:0] DQS[8:0] I/O I/O SDA I/O VDD/VDDQ VDDSPD VREF VSS NC NF Supply Supply Supply Supply – Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA[1:0]) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA[1:0] define which mode register (or extended mode register) is loaded during the LOAD MODE REGISTER command. Bank address: BA[1:0] define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and (registered LOW) deactivates the internal clock, input buffers, and output drivers. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. Chip selects: S# (registered LOW) enables and (registered HIGH) disables the command decoder. Presence-detect address inputs: These pins are used to configure the presence-detect device. Serial clock for presence-detect: SCL is used to synchronize the presencedetect data transfer to and from the module. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Data input/output: Data bus. Data strobe: Output with read data, input with write data. DQS is edgealigned with read data, center-aligned with write data. Used to capture data. Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Power supply: 2.5V ±0.2V (-40B: 2.6V ±0.1V). Serial EEPROM positive power supply: 2.3–3.6V. SSTL_2 reference voltage (VDD/2). Ground. No connect: These pins are not connected on the module. No function: These pins are connected, but provide no function to the module. PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved. 512MB (x72, DR ECC) 184-Pin DDR UDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# S0# DQS0 DQS4 DQS9 DQS13 DM CS# DQS DQ DQ DQ DQ U17 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U1 DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS5 DQS10 DQS14 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ U16 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U2 DQ DQ DQ DQ DQ DQS2 DQS6 DQS11 DQS15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ DQ U15 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U3 DQ DQ DQ DQ DQS3 DQS7 DQS12 DQS16 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ DQ U14 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U4 DQ DQ DQ DQ DQ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS# DQS DQ DQ DQ U9 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U18 DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ DQ U13 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U5 DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ U6 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U12 DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ DQ U11 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U7 DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ U8 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U10 DQ DQ DQ DQ DQS8 DQS17 Rank0 = U1, U3, U6, U8, U9, U11, U13, U14, U16 Rank1 = U2, U4, U5, U7, U10, U12, U15, U17, U18 U19 SCL SPD EEPROM WP A0 VSS A1 U4, U5, U9 U13, U14, U18 CK1 CK1# U1-U3, U15-U17 CK2 CK2# U6-U8, U10-U12 SDA A2 SA0 SA1 SA2 BA[1:0] BA[1:0]: DDR SDRAM A[12:0] A[12:0]: DDR SDRAM VDDSPD SPD EEPROM CAS#: DDR SDRAM VDD/VDDQ DDR SDRAM VREF DDR SDRAM VSS DDR SDRAM RAS# RAS#: DDR SDRAM CAS# WE# WE#: DDR SDRAM CKE1 CKE0: DDR SDRAM Rank0 CKE0 CKE1: DDR SDRAM Rank1 PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN CK0 CK0# 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved. 512MB (x72, DR ECC) 184-Pin DDR UDIMM General Description General Description The MT18VDDF6472A is high-speed, CMOS, dynamic random access 512MB a memory modules organized in x72 configuration. These modules use 256Mb DDR SDRAM devices with four internal banks. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various DDR SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0], which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected to VSS, permanently disabling hardware write protect. PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved. 512MB (x72, DR ECC) 184-Pin DDR UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 6 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated on the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 6: Symbol VDD/VDDQ VIN, VOUT II IOZ TA Absolute Maximum Ratings Parameter Min Max Units VDD/VDDQ supply voltage relative to VSS Voltage on any pin relative to VSS Address inputs, Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 1.35V (All other pins not under RAS#, CAS#, WE#, BA test = 0V) S#, CKE CK[2:0], CK#[2:0] DM Output leakage current; 0V VOUT VDDQ; DQ are DQ, DQS disabled DRAM ambient operating temperature1 Commercial Industrial –1.0 –0.5 –36 3.6 3.2 36 V V µA 18 –12 –4 –10 18 12 4 10 µA 0 –40 70 85 °C °C Notes: 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s Web site. Input Capacitance Micron encourages designers to simulate the performance of the module to achieve optimum values. Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades, as shown in Table 7. Table 7: Module and Component Speed Grades Module Speed Grade Component Speed Grade -335 -265 -6 -75 PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved. 512MB (x72, DR ECC) 184-Pin DDR UDIMM Electrical Specifications IDD Specifications Table 8: IDD Specifications and Conditions – 512MB (Die Revision K) Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition tRC tRC (MIN); tCK tCK = = (MIN); Operating one bank active-precharge current: DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN); tCK = t CK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS, and DM Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) Auto refresh current tREFC = 7.8125µs Self refresh current: CKE 0.2V Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Notes: Symbol -335 Units IDD01 846 mA IDD11 1071 mA IDD2P2 72 mA IDD2F2 900 mA IDD3P2 540 mA IDD3N2 990 mA IDD4R1 1476 mA IDD4W1 1476 mA IDD52 1476 108 72 2466 mA mA mA mA IDD5A2 IDD62 IDD71 1. Value calculated as one module rank in this operating condition; all other module ranks are in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved. 512MB (x72, DR ECC) 184-Pin DDR UDIMM Electrical Specifications Table 9: IDD Specifications and Conditions – 512MB (Die Revision M) Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition t t t t Operating one bank active-precharge current: RC = RC (MIN); CK = CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN); tCK = t CK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS, and DM Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) Auto refresh current tREFC = 7.8125µs Self refresh current: CKE 0.2V Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Notes: Symbol -335 Units IDD01 576 mA IDD11 711 mA IDD2P2 72 mA IDD2F2 414 mA IDD3P2 252 mA IDD3N2 540 mA IDD4R1 801 mA IDD4W1 891 mA IDD52 981 108 72 1611 mA mA mA mA IDD5A2 IDD62 IDD71 1. Value calculated as one module rank in this operating condition; all other module ranks are in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved. 512MB (x72, DR ECC) 184-Pin DDR UDIMM Serial Presence-Detect Serial Presence-Detect Table 10: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICC 2.3 VDDSPD × 0.7 –1.0 – – – – – 3.6 VDDSPD + 0.5 VDDSPD × 0.3 0.4 10 10 30 2.0 V V V V µA µA µA mA Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD Power supply current: SCL clock frequency = 100 kHz Table 11: Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time Clock/data fall time Clock/data rise time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: Symbol Min Max Units Notes tAA 0.2 1.3 200 – – 0 0.6 0.6 – 1.3 – 100 0.6 0.6 – 0.9 – – 300 300 – – – 50 – 400 – – – 10 µs µs ns ns ns µs µs µs ns µs kHz ns µs µs ms 1 tBUF tDH tF tR tHD:DAT tHD:STA tHIGH tI tLOW fSCL tSU:DAT tSU:STA tSU:STO t WRC 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron’s SPD page: www.micron.com/SPD. PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved. 512MB (x72, DR ECC) 184-Pin DDR UDIMM Module Dimensions Module Dimensions Figure 3: 184-Pin DDR UDIMM 4.0 (0.157) MAX Front view 133.5 (5.256) 133.2 (5.244) 2.0 (0.79) R (4X) U1 U2 U3 U4 U9 U5 U6 U7 U8 U19 2.5 (0.98) D (2X) 17.78 (0.07) TYP. 25.53 (1.005) 25.27 (0.995) 2.3 (0.91) TYP. 0.90 (0.035) R 2.21 (0.087) TYP. 1.27 (0.05) TYP PIN 1 1.02 (0.04) TYP PIN 92 1.37 (0.054) 1.17 (0.046) 1.0 (0.039) TYP. 73.28 (2.885) TYP 120.65 (4.75) TYP Back view U10 U11 U12 U13 U18 U14 U15 U16 U17 10.0 (0.394) TYP. 2.92 (0.115) TYP. 6.35 (0.250) TYP PIN 184 49.53 (1.95) TYP Notes: PIN 93 64.77 (2.55) TYP 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef84a58109 / Source: 09005aef84a58159 DDF18C64x72AY.fm - Rev. A 2/12 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2012 Micron Technology, Inc. All rights reserved.