60 GHz Receiver (Rx) Waveguide Module

60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
The PEM002 is a highly integrated millimeter wave receiver that covers the 60 GHz global unlicensed spectrum allocations
packaged in a standard waveguide module. Receiver architecture is a double conversion, sliding IF with wide bandwidth
capability through the conversion chain down to baseband. The I/Q analog interface along with built-in AM and FM detectors
provides for flexibility in design and applications. The receiver incorporates a complete waveguide interface with low-loss
transition between the chip and the WR15 waveguide port. The integrated package is small and lightweight, with a simple
to use multi-pin ST4 connector for power, reference clock, digital control port and baseband signals. Either of two reference
clocks can be used for setting 540 MHz or 500 MHz channel spacing.
Features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Complete millimeter wave receiver
WR-15, UG-385/U flange
Operates in the 57 to 66 GHz unlicensed band
6 dB noise figure
Up to 1.8 GHz modulation bandwidth
I/Q analog baseband interface
Integrated AM/ASK and FM/FSK detectors
On chip synthesizer covers 57 to 64.8 GHz
500 MHz or 540 MHz step size
285.714 MHz clock for 500 MHz step size
308.572 MHz clock for 540 MHz step size
Power, control, signals on ST4 connector
Temperature sensor
Applications
•
•
•
•
•
•
•
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•
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802.11ad: 58.32, 60.48, 62.64, 64.80 GHz
802.11aj: 59.94, 61.02, 62.10, 63.18 GHz
Any Channel (500 MHz or 540 MHz) 57-64.8 GHz
Multi-Gbps Digital Communications
HD Video Transmission
Millimeter Wave Radar
Millimeter Wave Radiometry
Millimeter Wave Imaging
Microwave Temperature Profiling (MTP)
Development for 802.11ad and 802.11aj
ATE Equipment for 60 GHz Manufacturing Test
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PEM002 REV
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60 GHz Receiver (Rx) Waveguide Module
PEM002
G
G
TECHNICAL DATA SHEET
1.057"
(26.85 mm)
WR-15 UG-385/U Flange
.750"
(19.05 mm)
.792"
(20.12 mm)
.591"
(15.00 mm)
Samtec ST4-20 Connector
.394"
(10.00 mm)
.354"
(9.00 mm)
.315"
(8.00 mm)
Pin 1
G
G
Figure 1 PEM002 Mechanical Dimensions
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60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
G
G
Samtec ST4-20
Pin 1
2.7V
1.5V
VCC
2.7V
2.7V
2.7V
2.7V
2.7V
2.7V
1.5V
VCC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VDD
VCC
VCC
VCC
VCC
VCC
VDD
CLOCK
DATA
SCANOUT
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
OUT_QM
OUT_QP
OUT_IM
OUT_IP
REFCLKM
REFCLKP
Q1_E
Q1_B_C
RESET
ENABLE
Mating Connector:
Samtec SS4-20-3.00-L-D-K-TR
Figure 2 PEM002 Interface Connector Pinout
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60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
Table 1 Performance Specifications*
Parameter
Min
Frequency Range
57.0
Typ
Max
Unit
64.8
GHz
Comment
Channel Spacing
540
MHz
308.571 MHz Reference
Channel Spacing
500
MHz
285.714 MHz Reference
GHz
Max BW setting, double-sided at 3 dB
Modulation Bandwidth
Gain, Max
Gain, Range
1.8
53
67
dB
70
65
dB
Gain, Step Size
1.25
dB
Image Rejection
>35
dB
Input IP3
-27
dBm
At Max Gain
Input P1dB
-36
dBm
At Min Gain
Sideband Suppression
27
dBc
Noise Figure
6
dB
Phase Noise @ 100 kHz
-72
dBc/Hz
Phase Noise @ 1 MHz
-86
dBc/Hz
Phase Noise @ 10 MHz
-111
dBc/Hz
Phase Noise @ 100 MHz
-125
dBc/Hz
Phase Noise @ 1 GHz
-127
dBc/Hz
PLL Loop Bandwidth
200
kHz
I/Q Balance Phase
±3
degrees
I/Q Balance Amplitude
±1
dB
*Test Conditions:
Reference Frequency
Temperature
Input Signal Level
IF Bandwidth
Output Impedance
Output Signal Level
At Max Gain
308.571 MHz
25°C
-65 dBm
Max
50 ohms, 4 output ports: I +/- and Q +/- (100 ohm differential)
Referenced to single 50 ohm output for gain specifications
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60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
Table 2 Recommended Operating Conditions
Description
Power Supplies
Serial Control Port
Logic High
Serial Control Port
Logic Low
Name
ST4 Pin #
Min
Vcc
8,22,24,26,
28,30,32
2.565
Vdd
10,34
1.425
1.0
-.05
DATA
38
CLOCK
36
ENABLE
39
RESET
37
SCANOUT
40
DATA
38
CLOCK
36
ENABLE
39
RESET
37
SCANOUT
40
Typ
Max
Unit
2.7
2.835
V
1.5
1.575
V
1.3
1.575
V
0.1
0.33
V
100
MHz
Serial Control Port Speed
Reference Clock1
I and Q Baseband2
Temperature Sensor3
REFCLKM
25
REFCLKP
27
OUT_QM
1
OUT_QP
3
OUT_IM
7
OUT_QP
9
Q1_E
31
Q1_B_C
33
-5
0
3
dBm
10
100
400
mVPP
Vcc 2.7V Supply Current
Icc
225
mA
Vdd 1.5V Supply Current
Idd
8
mA
Operating Temperature
TA
-40
85
°C
1
Reference clock power level specified at 100 ohms differential
2
Baseband voltage at each of the 4 baseband outputs (I +/-, Q +/-)
3
Temperature sensor is a 2N3904 NPN transistor die connected as a diode junction
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60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
Table 3 Absolute Maximum Ratings
Description
Power Supplies
Serial Control Port
Logic High
Name
Vcc
Vdd
10,34
DATA
38
CLOCK
36
ENABLE
39
1
37
RESET
Serial Control Port
Logic Low
SCANOUT
40
DATA
38
CLOCK
36
ENABLE
39
1
37
RESET
Reference Clock
I and Q Baseband
SCANOUT
40
REFCLKM
25
REFCLKP
27
OUT_QM
1
OUT_QP
3
OUT_IM
7
OUT_QP
9
GND
1
ST4 Pin #
8,22,24,26,
28,30,32
MAX
2.85 V
1.6 V
1.575
-.05
5 dBm
5,11,17,23,29,35
750 mVPP
± 50 mV
Power Dissipation
PD
760 mW
Storage Temperature
TS
-55 to 150 C
Operating Temperature
TA
-40 to 85 C
Assertion of RESET, active high, asynchronously resets all registers
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60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
Receiver Architecture
The PEM002 receiver uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at 1/7 the
RF carrier frequency, and the VCO is at 2/7 the RF carrier frequency. The LO is 3x the VCO frequency. The LO and IF are
generated from a built-in synthesizer that has a step size at the RF carrier frequency of either 500 MHz or 540 MHz depending
upon which reference clock frequency is used. The 540 MHz step size uses a 308.571 MHz reference, and the 500 MHz step
uses a 285.714 MHz frequency. The IEEE channels for 802.11ad and 802.11aj are supported when the 540 MHz step size is
used. An RF signal in the range of 57 to 64.8 GHz is coupled to the LNA via the low-loss WR15 waveguide port. The LO is
mixed with the RF signal after the LNA and down converted the IF signal in the 8 to 9 GHz range. A notch filter attenuates the
image frequency. The IF signal is filtered with a variable gain amplifier and filter with approximately 20 dB range, which is then
fed into the quadrature mixers which down converts directly to baseband. There are also selectable AM and FM detectors for
non-coherent modulation schemes. Additional variable gain and filtering are available in the baseband amplifier section which
follows the I/Q mixers and detectors. The overall phase noise and I/Q balance specifications are sufficient for up to 16 QAM
operation. Configuration and settings are controlled through a digital serial interface port. The block diagram below shows
the various stages and circuits in the module.
Synthesizer
57.0 to 64.8 GHz 0.5 or 0.54 GHz step
x3
REFCLKP
REFCLKM
Div
2
LNA
AM
DET
WR-15 Waveguide
UG-385/U Flange
Var BB
Filter
BB VGA
OUT_IP
OUT_IM
0º
90º
Var IF
Filter
IF VGA
OUT_QP
OUT_QM
FM
DET
Var BB
Filter
BB VGA
Serial Control Registers
SCANOUT
DATA
CLOCK
ENABLE
RESET
+1.5
+2.7
Figure 3 PEM002 Block Diagram
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60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
Synthesizer Design
The PEM002 receiver uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at 1/7 the
RF carrier frequency, and the VCO is at 2/7 the RF carrier frequency. The LO is 3x the VCO frequency.
The tables below show the RF carrier, IF, VCO and LO for the frequency range from 57 GHz to 64.80 GHz at 540 MHz and
500 MHz channel spacing respectively. The reference clock for the synthesizer at 540 MHz spacing is 308.571 MHz; for 500
MHz spacing it is 285.714 MHz. The loop bandwidth of the synthesizer phase lock loop is 200 kHz.
540 MHz Spacing
500 MHz Spacing
fRF
IF
VCO
LO
fRF
IF
VCO
LO
57.24
8.177
16.354
49.063
57.00
8.143
16.286
48.857
57.78
8.254
16.509
49.526
57.50
8.214
16.429
49.286
58.32
8.331
16.663
49.989
58.00
8.286
16.571
49.714
58.86
8.409
16.817
50.451
58.50
8.357
16.714
50.143
59.40
8.486
16.971
50.914
59.00
8.429
16.857
50.571
59.94
8.563
17.126
51.377
59.50
8.500
17.000
51.000
60.48
8.640
17.280
51.840
60.00
8.571
17.413
51.429
61.02
8.717
17.434
52.303
60.50
8.643
17.286
51.587
61.56
8.794
17.589
52.766
61.00
8.714
17.429
52.286
62.10
8.871
17.743
53.229
61.50
8.786
17.571
52.714
62.64
8.949
17.897
53.691
62.00
8.857
17.714
53.143
63.18
9.026
18.051
54.154
62.50
8.929
18.587
53.571
63.72
9.103
18.206
54.617
63.00
9.000
18.000
54.000
64.26
9.180
18.360
55.080
63.50
9.071
18.143
54.429
64.80
9.257
18.514
55.543
64.00
9.143
18.286
54.857
Figure 4 Synthesizer RF, IF, VCO and LO Frequencies
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60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
Digital Control Registers and Serial Interface Protocol - Write Operation
The PEM002 is configured via the serial control port which transfers data synchronously to or from (write or read operation)
a register location. Register locations are organized into 16, byte-wide (8-bit) locations. The register locations are written to
or read from one byte at a time as shown in Figures 5 and 6 respectively. Figure 5 shows the sequence of the digital control
signals for the ENABLE, CLOCK and DATA input pins (ST4 connector, pins 39, 36 and 38 respectively) to write a single byte
into the control register. After the ENABLE signal goes low, the first of 18 data bits (bit 0) is placed on the data pin, and 2
ns or more after the DATA signal stabilizes, the CLOCK signal goes high which clocks in data bit 0. The DATA signal must
remain stable for at least 2 ns after the rising edge of the CLOCK. The signal levels are 1.5V CMOS, 50 kΩ impedance, with
a maximum clock rate of 100 MHz.
A write operation requires an 18 bit field associated with 18 clock pulses as shown in Figure 5. The 18 bit field contains the
8-bit data (LSB is clocked in first), followed by the byte address (BYTE 0 through BYTE 15, 000000 to 001111, LSB first,
only 4 of the 6 bits are used with the two MSBs set to 0), the read/write (R/W) bit (write = 1), and the module address which
distinguishes between a transmitter module and receiver module (for the PEM002 receiver, RX module = 111).
After clock pulse 17 (18 total pulses), the ENABLE signal is returned to a high state to load the register byte into the module.
The CLOCK signal must be stable in the low state at least 2 ns prior to the rising edge of the ENABLE signal.
ENABLE
0
1
2
0
1
2
17
CLOCK
5
6
7
8
Byte Address
LSB
MSB
Data
LSB
9 10 11 12 13 14 15 16 17
R/W TX/RX Module
MSB
4
LSB
3
MSB
DATA
Figure 5 Write Operation Timing Diagram
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60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
Digital Control Registers and Serial Interface Protocol - Read Operation
Figure 6 shows the sequence of control signals at the ENABLE, CLOCK and DATA pins to read a single byte at a register
location. A read operation requires a 27 bit field: The first 18 bits are used to clock in the bits on the DATA input pin. The first 8
bits during a read operation are “don’t care” bits as they are placeholders for the 8-bit byte data which would be present during
a write operation. The following 10 bits are composed of the byte address (BYTE 0 through BYTE 15, 000000 to 001111, LSB
first, only 4 of the 6 bits are used with the two MSBs set to 0), the read/write (R/W) bit (read = 0), and the module address which
distinguishes between a transmitter module and receiver module (for the PEM002 receiver, RX module = 111).
After clock pulse 17 (18 total pulses), the ENABLE signal is returned to a high state while the clock signal is low, then a single
clock pulse (pulse 18) is sent during the ENABLE signal high period. The ENABLE signal then returns to the low state while
the CLOCK signal is low. At each of the subsequent 8 CLOCK pulses, the 8-bit data from the specified register location is
available at the SCANOUT pin, LSB first. Note that the DATA signal must remain in the low state during the period from clock
pulse 18 through 26. Following clock pulse 26, the ENABLE signal goes high while the CLOCK signal is low to end the read
operation.
ENABLE
0
1
2
0
1
2
17 18
26
CLOCK
5
6
7
8
Byte Address
LSB
MSB
LSB
SCAN OUT
9 10 11 12 13 14 15 16 17
R/W TX/RX Module
MSB
4
Data
LSB
3
MSB
DATA
0
1
2
3
4
5
6
7
MSB
LSB
Read Data
Figure 6 Read Operation Timing Diagram
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60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
Table 4.1 Register Byte Functions
Bit
Function
Name
BYTE 0
7
6
ask_pwrdn
Active high to power down ASK demodulator
bbamp_pwrdn_i
Active high to power down I-channel baseband amplifier
5
4
bbamp_pwrdn_q
Active high to power down Q-channel baseband amplifier
divider_pwrdn
Active high to power down local oscillator divider
3
if_bgmux_pwrdn
Active high to power down one of three on-chip refs (IF) and associated mux
2 ifmix_pwrdn_i
1 ifmix_pwrdn_q
0 ifvga_pwrdn
BYTE 1
7 ipc_pwrdn
Active high to power down I-channel IF to baseband mixer
Active high to power down Q-channel IF to baseband mixer
Active high to power down IF variable gain amplifier
Active high to power down module current reference generator
6
5
4
3
lna_pwrdn
Active high to power down low noise amplifier and reference
rfmix_pwrdn
Active high to power down RF to IF mixer
tripler_pwrdn
Active high to power down frequency tripler
bbamp_atten1_0
First baseband attenuator: bits <2:3>
2
bbamp_atten1_1
11 = 18 dB; 10 = 12 dB; 01 = 6 dB; 00 = 0 dB
1 bbamp_atten2_0
0 bbamp_atten2_1
BYTE 2
7
6
5
4
3
2
1
0
bbamp_attenfi_0
bbamp_attenfi_1
bbamp_attenfi_2
bbamp_attenfq_0
bbamp_attenfq_1
bbamp_attenfq_2
Second baseband attenuator: bits <0:1>
11 = 18 dB; 10 = 12 dB; 01 = 6 dB; 00 = 0 dB
I Channel baseband fine attenuator: bits <5:7>
101 = 5 dB; 100 = 4 dB; 011 = 3 dB; 010 = 2 dB; 001 = 1 dB; 000 = 0 dB
Q Channel baseband fine attenuator: bits <2:4>
101 = 5 dB; 100 = 4 dB; 011 = 3 dB; 010 = 2 dB; 001 = 1 dB; 000 = 0 dB
bbamp_selask
Active high to switch the ASK detector into the I channel baseband amplifier
bbamp_sigshort
Active high to short the inputs to the I and Q channel baseband amplifiers
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TECHNICAL DATA SHEET
PEM002
Table 4.2 Register Byte Functions
Bit
Function
Name
BYTE 3
7
6
bbamp_selbw_0
Baseband amplifiers low pass filter corner: bits <6:7>
bbamp_selbw_1
00 = 1.4 GHz; 01 = 500 MHz ; 11 = 300 MHz; 00 = 200 MHz
5
4
bbamp_selhp_0
Baseband amplifiers high pass filter corner: bits <4:5>
bbamp_selhp_1
00 = 30 kHz; 01 = 300 kHz ; 10 = 1.5 MHz
3
bg_monitor_sel_1
2 bg_monitor_sel_0
1 If_refsel
0 lna_refsel
BYTE 4
7 ifvga_bias_2
6 ifvga_bias_1
5
4
3
ifvga_bias_0
2
ifvga_tune_2
ifvga_tune_4
Reserved: bits <3:0> = 0011 for normal operation
IF VGA bias and IF filter alignment; bits <7:0> = 1001111x for normal operation
ifvga_tune_3
1 ifvga_tune_1
0 not used
BYTE 5
7
6
5
4
3
2
1
0
ifvga_vga_adj_3
ifvga_vga_adj_2
IF VGA gain control bits; bits <7:4> = 0000 highest gain, 1111 lowest gain
ifvga_vga_adj_1
Attenuation 1.25 dB/step, ≈ 20 dB maximum
ifvga_vga_adj_0
rfmix_tune_3
rfmix_tune_2
IF filter alignment in the RF mixer; bits <3:0> = 1111 for normal operation
rfmix_tune_1
rfmix_tune_0
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PEM002
Table 4.3 Register Byte Functions
Bit
Function
Name
BYTE 6
7
6
tripler_bias_13
tripler_bias_12
5
4
tripler_bias_10
3
tripler_bias_9
2
1
tripler_bias_8
tripler_bias_11
tripler_bias_7
0 tripler_bias_6
BYTE 7
7 tripler_bias_5
6 tripler_bias_4
5 tripler_bias_3
4
3
tripler_bias_2
4
3
2
1
0
Frequency tripler bias (lower 6 bit portion): bits <7:2> = 011011 default
tripler_bias_1
2 tripler_bias_0
1 bbamp_sel_fm
0 fm_pwrdn
BYTE 8
7
6
5
Frequency tripler bias (upper 8 bit portion): bits <7:0> = 10111111 default
Active high to switch the FM detector into the Q channel baseband amplifier
Active high to power down FM detector
lna_bias_2
lna_bias_1
IF VGA gain control bits; bits <7:4> = 0000 highest gain, 1111 lowest gain
lna_bias_0
not used
not used
ifvga_q_cntrl_2
ifvga_q_cntrl_1
ifvga_q_cntrl_0
Not used; bits <4:3> = xx
IF filter Q in the VGA amplifier; bits <2:0> = 000 for highest Q and gain
For reduced Q and wider bandwidth, bits <2:0> = 001,100,101,111 in sequence
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PEM002
Table 4.4 Register Byte Functions
Bit
Function
Name
BYTE 9
7 not used
6 not used
5 not used
4
not used
3
not used
2 not used
1 not used
0 not used
BYTE 10
7 rdacin_5
6 rdacin_4
5 rdacin_3
4 rdacin_2
3 rdacin_1
2 rdacin_0
1 synreset
0 divratio_4
BYTE 11
7
divratio_3
6
divratio_2
5
divratio_1
4
3
divratio_0
2
1
0
Not used: bits <7:0> = xxxxxxxx
VCO amplitude DAC; bits<7:2> = 111100 for normal operation
Synthesizer reset; bit <1> = 0 for normal operation
Synthesizer divider ratio bit 4 (see Tables 5.1 and 5.2)
Synthesizer divider ratio bits 3:0 (see Tables 5.1 and 5.2)
band_2
band_1
VCO band tuning bits 2:0 (see Tables 5.1 and 5.2)
band_0
rfseldiv
Reserved; bit <0> = 1 for normal operation
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PEM002
Table 4.5 Register Byte Functions
Bit
Function
Name
BYTE 12
7
6
cpbias_2
cpbias_1
5
4
vrsel_3
3
vrsel_2
Synthesizer charge pump bias; bits <7:5> = 010 for normal operation
cpbias_0
2 vrsel_1
1 vrsel_0
0 refselvco
BYTE 13
7 muxref
6 div_4
5 en_dc
Synthesizer lock detector window width; bits <4:1> = 1111 for normal operation
Reserved; bit <0> = 1 for normal operation
Reserved; bit <7> = 1 for normal operation
Enable synthesizer divider bit 4; bit <6> = 0 for normal operation
Synthesizer reference input DC coupling; bit <5> = 0 for normal operation
4
3
ini
Reserved; bit <4> = 0 for normal operation
pd_div_15
Active high to power down 1.5V circuits in synthesizer divider
2
1
pd_div_27
Active high to power down 2.7V circuits in synthesizer divider
pd_qp
Active high to power down synthesizer charge pump
0 pd_vco
BYTE 14
7
6
5
4
3
2
1
0
Active high to power down synthesizer VCO
pd_cal
Active high to power down VCO calibration; bit <7> = 0 for normal operation
muxout
Multiplexer control for ability to read byte 15; bit <6> = 1 for normal operation
pdcalc15
Active high to power down VCO ALC; bit <5> = 1 for normal operation
pload
Active high to load adjustment of VCO; bit <4> = 1 for normal operation
wide_1
wide_2
slew_1
slew_0
Control for VCO ALC loop; bits <3:2> = 01 for normal operation
Slew rate control of sub-integer N divider; bits <1:0> = 10 for normal operation
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inventory and certifications: 60 GHz Receiver (Rx) Waveguide Module PEM002
PEM002 REV
15
60 GHz Receiver (Rx) Waveguide Module
TECHNICAL DATA SHEET
PEM002
Table 4.6 Register Byte Functions
Table 4.6 Register Byte Functions
Bit
Name
BYTE 15
7 comp_p
6 comp_n
5 rdacmsb_2
4
3
2
1
0
Function
Synthesizer lock indication (read only): bits <7:6> = 01 locked,
= 11 above window, = 00 below window, = 10 disallowed indicating error
rdacmsb_1
rdacmsb_0
Reserved (read only)
rdacmux_0
rdacmux_1
rdacmux_2
Table 5.1 540 MHz Channels
Channel
57.24
57.78
58.32
58.86
59.40
59.94
60.48
61.02
61.56
62.10
62.64
63.18
63.72
64.26 2
64.80 2
Divider Band 1 Byte 10
Byte 11
001
001
010
010
011
011
100
100
101
101
110
110
111
111
111
01010011
01000011
00110101
00100101
00010111
00000111
11111001
00001001
00011011
00101011
00111101
01001101
01011111
01101111
01111111
10101
10100
10011
10010
10001
10000
11111
00000
00001
00010
00011
00100
00101
00110
00111
11110001
11110001
11110001
11110001
11110001
11110001
11110001
11110000
11110000
11110000
11110000
11110000
11110000
11110000
11110000
Reference: 308.571 MHz
Note 1: Band setting typical, may
change from module to module and
temperature.
Note 2: Operation above 64 GHz not
guaranteed over full operating
temperature range.
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inventory and certifications: 601GHz Receiver (Rx) Waveguide Module PEM002
Channel
57.0
57.5
58.0
58.5
59.0
59.5
60.0
60.5
Divider Band
00001
00010
00011
00100
00101
00110
00111
01000
000
000
001
001
010
010
011
011
Byte 10
Byte 11
11110000
11110000
11110000
11110000
11110000
11110000
11110000
11110000
00010001
00100001
00110011
01000011
01010101
01100101
01110111
PEM002 REV
10000111
16
59.40
59.94
60.48
61.02
61.56
62.10
62.64
63.18
60 63.72
GHz
64.26 2
64.80 2
10001
10000
11111
00000
00001
00010
00011
00100
Receiver
00101
00110
00111
TECHNICAL DATA SHEET
011
011
100
100
101
101
110
110
(Rx)
111
111
111
11110001 00010111
11110001 00000111
11110001 11111001
11110000 00001001
Reference: 308.571 MHz
11110000 00011011
11110000 00101011
Note 1: Band setting typical, may
11110000 00111101
change from module to module and
11110000 01001101
temperature.
Waveguide
Module
11110000 01011111
Note 2: Operation above 64 GHz not
11110000 01101111
guaranteed over full operating
11110000 01111111
temperature range.
PEM002
Table 5.1 500 MHz Channels
Channel
57.0
57.5
58.0
58.5
59.0
59.5
60.0
60.5
61.0
61.5
62.0
62.5
63.0
63.5
64.0
Divider Band 1 Byte 10
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
000
000
001
001
010
010
011
011
100
100
101
101
110
110
111
11110000
11110000
11110000
11110000
11110000
11110000
11110000
11110000
11110000
11110000
11110000
11110000
11110000
11110000
11110000
Byte 11
00010001
00100001
00110011
01000011
01010101
01100101
01110111
10000111
10011001
10101001
10111011
11001011
11011101
11101101
11111111
Reference: 285.714 MHz
Note 1: Band setting typical, may
change from module to module and
temperature.
60 GHz Receiver (Rx) Waveguide Module from Pasternack Enterprises has same day shipment for domestic and International
orders. Our RF, microwave and fiber optic products maintain a 99% availability and are part of the broadest selection in the
industry.
Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price,
inventory and certifications: 60 GHz Receiver (Rx) Waveguide Module PEM002
URL: http://www.pasternack.com/60-ghz-receiver-module-pem002-p.aspx
PEM002 REV
17
PEM002 CAD Drawing
Millimeter Wave Receiver Module Operating From 57 GHz To 64 GHz
© 2013 Pasternack Enterprises All Rights Reserved
PEM002 REV
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