Micropower Single-Supply Rail-to-Rail Input/Output Op Amps OP191/OP291/OP491 NC OUTA 1 8 +V 7 +V –INA 2 7 OUTB 6 OUTA +INA 3 6 –INB 5 NC 5 +INB –V 4 NC = NO CONNECT –V 4 Figure 1. 8-Lead Narrow-Body SOIC OUTA 1 14 OUTD –INA 2 13 –IND +INA 3 12 +IND +V 4 11 –V OP491 +INB 5 10 +INC –INB 6 9 –INC OUTB 7 8 OUTC OP291 Figure 2. 8-Lead Narrow-Body SOIC OUTA 1 –INA 2 - + + - +INA 3 OP491 +V 4 +INB 5 –INB 6 - + OUTB 7 Figure 3. 14-Lead Narrow-Body SOIC OUTD 13 –IND 12 +IND 11 –V 10 +INC 9 –INC 8 OUTC Figure 4. 14-Lead PDIP OUTA 1 14 OUTD –INA 2 13 –IND +INA 3 12 +IND +V 4 11 –V +INB 5 10 +INC –INB 6 9 –INC OUTB 7 8 OUTC OP491 14 00294-005 OP191 00294-001 +INA 3 00294-002 8 00294-003 Industrial process control Battery-powered instrumentation Power supply control and protection Telecommunications Remote sensors Low voltage strain gage amplifiers DAC output amplifiers NC 1 –INA 2 + APPLICATIONS PIN CONFIGURATIONS - Single-supply operation: 2.7 V to 12 V Wide input voltage range Rail-to-rail output swing Low supply current: 300 μA/amp Wide bandwidth: 3 MHz Slew rate: 0.5 V/μs Low offset voltage: 700 μV No phase reversal 00294-004 FEATURES Figure 5. 14-Lead TSSOP GENERAL DESCRIPTION The OP191, OP291, and OP491 are single, dual, and quad micropower, single-supply, 3 MHz bandwidth amplifiers featuring rail-to-rail inputs and outputs. All are guaranteed to operate from a +3 V single supply as well as ±5 V dual supplies. Fabricated on Analog Devices CBCMOS process, the OPx91 family has a unique input stage that allows the input voltage to safely extend 10 V beyond either supply without any phase inversion or latch-up. The output voltage swings to within millivolts of the supplies and continues to sink or source current all the way to the supplies. The ability to swing rail-to-rail at both the input and output enables designers to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios. The OP191/OP291/OP491 are specified over the extended industrial –40°C to +125°C temperature range. The OP191 single and OP291 dual amplifiers are available in 8-lead plastic SOIC surface-mount packages. The OP491 quad is available in a 14-lead PDIP, a narrow 14-lead SOIC package, and a 14-lead TSSOP. Applications for these amplifiers include portable telecommunications equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezo electric, and resistive transducers. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1994–2010 Analog Devices, Inc. All rights reserved. OP191/OP291/OP491 TABLE OF CONTENTS Features .............................................................................................. 1 Overdrive Recovery ................................................................... 18 Applications ....................................................................................... 1 Applications Information .............................................................. 19 Pin Configurations ........................................................................... 1 Single 3 V Supply, Instrumentation Amplifier ....................... 19 General Description ......................................................................... 1 Single-Supply RTD Amplifier ................................................... 19 Revision History ............................................................................... 2 A 2.5 V Reference from a 3 V Supply ...................................... 20 Specifications..................................................................................... 3 5 V Only, 12-Bit DAC Swings Rail-to-Rail ............................. 20 Electrical Specifications ............................................................... 3 A High-Side Current Monitor .................................................. 20 Absolute Maximum Ratings............................................................ 7 A 3 V, Cold Junction Compensated Thermocouple Amplifier ....................................................................................................... 21 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 17 Input Overvoltage Protection ................................................... 18 Output Voltage Phase Reversal ................................................. 18 Single-Supply, Direct Access Arrangement for Modems ...... 21 3 V, 50 Hz/60 Hz Active Notch Filter with False Ground ..... 22 Single-Supply, Half-Wave, and Full-Wave Rectifiers ............. 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 24 REVISION HISTORY 4/10—Rev. D to Rev. E Changes to Input Voltage Parameter, Table 4 ............................... 7 3/04—Rev. B to Rev. C. Changes to OP291 SOIC Pin Configuration .................................1 4/06—Rev. C to Rev. D Changes to Noise Performance, Voltage Density, Table 1 ........... 3 Changes to Noise Performance, Voltage Density, Table 2 ........... 4 Changes to Noise Performance, Voltage Density, Table 3 ........... 5 Changes to Figure 23 and Figure 24 ............................................. 10 Changes to Figure 42 ...................................................................... 13 Changes to Figure 43 ...................................................................... 14 Changes to Figure 57 ...................................................................... 16 Added Figure 58.............................................................................. 16 Changed Reference from Figure 47 to Figure 12........................ 17 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 24 11/03—Rev. A to Rev. B. Edits to General Description ...........................................................1 Edits to Pin Configuration ...............................................................1 Changes to Ordering Guide .............................................................5 Updated Outline Dimensions ....................................................... 19 12/02—Rev. 0 to Rev. A. Edits to General Description ...........................................................1 Edits to Pin Configuration ...............................................................1 Changes to Ordering Guide .............................................................5 Edits to Dice Characteristics ............................................................5 Rev. E | Page 2 of 24 OP191/OP291/OP491 SPECIFICATIONS ELECTRICAL SPECIFICATIONS @ VS = 3.0 V, VCM = 0.1 V, VO = 1.4 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage OP191G Symbol Conditions Min VOS Typ Max Unit 80 500 1 700 1.25 65 95 11 22 3 μV mV μV mV nA nA nA nA V dB dB V/mV V/mV μV/°C pA/°C pA/°C −40°C ≤ TA ≤ +125°C OP291G/OP491G VOS 80 −40°C ≤ TA ≤ +125°C Input Bias Current IB 30 −40°C ≤ TA ≤ +125°C Input Offset Current IOS 0.1 −40°C ≤ TA ≤ +125°C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density VCM = 0 V to 2.9 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = 0.3 V to 2.7 V −40°C ≤ TA ≤ +125°C 0 70 65 25 ∆VOS/∆T ∆IB/∆T ∆IOS/∆T VOH VOL ISC ZOUT PSRR ISY RL = 100 kΩ to GND −40°C to +125°C RL = 2 kΩ to GND −40°C to +125°C RL = 100 kΩ to V+ −40°C to +125°C RL = 2 kΩ to V+ −40°C to +125°C Sink/source −40°C to +125°C f = 1 MHz, AV = 1 VS = 2.7 V to 12 V −40°C ≤ TA ≤ +125°C VO = 0 V −40°C ≤ TA ≤ +125°C +SR –SR BWP tS GBP θO CS RL = 10 kΩ RL = 10 kΩ 1% distortion To 0.01% en p-p en in 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz, RL = 10 kΩ Rev. E | Page 3 of 24 2.95 2.90 2.8 2.70 90 87 70 50 1.1 100 20 2.99 2.98 2.9 2.80 4.5 ±8.75 ±6.0 ±13.50 ±10.5 200 V V V V mV mV mV mV mA mA Ω 80 75 110 110 200 330 dB dB μA μA 40 10 35 75 130 350 480 0.4 0.4 1.2 22 3 45 145 V/μs V/μs kHz μs MHz Degrees dB 2 30 0.8 μV p-p nV/√Hz pA/√Hz OP191/OP291/OP491 @ VS = 5.0 V, VCM = 0.1 V, VO = 1.4 V, TA = 25°C, unless otherwise noted. +5 V specifications are guaranteed by +3 V and ±5 V testing. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage OP191 Symbol Conditions Min VOS Typ Max Unit 80 500 1.0 700 1.25 65 95 11 22 5 μV mV μV mV nA nA nA nA V dB dB V/mV V/mV μV/°C pA/°C pA/°C −40°C ≤ TA ≤ +125°C OP291/OP491 VOS 80 −40°C ≤ TA ≤ +125°C Input Bias Current IB 30 −40°C ≤ TA ≤ +125°C Input Offset Current IOS 0.1 −40°C ≤ TA ≤ +125°C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density ∆VOS/∆T ∆IB/∆T ∆IOS/∆T VOH VOL ISC ZOUT PSRR ISY VCM = 0 V to 4.9 V –40°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = 0.3 V to 4.7 V −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C RL = 100 kΩ to GND −40°C to +125°C RL = 2 kΩ to GND −40°C to +125°C RL = 100 kΩ to V+ −40°C to +125°C RL = 2 kΩ to V+ −40°C to +125°C Sink/source −40°C to +125°C f = 1 MHz, AV = 1 VS = 2.7 V to 12 V −40°C ≤ TA ≤ +125°C VO = 0 V −40°C ≤ TA ≤ +125°C +SR –SR BWP tS GBP θO CS RL = 10 kΩ RL = 10 kΩ 1% distortion To 0.01% en p-p en in 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz, RL = 10 kΩ Rev. E | Page 4 of 24 0 70 65 25 4.95 4.90 4.8 4.65 93 90 70 50 1.1 100 20 4.99 4.98 4.85 4.75 4.5 ±8.75 ±6.0 ±13.5 ±10.5 200 V V V V mV mV mV mV mA mA Ω 80 75 110 110 220 350 dB dB μA μA 40 10 35 75 155 400 500 0.4 0.4 1.2 22 3 45 145 V/μs V/μs kHz μs MHz Degrees dB 2 42 0.8 μV p-p nV/√Hz pA/√Hz OP191/OP291/OP491 @ VO = ±5.0 V, –4.9 V ≤ VCM ≤ +4.9 V, TA = +25°C, unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage OP191 Symbol Conditions Min VOS Typ Max Unit 80 500 1 700 1.25 65 95 μV mV μV mV nA nA 11 22 +5 nA nA V dB dB −40°C ≤ TA ≤ +125°C OP291/OP491 VOS 80 −40°C ≤ TA ≤ +125°C Input Bias Current IB 30 −40°C ≤ TA ≤ +125°C Input Offset Current IOS 0.1 −40°C ≤ TA ≤ +125°C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing Short-Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density VCM = ±5 V −40°C ≤ TA ≤ +125°C RL = +10 kΩ, VO = ±4.7 V −40°C ≤ TA ≤ +125°C −5 75 67 25 ∆VOS/∆T ∆IB/∆T ∆IOS/∆T VO ISC ZOUT PSRR ISY 100 97 70 50 1.1 100 20 V/mV μV/°C pA/°C pA/°C RL = 100 kΩ to GND −40°C to +125°C RL = 2 kΩ to GND –40°C ≤ TA ≤ +125°C Sink/source −40°C to +125°C f = 1 MHz, AV = 1 ±4.93 ±4.90 ±4.80 ±4.65 ±8.75 ±6 ±4.99 ±4.98 ±4.95 ±4.75 ±16.00 ±13 200 V V V V mA mA Ω VS = ±5 V −40°C ≤ TA ≤ +125°C VO = 0 V −40°C ≤ TA ≤ +125°C 80 75 110 100 260 390 dB dB μA μA ±SR BWP tS GBP θO CS RL = 10 kΩ 1% distortion To 0.01% en p-p en in 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz Rev. E | Page 5 of 24 420 550 0.5 1.2 22 3 45 145 V/μs kHz μs MHz Degrees dB 2 42 0.8 μV p-p nV/√Hz pA/√Hz OP191/OP291/OP491 5V Vs = ±5V RL = 2kΩ AV = +1 VIN = 20V p-p 5V 200μs 100 90 INPUT OUTPUT 10 Figure 6. Input and Output with Inputs Overdriven by 5 V Rev. E | Page 6 of 24 00294-006 0% OP191/OP291/OP491 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Input Voltage Differential Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range N, R, RU Packages Operating Temperature Range OP191G/OP291G/OP491G Junction Temperature Range N, R, RU Packages Lead Temperature (Soldering, 60 sec) Rating 16 V GND to (VS + 10 V) 7V Indefinite THERMAL RESISTANCE θJA is specified for the worst-case conditions; that is, θJA is specified for device in socket for PDIP packages; θJA is specified for device soldered in circuit board for TSSOP and SOIC packages. Table 5. Thermal Resistance −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Type 8-Lead SOIC (R) 14-Lead PDIP (N) 14-Lead SOIC (R) 14-Lead TSSOP (RU) ESD CAUTION Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. Rev. E | Page 7 of 24 θJA 158 76 120 180 θJC 43 33 36 35 Unit °C/W °C/W °C/W °C/W OP191/OP291/OP491 TYPICAL PERFORMANCE CHARACTERISTICS 180 40 VS = 3V TA = 25°C BASED ON 1200 OP AMPS 160 INPUT BIAS CURRENT (nA) 140 120 100 80 60 40 20 VCM = 2.9V 10 0 VS = 3V –10 VCM = 0.1V –20 –30 00294-012 –40 20 0 –0.18 –0.10 –0.02 0.06 –60 –40 0.22 0.14 VCM = 0V –50 25 INPUT OFFSET VOLTAGE (mV) 125 Figure 10. Input Bias Current vs. Temperature, VS = 3 V 120 0 VS = 3V –40°C < TA < +125°C BASED ON 600 OP AMPS 60 40 0 00294-013 20 0 1 2 3 5 4 6 VCM = 0.1V –0.4 VCM = 2.9V VS = 3V –0.6 VCM = 3V –0.8 –1.0 VCM = 0V –1.2 –1.4 00294-016 INPUT OFFSET CURRENT (nA) –0.2 80 UNITS 85 TEMPERATURE (°C) Figure 7. OP291 Input Offset Voltage Distribution, VS = 3 V 100 –1.6 –1.8 –40 7 Figure 11. Input Offset Current vs. Temperature, VS = 3 V 0 36 VS = 3V VCM = 0.1V INPUT BIAS CURRENT (nA) 24 –0.04 VCM = 0V –0.06 VCM = 3V –0.08 VCM = 2.9V 25 85 12 6 0 –6 –12 –18 00294-017 –30 –36 125 TEMPERATURE (°C) Figure 9. Input Offset Voltage vs. Temperature, VS = 3 V 18 –24 00294-014 –0.12 –0.14 –40 VS = 3V 30 –0.10 125 TEMPERATURE (°C) Figure 8. OP291 Input Offset Voltage Drift Distribution, VS = 3 V –0.02 85 25 INPUT OFFSET VOLTAGE (µV/°C) INPUT OFFSET VOLTAGE (mV) 00294-015 UNITS VCM = 3V 30 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 INPUT COMMON-MODE VOLTAGE (V) Figure 12. Input Bias Current vs. Input Common-Mode Voltage, VS = 3 V Rev. E | Page 8 of 24 OP191/OP291/OP491 50 3.00 VS = 3V TA = 25°C 40 30 CLOSED-LOOP GAIN (dB) 2.95 2.90 +VO @ RL = 2kΩ 2.85 20 10 0 –10 –20 –30 2.80 25 85 00294-021 VS = 3V 2.75 –40 –40 00294-018 OUTPUT VOLTAGE SWING (V) +VO @ RL = 100kΩ –50 10 125 100 1k TEMPERATURE (°C) Figure 13. Output Voltage Swing vs. Temperature, VS = 3 V 1M 10M 160 VS = 3V TA = 25°C 80 60 40 90 20 45 0 0 –20 –45 –40 –90 10M 1k 10k 100k 1M FREQUENCY (Hz) 120 100 80 60 40 20 0 00294-022 100 CMRR (dB) OPEN PHASE SHIFT (Degrees) 120 100 CMRR VS = 3V TA = 25°C 140 –20 –40 100 00294-019 140 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 17. CMRR vs. Frequency, VS = 3 V Figure 14. Open-Loop Gain and Phase vs. Frequency, VS = 3 V 90 1200 VS = 3V RL = 100kΩ, VCM = 2.9V 1000 89 RL = 100kΩ, VCM = 0.1V 88 CMRR (dB) 800 600 87 86 400 VS = 3V, VO = 0.3V/2.7V 0 –40 25 85 84 –40 125 00294-023 85 200 00294-020 OPEN-LOOP GAIN (dB) 100k Figure 16. Closed-Loop Gain vs. Frequency, VS = 3 V 160 OPEN-LOOP GAIN (V/mV) 10k FREQUENCY (Hz) 25 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. CMRR vs. Temperature, VS = 3 V Figure 15. Open-Loop Gain vs. Temperature, VS = 3 V Rev. E | Page 9 of 24 125 OP191/OP291/OP491 0.35 160 VS = 3V 120 PSRR (dB) 100 80 +PSRR 60 –PSRR 40 20 00294-024 0 –20 –40 100 1k 10k 100k 1M 0.30 0.25 0.20 0.15 0.10 00294-027 140 SUPPLY CURRENT/AMPLIFIER (mA) ±PSRR VS = 3V TA = 25°C 0.05 –40 10M 25 Figure 19. PSRR vs. Frequency, VS = 3 V Figure 22. Supply Current vs. Temperature, VS = +3 V, +5 V, ±5 V 113 3.0 VIN = 2.8V p-p VS = 3V AV = +1 RL = 100kΩ VS = 3V 2.5 MAXIMUM OUTPUT SWING (V) 112 111 110 109 2.0 1.5 1.0 0.5 00294-025 108 107 –40 85 25 0 100 125 00294-028 PSRR (dB) 125 85 TEMPERATURE (°C) FREQUENCY (Hz) 1k 10k 100k 1M FREQUENCY (Hz) TEMPERATURE (°C) Figure 23. Maximum Output Swing vs. Frequency, VS = 3 V Figure 20. PSRR vs. Temperature, VS = 3 V 1k 1.6 VS = 3V +SR 1.0 0.8 0.6 0.4 –SR 0.2 0 –40 00294-026 SLEW RATE (V/µs) 1.2 25 85 100 10 125 00294-029 VOLTAGE NOISE DENSITY (nV/ Hz) 1.4 10 100 1k FREQUENCY (Hz) TEMPERATURE (°C) Figure 24. Voltage Noise Density, VS = 5 V or ±5 V Figure 21. Slew Rate vs. Temperature, VS = 3 V Rev. E | Page 10 of 24 10k OP191/OP291/OP491 70 40 VS = 5V TA = 25°C BASED ON 600 OP AMPS 60 +IB –IB VCM = 5V 20 50 10 40 IB (nA) UNITS VS = 5V 30 30 0 –10 –20 0 –0.50 –0.30 –0.10 0.10 25 INPUT OFFSET VOLTAGE (mV) 1.6 VS = 5V –40°C < TA < +125°C BASED ON 600 OP AMPS 60 40 20 2 3 5 4 6 1.0 VCM = 0V 0.8 0.6 0.4 0.2 0 00294-031 1 1.2 VCM = 5V –0.2 –40 7 25 125 85 TEMPERATURE (°C) INPUT OFFSET VOLTAGE (µV/°C) Figure 26. OP291 Input Offset Voltage Drift Distribution, VS = 5 V Figure 29. Input Offset Current vs. Temperature, VS = 5 V 36 0.15 VS = 5V VS = 5V 30 24 INPUT BIAS CURRENT (nA) 0.10 VCM = 0V 0.05 0 VCM = 5V –0.05 18 12 6 0 –6 –12 –18 25 85 –30 –36 125 0 1 2 3 4 5 COMMON-MODE INPUT VOLTAGE (V) TEMPERATURE (°C) Figure 27. Input Offset Voltage vs. Temperature, VS = 5 V 00294-035 –24 00294-032 –0.10 –40 00294-034 80 0 VS = 5V 1.4 INPUT OFFSET CURRENT (nA) 100 UNITS 125 Figure 28. Input Bias Current vs. Temperature, VS = 5 V 120 VOS (mV) 85 TEMPERATURE (°C) Figure 25. OP291 Input Offset Voltage Distribution, VS = 5 V 0 –IB +IB –40 –40 0.50 0.30 VCM = 0V –30 00294-030 10 00294-033 20 Figure 30. Input Bias Current vs. Common-Mode Input Voltage, VS = 5 V Rev. E | Page 11 of 24 OP191/OP291/OP491 50 5.00 VS = 5V TA = 25°C 40 4.95 30 CLOSED-LOOP GAIN (dB) 4.90 4.85 RL = 2kΩ 4.80 20 10 0 –10 –20 –30 4.75 4.70 –40 –40 00294-036 VS = 5V 85 25 00294-039 OUTPUT VOLTAGE SWING (V) RL = 100kΩ –50 125 10 100 1M 10M Figure 34. Closed-Loop Gain vs. Frequency, VS = 5 V 160 160 VS = 5V TA = 25°C 80 60 40 90 20 45 0 0 –20 –45 –40 –90 10M 1k 10k 100k 1M FREQUENCY (Hz) 120 100 80 60 40 20 0 00294-040 100 CMRR (dB) OPEN PHASE SHIFT (Degrees) 120 100 CMRR VS = 5V TA = 25°C 140 –20 –40 100 00294-037 140 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 35. CMRR vs. Frequency, VS = 5V Figure 32. Open-Loop Gain and Phase vs. Frequency, VS = 5 V 96 140 VS = 5V 95 RL = 100kΩ, VCM = 5V 120 VS = 5V 94 93 CMRR (dB) 100 80 60 RL = 100kΩ, VCM = 0V 92 91 90 89 RL = 2kΩ, VCM = 5V 88 20 0 –40 RL = 2kΩ, VCM = 0V 25 85 00294-041 40 87 00294-038 OPEN-LOOP GAIN (dB) 100k FREQUENCY (Hz) Figure 31. Output Voltage Swing vs. Temperature, VS = 5 V OPEN-LOOP GAIN (V/mV) 10k 1k TEMPERATURE (°C) 86 –40 125 25 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 36. CMRR vs. Temperature, VS = 5 V Figure 33. Open-Loop Gain vs. Temperature, VS = 5 V Rev. E | Page 12 of 24 125 OP191/OP291/OP491 20 160 ±PSRR VS = 5V TA = 25°C 18 SHORT-CIRCUIT CURRENT (mA) 120 PSRR (dB) 100 80 +PSRR 60 40 –PSRR 20 –20 –40 100 1k 10k 100k 1M 16 –ISC, VS = ±5V 14 +ISC, VS = +3V 12 10 –ISC, VS = +3V 8 6 00294-042 0 +ISC, VS = ±5V 00294-045 140 4 –40 10M 25 85 125 TEMPERATURE (°C) FREQUENCY (Hz) Figure 40. Short-Circuit Current vs. Temperature, VS = +3 V, +5 V, ±5 V Figure 37. PSRR vs. Frequency, VS = 5 V 80 0.6 VS = ±5V 70 0.5 60 +SR VOLTAGE (μV) SR (V/µs) 0.4 –SR 0.3 0.2 50 40 30 10kΩ 20 A 0 –40 85 25 10 00294-043 VS = 5V 0 125 10kΩ 0 500 1000 5.0 VS = 5V +SR –SR 0.25 0.20 0.15 00294-044 0.10 0 –40 25 85 4.0 3.5 3.0 2.5 2.0 1.5 1.0 00294-047 MAXIMUM OUTPUT SWING (V) 0.40 0.05 2500 VIN = 4.8V p-p VS = 5V AV = +1 RL = 100kΩ 4.5 0.30 2000 Figure 41. Channel Separation, VS = ±5 V 0.50 SR (V/µs) 1500 FREQUENCY (Hz) Figure 38. OP291 Slew Rate vs. Temperature, VS = 5 V 0.35 VO VIN = 10V p-p @ 1kHz TEMPERATURE (°C) 0.45 1kΩ B 00294-046 0.1 0.5 0 100 125 1k 10k 100k FREQUENCY (Hz) TEMPERATURE (°C) Figure 42. Maximum Output Swing vs. Frequency, VS = 5 V Figure 39. OP491 Slew Rate vs. Temperature, VS = 5 V Rev. E | Page 13 of 24 1M OP191/OP291/OP491 1.6 VIN = 9.8V p-p VS = ±5V AV = +1 RL = 100kΩ 6 4 2 0 100 1k 10k FREQUENCY (Hz) 100k VCM = –5V 1.0 0.8 0.6 0.4 0.2 VCM = +5V 0 –0.2 1M 25 –40 Figure 43. Maximum Output Swing vs. Frequency, VS = ±5 V Figure 46. Input Offset Current vs. Temperature, VS = ±5 V 0.15 36 VS = ±5V 24 INPUT BIAS CURRENT (nA) 0.10 0 VCM = +5V 25 –12 –36 125 85 0 –24 00294-049 –0.05 12 00294-052 VCM= –5V 0.05 –5 –4 TEMPERATURE (°C) 0 1 2 3 4 5 5.00 VS = ±5V 4.90 –IB VCM = +5V 20 10 0 –10 VCM = –5V –IB –30 +IB –40 25 85 4.85 4.80 4.75 0 RL = 2kΩ VS = ±5V –4.75 –4.80 –4.85 RL = 2kΩ –4.90 00294-050 –20 RL = 2kΩ 4.95 +IB 30 –50 –40 –1 Figure 47. Input Bias Current vs. Common-Mode Voltage, VS = ±5 V OUTPUT VOLTAGE SWING (V) 40 –2 COMMON-MODE INPUT VOLTAGE (V) Figure 44. Input Offset Voltage vs. Temperature, VS = ±5 V 50 –3 –4.95 –5.00 –40 125 TEMPERATURE (°C) RL = 2kΩ 25 85 TEMPERATURE (°C) Figure 45. Input Bias Current vs. Temperature, VS = ±5 V Figure 48. Output Voltage Swing vs. Temperature, VS = ±5 V Rev. E | Page 14 of 24 00294-053 –0.10 –40 IB (nA) 125 85 TEMPERATURE (°C) VS = ±5V INPUT OFFSET VOLTAGE (mV) 1.2 00294-051 INPUT OFFSET CURRENT (nA) 8 VS = ±5V 1.4 00294-048 MAXIMUM OUTPUT SWING (V) 10 125 OP191/OP291/OP491 160 70 VS = ±5V TA = 25°C 60 120 30 45 20 90 10 135 100 80 60 40 0 180 –10 225 0 –20 270 –20 1k 10k 100k 1M –40 100 00294-054 –30 20 10M FREQUENCY (Hz) 00294-057 0 CMRR (dB) 40 PHASE SHIFT (Degrees) 1k Figure 49. Open-Loop Gain and Phase vs. Frequency, VS = ±5 V 100k 1M 10M Figure 52. CMRR vs. Frequency, VS = ±5 V 200 102 VS = ±5V VS = ±5V 180 160 101 100 RL = 2kΩ 99 120 98 CMRR (dB) 140 100 80 97 96 95 65 94 40 0 –40 00294-055 RL = 2kΩ 25 85 25 93 92 –40 125 85 25 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 50. Open-Loop Gain vs. Temperature, VS = ±5 V Figure 53. CMRR vs. Temperature, VS =± 5 V 50 160 VS = ±5V TA = 25°C 120 20 100 10 80 PSRR (dB) 30 0 –10 40 20 –30 0 00294-056 –50 10 100 1k 10k 100k 1M +PSRR 60 –20 –40 ±PSRR VS = ±5V TA = 25°C 140 –PSRR 00294-059 40 CLOSED-LOOP GAIN (dB) 10k FREQUENCY (Hz) 00294-058 OPEN-LOOP GAIN (dB) 50 OPEN-LOOP GAIN (V/mV) CMRR VS = ±5V TA = 25°C 140 –20 –40 100 10M FREQUENCY (Hz) 1k 10k 100k 1M FREQUENCY (Hz) Figure 51. Closed-Loop Gain vs. Frequency, VS = ±5 V Figure 54. PSRR vs. Frequency, VS = ±5 V Rev. E | Page 15 of 24 10M OP191/OP291/OP491 115 1k VS = ±5V PSRR (dB) OP291 105 100 00294-060 95 90 –40 25 85 100 10 125 00294-078 VOLTAGE NOISE DENSITY (nV/ Hz) OP491 110 10 100 1k 10k FREQUENCY (Hz) TEMPERATURE (°C) Figure 55. OP291/OP491 PSRR vs. Temperature, VS = ±5 V Figure 58. Voltage Noise Density, VS = 3 V 0.7 VS = ±5V 1.00V 0.6 100 +SR 90 0.5 SR (V/µs) –SR 0.4 0.3 INPUT 0.2 OUTPUT 00294-061 0.1 25 85 0% 500mV 125 2.00µs 100mV 00294-063 0 –40 V S = 3V R L = 200kΩ 10 TEMPERATURE (°C) Figure 56. Slew Rate vs. Temperature, VS = ±5 V 1k VS = 3V Figure 59. Large Signal Transient Response, VS = 3 V 2.00V AV = +100 100 90 AV = +10 10 INPUT AV = +1 1 10k 100k 1M V S = ±5V R L = 200kΩ A V = +1V/V 10 OUTPUT 0% 1.00V 2.00µs 100mV 00294-064 0.1 1k 00294-062 OUTPUT IMPEDANCE (Ω) 100 2M FREQUENCY (Hz) Figure 57. Output Impedance vs. Frequency Figure 60. Large Signal Transient Response, VS = ±5 V Rev. E | Page 16 of 24 OP191/OP291/OP491 THEORY OF OPERATION Notice that the input stage includes 5 kΩ series resistors and differential diodes, a common practice in bipolar amplifiers to protect the input transistors from large differential voltages. These diodes turn on whenever the differential voltage exceeds approximately 0.6 V. In this condition, current flows between the input pins, limited only by the two 5 kΩ resistors. This characteristic is important in circuits where the amplifier may be operated open-loop, such as a comparator. Evaluate each circuit carefully to make sure that the increase in current does not affect the performance. The OP191/OP291/OP491 are single-supply, micropower amplifiers featuring rail-to-rail inputs and outputs. To achieve wide input and output ranges, these amplifiers employ unique input and output stages. In Figure 61 , the input stage comprises two differential pairs, a PNP pair and an NPN pair. These two stages do not work in parallel. Instead, only one stage is on for any given input signal level. The PNP stage (Transistor Q1 and Transistor Q2) is required to ensure that the amplifier remains in the linear region when the input voltage approaches and reaches the negative rail. On the other hand, the NPN stage (Transistor Q5 and Transistor Q6) is needed for input voltages up to and including the positive rail. The output stage in OP191 devices uses a PNP and an NPN transistor, as do most output stages; however, Q32 and Q33, the output transistors, are actually connected with their collectors to the output pin to achieve the rail-to-rail output swing. As the output voltage approaches either the positive or negative rail, these transistors begin to saturate. Thus, the final limit on output voltage is the saturation voltage of these transistors, which is about 50 mV. The output stage does have inherent gain arising from the collectors and any external load impedance. Because of this, the open-loop gain of the amplifier is dependent on the load resistance. For the majority of the input common-mode range, the PNP stage is active, as is shown in Figure 12. Notice that the bias current switches direction at approximately 1.2 V to 1.3 V below the positive rail. At voltages below this, the bias current flows out of the OP291, indicating a PNP input stage. Above this voltage, however, the bias current enters the device, revealing the NPN stage. The actual mechanism within the amplifier for switching between the input stages comprises Transistor Q3, Transistor Q4, and Transistor Q7. As the input common-mode voltage increases, the emitters of Q1 and Q2 follow that voltage plus a diode drop. Eventually, the emitters of Q1 and Q2 are high enough to turn on Q3, which diverts the 8 μA of tail current away from the PNP input stage, turning it off. Instead, the current is mirrored through Q4 and Q7 to activate the NPN input stage. Q22 8µA Q26 –IN Q32 Q23 Q3 5kΩ Q20 Q16 Q5 Q6 Q1 Q2 Q8 Q10 Q12 Q14 Q30 10pF Q17 Q21 Q9 Q11 Q13 Q15 Q24 Q18 Q4 Q7 Q19 VOUT Q31 Q25 Q28 Q29 Q33 00294-065 +IN 5kΩ Q27 Figure 61. Simplified Schematic Rev. E | Page 17 of 24 OP191/OP291/OP491 INPUT OVERVOLTAGE PROTECTION OUTPUT VOLTAGE PHASE REVERSAL As with any semiconductor device, whenever the condition exists for the input to exceed either supply voltage, check the input overvoltage characteristic. When an overvoltage occurs, the amplifier could be damaged depending on the voltage level and the magnitude of the fault current. Figure 62 shows the characteristics for the OP191 family. This graph was generated with the power supplies at ground and a curve tracer connected to the input. When the input voltage exceeds either supply by more than 0.6 V, internal PN junctions energize, allowing current to flow from the input to the supplies. As described, the OP291/OP491 do have 5 kΩ resistors in series with each input to help limit the current. Calculating the slope of the current vs. voltage in the graph confirms the 5 kΩ resistor. Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. Typically, for single-supply bipolar op amps, the negative supply determines the lower limit of their common-mode range. With these devices, external clamping diodes with the anode connected to ground and the cathode to the inputs prevent input signal excursions from exceeding the device’s negative supply (that is, GND), preventing a condition that could cause the output voltage to change phase. JFET input amplifiers can also exhibit phase reversal, and, if so, a series input resistor is usually required to prevent it. IIN +2mA +1mA –10V –5V +5V +10V VIN The OP191 is free from reasonable input voltage range restrictions due to its novel input structure. In fact, the input signal can exceed the supply voltage by a significant amount without causing damage to the device. As shown in Figure 64, the OP191 family can safely handle a 20 V p-p input signal on ±5 V supplies without exhibiting any sign of output voltage phase reversal or other anomalous behavior. Thus, no external clamping diodes are required. OVERDRIVE RECOVERY –2mA Figure 62. Input Overvoltage Characteristics This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. For an input of 10 V over the supply, the current is limited to 1.8 mA. If the voltage is large enough to cause more than 5 mA of current to flow, then an external series resistor should be added. The size of this resistor is calculated by dividing the maximum overvoltage by 5 mA and subtracting the internal 5 kΩ resistor. For example, if the input voltage could reach 100 V, the external resistor should be (100 V/5 mA) − 5 kΩ = 15 kΩ. This resistance should be placed in series with either or both inputs if they are subjected to the overvoltages. The overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to its linear region from a saturated condition. This recovery time is important in applications where the amplifier must recover quickly after a large transient event, such as a comparator. The circuit shown in Figure 63 was used to evaluate the OPx91 overdrive recovery time. The OPx91 takes approximately 8 μs to recover from positive saturation and approximately 6.5 μs to recover from negative saturation. R1 9kΩ VIN 10V STEP 3 + 1/2 OP291 R2 10kΩ 2 – VS = ±5V Figure 63. Overdrive Recovery Time Test Circuit 5µs 8 1/2 OP291 – 4 1 VOUT 10 0% 10 0% –5V 20mV TIME (200µs/DIV) Figure 64. Output Voltage Phase Reversal Behavior Rev. E | Page 18 of 24 20mV TIME (200µs/DIV) 00294-067 2 + VOUT (2V/DIV) 3 VIN (2.5V/DIV) VIN 20V p-p 5µs 100 90 100 90 +5V VOUT 1 R3 10kΩ 00294-068 00294-066 –1mA OP191/OP291/OP491 APPLICATIONS INFORMATION SINGLE-SUPPLY RTD AMPLIFIER SINGLE 3 V SUPPLY, INSTRUMENTATION AMPLIFIER The OP291 low supply current and low voltage operation make it ideal for battery-powered applications, such as the instrumentation amplifier shown in Figure 65. The circuit uses the classic two op amp instrumentation amplifier topology, with four resistors to set the gain. The equation is simply that of a noninverting amplifier, as shown in Figure 65. The two resistors labeled R1 should be closely matched both to each other and to the two resistors labeled R2 to ensure good common-mode rejection performance. Resistor networks ensure the closest matching as well as matched drifts for good temperature stability. Capacitor C1 is included to limit the bandwidth and, therefore, the noise in sensitive applications. The value of this capacitor should be adjusted depending on the desired closedloop bandwidth of the instrumentation amplifier. The RC combination creates a pole at a frequency equal to 1/(2π × R1C1). If AC-CMRR is critical, then a matched capacitor to C1 should be included across the second resistor labeled R1. The circuit in Figure 66 uses three op amps of the OP491 to develop a bridge configuration for an RTD amplifier that operates from a single 5 V supply. The circuit takes advantage of the OP491 wide output swing range to generate a high bridge excitation voltage of 3.9 V. In fact, because of the rail-to-rail output swing, this circuit works with supplies as low as 4.0 V. Amplifier A1 servos the bridge to create a constant excitation current in conjunction with the AD589, a 1.235 V precision reference. The op amp maintains the reference voltage across the parallel combination of the 6.19 kΩ and 2.55 MΩ resistors, which generate a 200 μA current source. This current splits evenly and flows through both halves of the bridge. Thus, 100 μA flows through the RTD to generate an output voltage based on its resistance. A 3-wire RTD is used to balance the line resistance in both 100 Ω legs of the bridge to improve accuracy. GAIN = 274 200Ω 10 TURNS 26.7kΩ 5V 26.7kΩ A3 3V 5 6 3 2 R1 OP291 7 VOUT 100Ω 2.55MΩ OP491 365Ω 1/2 OP291 1 6.19kΩ VOUT = (1 + R2 R1 ) = VIN R2 OP491 R1 C1 100pF 365Ω 100kΩ A1 1/4 R2 VOUT OP491 A2 1/4 4 100kΩ 0.01pF ALL RESISTORS 1% OR BETTER AD589 00294-069 – 1/2 1/4 37.4kΩ 00294-070 + VIN 100Ω RTD 8 5V Figure 65. Single 3 V Supply Instrumentation Amplifier Figure 66. Single-Supply RTD Amplifier Because the OP291 accepts rail-to-rail inputs, the input common-mode range includes both ground and the positive supply of 3 V. Furthermore, the rail-to-rail output range ensures the widest signal range possible and maximizes the dynamic range of the system. Also, with its low supply current of 300 μA/device, this circuit consumes a quiescent current of only 600 μA yet still exhibits a gain bandwidth of 3 MHz. A question may arise about other instrumentation amplifier topologies for single-supply applications. For example, a variation on this topology adds a fifth resistor between the two inverting inputs of the op amps for gain setting. While that topology works well in dual-supply applications, it is inherently inappropriate for single-supply circuits. The same could be said for the traditional three op amp instrumentation amplifier. In both cases, the circuits simply cannot work in single-supply situations unless a false ground between the supplies is created. Amplifier A2 and Amplifier A3 are configured in the two op amp instrumentation amplifier topology described in the Single 3 V Supply, Instrumentation Amplifier section. The resistors are chosen to produce a gain of 274, such that each 1°C increase in temperature results in a 10 mV change in the output voltage, for ease of measurement. A 0.01 μF capacitor is included in parallel with the 100 kΩ resistor on Amplifier A3 to filter out any unwanted noise from this high gain circuit. This particular RC combination creates a pole at 1.6 kHz. Rev. E | Page 19 of 24 OP191/OP291/OP491 In many single-supply applications, the need for a 2.5 V reference often arises. Many commercially available monolithic 2.5 V references require a minimum operating supply voltage of 4 V. The problem is exacerbated when the minimum operating system supply voltage is 3 V. The circuit illustrated in Figure 67 is an example of a 2.5 V reference that operates from a single 3 V supply. The circuit takes advantage of the OP291 rail-to-rail input and output voltage ranges to amplify an AD589 1.235 V output to 2.5 V. The OP291 low TCVOS of 1 μV/°C helps maintain an output voltage temperature coefficient of less than 200 ppm/°C. The circuit overall temperature coefficient is dominated by the temperature coefficient of R2 and R3. Lower temperature coefficient resistors are recommended. The entire circuit draws less than 420 μA from a 3 V supply at 25°C. 3V R1 17.4kΩ 3V 8 1/2 4 2 R3 100kΩ 2.5VREF 1 OP291 R2 100kΩ RESISTORS = 1%, 100ppm/°C POTENTIOMETER = 10 TURN, 100ppm/°C 00294-071 3 AD589 R1 5kΩ Figure 67. A 2.5 V Reference that Operates on a Single 3 V Supply 5 V ONLY, 12-BIT DAC SWINGS RAIL-TO-RAIL The OPx91 family is ideal for use with a CMOS DAC to generate a digitally controlled voltage with a wide output range. Figure 68 shows the DAC8043 used in conjunction with the AD589 to generate a voltage output from 0 V to 1.23 V. The DAC is operated in voltage switching mode, where the reference is connected to the current output, IOUT, and the output voltage is taken from the VREF pin. This topology is inherently noninverting as opposed to the classic current output mode, which is inverting and, therefore, unsuitable for single supply. The OP291 serves two functions. First, it is required to buffer the high output impedance of the DAC VREF pin, which is on the order of 10 kΩ. The op amp provides a low impedance output to drive any following circuitry. Second, the op amp amplifies the output signal to provide a rail-to-rail output swing. In this particular case, the gain is set to 4.1 to generate a 5.0 V output when the DAC is at full scale. If other output voltage ranges are needed, such as 0 V to 4.095 V, the gain can easily be adjusted by altering the value of the resistors. A HIGH-SIDE CURRENT MONITOR In the design of power supply control circuits, a great deal of design effort is focused on ensuring a pass transistor’s longterm reliability over a wide range of load current conditions. As a result, monitoring and limiting device power dissipation is of prime importance in these designs. The circuit illustrated in Figure 69 is an example of a 5 V, single-supply, high-side current monitor that can be incorporated into the design of a voltage regulator with fold-back current limiting or a high current power supply with crowbar protection. This design uses an OP291 rail-to-rail input voltage range to sense the voltage drop across a 0.1 Ω current shunt. A p-channel MOSFET used as the feedback element in the circuit converts the op amp differential input voltage into a current. This current is then applied to R2 to generate a voltage that is a linear representation of the load current. The transfer equation for the current monitor is given by ⎛R ⎞ Monitor Output = R2 × ⎜ SENSE ⎟ × I L ⎝ R1 ⎠ For the element values shown, the monitor output transfer characteristic is 2.5 V/A. RSENSE 0.1Ω IL 5V 5V 5V R1 100Ω 5V 3 8 1/2 OP291 8 R1 17.8kΩ 1.23V 3 2 VDD RFB IOUT DAC8043 VREF 2 S M1 1 GND CLK SR1 LD 7 6 5 3 8 1/2 DIGITAL CONTROL R3 232Ω 1% R2 32.4kΩ 1% OP291 2 1 D VOUT = –––– (5V) 4096 4 R4 100kΩ 1% 00294-072 4 G 3N163 MONITOR OUTPUT 5V AD589 1 4 Figure 68. 5 V Only, 12-Bit DAC Swings Rail-to-Rail Rev. E | Page 20 of 24 D R2 2.49kΩ Figure 69. A High-Side Load Current Monitor 00294-073 A 2.5 V REFERENCE FROM A 3 V SUPPLY OP191/OP291/OP491 A 3 V, COLD JUNCTION COMPENSATED THERMOCOUPLE AMPLIFIER The OP291 low supply operation makes it ideal for 3 V batterypowered applications such as the thermocouple amplifier shown in Figure 70. The K-type thermocouple terminates in an isothermal block where the junction ambient temperature is continuously monitored using a simple 1N914 diode. The diode corrects the thermal EMF generated in the junctions by feeding a small voltage, scaled by the 1.5 MΩ and 475 Ω resistors, to the op amp. The transmit signal, TXA, is inverted by A2 and then reinverted by A3 to provide a differential drive to the transformer, where each amplifier supplies half the drive signal. This is needed because of the smaller swings associated with a single supply as opposed to a dual supply. Amplifier A1 provides some gain for the received signal, and it also removes the transmit signal present at the transformer from the received signal. To do this, the drive signal from A2 is also fed to the noninverting input of A1 to cancel the transmit signal from the transformer. 390pF 37.4kΩ To calibrate this circuit, immerse the thermocouple measuring junction in a 0°C ice bath and adjust the 500 Ω potentiometer to 0 V out. Next, immerse the thermocouple in a 250°C temperature bath or oven and adjust the scale adjust potentiometer for an output voltage of 2.50 V. Within this temperature range, the K-type thermocouple is accurate to within ±3°C without linearization. 20kΩ,1% A1 0.1μF RXA 14 13 1/4 OP491 12 0.0047μF 3.3kΩ A2 10 1.235V 1/4 10kΩ AD589 ISOTHERMAL BLOCK 7.15kΩ 1N914 1% 2 K-TYPE THERMOCOUPLE 40.7μV/°C 475Ω 1% OP291 500Ω 10 TURN 11.2mV ZERO ADJUST TXA 20kΩ,1% T1 750pF 8 1/2 COLD JUNCTIONS 37.4kΩ,1% 0.1μF 0.033μF 20kΩ,1% 4.99kΩ 1% AL CR CHROMEL 9 SCALE ADJUST 1.33MΩ 20kΩ 24.3kΩ 1% 24.9kΩ 1% 475Ω,1% 8 3 4 1/4 0V = 0°C 3V = 300°C 5.1V TO 6.2V ZENER 5 A3 6 OP491 7 5 2.1kΩ 1% Figure 70. A 3 V, Cold Junction Compensated Thermocouple Amplifier 3V OR 5V 4 1 SINGLE-SUPPLY, DIRECT ACCESS ARRANGEMENT FOR MODEMS A4 2 100kΩ 1/4 OP491 11 3 100kΩ 10μF 0.1μF 00294-075 An important building block in modems is the telephone line interface. In the circuit shown in Figure 71, a direct access arrangement is used to transmit and receive data from the telephone line. Amplifier A1 is the receiving amplifier; Amplifier A2 and Amplifier A3 are the transmitters. The fourth amplifier, A4, generates a pseudo ground halfway between the supply voltage and ground. This pseudo ground is needed for the ac-coupled bipolar input signals. 1:1 20kΩ,1% VOUT 1 00294-074 1.5MΩ 1% ALUMEL OP491 3.0V 20kΩ,1% Figure 71. Single-Supply, Direct Access Arrangement for Modems The OP491 bandwidth of 3 MHz and rail-to-rail output swings ensure that it can provide the largest possible drive to the transformer at the frequency of transmission. Rev. E | Page 21 of 24 OP191/OP291/OP491 3 V, 50 HZ/60 HZ ACTIVE NOTCH FILTER WITH FALSE GROUND To process ac signals in a single-supply system, it is often best to use a false ground biasing scheme. Figure 72 illustrates a circuit that uses this approach. In this circuit, a false-ground circuit biases an active notch filter used to reject 50 Hz/60 Hz power line interference in portable patient monitoring equipment. Notch filters are quite commonly used to reject power line frequency interference that often obscures low frequency physiological signals, such as heart rates, blood pressure readings, EEGs, and EKGs. This notch filter effectively squelches 60 Hz pickup at a filter Q of 0.75. Substituting 3.16 kΩ resistors for the 2.67 kΩ resistors in the twin-T section (R1 through R5) configures the active filter to reject 50 Hz interference. R2 2.67kΩ R1 2.67kΩ 3V C1 1μF 11 2 1/4 1 OP491 VIN 3 R3 2.67kΩ A1 4 R4 2.67kΩ R5 1.33kΩ (2.67kΩ ÷ 2) C3 2μF (1μF × 2) R6 100kΩ C2 1μF 5 VOUT 1/4 OP491 6 R8 1kΩ 7 A2 R7 1kΩ R11 100kΩ C5 3V SINGLE-SUPPLY, HALF-WAVE, AND FULL-WAVE RECTIFIERS An OPx91 device configured as a voltage follower operating on a single supply can be used as a simple half-wave rectifier in low frequency (<2 kHz) applications. A full-wave rectifier can be configured with a pair of OP291s, as illustrated in Figure 73. The circuit works in the following way. When the input signal is above 0 V, the output of Amplifier A1 follows the input signal. Because the noninverting input of Amplifier A2 is connected to the output of A1, op amp loop control forces the inverting input of the A2 to the same potential. The result is that both terminals of R1 are equipotential; that is, no current flows. Because there is no current flow in R1, the same condition exists for R2; thus, the output of the circuit tracks the input signal. When the input signal is below 0 V, the output voltage of A1 is forced to 0 V. This condition now forces A2 to operate as an inverting voltage follower because the noninverting terminal of A2 is also at 0 V. The output voltage at VOUTA is then a full-wave rectified version of the input signal. If needed, a buffered, half-wave rectified version of the input signal is available at VOUTB. R1 100kΩ 0.01μF R12 499Ω 9 1/4 OP491 10 A3 8 R2 100kΩ 5V C6 1.5V 1μF R10 1MΩ VIN 2V p-p <2kHz 6 VOUTA 1/2 3 OP291 8 1/2 OP291 00294-076 R9 1MΩ C4 1μF The filter section uses a pair of OP491s in a twin-T configuration whose frequency selectivity is very sensitive to the relative matching of the capacitors and resistors in the twin-T section. Mylar is the material of choice for the capacitors, and the relative matching of the capacitors and resistors determines the pass band symmetry of the filter. Using 1% resistors and 5% capacitors produces satisfactory results. 4 2 1 5 FULL-WAVE RECTIFIED OUTPUT 7 A2 A1 VOUTB HALF-WAVE RECTIFIED OUTPUT Figure 72. A 3 V Single-Supply, 50 Hz/60 Hz Active Notch Filter with False Ground 1V VIN (1V/DIV) 500mV 100 90 VOUTA (0.5V/DIV) 10 VOUTB (0.5V/DIV) 0% 500mV 200μs 00294-077 Amplifier A3 is the heart of the false ground bias circuit. It buffers the voltage developed by R9 and R10 and is the reference for the active notch filter. Because the OP491 exhibits a rail-to-rail input common-mode range, R9 and R10 are chosen to split the 3 V supply symmetrically. An in-the-loop compensation scheme used around the OP491 allows the op amp to drive C6, a 1 μF capacitor, without oscillation. C6 maintains a low impedance ac ground over the operating frequency range of the filter. TIME (200μs/DIV) Figure 73. Single-Supply, Half-Wave, and Full-Wave Rectifiers Using an OP291 Rev. E | Page 22 of 24 OP191/OP291/OP491 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 5 1 4 6.20 (0.2441) 5.80 (0.2284) 1.27 (0.0500) BSC 1.75 (0.0688) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 74. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) [S-Suffix] Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 3.80 (0.1496) 8 14 1 7 6.20 (0.2441) 5.80 (0.2283) 1.27 (0.0500) BSC COPLANARITY 0.10 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) 0.25 (0.0098) 0.10 (0.0039) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 060606-A COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 75. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) [S-Suffix] Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. E | Page 23 of 24 0.75 0.60 0.45 061908-A 1.05 1.00 0.80 OP191/OP291/OP491 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 14 8 1 7 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) SEATING PLANE 0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 070606-A 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) Figure 77. 14-Lead Plastic Dual In-Line Package [PDIP] (N-14) [P-Suffix] Dimensions shown in inches and (millimeters) ORDERING GUIDE Model 1 OP191GS OP191GS-REEL OP191GS-REEL7 OP191GSZ OP191GSZ-REEL OP191GSZ-REEL7 OP291GS OP291GS-REEL OP291GS-REEL7 OP291GSZ OP291GSZ-REEL OP291GSZ-REEL7 OP491GP OP491GPZ OP491GRU-REEL OP491GRUZ-REEL OP491GS OP491GS-REEL OP491GS-REEL7 OP491GSZ OP491GSZ-REEL OP491GSZ-REEL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 14-Lead PDIP 14-Lead PDIP 14-Lead TSSOP 14-Lead TSSOP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N Z = RoHS Compliant Part. ©1994–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00294-0-4/10(E) Rev. E | Page 24 of 24 Package Option R-8 [S-Suffix] R-8 [S-Suffix] R-8 [S-Suffix] R-8 [S-Suffix] R-8 [S-Suffix] R-8 [S-Suffix] R-8 [S-Suffix] R-8 [S-Suffix] R-8 [S-Suffix] R-8 [S-Suffix] R-8 [S-Suffix] R-8 [S-Suffix] N-14 [P-Suffix] N-14 [P-Suffix] RU-14 RU-14 R-14 [S-Suffix] R-14 [S-Suffix] R-14 [S-Suffix] R-14 [S-Suffix] R-14 [S-Suffix] R-14 [S-Suffix]