DATA SHEET MOS INTEGRATED CIRCUIT µPD98404 ADVANCED ATM SONET FRAMER DESCRIPTION The µPD98404 NEASCOT-P30TM is an LSI for ATM applications, which can be used in ATM adapter boards for connecting PCs or workstations to an ATM network and can also be used in ATM hubs and ATM switches. This LSI provides the TC sub-layer functions in the SONET/SDH-base physical layer within the ATM protocol defined by the ATM Forum’s UNI3.1 recommendations. This product’s main functions include transmission functions such as mapping of ATM cells sent from the ATM layer to the payload field in a 155 Mbps SONET STS-3c/SDH STM-1 frame and transmission to PMD (Physical Media Dependent) sub-layer in the physical layer. Its reception functions include separation of the overhead from the ATM cells in data streams received from PMD sub-layer and transmission of the ATM cells to the ATM layer. In addition, this LSI includes a clock recovery function that extracts a reception sync clock from bit streams in received data and a clock synthesis function that generates a clock for transmissions. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD98404 User’s Manual: S11821E FEATURES • • • • • • • • • • • • On-chip clock recovery/clock synthesis functions Provides TC sub-layer function for the ATM protocol’s physical layer Supported frame formats include 155 Mbps SONET STS-3c/SDH STM-1 Conforms to ATM Forum UTOPIA interface Level 2 V1.0 (af-phy-0039.000 June 1995) Supports three UTOPIA interfaces: • Single PHY octet-level handshaking • Single PHY cell-level handshaking • Multi PHY mode Selectable to drop/bypass unassigned cells On-chip internal loopback functions for PMD layer loopback and ATM layer loopback Supports two PMD interfaces: serial and parallel • 155.52 Mbps serial interface • 19.44 MHz parallel interface Provides registers for writing/reading overhead information SOH (section overhead) :J0 byte, Z0 (first and second) bytes, F1 byte LOH (line overhead) :K1 byte, K2 byte POH (path overhead) :F2 byte, C2 byte, H4 byte Provides pseudo error frame transmit function for various errors Supports JTAG boundary scan test function (IEEE 1149.1) CMOS technology +3.3 V single power supply The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S11822EJ4V0DS00 (4th edition) Date Published May 2000 N CP(K) Printed in Japan The mark shows major revised points. © 1997, 1999 µPD98404 • Provides abundant OAM (Operation and Maintenance) functions Receive side Transmit side • Transmission of various alarm data • * Source-triggered automatic loopback transmission LOS (Loss Of Signal) Line RDI, Path RDI OOF (Out Of Frame) Line REI, Path REI LOF (Loss Of Frame) * Command-specified transmission LOP (Loss Of Pointer) Line AIS, Path AIS • Detection of alarm and fault signals OCD (Out of Cell Delineation) Pseudo error generation frame transmit functions LOC (Loss Of Cell delineation) LOS generated frame Line RDI, Path RDI OOF, LOF generated frame Line AIS, Path AIS LOP generated frame • OCD, LCD generated frame Detection and display of quality loss sources B1 error, B2 error, B3 error, B1 error generated frame Line REI, Path-REI B2 error generated frame • B3 error generated frame On-chip error counters B1 byte error counter (16-bit) B2 byte error counter (20-bit) B3 byte error counter (16-bit) Line REI error counter (20-bit) Path REI error counter (16-bit) Rx Frequency justification processing counter (12-bit) HEC error drop cell counter (20-bit) FIFO overflow drop cell counter (20-bit) Idle cell counter (20-bit) ORDERING INFORMATION Part number µPD98404GJ-KEU 2 Package 144-pin plastic QFP (fine pitch) (20 × 20 mm) Data Sheet S11822EJ4V0DS00 µPD98404 SYSTEM CONFIGURATION EXAMPLE The following is an example of a system configuration using the µPD98404. ATM adapter card application Control memory SAR chip µ PD98401A NEASCOT-S15TM Optical fiber transceiver /receiver PHY chip µ PD98404 NEASCOT-P30 19.44 MHz Oscillator Bus bridge Hub (terminal side) application Microprocessor Switch device µ PD98412 NEASCOT-X15TM UTOPIA Level2 Oscillator µ PD98404 NEASCOT-P30 Optical fiber transceiver /receiver µPD98404 NEASCOT-P30 Optical fiber transceiver /receiver Data Sheet S11822EJ4V0DS00 3 Cell scrambler HEC generator Tx FIFO, 7 cells Descrambler Scrambler + Data Sheet S11822EJ4V0DS00 BIP generator (transmit side) Transmission overhead processor (A1, A2, K2, Z2, G1, H1, H2, H3) Reception overhead processor (K2, Z2, G1, H1, H2, H3) BIP generator (receive side) Transmission timing generator OAM controller (performance register, etc.) Management interface signal Rx FIFO, 7 cells UTOPIA interface signal Cell descrambler Controller interface + Cell synchronization HEC verification HEC correction ATM layer interface Clock recovery & clock synthesizer & PMD layer interface PMD interface signal Parallel to serial Pointer processor Transmission overhead registers (J0, Z0, C2, K2,etc.) Reception overhead registers (J0, Z0, C2, K2, etc.) Interrupt source register Mode register BLOCK DIAGRAM 4 Serial to parallel Frame synchronization (A1, A2) µPD98404 µPD98404 PIN CONFIGURATION Test interface RDIT, RDIC RCIT, RCIC TDOT, TDOC Serial TEST0 - TEST2 PMD interface RDO0 - RDO7 RSOC TCOT, TCOC RENBL_B TFKT, TFKC EMPTY_B/RCLAV RADD0-RADD4 AIN1 TDI0 - TDI7 REFCLK 2 8 5 ATM layer interface 8 TCLK PSEL0, PSEL1 TSOC RPD0 - RPD7 TENBL_B RPC 8 8 RCLK TPD0 - TPD7 FULL_B/TCLAV Parallel TADD0 - TADD4 TPC 5 UMPSEL TFC MSEL PMDALM 3 MADD0 - MADD6 PHYALM0 - PHYALM2 MD0 - MD7 RxFP 7 8 CS_B TxFP DS_B/RD_B TFSS Management interface R/W_B/WR_B RCL ACK_B/RDY_B TCL PHINT_B JDI JDO JCK GND, GND-TPE, GND-RPE GND-SP, GND-CS, GND-CR JMS Power supply, GND RESET_B JRST_B VDD, VDD-TPE, VDD-RPE VDD-SP, VDD-CS, VDD-CR JTAG boundary scan interface Remark Active low pins are indicated with the suffix “_B” in this document. Data Sheet S11822EJ4V0DS00 5 µPD98404 PIN CONFIGURATION (TOP VIEW) 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 GND GND RADD4 RADD3 RADD2 RADD1 RADD0 RDO7 RDO6 RDO5 RDO4 RDO3 RDO2 RDO1 RDO0 VDD RCLK RENBL_B RSOC EMPTY_B/RCLAV GND FULL_B/TCLAV TSOC TENBL_B TCLK VDD TDI7 TDI6 TDI5 TDI4 TDI3 TDI2 TDI1 TDI0 GND GND 144-pin plastic QFP (fine pitch) (20 × 20 mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 GND GND-SP VDD-TPE TFKT TFKC GND-TPE TCOT TCOC VDD-TPE GND-TPE TDOT TDOC VDD-TPE GND-RPE RCIT RCIC VDD-RPE RDIT RDIC GND-RPE GND-CR VDD-CR RPC VDD RPD0 RPD1 RPD2 RPD3 RPD4 RPD5 RPD6 RPD7 PSEL0 PSEL1 GND GND 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD JCK JDO JDI JMS JRST_B TEST0 TEST1 TEST2 PHYALM0 PHYALM1 PHYALM2 TFSS TxFP TCL GND TPD0 TPD1 TPD2 TPD3 TPD4 TPD5 TPD6 TPD7 TPC TFC VDD REFCLK GND-CS GND-CS AIN1 VDD-CS VDD-CS GND-CS VDD-SP VDD 6 Data Sheet S11822EJ4V0DS00 VDD TADD4 TADD3 TADD2 TADD1 TADD0 GND RESET_B PHINT_B ACK/RDY_B R/W_B/WR_B DS_B/RD_B CS_B VDD MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 GND UMPSEL MADD6 MADD5 MADD4 MADD3 MADD2 MADD1 MADD0 MSEL PMDALM RCL RxFP VDD µPD98404 PIN ALLOCATION Number Pin name Number Pin name Number Pin name Number Pin name 1 VDD 37 GND 73 VDD 109 GND 2 JCK 38 GND-SP 74 RxFP 110 GND 3 JDO 39 VDD-TPE 75 RCL 111 TDI0 4 JDI 40 TFKT 76 PMDALM 112 TDI1 5 JMS 41 TFKC 77 MSEL 113 TDI2 6 JRST_B 42 GND-TPE 78 MADD0 114 TDI3 7 TEST0 43 TCOT 79 MADD1 115 TDI4 8 TEST1 44 TCOC 80 MADD2 116 TDI5 9 TEST2 45 VDD-TPE 81 MADD3 117 TDI6 10 PHYALM0 46 GND-TPE 82 MADD4 118 TDI7 11 PHYALM1 47 TDOT 83 MADD5 119 VDD 12 PHYALM2 48 TDOC 84 MADD6 120 TCLK 13 TFSS 49 VDD-TPE 85 UMPSEL 121 TENBL_B 14 TxFP 50 GND-RPE 86 GND 122 TSOC 15 TCL 51 RCIT 87 MD0 123 FULL_B/TCLAV 16 GND 52 RCIC 88 MD1 124 GND 17 TPD0 53 VDD-RPE 89 MD2 125 EMPTY_B/RCLAV 18 TPD1 54 RDIT 90 MD3 126 RSOC 19 TPD2 55 RDIC 91 MD4 127 RENBL_B 20 TPD3 56 GND-RPE 92 MD5 128 RCLK 21 TPD4 57 GND-CR 93 MD6 129 VDD 22 TPD5 58 VDD-CR 94 MD7 130 RDO0 23 TPD6 59 RPC 95 VDD 131 RDO1 24 TPD7 60 VDD 96 CS_B 132 RDO2 25 TPC 61 RPD0 97 DS_B/RD_B 133 RDO3 26 TFC 62 RPD1 98 R/W_B/WR_B 134 RDO4 27 VDD 63 RPD2 99 ACK_B/RDY_B 135 RDO5 28 REFCLK 64 RPD3 100 PHINT_B 136 RDO6 29 GND-CS 65 RPD4 101 RESET_B 137 RDO7 30 GND-CS 66 RPD5 102 GND 138 RADD0 31 AIN1 67 RPD6 103 TADD0 139 RADD1 32 VDD-CS 68 RPD7 104 TADD1 140 RADD2 33 VDD-CS 69 PSEL0 105 TADD2 141 RADD3 34 GND-CS 70 PSEL1 106 TADD3 142 RADD4 35 VDD-SP 71 GND 107 TADD4 143 GND 36 VDD 72 GND 108 VDD 144 GND Data Sheet S11822EJ4V0DS00 7 µPD98404 PIN NAMES ACK_B : Read/write Cycle Receive Acknowledge REFCLK : System Clock AIN1 : External Filter Connection RENBL_B : Receive Data Enable CS : Chip Select RESET_B : System Reset DS_B : Data Strobe RPC : Receive Parallel Data Clock EMPTY_B : Output Buffer Empty RPD0-RPD7 : Receive Parallel Data FULL_B : Buffer Full RSOC : Receive Start Address of ATM Cell GND : Ground RxFP : Receive Frame Pulse GND-RPE : Ground for Receive PECL Buffer R/W_B : Read/write Control GND-CR : Ground for Clock Recovery Circuit TADD0-TADD4 : Transmit PHY Device Address GND-CS : Ground for Clock Synthesis TCL : Internal Transmit System Clock GND-SP : Ground for Serial/Parallel Circuit TCLAV : Transmit Cell Available GND-TPE : Ground for Transmit PECL Buffer TCLK : Transmit Data Transferring Clock JCK : JTAG Clock TCOC : Transmit Clock Output Complement JDI : JTAG Data Input TCOT : Transmit Clock Output True JDO : JTAG Data Output TDI0-TDI7 : Transmit Data Input from the ATM Layer JMS : JTAG Mode Select TDOC : Transmit Data Output Complement JRST_B : JTAG Reset TDOT : Transmit Data Output True MADD0-MADD6 : Management Interface Address Bus TENBL_B : Transmit Data Enable MD0-MD7 : Management Interface Data Bus TEST0-TEST2 : Test Mode Pin MSEL : Management Interface Mode Select TFC : Transmit Reference Clock PHINT_B : Physical Interrupt TFKC : Transmit Reference Clock Complement PHYALM0- : PHY Alarm Detection TFKT : Transmit Reference Clock True TFSS : Transmit Frame Set Signal TPC : Transmit Parallel Data Clock PSEL0, PSEL1 : PMD Mode Select TPD0-TPD7 : Transmit Parallel Data RADD0-RADD4 : Receive PHY Device Address TSOC : Transmit Start Address of ATM Cell RCIC : Receive Clock Input Complement TxFP : Transmit Frame Pulse RCIT : Receive Clock Input True UMPSEL : Utopia Multi-PHY Mode Select RCL : Internal Receive System Clock VDD : Supply Voltage for Logic Circuit RCLAV : Receive Cell Available VDD-RPE : Voltage Supply for Receive PECL Buffer RCLK : Receive Data Transferring Clock VDD-CR : Voltage Supply for Clock Recovery Circuit RD_B : Read Select VDD-CS : Voltage Supply for Clock Synthesis RDIC : Receive Data Input Complement VDD-SP : Voltage Supply for Serial/Parallel Circuit RDIT : Receive Data Input True VDD-TPE : Voltage Supply for Transmit PECL Buffer RDO0-RDO7 : Receive Data Output WR_B : Write Select RDY_B : Ready Signal PHYALM2 PMDALM 8 : PMD Device Alarm Data Sheet S11822EJ4V0DS00 µPD98404 1. PIN FUNCTIONS (1/2) 1.1 PMD Interface Pin name RDIT Pin No. 54 I/O level I/O Function P-ECL I Serial receive data input. When PSEL [1:0] is set to 00, the data is True(+) RDIC 55 P-ECL sampled on a clock recovered by the internal clock recovery PLL. I to RCIT/RCIC. Complement(-) RCIT 51 P-ECL I True(+) RCIC 52 P-ECL When PSEL [1:0] is set to 01, the data is sampled on the clock input Serial receive clock input (155.52 MHz). When PSEL [1:0] is set to 01, the input is used as a receive clock. I Complement(-) TDOT 47 P-ECL O True(+) TDOC 48 P-ECL Serial transmit data output. The data is output in sync with the rising edge of the serial clock TCOT. O Complement(-) TCOT 43 P-ECL O True(+) Serial transmit clock output (155.52 MHz). When PSEL [1:0] is set to 00, the clock generated by the internal synthesizer PLL is output as the transmit clock. When PSEL [1:0] is set to 01, the clock supplied to TFKT/TFKC is output. TCOC 44 P-ECL O Complement(-) Depending on the mode selected, the transmit data may be latched by the receive clock for output. Even in such a case, this pin outputs the clock of the internal synthesizer or the clock input to the TFKT/TFKC pin in accordance with the setting of the PSEL[1:0] pins. It does not output the receive recovery clock. TFKT 40 P-ECL I TFKC 41 P-ECL Serial transmit clock input (155.52 MHz). When PSEL [1:0] is set to 01, the input is used as the transmit clock. True(+) I Complement(-) RPD0- 61-68 TTL* I RPD7 Parallel receive data input. When PSEL [1:0] is set to 1X, these pins input receive data. The data is sampled in sync with the rising edge of parallel receive clock RPC. RPC 59 TTL* I Parallel receive clock input (19.44 MHz). When PSEL [1:0] is set to 1X to select parallel mode, this pin inputs a 19.44 MHz receive clock. TPD0- 17-24 TTL* O TPD7 Parallel transmit data output. When PSEL [1:0] is set to 1X to select parallel mode, these pins output transmit data in sync with the rising edge of PC. TPC 25 TTL* O Parallel transmit clock output. When PSEL [1:0] is set to 1X, this pin outputs the clock (19.44 MHz) supplied to TFC. Data Sheet S11822EJ4V0DS00 9 µPD98404 (2/3) Pin name TFC Pin No. I/O level I/O Function 26 TTL* I Parallel transmit clock input. When PSEL [1:0] is set to 1X to select parallel mode, this pin inputs a parallel transmit clock of 19.44 MHz. If the TxCL bits [1:0] of the MDR1 register are set to 10 in the serial mode with PSEL[1:0] = “00”, input the 19.44 MHz source clock of the internal clock synthesizer PLL. REFCLK 28 TTL* I Reference clock input. This pin supplies a system clock of 19.44 MHz to the internal clock recovery/synthesizer. Always input this clock. PSEL0, 69, 70 TTL* I PSEL1 PMD interface mode select input. These pins select the interface mode of the PMD layer to be used. PSEL [1:0] = 00 :Serial mode. The clock generated by the internal clock recovery/synthesizer PLL is used for transmission and reception. PSEL [1:0] = 01 :Serial mode. The clock input of the external RCIT/RCIC and TFKT/TFKC is used for transmission and reception. PSEL [1:0] = 1x:Parallel mode. The clock input of RPC and TFC is used. AIN1 31 Analog O This pin connects the loop filter of the internal synthesizer PLL. Leave open. PMDALM 76 TTL* I PMD layer alarm signal input. The signal level of this pin is reflected in the state bit of an internal register. The transition of the bit can be used as an interrupt source. The state signal from a peripheral device is input. PHYALM0- 10-12 TTL* O PHYALM2 PHY layer alarm detection signal output. These pins output a signal indicating that an internally monitored error state (PMDALM, CMDARM, LOS, OOF, LOF, LOP, OCD, LCD, Line AIS, Path AIS, Line RDI, or Path RDI) has been detected. The pins can output an error either singly or in combination. The type of the error to be indicated is selected by setting the internal AMPR, AMR1, and AMR2 registers. For details on use, refer to 3.5 Alarm Report Pins (PHYALM[2:0], PMDALM) in µPD98404 User’s Manual (S11821E). RxFP 74 TTL* O Frame pulse output for the receive side (8 kHz). This pin outputs a pulse signal at one-clock intervals in sync with the RCL clock in the frame synchronization state. 10 Data Sheet S11822EJ4V0DS00 µPD98404 (3/3) Pin name TxFP Pin No. I/O level I/O Function 14 TTL* O Frame pulse signal output for the transmit side (8 kHz). This pin outputs a pulse signal at one-clock intervals in sync with the TCL clock. TFSS 13 TTL* I Transmit frame output disable signal input. When the signal is high, the transmit frame output stops. When the signal is low, transmission starts from the beginning of a frame. The µPD98404 samples this signal at the rising edge of the TCL clock. The transmit frame output is resumed at the ninth rising edge of the TCL clock after the rising edge at which the high level of this signal was last detected. RCL 75 TTL* O Internal system clock output for the receive side (19.44 MHz). This pin outputs the receive clock divided by 8. The source receive clock depends on the selected mode, which is either the clock generated by the internal clock recovery PLL or the clock supplied from the RCIT/RCIC and RFC pins. Clock output from this pin is stopped while the device is being reset. TCL 15 TTL* O Internal system clock output of the transmit side (19.44 MHz). This pin outputs the transmit clock divided by 8. The source transmit clock depends on the selected mode, which is either the clock generated by the internal synthesizer or the clock supplied from the TCIT/TCIC and TFC pins. Clock output from this pin is stopped while the device is being reset. 1.2 ATM layer interface (1/2) Pin name Pin No. I/O level I/O RDO0- 130-137 TTL* O Function Receive data output. (2 or 3- These pins form an 8-bit data bus that outputs receive data to an ATM RDO7 state) layer device. The data is output in sync with the rising edge of the RCLK clock. These pins operate in two or three states, depending on the UTOPIA interface mode. RCLK 128 TTL* I Receive clock input. This pin supplies a clock of up to 40 MHz for receive data transfer. RSOC 126 TTL* O Receive cell start position signal output. (2 or 3- This pin outputs a signal indicating the position of the first byte of a state) receive cell. This pin operates in two or three states, depending on the UTOPIA interface mode. RENBL_B 127 TTL* I Receive enable signal input. This pin inputs a signal indicating that the ATM layer is ready to receive data. Data Sheet S11822EJ4V0DS00 11 µPD98404 (2/2) Pin name Pin No. I/O level I/O EMPTY_B/ 125 TTL* O RCLAV Function Receive FIFO data transfer disable signal output or (2 or 3- receive FIFO cell data transfer enable signal output. state) This pin functions as either EMPTY_B (2-state operation) or RCLAV (3-state operation), depending on the selected mode of the UTOPIA interface. EMPTY_B indicates that the receive FIFO has no receive data bytes to be transferred to the ATM layer. RCLAV indicates that the receive FIFO has data of at least once cell to be transferred to the ATM layer. This pin operates in two or three states, depending on the UTOPIA interface mode. RADD0- 138-142 TTL* I RADD4 TDI0- PHY address input for the receive side. In multi-PHY mode, these pins input the address of the PHY layer device to be selected. 111-118 TTL* I TDI7 Transmit data input. These pins form an 8-bit data bus that inputs transmit data. The data is input in sync with the rising edge of the TCLK clock. TCLK 120 TTL* I Transmit clock input. This pin inputs a clock of 20 to 40 MHz for transmit data transfer. Caution The µPD98404 also uses this clock as the system clock of the management interface block. Therefore, always input a clock of 20 MHz or higher. TSOC 122 TTL* I Transmit cell start position input. This pin inputs a signal indicating the position of the first byte of the transmit cell input to the µPD98404. TENBL_B 121 TTL* I Transmit enable input. This pin inputs a signal indicating that an ATM layer device is outputting valid transmit data to TDI0 - TDI7. FULL_B/ 123 TTL* TCLAV O Transmit FIFO data transfer disable signal output or transmit FIFO (2 or 3- cell data transfer enable signal output. state) This pin functions as either FULL_B (2-state operation) or TCLAV (3state operation), depending on the selected UTOPIA interface mode. FULL_B indicates that the transmit FIFO has no free area to receive transmit data. TCLAV indicates that the transmit FIFO has a free area of at least one cell for storing transmit data. This pin operates in two or three states, depending on the UTOPIA interface mode. TADD0- 103-107 TTL* I TADD4 UMPSEL 12 PHY address input for the transmit side. When used in multi-PHY mode, these pins input an address for selecting a PHY layer device. 85 TTL* I Multi-PHY mode select signal input. • When the signal is high, multi-PHY mode is selected. • When the signal is low, single PHY mode is selected. Data Sheet S11822EJ4V0DS00 µPD98404 1.3 Management interface Pin name MSEL (1/2) Pin No. I/O level I/O Function 77 TTL* I Mode select signal input. The level of input to this pin determines the management interface mode. MSEL = 1: Pin functions RD_B, WR_B, and RDY_B are selected. MSEL = 0: Pin functions DS_B, R/W_B, and ACK_B are selected. MADD0- 78-84 TTL* I MADD6 Address input. These pins form an address bus to input the address of an internal register of the µPD98404. MD0-MD7 87-94 TTL* I/O 8-bit data bus. (3- These pins form a data bus to read or write data of an internal register state) CS_B 96 TTL* I of the µPD98404. Chip select signal input. When the signal is low, access to an internal register is enabled. DS_B/ 97 TTL* I RD_B Data strobe signal input or read signal input. This pin functions as either DS_B or RD_B, depending on the mode selected by the MSEL pin. MSEL = 0: This pin functions as DS_B to input the data strobe signal. MSEL = 1: This pin functions as RD_B to select read access. R/W_B/ 98 TTL* I Read/write signal input or write signal input. This pin functions as either R/W_B or WR_B, depending on the mode selected by the WR_B MSEL pin. MSEL = 0: This pin functions as R/W_B that inputs the read/write control signal. High: Read cycle Low: Write cycle MSEL = 1: This pin functions as WR_B that selects write access. ACK_B/ 99 TTL* RDY_B O Data acknowledge signal output or ready signal output. (3- functions as either ACK_B or RDY_B, depending on the mode state) This pin selected by the MSEL pin. MSEL = 0 : The pin functions as ACK_B that outputs the data strobe signal. MSEL = 1 : The pin functions as RDY_B that selects read access. PHINT_B 100 TTL* O Interrupt signal output. This pin notifies the host that an internal interrupt source has been detected. The pin is active low. Data Sheet S11822EJ4V0DS00 13 µPD98404 (2/2) Pin name Pin No. I/O level I/O Function RESET_B 101 TTL* I System reset signal input. The signal initializes the µPD98404. The input signal should be kept low for 1 µs or more. Especially, in case of the power on, above-mentioned pulse width must be kept after the supply voltage reaches equal to or more than 90% at least. When the RESET_B signal is input, the following clock must be input according to the PMD interface mode. Serial mode : TCLK/RCLK clock Parallel mode : TCLK/RCLK and TFC/RPC clocks 1.4 JTAG boundary scan Pin name JDI Pin No. I/O level I/O 4 TTL* I Function Boundary scan data input. When not being used, this pin should be grounded. JDO 3 TTL* O Boundary scan data output. (3- When not being used, this pin should be left open. state) JCK 2 TTL* I Boundary scan clock input. When not being used, this pin should be grounded. JMS 5 TTL* I Boundary scan mode select signal input. When not being used, this pin should be grounded. JRST_B 6 TTL* I Boundary scan reset signal input. When not being used, this pin should be grounded. Remark Processing of JTAG boundary scan pins not used (during normal operation) The reason that the JRST_B pin is grounded when it is not used (during normal operation) is to better prevent malfunctioning of the JTAG logic. The JTAG pin may be also processed in either of the following ways: • Reset the JTAG logic without using the JRST_B pin Reset the JTAG logic by using the JMS and JCK pins and keep it in the reset status (the JRST_B pin is pulled up). Fix the JMS pin to 1 (pull up) and input 5 clock cycles or more to the JCK pin. • Reset the JTAG logic by using the JRST_B pin Input a low pulse of the same width as RESET_B of the µPD98404 to the JRST_B pin. If both the JMS and JRST_B pins are pulled up and kept high, the JTAG logic is not released from the reset status. Therefore, the normal operation is not affected. Fix the input level of the JDI and JCK pins by pulling them down or up. 14 Data Sheet S11822EJ4V0DS00 µPD98404 1.5 Internal test pins Pin name TEST0- Pin No. I/O level I/O Function 7-9 TTL* I These pins are used to test the µPD98404. In normal operation, all these pins should be grounded. TEST2 TEST [2:0] =000 : Normal operation TEST [2:0] =Other than 000 : Test mode 1.6 Power and ground Pin name VDD Pin No. I/O 1, 27, 36, 60, 73, 95, - Function Power supply (+3.3 V ±5%) and ground for the general logic block. 108, 119, 129 GND 16, 37, 71, 72, 86, 102, - 109, 110, 124, 143, 144 VDD-TPE 39, 45, 49 - Power supply (+3.3 V ±5%) and ground for output PECL I/O. Any noise in this power supply will affect the jitter characteristics. GND-TPE 42, 46 - VDD-RPE 53 - Power supply (+3.3 V ±5%) and ground for input PECL I/O. noise in this power supply will affect the jitter characteristics. GND-RPE VDD-SP 50, 56 - 35 - A means of eliminating this noise, such as a filter, is needed. Any A means of eliminating this noise, such as a filter, is needed. Power supply (+3.3 V ±5%) and ground for the serial /parallel block. Any noise in this power supply will affect the jitter characteristics. A GND-SP 38 - VDD-CS 32, 33 - means of eliminating this noise, such as a filter, is needed. Power supply (+3.3 V ±5%) and ground for the clock synthesizer PLL block. GND-CS 29, 30, 34 - Any noise in this power supply will affect the jitter characteristics. A means of eliminating this noise, such as a filter, is needed. VDD-CR 58 - Power supply (+3.3 V ±5%) and ground for the clock recovery PLL block. GND-CR 57 - Any noise in this power supply will affect the jitter characteristics. A means of eliminating this noise, such as a filter, is needed. Data Sheet S11822EJ4V0DS00 15 µPD98404 1.7 Recommended connection of unused pins Pin Recommended Connection of Unused Pins Each input pin at level Connect to ground (parallel input pin in serial mode) other than P-ECL RPD0 through RPD7, RPC, TFC (Multi-PHY pins in single PHY mode) TADD0 to TADD4, RADD0 through RADD4 (others) TFSS (essential) Each input pin at P-ECL Pull up True(+) pins (TFKT, RCIT, RDIT) to 3.3 V. Connect level Complement(−) pins (TFKC, RCIC, RDIC) to ground. Output pin Leave open. (Parallel input pins in serial mode) TPD0 to TPD7 TPC (others) TxFP, RxFP, TCL, RCL Output pin at P-ECL level Leave open. TDOT, TDOC, TCOT, TCOC AIN1 Leave Open. Because noise on this pin affects the characteristics of the internal PLL, do not wire a clock line in the vicinity. 16 Data Sheet S11822EJ4V0DS00 µPD98404 2. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings “ ” mark indicates portion which have been revised from old edition. Item Symbol Power supply voltage Condition VDD Input/output voltage Ratings Unit –0.5 to +4.6 V VI1/VO1 Pin other than P-ECL, analog level –0.5 to +6.6 or VDD +3.0 V VI2/VO2 P-ECL, analog level –0.5 to +4.6 or VDD +0.5 V Operating temperature TA –45 to +85 °C Storage temperature Tstg –65 to +150 °C Caution If even one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the values at which the product can be used without physical damage. Be sure not to exceed or fall below these values when using the product. Capacitance Parameter Symbol Condition MIN. TYP. MAX. Unit Input capacitance CI Frequency: = 1 MHz 6 10 pF Output capacitance CO Frequency: = 1 MHz 6 10 pF Input/output capacitance CIO Frequency: = 1 MHz 6 10 pF MIN. TYP. MAX. Unit 3.3 VDD × 1.05 V Recommended Operating Conditions Parameter Symbol Condition Power supply voltage VDD VDD × 0.95 Operating temperature range TA −40 +85 °C Low-level input voltage VIL1 Pin other than P-ECL level pin 0 0.8 V VIL2 P-ECL level pin VDD − 2.82 VDD − 1.50 V VIH1 Pin other than P-ECL level pin 2.2 5.25 V VIH2 P-ECL level pin VDD − 1.49 VDD − 0.40 V 300 1900 mV High-level input voltage Differential input voltage Remark VIDIFF2 P-ECL level pins : RDIT, RDIC, RCIT, RDIC, TDOT, TDOC, TCOT, TCOC, TFKT, TFKC Analog pins : AIN1 Data Sheet S11822EJ4V0DS00 17 µPD98404 DC Characteristics (VDD = 3.3 ±0.15 V, TA = −40 to +85°°C) Parameter Symbol Condition MIN. TYP. MAX. Unit Off-state output current IOZ VI = VDD or GND ±10 µA Input leakage current ILI1 VI = VDD or GND ±10 µA P-ECL level pin ±10 µA IOL = +8mA, VDD = 3.3 V 0.4 V Pin other than P-ECL level pin ILI2 Low-level output voltage VOL1 Pin other than P-ECL level pin RL = 50 Ω, VT = VDD − 2 V VOL2 VDD − 2.175 VDD − 1.975 VDD − 1.755 V P-ECL level pin High-level output voltage IOH = −8 mA, VDD = 3.3 V VOH1 2.4 V Pin other than P-ECL level pin RL = 50 Ω, VT = VDD − 2 V VOH2 VDD − 1.14 VDD − 0.92 VDD − 0.69 V 200 mA P-ECL level pin Power supply current IDD During normal operation AC Characteristics (VDD = 3.3 ±0.15 V, TA = −40 to +85°°C) AC Test Condition The propagation delay time is defined as shown below. 0.7VDD Input pin 0.5VDD 0.3VDD 0.5VDD Output pin tPD AC Testing Load Circuit Device Under Test CL = 50pF 18 Data Sheet S11822EJ4V0DS00 450 µPD98404 Management Interface a) Internal register read Parameter Symbol Address setup time (to DS_B↓ [RD_B↓]) tSADDS 10 CS_B setup time (to DS_B↓ [RD_B↓]) tSCSDS 5 R/W_B[WR_B] setup time (to DS_B↓ [RD_B↓]) tSRWDS 5 ns Address hold time (to DS_B↑ [RD_B↑]) tHADDS 4 ns CS_B hold time (to DS_B↑ [RD_B↑]) tHCSDS 0 ns R/W_B [WR_B] hold time (to DS_B↑ [RD_B↑]) tHRWDS 4 ns DS_B↓ [RD_B↓] → ACK_B [RDY_B] output delay time tVAKDS Load capacity = 50 pF 15 ns DS_B↓ [RD_B↓] → data output delay time tVDADS Load capacity = 50 pF 20 ns DS_B↑ [RD_B↑] → ACK_B [RDY_B] float delay time tIAKDSR Load capacity = 50 pF 5 30 ns DS_B↑ [RD_B↑] → data float delay time tIDADS Load capacity = 50 pF 15 ACK↓ → data output delay time tDDAAK Load capacity = 50 pF Note Condition MIN. TYP. MAX. Unit ns 9 × tCYTK ns 45 ns 10 ns DS_B[RD_B] pulse width tWDS 50 ns DS_B↑[RD_B↑]→DS_B↓[RD_B↓]↓ recovery time tDSINT 4 × tCYTK ns Note tWDS defines the time during which the µPD98404 can recognize DS_B [RD_B] as a low level, and does not define the pulse width of DS_B [RD_B] with which data can be accurately read. The time required for the µPD98404 to make ACK_B [RDY_B] low after DS_B [RD_B] has gone low differs depending on the register to be accessed. Make DS_B [RD_B] high after confirming that ACK_B [RDY_B]. The time required for the µPD98404 to make ACK_B [RDY_B] low after DS_B [RD_B] has gone low is “4 x TCLK clock cycle (tCYTK)” at best. So that any register can be read without using ACK_B [RDY_B], widen the pulse width of DS_B [RD_B] to at least to “4 x TCLK clock cycle”. Remark tCYTK is the cycle of the TCLK clock. Data Sheet S11822EJ4V0DS00 19 µPD98404 (i) When MSEL = “0” (Motorola compatible) MADD0 - MADD6 tSADDS tHADDS CS_B tSCSDS tHCSDS MD0 - MD7 tVDADS Invalid tDDAAK Data tIDADS DS_B tWDS R/W_B tSRWDS tHRWDS ACK_B tVAKDS tIAKDSR (ii) When MSEL = “1” (Intel compatible) MADD0 - MADD6 tSADDS tHADDS CS_B tSCSDS tHCSDS MD0 - MD7 tVDADS Invalid tDDAAK Data tIDADS RD_B tWDS WR_B tSRWDS tHRWDS RDY_B tVAKDS 20 Data Sheet S11822EJ4V0DS00 tIAKDSR µPD98404 b) Internal register write Parameter Symbol Address setup time (to DS_B↓ [WR_B↓]) tSADDS 10 CS_B setup time (to DS_B↓ [WR_B↓]) tSCSDS 5 R/W_B[RD_B] setup time (to DS_B↓ [WR_B↓]) tSRWDS 5 ns Data setup time (to DS_B↑ [WR_B↑]) tSDADS 15 ns Address hold time (to DS_B↑ [WR_B↑]) tHADDS 4 ns CS_B hold time (to DS_B↑ [WR_B↑]) tHCSDS 0 ns R/W_B [WR_B] hold time (to DS_B↑ [WR_B↑]) tHRWDS 4 ns Data hold time (to DS_B↑ [WR_B↑]) tHDADS 4 ns DS_B↓ [WR_B↓] → ACK_B [RDY_B] output delay time tVAKDS Load capacity = 50 pF 15 ns DS_B↑ [WR_B↑] → ACK_B [RDY_B] float delay time tIAKDSW Load capacity = 50 pF 10 ns Note Condition MIN. TYP. MAX. Unit ns 9 × tCYTK ns DS_B [WR_B] pulse width tWDS 50 ns DS_B↑[WR_B↑]→DS_B↓[WR_B↓]↓ recovery time tDSINT 4 × tCYTK ns Note tWDS defines the time during which the µPD98404 can recognize DS_B [WR_B] as a low level, and does not define the pulse width of DS_B [WR_B] with which data can be accurately read. The time required for the µPD98404 to make ACK_B [RDY_B] low after DS_B [WR_B] has gone low differs depending on the register to be accessed. Make DS_B [WR_B] high after confirming that ACK_B [RDY_B] has gone low. The time required for the µPD98404 to make ACK_B [RDY_B] low after DS_B [WR_B] has gone low is “4 x TCLK clock cycle (tCYTK)” at best. So that any register can be write without using ACK_B [RDY_B], widen the pulse width of DS_B [WR_B] to at least to “4 x TCLK clock cycle”. Remark tCYTK is the cycle of the TCLK clock. Data Sheet S11822EJ4V0DS00 21 µPD98404 (i) When MSEL = “0” (Motorola compatible) MADD0 - MADD6 tSADDS tHADDS CS_B tSCSDS tHCSDS Data MD0 - MD7 tSDADS tHDADS DS_B tWDS R/W_B tSRWDS tHRWDS ACK_B tVAKDS tIAKDSW (ii) When MSEL = “1” (Intel compatible) MADD0 - MADD6 tSADDS tHADDS CS_B tSCSDS tHCSDS Data MD0 - MD7 tSDADS tHDADS WR_B tWDS RD_B tSRWDS tHRWDS RDY_B tVAKDS 22 Data Sheet S11822EJ4V0DS00 tIAKDSW µPD98404 c) Internal register read/write (NEASCOT-S15 connection mode, MSEL = “0”) (i) Read timing Parameter Symbol Condition MIN. TYP. MAX. Unit Address setup time (to CS_B↓) tSADCS 10 ns R/W_B setup time (to CS_B↓) tSRWCS 10 ns Address hold time (to CS_B↓) tHADCSR 5×tCYTK+10 ns R/W_B hold time (to CS_B↓) tHRWCSR 15×tCYTK+10 ns DS_B hold time (to CS_B↓) tHDSCS 15×tCYTK+10 ns DS_B↓ → data output delay time tVDADS Load capacity = 50 pF DS_B↑ → data float delay time tIDADS Load capacity = 50 pF CS_B pulse width tWCS 15 × tCYTK ns DS_B pulse width tWDS 4 × tCYTK ns Remark 15 30 + tCYTK ns 45 ns tCYTK is the cycle of the TCLK clock. tSADCS tHADCSR MADD0 - MADD6 tWCS CS_B Data tVDADS MD0 - MD7 tHDSCS tIDADS DS_B tWDS R/W_B tSRWCS tHRWCSR Data Sheet S11822EJ4V0DS00 23 µPD98404 (ii) Write timing Parameter Symbol Condition MIN. TYP. MAX. Unit Address setup time (to CS_B↓) tSADCS 10 ns R/W_B setup time (to CS_B↓) tSRWCS 10 ns Data setup time (to CS_B↓) tSDACS 10 ns Address hold time (to CS_B↑) tHADCSW 10 ns R/W_B hold time (to CS_B↑) tHRWCSW 10 ns tHDACS 10 ns tWCS 4 × tCYTK ns Data hold time (to CS_B↑) CS_B pulse width Remark tCYTK is the cycle of the TCLK clock. tSADDS tHADCSW MADD0-MADD6 tWCS CS_B tSDACS tHDACS Data MD0-MD7 DS_B tHRWCSW tSRWCS R/W_B Caution 24 If the device is reset via software by setting the CMR2 register, do not read or write all the registers for the duration of at least “20 x TCLK clock cycle (tCYTK)” from that write cycle. Otherwise, the registers may not be read or written correctly. Data Sheet S11822EJ4V0DS00 µPD98404 OAM interface Parameter Symbol TCLK↑ → PHYARM2-0 delay time tDARRL Condition MIN. TYP. Load capacity = 50 pF MAX. Unit 25 ns MAX. Unit TCLK tDARRL tDARRL PHYARM2-0 Control signal interface Parameter Symbol Condition MIN. TYP. TFSS setup time (to TCL↑) tSTFTL 20 ns TFSS hold time (to TCL↑) tHTFTL 5 ns TCL↑ → TxFP delay time tDTFTL Load capacity = 50 pF 25 ns RCL↑ → RxFP delay time tDRFRL Load capacity = 50 pF 25 ns TCL tDTFTL TFSS tSTFTL tDTFTL tHTFTL TxFP RCL tDRFRL tDRFRL RxFP Data Sheet S11822EJ4V0DS00 25 µPD98404 UTOPIA interface (transmit side) Parameter Symbol Condition MIN. TYP. MAX. Unit TCLK cycle time tCYTK 25 50 ns TCLK high level width tWTKH 0.4 × tCYTK 0.6 × tCYTK ns TCLK low level width tWTKL 0.4 × tCYTK 0.6 × tCYTK ns TCLK↑ → TCLAV↑↓ delay time tDCATK Load capacity = 50 pF 1 19 ns TCLK↑ → TCLAV output delay time tVCATK Load capacity = 50 pF 1 19 ns TCLK↑ → TCLAV data float delay time tICATK Load capacity = 50 pF 1 25 ns TDI0-7 setup time (to TCLK↑) tSDITK 4 ns TDI0-7 hold time (to TCLK↑) tHDITK 1 ns TSOC setup time (to TCLK↑) tSSOTK 4 ns TSOC hold time (to TCLK↑) tHSOTK 1 ns TADD0-7 setup time (to TCLK↑) tSADTK 4 ns TADD0-7 hold time (to TCLK↑) tHADTK 1 ns TENBL_B setup time (to TCLK↑) tSENTK 4 ns TENBL_B hold time (to TCLK↑) tHENTK 1 ns tCYTK tWTKH tWTKL TCLK tSADTK tHADTK TADD0-7 TCLAV tDCATK tDCATK tICATK tVCATK TENBL_B tSSOTK tHSOTK tSDITK tHDITK TSOC TDI0-7 26 Data Sheet S11822EJ4V0DS00 tSENTK tHENTK µPD98404 UTOPIA interface (receive side) Parameter Symbol Condition MIN. TYP. MAX. Unit RCLK cycle time tCYRK 25 ns RCLK high level width tWRKH 0.4 × tCYRK 0.6 × tCYRK ns RCLK low level width tWRKL 0.4 × tCYRK 0.6 × tCYRK ns RCLK↑ → RCLAV↑↓ delay time tDCARK Load capacity = 50 pF 1 19 ns RCLK↑ → RCLAV output delay time tVCARK Load capacity = 50 pF 1 19 ns RCLK↑ → RCLAV data float delay time tICARK Load capacity = 50 pF 1 25 ns RCLK↑ → RDO0-7↑↓ delay time tDDORK Load capacity = 50 pF 1 19 ns RCLK↑ → RDO0-7 output delay time tVDORK Load capacity = 50 pF 1 19 ns RCLK↑ → RDO0-7 data float delay time tIDORK Load capacity = 50 pF 1 25 ns RCLK↑ → RSOC↑↓ delay time tDSORK Load capacity = 50 pF 1 19 ns RCLK↑ → RSOC output delay time tVSORK Load capacity = 50 pF 1 19 ns RCLK↑ → RSOC data float delay time tISORK Load capacity = 50 pF 1 25 ns RADD0-7 setup time (to RCLK↑) tSADRK 4 ns RADD0-7 hold time (to RCLK↑) tHADRK 1 ns RENBL_B setup time (to RCLK↑) tSENRK 4 ns RENBL_B hold time (to RCLK↑) tHENRK 1 ns tCYTK tWTKH tWTKL TCLK tSADTK tHADTK TADD0-7 TCLAV tDCATK tDCATK tICATK tVCATK TENBL_B tSSOTK tHSOTK tSDITK tHDITK tSENTK tHENTK TSOC TDI0-7 Data Sheet S11822EJ4V0DS00 27 µPD98404 PMD parallel interface (receive side) Parameter Symbol Condition MIN. TYP. MAX. Unit RPC cycle time tCYRP 50 ns RPC high level width tWRPH 0.4 × tCYRP 0.6 × tCYRP ns RPC low level width tWRPL 0.4 × tCYRP 0.6 × tCYRP ns RPD0 - RPD7 setup time (to RPC↑) tSPDRP 10 ns RPD0 - RPD7 hold time (to RPC↑) tHPDRP 5 ns tCYRP tWRPH tWRPL RPC tSPDRP tHPDRP RPD0-7 PMD parallel interface (transmit side) Parameter Symbol Condition MIN. TYP. MAX. Unit TFC cycle time tCYTF 50 ns TFC high level width tWTFH 0.4 × tCYTF 0.6 × tCYTF ns TFC low level width tWTFL 0.4 × tCYTF 0.6 × tCYTF ns TFC↑ → TPC↑ delay time tDPCTFH Load capacity = 50 pF 25 ns TFC↓ → TPC↓ delay time tDPCTFL Load capacity = 50 pF 25 ns TPC↑ → TPD0-TPD7 delay time tDPDTC Load capacity = 50 pF +5 ns tCYTF tWTFH tWTFL TFC tDPCTFH tDPCTFL TPC tDPDTC TPD0-7 28 Data Sheet S11822EJ4V0DS00 –5 µPD98404 PMD serial interface (transmit side) Parameter Symbol Note Condition MIN. TYP. MAX. Unit 51.4403 +20ppm ns REFCLK cycle time tCYRF −20ppm REFCLK high level width tWRFH 0.4 × tCYRF 0.6 × tCYRF ns REFCLK low level width tWRFL 0.4 × tCYRF 0.6 × tCYRF ns TFKT(C) cycle time tCYSF −0.005UI +0.005UI ns Caution 6.43 To get the TCL clock which is a jitter below 0.01UI, the basis signal which has at least equal to or more than 40 ppm precision must be inputted. (i) When using a clock synthesizer tCYRF tWRFH tWRFL REFCLK (ii) When using an external serial clock tCYSF TFKT (TFKC) Data Sheet S11822EJ4V0DS00 29 µPD98404 PMD serial interface (receive side) Parameter Symbol Condition MIN. TYP. MAX. Unit 6.43 +0.005UI ns RCIT(RCIC) cycle time tCYSC −0.005UI RDIT(RCIC) setup time tSDISC 3 ns RDIT(RCIC) hold time tHDISC 1 ns tCYSC RCIT (RCIC) tSDISC tHDISC RDIT (RDIC) 30 Data Sheet S11822EJ4V0DS00 µPD98404 3. PACKAGE DRAWINGS 144 PIN PLASTIC QFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D Q 144 1 R 37 36 F G H I J M P K M N S L NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. S ITEM A MILLIMETERS 22.0±0.3 B 20.0±0.2 C 20.0±0.2 D 22.0±0.3 F 1.25 G 1.25 H 0.22 +0.05 −0.04 I 0.10 J 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.03 −0.07 N 0.10 P 2.7 Q 0.125±0.075 R 3° +7° −3° S 3.0 MAX. S144GJ-50-JEU, KEU-1 Data Sheet S11822EJ4V0DS00 31 µPD98404 4. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and conditions other than those recommended below, contact our sales personnel. Surface Mount Type Soldering Conditions • µPD98404GJ-KEU: 144-pin plastic QFP (fine pitch) (20 × 20 mm) Soldering method Soldering conditions Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: two times or less Note Exposure limit: 3 days (after that, prebake at 125°C for 20 hours) Partial heating Pin temperature: 300°C max., Duration: 3 seconds max. (per device side) Recommended soldering code IR35-203-2 – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. 32 Data Sheet S11822EJ4V0DS00 µPD98404 [MEMO] Data Sheet S11822EJ4V0DS00 33 µPD98404 [MEMO] 34 Data Sheet S11822EJ4V0DS00 µPD98404 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S11822EJ4V0DS00 35 µPD98404 NEASCOT-P30, NEASCOT-S15, and NEASCOT-X15 are trademarks of NEC Corporation. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. 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Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8