2.5 kV Isolated RS-485 Transceivers with Integrated Transformer Driver ADM2482E/ADM2487E FEATURES FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 D1 D2 OSC DE GALVANIC ISOLATION TxD RxD Y Z A B RE GND1 GND2 07379-001 Isolated RS-485/RS-422 transceivers, configurable as half duplex or full duplex Integrated oscillator driver for external transformer ±15 kV ESD protection on RS-485 input/output pins Complies with TIA/EIA-485-A-98 and ISO 8482:1987(E) Data rate: 500 kbps/16 Mbps 5 V or 3.3 V operation (VDD1) 256 nodes on bus True fail-safe receiver inputs Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 VDE certificates of conformity DIN VVDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak Thermal shutdown protection Operating temperature range: −40°C to +85°C Wide-body, 16-lead SOIC package Figure 1. APPLICATIONS Isolated RS-485/RS-422 interfaces Industrial field networks Multipoint data transmission systems GENERAL DESCRIPTION The ADM2482E/ADM2487E are isolated data transceivers with ±15 kV ESD protection and are suitable for high speed, halfduplex or full-duplex communication on multipoint transmission lines. For half-duplex operation, the transmitter outputs and receiver inputs share the same transmission line. Transmitter Output Pin Y is linked externally to Receiver Input Pin A, and Transmitter Output Pin Z to Receiver Input Pin B. The parts are designed for balanced transmission lines and comply with TIA/EIA-485-A-98 and ISO 8482:1987(E). The devices employ the Analog Devices, Inc., iCoupler® technology to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. An on-chip oscillator outputs a pair of square waveforms that drive an external transformer to provide isolated power. The logic side of the device is powered with either a 5 V or a 3.3 V supply, and the bus side is powered with an isolated 3.3 V supply. The ADM2482E/ADM2487E driver has an active high enable, and the receiver has an active low enable. The driver output enters a high impedance state when the driver enable signal is low. The receiver output enters a high impedance state when the receiver enable signal is high. The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention might cause excessive power dissipation. The part is fully specified over the industrial temperature range of −40°C to +85°C and is available in a 16-lead, wide-body SOIC package. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved. ADM2482E/ADM2487E TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits ..................................................................................... 12 Applications ....................................................................................... 1 Switching Characteristics .............................................................. 13 Functional Block Diagram .............................................................. 1 Circuit Description......................................................................... 14 General Description ......................................................................... 1 Electrical Isolation...................................................................... 14 Revision History ............................................................................... 2 Truth Tables................................................................................. 14 Specifications..................................................................................... 3 Thermal Shutdown .................................................................... 15 Timing Specifications .................................................................. 4 True Fail-Safe Receiver Inputs .................................................. 15 Package Characteristics ............................................................... 5 Magnetic Field Immunity.......................................................... 15 Regulatory Information ............................................................... 5 Applications Information .............................................................. 16 Insulation and Safety-Related Specifications ............................ 5 Printed Circuit Board Layout ................................................... 16 VDE 0884-2 Insulation Characteristics ..................................... 6 Transformer Suppliers ............................................................... 16 Absolute Maximum Ratings............................................................ 7 Isolated Power Supply Circuit .................................................. 16 ESD Caution .................................................................................. 7 Typical Applications ................................................................... 17 Pin Configuration and Function Descriptions ............................. 8 Outline Dimensions ....................................................................... 18 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 18 REVISION HISTORY 2/09—Rev. 0 to Rev. A Edits to Features ................................................................................ 1 Added Table 5.................................................................................... 5 Changes to Table 6 ............................................................................ 5 Added Table 7.................................................................................... 6 Changes to Figure 9 ........................................................................ 13 Added Table 13 ............................................................................... 16 Changes to Ordering Guide .......................................................... 18 5/08—Revision 0: Initial Version Rev. A | Page 2 of 20 ADM2482E/ADM2487E SPECIFICATIONS Each voltage is relative to its respective ground; 3.0 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, unless otherwise noted. Table 1. Parameter SUPPLY CURRENT Power Supply Current, Logic Side TxD/RxD Data Rate < 500 kbps ADM2487E TxD/RxD Data Rate = 500 kbps Symbol Min Typ ∆|VOD| for Complementary Output States Common-Mode Output Voltage ∆|VOC| for Complementary Output States Short-Circuit Output Current Output Leakage Current (Y, Z) Test Conditions 3.5 4 mA mA 6.0 mA Unloaded output Half-duplex configuration, RTERMINATION = 120 Ω, see Figure 25 Half-duplex configuration, RTERMINATION = 120 Ω, see Figure 25 17 40 mA mA 50 mA 5.0 5.0 5.0 0.2 3.0 0.2 250 125 V V V V V V mA μA IDD2 ADM2482E TxD/RxD Data Rate = 16 Mbps DRIVER Differential Outputs Differential Output Voltage, Loaded Unit IDD1 ADM2482E TxD/RxD Data Rate = 16 Mbps Power Supply Current, Bus Side TxD/RxD Data Rate < 500 kbps ADM2487E TxD/RxD Data Rate = 500 kbps Max |VOD2| |VOD3| ∆|VOD| VOC ∆|VOC| IOS IO 2.0 1.5 1.5 −100 Logic Inputs Input Threshold Low Input Threshold High Input Current RECEIVER Differential Inputs Differential Input Threshold Voltage Input Voltage Hysteresis Input Current (A, B) Line Input Resistance Logic Outputs Output Voltage Low Output Voltage High Short-Circuit Current Tristate Output Leakage Current μA VIL VIH II 0.25 × VDD1 −10 +0.01 VTH VHYS II −200 −125 15 RIN VOLRxD VOHRxD IOS IOZR 0.7 × VDD1 +10 −30 125 mV mV μA −7 V < VCM < +12 V VOC = 0 V DE = 0 V, VDD = 0 V or 3.6 V, VIN = 12 V DE = 0 V, VDD = 0 V or 3.6 V, VIN = −7 V −7 V < VCM < +12 V 96 kΩ 0.4 100 ±1 Rev. A | Page 3 of 20 DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V DE, RE, TxD DE, RE, TxD DE, RE, TxD μA 0.2 VDD1 − 0.2 RL = 100 Ω (RS-422), see Figure 19 RL = 54 Ω (RS-485), see Figure 19 −7 V ≤ VTEST ≤ +12 V, see Figure 20 RL = 54 Ω or 100 Ω, see Figure 19 RL = 54 Ω or 100 Ω, see Figure 19 RL = 54 Ω or 100 Ω, see Figure 19 V V μA −125 VDD1 − 0.3 Unloaded output VDD2 = 3.6 V, half-duplex configuration, RTERMINATION = 120 Ω, see Figure 25 VDD2 = 3.6 V, half-duplex configuration, RTERMINATION = 120 Ω, see Figure 25 V V mA μA IORxD = 1.5 mA, VA − VB = −0.2 V IORxD = −1.5 mA, VA − VB = 0.2 V VDD1 = 5.0 V, 0 V < VO < VDD1 ADM2482E/ADM2487E Parameter TRANSFORMER DRIVER Oscillator Frequency Symbol Min Typ Max Unit Test Conditions fOSC 400 230 RON VSTART 600 430 1.5 2.5 kHz kHz Ω V kV/μs VDD1 = 5.0 V VDD1 = 3.3 V Switch-On Resistance Start-Up Voltage COMMON-MODE TRANSIENT IMMUNITY 1 500 330 0.5 2.2 1 25 VCM = 1 kV, transient magnitude = 800 V CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common-mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. TIMING SPECIFICATIONS TA = −40°C to +85°C, unless otherwise noted. Table 2. ADM2482E Parameter DRIVER Propagation Delay Output Skew Rise Time/Fall Time Enable Time Disable Time RECEIVER Propagation Delay Output Skew Enable Time Disable Time Symbol Min Typ Max Unit Test Conditions tDPLH, tDPHL tDSKEW tDR, tDF tZL, tZH tLZ, tHZ 100 8 15 120 150 ns ns ns ns ns RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26 RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26 RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26 RL = 110 Ω, CL = 50 pF, see Figure 22 and Figure 28 RL = 110 Ω, CL = 50 pF, see Figure 22 and Figure 28 tPLH, tPHL tSKEW tZL, tZH tLZ, tHZ 110 8 13 13 ns ns ns ns CL = 15 pF, see Figure 23 and Figure 27 CL = 15 pF, see Figure 23 and Figure 27 RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 29 RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 29 Max Unit Test Conditions 700 100 1100 2.5 200 ns ns ns μs ns RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26 RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26 RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26 RL = 110 Ω, CL = 50 pF, see Figure 22 and Figure 28 RL = 110 Ω, CL = 50 pF, see Figure 22 and Figure 28 200 30 13 13 ns ns ns ns CL = 15 pF, see Figure 23 and Figure 27 CL = 15 pF, see Figure 23 and Figure 27 RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 29 RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 29 Table 3. ADM2487E Parameter DRIVER Propagation Delay Output Skew Rise Time/Fall Time Enable Time Disable Time RECEIVER Propagation Delay Output Skew Enable Time Disable Time Symbol Min tDPLH, tDPHL tDSKEW tDR, tDF tZL, tZH tLZ, tHZ 250 tPLH, tPHL tSKEW tZL, tZH tLZ, tHZ 200 Typ Rev. A | Page 4 of 20 ADM2482E/ADM2487E PACKAGE CHARACTERISTICS Table 4. Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 Input IC Junction-to-Case Thermal Resistance Symbol RI-O CI-O CI θJCI Output IC Junction-to-Case Thermal Resistance θJCO 1 2 Min Typ 1012 3 4 33 Max 28 Unit Ω pF pF °C/W °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside Thermocouple located at center of package underside Device considered a 2-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION Table 5. ADM2482E/ADM2487E Approvals Organization UL Approval Type Recognized under the component recognition program of underwriters laboratories, Inc. VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Notes In accordance with UL 1577, each ADM2482E/ADM2487E is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection limit = 5 μA) In accordance with DIN V VDE V 0884-10, each ADM2482E/ADM2487E is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC) INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (External Clearance) Symbol L(I01) Value 2500 5.15 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 5.5 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >175 IIIa mm V Rev. A | Page 5 of 20 Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance along body Insulation distance through insulation DIN IEC 112/VDE 0303-1 Material group (DIN VDE 0110: 1989-01, Table 1) ADM2482E/ADM2487E VDE 0884-2 INSULATION CHARACTERISTICS This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits. An asterisk (*) on packages denotes DIN V VDE V 0884-10 approval. Table 7. Description CLASSIFICATIONS Installation Classification per DIN VDE 0110 for Rated Mains Voltage ≤150 V rms ≤300 V rms ≤400 V rms Climatic Classification Pollution Degree VOLTAGE Maximum Working Insulation Voltage Input-to-Output Test Voltage Method b1 Method a: After Environmental Tests, Subgroup 1 Method a After Input and/or Safety Test, Subgroup 2/3): Highest Allowable Overvoltage 1 SAFETY-LIMITING VALUES 2 Case Temperature Input Current Output Current Insulation Resistance at TS 3 1 2 3 Conditions Symbol Characteristic Unit I to IV I to III I to II 40/85/21 2 (DIN VDE 0110: 1989-01, see Table 1) VIORM VPR 560 V peak 1050 896 V peak V peak 672 V peak VTR 4000 V peak TS IS, INPUT IS, OUTPUT RS 150 265 335 >109 °C mA mA Ω VIORM × 1.875 = VPR, 100% production tested, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge <5 pC VIORM × 1.2 = VPR, tm = 60 sec, partial discharge <5 pC Transient overvoltage, tTR = 10 sec. The safety-limiting value is the maximum value allowed in the event of a failure. See Figure 3 for the thermal derating curve. VIO = 500 V. Rev. A | Page 6 of 20 ADM2482E/ADM2487E ABSOLUTE MAXIMUM RATINGS Each voltage is relative to its respective ground; TA = 25°C, unless otherwise noted. Table 8. Parameter VDD1 VDD2 Digital Input Voltages (DE, RE, TxD) Digital Output Voltages RxD D1, D2 Driver Output/Receiver Input Voltage Range Average Output Current per Pin ESD (Human Body Model) on A, B, Y, and Z pins Operating Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating −0.5 V to +6 V −0.5 V to +6 V −0.5 V to VDD1 + 0.5 V −0.5 V to VDD1 + 0.5 V 13 V −9 V to +14 V −35 mA to +35 mA ±15 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +85°C −55°C to +150°C 300°C 215°C 220°C Rev. A | Page 7 of 20 ADM2482E/ADM2487E D1 1 16 VDD2 D2 2 15 GND2 14 A 13 B 12 Z RE 6 11 Y DE 7 10 NC TxD 8 9 GND2 GND1 3 VDD1 4 RxD 5 ADM2482E/ ADM2487E TOP VIEW (Not to Scale) NC = NO CONNECT 07379-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic D1 D2 GND1 VDD1 5 RxD 6 RE 7 8 9 10 11 12 13 14 15 16 DE TxD GND2 NC Y Z B A GND2 VDD2 Description Transformer Driver Terminal 1. Transformer Driver Terminal 2. Ground, Logic Side. Power Supply, Logic Side (3.3 V or 5 V). Decoupling capacitor to GND1 required; capacitor value should be between 0.01 μF and 0.1 μF. Receiver Output Data. This output is high when (A – B) > +200 mV and low when (A – B) < –200 mV. The output is tristated when the receiver is disabled, that is, when RE is driven high. Receiver Enable Input. This is an active low input. Driving this input low enables the receiver; driving it high disables the receiver. Driver Enable Input. Driving this input high enables the driver; driving it low disables the driver. Transmit Data. Ground, Bus Side. No Connect. This pin must be left floating. Driver Noninverting Output. Driver Inverting Output. Receiver Inverting Input. Receiver Noninverting Input. Ground, Bus Side. Power Supply, Bus Side (Isolated 3.3 V Supply). Decoupling capacitor to GND2 required; capacitor value should be between 0.01 μF and 0.1 μF. Rev. A | Page 8 of 20 ADM2482E/ADM2487E TYPICAL PERFORMANCE CHARACTERISTICS 2.30 60 NO LOAD 54Ω LOAD 120Ω LOAD 50 SUPPLY CURRENT IDD1 (mA) 2.20 2.15 2.10 2.05 60 85 0 –40 60 85 NO LOAD 54Ω LOAD 120Ω LOAD 30 25 20 15 10 5 10 35 TEMPERATURE (°C) 60 85 tDPHL 400 300 200 100 0 –40 07379-030 –15 tDPLH 500 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 4. ADM2487E IDD2 Supply Current vs. Temperature (See Figure 25) (Data Rate = 500 kbps, VDD1 = 5 V, VDD2 = 3.3 V, DE = 1 V, RE = 0 V) 07379-033 DRIVER PROPAGATION DELAY (ns) SUPPLY CURRENT IDD2 (mA) 10 35 TEMPERATURE (°C) 600 35 Figure 7. ADM2487E Driver Propagation Delay vs. Temperature 70 4.0 NO LOAD 54Ω LOAD 120Ω LOAD 65 DRIVER PROPAGATION DELAY (ns) 3.9 SUPPLY CURRENT IDD1 (mA) –15 Figure 6. ADM2482E Supply Current vs. Temperature (See Figure 25) (Data Rate = 16 Mbps, VDD1 = 5 V, VDD2 = 3.3 V, DE = 1, RE = 0 V) 40 3.8 3.7 3.6 3.5 3.4 3.3 3.2 60 tDPLH 55 tDPHL 50 45 40 35 30 25 –15 10 35 TEMPERATURE (°C) 60 85 20 –40 07379-031 3.1 –40 20 07379-032 10 35 TEMPERATURE (°C) 07379-029 –15 Figure 3. ADM2487E IDD1 Supply Current vs. Temperature (Data Rate = 500 kbps, VDD1 = 5 V, VDD2 = 3.3 V, DE = 1 V, RE = 0 V) 0 –40 30 10 2.00 1.95 –40 40 Figure 5. ADM2482E IDD1 Supply Current vs. Temperature (Data Rate = 16 Mbps, VDD1 = 5 V, VDD2 = 3.3 V, DE = 1 V, RE = 0 V) Rev. A | Page 9 of 20 –15 10 35 TEMPERATURE (°C) 60 85 Figure 8. ADM2482E Driver Propagation Delay vs. Temperature 07379-034 SUPPLY CURRENT IDD1 (mA) 2.25 NO LOAD 54Ω LOAD 120Ω LOAD ADM2482E/ADM2487E 0.32 0 0.30 –20 OUTPUT VOLTAGE (V) –30 –40 –50 0.28 0.26 0.24 0.22 –60 0 1 2 3 4 5 OUTPUT VOLTAGE (V) 0.20 –40 07379-016 –70 –20 0 20 40 60 80 TEMPERATURE (°C) 07379-019 OUTPUT CURRENT (mA) –10 Figure 12. Receiver Output Low Voltage vs. Temperature (IDD2 = 4 mA) Figure 9. Output Current vs. Receiver Output High Voltage 60 D1 40 30 1 20 D2 10 0 1 2 3 4 5 OUTPUT VOLTAGE (V) CH1 2.0V Ω CH2 2.0V Ω M400ns 125MS/s 8.0ns/pt Figure 10. Output Current vs. Receiver Output Low Voltage A CH2 1.52V 07379-020 0 07379-017 2 1.52V 07379-021 OUTPUT CURRENT (mA) 50 Figure 13. Switching Waveforms (50 Ω Pull-Up to VDD1 on D1 and D2) 4.75 D1 4.73 4.72 1 4.71 D2 4.70 4.69 4.68 4.67 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 07379-018 OUTPUT VOLTAGE (V) 4.74 CH1 2.0V Ω CH2 2.0V Ω M80ns 625MS/s 1.6ns/pt A CH2 Figure 14. Switching Waveforms (Break-Before-Make, 50 Ω Pull-Up to VDD1 on D1 and D2) Figure 11. Receiver Output High Voltage vs. Temperature (IDD2 = −4 mA) Rev. A | Page 10 of 20 ADM2482E/ADM2487E T TxD 1 TxD Z, B 1 2 Z, B 2 Y, A Y, A RxD 4 RxD CH2 2.00V CH4 2.00V M 200ns T 47.80% A CH2 1.72V CH1 2.0V Ω CH2 2.0V Ω CH3 2.0V Ω CH4 2.0V Ω Figure 15. ADM2487E Driver/Receiver Propagation Delay, Low to High (RDIFF = 54 Ω, CL1 = CL2 = 100 pF) M 40.0ns 1.25GS/s IT 16.0ps/pt A CH2 1.68V 07379-037 CH1 2.00V CH3 2.00V 07379-035 4 Figure 17. ADM2482E Driver/Receiver Propagation Delay, High to Low (RDIFF = 54 Ω, CL1 = CL2 = 100 pF) T 1 TxD TxD Z, B 1 2 Z, B Y, A Y, A 2 RxD 4 RxD CH2 2.00V CH4 2.00V M 200ns T 48.60% A CH2 1.72V CH1 2.0V Ω CH2 2.0V Ω CH3 2.0V Ω CH4 2.0V Ω Figure 16. ADM2487E Driver/Receiver Propagation Delay, High to Low (RDIFF = 54 Ω, CL1 = CL2 = 100 pF) M 40.0ns 1.25GS/s IT 16.0ps/pt A CH2 1.68V 07379-038 CH1 2.00V CH3 2.00V 07379-036 4 Figure 18. ADM2482E Driver/Receiver Propagation Delay, Low to High (RDIFF = 54 Ω, CL1 = CL2 = 100 pF) Rev. A | Page 11 of 20 ADM2482E/ADM2487E TEST CIRCUITS VOD2 RL 2 RL 2 VOC S1 Figure 22. Driver Enable/Disable 375Ω A 60Ω 375Ω V TEST Z Figure 20. Driver Voltage Measurement VOUT RE B CL Figure 23. Receiver Propagation Delay +1.5V TxD VCC S1 Y CL RL –1.5V RE CL RE IN Figure 21. Driver Propagation Delay Figure 24. Receiver Enable/Disable VDD2 VDD1 VDD2 GALVANIC ISOLATION DE TxD Y Z 120Ω A RxD B GND2 Figure 25. Supply Current Measurement Test Circuit Rev. A | Page 12 of 20 07379-005 RE GND1 S2 VOUT 07379-009 CL 07379-006 RDIFF Z 07379-008 VOD3 07379-004 TxD S2 CL 50pF Z DE Figure 19. Driver Voltage Measurement Y RL 110Ω TxD 07379-003 Z VCC VOUT Y 07379-007 Y TxD ADM2482E/ADM2487E SWITCHING CHARACTERISTICS VDD1 VDD1 /2 VDD1 /2 VDD1 0V tDPLH tDPHL DE Z tZL tDSKEW = |tDPLH – tDPHL | 90% POINT VDIFF Y, Z VOL + 0.5V VOL tZH 90% POINT VDIFF = V(Y) – V(Z) tLZ 2.3V tHZ 2.3V VOH 10% POINT tDR 07379-010 10% POINT VOH – 0.5V Y, Z tDF 0V Figure 26. Driver Propagation Delay, Rise/Fall Timing 07379-012 Y –VO 0.5VDD1 0V 1/2VO VO +VO 0.5VDD1 Figure 28. Driver Enable/Disable Timing 0.7VDD1 RE 0.5VDD1 0.5VDD1 0.3VDD1 0V 0V tPLH tPHL tZL tLZ 1.5V RxD tZH VOH VOL + 0.5V OUTPUT LOW VOL tHZ OUTPUT HIGH 1.5V tSKEW = |tPLH – tPHL| 1.5V VOL 07379-011 RxD Figure 27. Receiver Propagation Delay RxD 1.5V VOH VOH – 0.5V 0V Figure 29. Receiver Enable/Disable Timing Rev. A | Page 13 of 20 07379-013 A–B ADM2482E/ADM2487E CIRCUIT DESCRIPTION ELECTRICAL ISOLATION TRUTH TABLES In the ADM2482E/ADM2487E, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 30). Driver input and data enable applied to the TxD and DE pins, respectively, and referenced to logic ground (GND1) are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (GND2). Similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground. The truth tables in this section use the abbreviations found in Table 10. iCoupler Technology The digital signals transmit across the isolation barrier using iCoupler technology. This technique uses chip scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are decoded into the binary value that was originally transmitted. Positive and negative logic transitions at the input cause narrow pulses (~1 ns) to be sent to the decoder, via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, then the input side is assumed to be unpowered or nonfunctional, in which case the output is forced to a default state (see Table 10). VDD1 VDD2 D1 D2 OSC ISOLATION BARRIER DE ENCODE DECODE TxD ENCODE DECODE Table 10. Truth Table Abbreviations Letter H I L X Z NC Table 11. Transmitting Supply Status VDD1 VDD2 On On On On On On On Off Off On Off Off Supply Status VDD1 On On On On On On Off Z A ENCODE DECODE R RE DIGITAL ISOLATION GND1 B TRANSCEIVER GND2 07379-022 RxD DE H H L X L X Inputs TxD H L X X X X Y H L Z Z Z Z Outputs Z L H Z Z Z Z Table 12. Receiving Y D Description High level Indeterminate Low level Irrelevant High impedance (off ) Disconnected Figure 30. ADM2482E/ADM2487E Digital Isolation and Transceiver Sections Rev. A | Page 14 of 20 VDD2 On On On On On Off Off Inputs A−B >−0.03 V <−0.2 V −0.2 V < A − B < −0.03 V Inputs open X X X Outputs RE L or NC L or NC L or NC L or NC H L or NC L or NC RxD H L I H Z H L ADM2482E/ADM2487E MAGNETIC FIELD IMMUNITY The limitation on the magnetic field immunity of the iCoupler is set by the condition in which an induced voltage in the receiving coil of the transformer is large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADM2482E/ADM2487E is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by ⎛ −dβ ⎞ 2 V =⎜ ⎟∑ πrn ; n = 1, 2, K , N ⎝ dt ⎠ where: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). 1 0.1 0.01 0.001 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 07379-023 The receiver inputs have a true fail-safe feature that ensures that the receiver output is high when the inputs are open or shorted. During line idle conditions, when no driver on the bus is enabled, the voltage across a terminating resistance at the receiver input decays to 0 V. With traditional transceivers, receiver input thresholds specified between −200 mV and +200 mV mean that external bias resistors are required on the A and B pins to ensure that the receiver outputs are in a known state. The true fail-safe receiver input feature eliminates the need for bias resistors by specifying the receiver input threshold between −30 mV and −200 mV. The guaranteed negative threshold means that when the voltage between A and B decays to 0 V, the receiver output is guaranteed to be high. 10 Figure 31. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. Figure 32 shows the magnetic flux density values in terms of more familiar quantities, such as maximum allowable current flow at given distances away from the ADM2482E/ADM2487E transformers. 1000 DISTANCE = 1m 100 DISTANCE = 5mm 10 DISTANCE = 100mm 1 0.1 0.01 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 07379-024 TRUE FAIL-SAFE RECEIVER INPUTS 100 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGAUSS) The ADM2482E/ADM2487E contain thermal shutdown circuitry that protects the parts from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150°C is reached. As the device cools, the drivers are re-enabled at a temperature of 140°C. Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field can be determined using Figure 31. MAXIMUM ALLOWABLE CURRENT (kA) THERMAL SHUTDOWN Figure 32. Maximum Allowable Current for Various Current-to-ADM2482E/ADM2487E Spacings With combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. Rev. A | Page 15 of 20 ADM2482E/ADM2487E APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD LAYOUT ISOLATED POWER SUPPLY CIRCUIT The isolated RS-485 transceiver of the ADM2482E/ADM2487E requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 33). The ADM2482E/ADM2487E integrate a transformer driver that, when used with an external transformer and linear voltage regulator (LDO), generates an isolated 3.3 V power supply to be supplied between VDD2 and GND2, as shown in Figure 34. Bypass capacitors are most conveniently connected between Pin 3 and Pin 4 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value must be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm. Pin D1 and Pin D2 of the ADM2482E/ADM2487E drive a center-tapped Transformer T1. A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP3330 LDO provides a regulated 3.3 V power supply to the ADM2482E/ADM2487E bus side circuitry (VDD2). Bypassing Pin 9 and Pin 16 is also recommended unless the ground pair on each package side is connected close to the package. GND1 VDD1 RxD RE DE VDD2 ADM2482E OR ADM2487E TOP VIEW (Not to Scale) TxD GND2 A B Z If the ADM2482E/ADM2487E are powered by 5 V on the logic side, then a step-down transformer should be used. For optimum efficiency, the transformer turns ratio should be chosen to ensure just enough headroom for the ADP3330 LDO to output a regulated 3.3 V output under all operating conditions. Y NC GND2 NC = NO CONNECT 07379-025 D2 Figure 33. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, care must be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout must be designed such that any coupling that does occur equally affects all pins on a given component side. ISOLATION BARRIER VCC 10µF MLC Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. The transformer primarily used with the ADM2482E/ADM2487E must be a center-tapped transformer winding. The turns ratio of the transformer must be set to provide the minimum required output voltage at the maximum anticipated load with the minimum input voltage. Table 13 shows ADM2482E/ADM2487E transformer suppliers. Table 13. Transformer Supplies Manufacturer Coilcraft Murata Primary Voltage 3.3 V DA2303-AL 782482/33VC 22µF Primary Voltage 5 V GA3157 782482/53VC Rev. A | Page 16 of 20 VDD1 D1 T1 OUT 3.3V 10µF D2 NR GND 1N5817 VDD2 ISOLATED 3.3V 100nF ADM2482E/ ADM2487E GND1 IN SD ERR VCC 100nF TRANSFORMER SUPPLIERS ADP3330 1N5817 GND2 Figure 34. Applications Diagram 07379-026 D1 When the ADM2482E/ADM2487E are powered by 3.3 V on the logic side, a step-up transformer is required to compensate for the forward voltage drop of the Schottky diodes and the voltage drop across the regulator. The transformer turns ratio should be chosen to ensure just enough headroom for the ADP3330 LDO to output a regulated 3.3 V output under all operating conditions. ADM2482E/ADM2487E line must be terminated at the receiving end in its characteristic impedance, and stub lengths off the main line must be kept as short as possible. For a half-duplex operation, this means that both ends of the line must be terminated, because either end can be the receiving end. TYPICAL APPLICATIONS Figure 35 and Figure 36 show typical applications of the ADM2482E/ADM2487E in half-duplex and full-duplex RS-485 network configurations. Up to 256 transceivers can be connected to the RS-485 bus. To minimize reflections, the MAXIMUM NUMBER OF TRANSCEIVERS ON BUS = 256 ADM2482E/ ADM2487E RxD R A A B B RE TxD Z D RxD R RE RT RT DE ADM2482E/ ADM2487E DE Z Y D Y A B ADM2482E/ ADM2487E R Z Y A D RxD RE B ADM2482E/ ADM2487E DE TxD Z R TxD Y D RxD RE DE TxD 07379-027 NOTES 1. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE. 2. ISOLATION NOT SHOWN. Figure 35. ADM2482E/ADM2487E Typical Half-Duplex RS-485 Network MAXIMUM NUMBER OF NODES = 256 MASTER SLAVE A R RxD B Y D RT RE DE Z D B RT Y A ADM2482E/ ADM2487E RE R RxD ADM2482E/ ADM2487E A B Z Y A B Z Y SLAVE SLAVE R ADM2482E/ ADM2487E RxD RE R D DE TxD RxD RE D ADM2482E/ ADM2487E DE TxD NOTES 1. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE. Figure 36. ADM2482E/ADM2487E Typical Full-Duplex RS-485 Network Rev. A | Page 17 of 20 07379-028 DE TxD TxD Z ADM2482E/ADM2487E OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 45° 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 1.27 (0.0500) 0.40 (0.0157) 032707-B 1 Figure 37. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADM2482EBRWZ 1 ADM2482EBRWZ-REEL71 ADM2487EBRWZ1 ADM2487EBRWZ-REEL71 EVAL-ADM2482EEB3Z EVAL2482EEB5Z EVAL-ADM2487EEB3Z EVAL2487EEB5Z 1 Data Rate (Mbps) 16 16 0.5 0.5 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Z = RoHS Compliant Part. Rev. A | Page 18 of 20 Package Description 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W Evaluation Board, 3.3 V Supply Evaluation Board, 5 V Supply Evaluation Board, 3.3 V Supply Evaluation Board, 5 V Supply Package Option RW-16 RW-16 RW-16 RW-16 ADM2482E/ADM2487E NOTES Rev. A | Page 19 of 20 ADM2482E/ADM2487E NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07379-0-2/09(A) Rev. A | Page 20 of 20