Errata SLAZ550H – September 2013 – Revised July 2015 MSP430FR4133 Device Erratasheet 1 Revision History Errata Number Rev B ✓ The check mark indicates that the issue is present in the specified revision. ADC39 ✓ ADC50 ✓ CPU40 ✓ EEM23 ✓ EEM28 ✓ GC1 ✓ PORT28 ✓ SYS23 ✓ USCI41 ✓ SLAZ550H – September 2013 – Revised July 2015 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated MSP430FR4133 Device Erratasheet 1 Package Markings 2 www.ti.com Package Markings PM64 LQFP (PM), 64 Pin DGG56 (DGG), 56 Pin DGG48 (DGG), 48 Pin 2 MSP430FR4133 Device Erratasheet SLAZ550H – September 2013 – Revised July 2015 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Detailed Bug Description www.ti.com 3 Detailed Bug Description ADC39 ADC10 Module Function Erroneous ADC results in extended sample mode Description If the extended sample mode is selected (ADCSHP = 0) and the ADCCLK is asynchronous to the SHI signal, the ADC may generate erroneous results. Workaround 1) Use the pulse sample mode (ADCSHP=1) OR 2) Use a synchronous clock for ADC and the SHI signal. For example, if SMCLK is used to source Timer to trigger SHI, ADCCLK should also be sourced by SMCLK. ADC50 ADC10 Module Function Erroneous ADC conversion result for internal temperature sensor in LPM3 mode Description When ACLK is used as ADC clock source and device is in LPM3 mode while sampling the on-chip temperature sensor, the ADC may generate erroneous conversion results. Workaround 1) Use SMCLK or MODCLK as the ADC clock source. A 100us sampling time is required if triggering ADC conversion from LPM3. OR 2) Use LPM0 or Active Mode. CPU40 CPUXv2 Module Function PC is corrupted when executing jump/conditional jump instruction that is followed by instruction with PC as destination register or a data section Description If the value at the memory location immediately following a jump/conditional jump instruction is 0X40h or 0X50h (where X = don't care), which could either be an instruction opcode (for instructions like RRCM, RRAM, RLAM, RRUM) with PC as destination register or a data section (const data in flash memory or data variable in RAM), then the PC value is auto-incremented by 2 after the jump instruction is executed; therefore, branching to a wrong address location in code and leading to wrong program execution. For example, a conditional jump instruction followed by data section (0140h). @0x8012 Loop DEC.W R6 @0x8014 DEC.W R7 @0x8016 JNZ Loop @0x8018 Value1 DW 0140h Workaround In assembly, insert a NOP between the jump/conditional jump instruction and program code with instruction that contains PC as destination register or the data section. In C, no workaround is necessary since the compiler automatically generates the necessary NOPs. EEM23 EEM Module SLAZ550H – September 2013 – Revised July 2015 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated MSP430FR4133 Device Erratasheet 3 Detailed Bug Description www.ti.com Function EEM triggers incorrectly when modules using wait states are enabled Description When modules using wait states (USB, MPY, CRC and FRAM controller in manual mode) are enabled, the EEM may trigger incorrectly. This can lead to an incorrect profile counter value or cause issues with the EEMs data watch point, state storage, and breakpoint functionality. Workaround None. NOTE: This erratum affects debug mode only. EEM28 EEM Module Function Clock outputs observed on port module during LPMx in debug mode Description When the device is in LPMx mode, if a debug halt is requested and if the port pin is configured as MCLK, SMCLK, or ACLK output, these clocks are observed on the port pin. Depending on the LPM mode (see Device User's Guide), peripherals that are clocked from MCLK, SMCLK, or ACLK are still halted during debug halt state. For example, if the device is in debug halt in LPM3 mode and a port pin is configured as SMCLK output, SMCLK can be observed on the pin. But the peripherals sourced from SMCLK are still halted as expected. Workaround None GC1 GC Module Function Uncorrectable memory bit error flag (GCCTL1.UBDIFG) does not trigger NMI Description GCCTL1.UBDIFG flag is an interrupt flag that gets set if an uncorrectable bit error has been detected in non-volatile memory. The GCCTL1.UBDIFG flag does not trigger a NMI request even if GCCTL0.UBDRSTEN = 0. In this case, the application is not notified via a NMI request if an uncorrectable bit error occurred in non-volatile memory. Workaround Set GCCTL0.UBDRSTEN = 1 to trigger a PUC. Check GCCTL1.UBDIFG flag after a PUC has been initiated. PORT28 PORT Module Function Pull-down resistor of TEST/SBWTCK pin Description The device's internal pull-down resistor on the TEST/SBWTCK pin gets disabled if the SYS control bit SFRRPCR.SYSRSTRE is cleared. This can lead to increased current consumption and unintentionally-enabled JTAG access to the device. Workaround 1) Do not clear the SFRRPCR.SYSRSTRE bit, use the SFRRPCR.SYSRSTRUP bit to define direction of the internal resistor on RST/NMI/SBWTDIO pin instead. OR 2) Ensure a zero voltage level of TEST/SBWTCK pin by connecting the pin to an external component (e.g. external pull-down resistor) on the PCB. SYS23 SYS Module Function RAM not preserved after BOR Description RAM content at addresses 0x20FE and 0x20FF is not preserved on BOR following one 4 MSP430FR4133 Device Erratasheet SLAZ550H – September 2013 – Revised July 2015 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Detailed Bug Description www.ti.com of the following conditions: - RST/NMI pin reset (RST/NMI BOR) - Software BOR (PMMSWBOR) - Access security area (Security violation BOR) - SVSH low condition event Workaround None. USCI41 eUSCI Module Function UCBUSY bit of eUSCIA module stuck to 1 when device is in SPI mode. Description When eUSCIA is configured in SPI mode, and the last transfer bit changes from 0 to 1, the UCBUSY bit gets stuck to 1. This happens in all four combinations of Clock Phase and Clock Polarity options (UCAxCTLW0.UCCKPH & UCAxCTLW0.UCCKPL bits). There is no data loss or corruption. Workaround Check on transmit or receive interrupt flag UCTXIFG/UCRXIFG instead of UCBUSY to know if the UCAxTXBUF buffer is empty or ready for the next complete character. SLAZ550H – September 2013 – Revised July 2015 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated MSP430FR4133 Device Erratasheet 5 Document Revision History 4 www.ti.com Document Revision History Changes from device specific erratasheet to document Revision A. 1. CPU40 Workaround was updated. 2. ADC39 Workaround was updated. 3. Package Markings section was updated. 4. EEM23 Workaround was updated. 5. Silicon Revision B was added to the errata documentation. 6. Errata PMM23 was added to the errata documentation. 7. EEM23 Description was updated. 8. PORT23 Description was updated. 9. EEM23 Function was updated. 10. Errata USCI38 was added to the errata documentation. Changes from document Revision A to Revision B. 1. Errata USCI38 was added to the errata documentation. Changes from document Revision B to Revision C. 1. Errata SYS23 was added to the errata documentation. Changes from document Revision C to Revision D. 1. Package Markings section was updated. 2. Errata ADC50 was added to the errata documentation. 3. Errata GC1 was added to the errata documentation. Changes from document Revision D to Revision E. 1. Errata LCDE1 was removed from the errata documentation. 2. Errata PORT23 was removed from the errata documentation. 3. Errata USCI38 was removed from the errata documentation. 4. Device name changed from "XMS" to "MSP430" 5. Errata CPU43 was removed from the errata documentation. 6. Errata PMM23 was removed from the errata documentation. Changes from document Revision E to Revision F. 1. EEM23 Description was updated. Changes from document Revision F to Revision G. 1. Errata PORT28 was added to the errata documentation. Changes from document Revision G to Revision H. 1. Errata USCI41 was added to the errata documentation. 6 MSP430FR4133 Device Erratasheet SLAZ550H – September 2013 – Revised July 2015 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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