Mayrim Verdejo TI Designs – Precision: Verified Design -48V Telecom Current/Voltage/Power Sense with Isolation TI Designs – Precision Circuit Description TI Designs – Precision are analog solutions created by TI’s analog experts. Verified Designs offer the theory, component selection, simulation, complete PCB schematic & layout, bill of materials, and measured performance of useful circuits. Circuit modifications that help to meet alternate design goals are also discussed. This verified design can accurately measure current, voltage and power on a bus that carries -48V and is 2 able to provide this data using an I C compatible interface. This design is targeted for Telecom applications because the most common Telecom equipment’s are fed with this negative supply voltage. It uses INA226 and ISO1541. The INA226 is a current 2 shunt and power monitor with an I C compatible interface. This device will precisely take these measurements and will use ISO1541 to translate the negative voltage to ground referenced signals. The 2 ISO1541 is a low-power, bidirectional I C compatible isolator. Design Resources Design Archive TINA-TI™ INA226 ISO1541 INA226EVM R1 35.7k VBUS 24 V Tranzorb RSHUNT R2 12.1k VIN+ VIN- Vs VS (INA) ISO1541 VBUS ISOLATION To Load Ask The Analog Experts WEBENCH® Design Center TI Designs – Precision Library All Design files SPICE Simulator Product Folder Product Folder Tools and Software Folder VIN+ INA226 SDA SCL VIN- A0 GND (GND_INA) VS GND (USBDIG) SDA USBDIG SCL GND A1 VIN- = GND_INA USBDIG not in board. -48V Zener +4.7V RZ GND (GND_INA) An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. TINA-TI is a trademark of Texas Instruments WEBENCH is a registered trademark of Texas Instruments TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2014, Texas Instruments Incorporated 1 www.ti.com 1 Design Summary The design requirements are as follows: • Bus Voltage: -48V • Ability to measure shunt voltages up to ±80mV • Ability to report current, bus voltage, shunt voltage and power • Compatible with I C interface 2 The design goals and performance are summarized in Table 1. Figure 1 depicts the measurement accuracy of the design. Table 1. Comparison of Design Goals and Measured Performance Goal Measured Relative Error (Iload= 50mA) 0.510% 0.403% Relative Error (Iload= -50mA) 0.510% 0.404% Relative Error (Iload= 750mA) 0.114% 0.013% Relative Error (Iload= -750mA) 0.114% 0.103% Measured Relative Error @ Rshunt= 100mΩ; Iload = 50mA to 750mA 0.450 0.400 Relative Error (%) 0.350 0.300 0.250 0.200 0.150 0.100 0.050 0.000 0 100 200 300 400 500 Load Current (mA) 600 700 800 900 Figure 1 Measured Relative Error with Rshunt=100mΩ and ILOAD = 50mA to 750mA TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 2 www.ti.com 2 Theory of Operation The challenges faced by Telecom DC/DC power supply developers today include achieving high efficiency, high integration, low system cost, ease of development and product differentiation. Customers are demanding additional features such as more sophisticated fault diagnosis, power measurement, and more extensive status 2 reporting over I C or CAN interface. Texas Instruments has digital current shunt monitors capable of reporting current, voltage and power when a positive power supply is applied to the input but most common telecom equipment’s are fed with a negative supply range of -48V. For this reason, we have created this TI Design. This design intends to provide a solution with TI products to Telecom companies looking to monitor current and power in their applications. The basic idea of the design is shown in Figure 2. This design has three stages. The first stage uses Texas Instruments INA226 current shunt monitor to measure the load current while the device is floating at the -48V rail. 2 The second part of this design incorporates a low power bidirectional isolator (ISO1541) with I C communication capabilities. This isolator translates these -48V reference signals to ground reference signals. The third stage uses TI SM-USB-DIG Platform and INA226EVM Software to display the data collected by the INA226 device. R1 35.7k To Load R2 12.1k VS (µC) Tranzorb INA226 SDA X VIN+ V Power Register Current Register ADC VIN- SCL I2C Interface GND Voltage Register I GND (GND_INA) ISO1541 ISOLATION VBUS 24V RSHUNT VS (INA) Alert Register VS SDA SCL µC GND A0 A1 Processor not in board VIN- = GND_INA -48V RZ Zener +4.7V GND (GND_INA) Figure 2 TI Design Basic Block Diagram 2.1 First Stage: INA226 Connections and External Components The first stage of the circuit uses the INA226 to monitor the shunt voltage and the bus supply voltage. The INA226 is limited to a bus input voltage range of 0V to 36V. This design is intended to be used at -48V; outside the INA226 input voltage capabilities. The following changes are needed to enable INA226 to monitor the shunt and the -48V bus supply voltage: a. Connect a 4.7V Zener diode between the GND and the Vs pins of the INA226. The INA226 will be powered by the potential generated by the voltage drop across the Zener diode and referenced to the negative rail (-48V). This will also provide the positive supply voltage (Vs) that the INA226 device needs for its operation. b. Incorporate a voltage divider on the Vbus pin input. This will help to limit the input voltage of Vbus to 36V maximum, even thou -48V are been applied to the input. TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 3 www.ti.com 2.1.1 INA226 Referenced to the negative rail The INA226 is typically powered by a separate supply that can range from 2.7V to 5.5V. In this design we are connecting a 4.7V Zener between the GND (GND_INA) and Vs pins of the INA226. Also, the INA226 ground pin (GND) is tied to the Vin- pin of the INA226, see Figure 3. This configuration will power the device by the potential generated by the voltage drop across the Zener diode and it will reference the device to the -48V rail. Note: In this design we refer the INA226 GND pin as GND_INA. To Load RSHUNT VIN+ INA226 VINGND (GND_INA) VS VIN- = GND_INA -48V Zener +4.7V Rz Figure 3 Connections for negative voltage reference A power resistor (Rz) is needed in series with the zener diode. Equation 1 was used to calculate the resistor value and Figure 4 shows a TINA-TI DC simulation with the circuit configuration, calculated values and results. For this calculation we need to consider the Zener bias current and the INA226 quiescent current. From INA226 datasheet specifications, we find the maximum quiescent current to be 420µA with Vs = 3.3V. As we are powering the device with +4.7V, we estimate the INA226 quiescent current to be around 600µA maximum. Rz = | Vin − − V zener | I zener + I INA226 = | −48V − (−4.7V ) | = 7.73kΩ 5mA + 600 µA (1) Equation 2 shows the power consumption calculation, needed to determine the power rating of the Rz resistor. 2 V 2 | Vin − − Vzener | | −48V − (−4.7V ) | Power = = 0.2425W = = R Rz 7.73kΩ 2 TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated (2) 4 www.ti.com Vzener -4.69V + V Zener -43.31V + -48V + V1 -48 Rz 7.73k V V Current 5.6mA Figure 4 Power Resistor Selection Simulation This device has more devices connected to the Vs pin, such as the ISO1541 isolator and some LED’s that have been included on this design. These other devices will increase the current flowing through this resistor. For this reason the Rz resistor value needs to be modified. Figure 5 shows all devices connected to the Vs pin. -43.3V R10 10k R7 910 R9 10k SDA GND_INA ISO1541 SCL D1 LED_Power To Alert Pin ~5mA SDA INA226 R6 910 GND_INA = -48V ~5mA Zener + 4.7V - SCL GND_INA ~0.5mA ~0.5mA GND_INA = -48V GND_INA = -48V ~600µA ~4.7mA GND_INA = -48V Figure 5 Devices connected to INA226 Vs pin TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 5 www.ti.com Table 2 Expected current to be flowing through Rz Device Current D2 (LED Diode for the Alert Pin) 5.0mA D1 (LED Diode for Power, Vs Pin) 5.0mA INA226 0.6mA ISO1541 4.7mA SDA Pullup 0.5mA SCL Pullup 0.5mA Zener diode 5.0mA ITOTAL= ~21.3mA For the new resistor value calculation we approximated ITOTAL to be 24mA. Rz = | Vin − − Vzener | I TOTAL = | −48V − (−4.7V ) | = 1.8kΩ 24mA 2 V 2 | Vin − − Vzener | | −48V − (−4.7V ) | Power = = = = 1.04W R Rz 1.8kΩ (3) 2 2.1.2 (4) Limiting the input voltage of Vbus The INA226 Vbus pin is limited to 36V. As we are using voltages greater than 36V a voltage divider is needed at the input of the bus voltage pin. Please note that INA226 measures the bus voltage, Vbus, with respect to GND_INA. Figure 6 shows the voltage divider and Equation 5 shows the basic voltage divider equation. (Vin- = GND_INA) + Vin- = -48V R2 Vbus R1 Figure 6 Voltage Divider TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 6 www.ti.com Vbus = R2 × Vin − R1 + R2 (5) We targeted a voltage divider ratio of 4:1 (4Vbus = Vin-), please see Equation 6. Vbus = 1 × Vin− 4 (6) Combining Equation 5 and Equation 6, R2 1 = R1 + R2 4 (7) If we rearrange Equation 7 we can define the relation for R1 and R2: R1 =3 R2 (8) Another important detail to consider is that the Vbus pin has an input impedance of 830kΩ. The 830kΩ impedance, RVbus, is connected in reference to GND_INA. Meaning it will be in parallel with R2. Equation 8 will be now, R1 =3 R2 // RVbus (9) For this design we chose R1=35.7kΩ and R2=12.1kΩ. With this combination of resistors and with Vin- at -48V, Vbus will have 12.02 in reference to GND_INA. Also, just 1mA of current will be flowing in that path. We could have selected lower resistor values, such as R1=3kΩ and R2=1kΩ, but this would drive around 10mA of current. The lower the resistor value the larger the current that will be flowing in that path. Vbus = 12.1k R2 × Vin − = × −48V = −12.02V 35.7 k + 12.1k R1 + R2 ( 10 ) Figure 7 shows a simple simulation in TINA-TI™ that shows the position and value of the selected resistors, how Vbus is measured and how much current we are expecting with these resistors values. Current 1.01mA R1 35.7k INA226 Vbus Vbus -35.98V Vbus + V A - R2 12.1k R_Vbus 830k GND_INA GND_INA -48V Vin- = GND_INA -48 Figure 7 TINA-TI Simulation of voltage divider TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 7 www.ti.com Protection against surge at Vbus input is provided by a TVS (transient voltage suppressor) diode. TVS devices are ideal for the protection of I/O interfaces, VCC bus and other vulnerable circuits used in Telecom. Since the bus voltage maximum specified as 36V, the TVS diode should have a breakdown voltage slightly lower than 36 V. The SMBJ24A was selected to protect the INA226 device. 2.1.3 INA226 Filtering and Input Considerations The TI Design board has an optional input filter to remove high-frequency noise from the inputs VIN+ and VIN–.The default values for R3 and R4 are 0-Ω resistors. Figure 8 shows the recommended values for the filter. Figure 9 shows the location of the filter in the board. The board comes populated with two 0-Ω resistors (R3 and R4). However, the filter capacitor is not installed. If a filter is needed, use the lowest possible series resistance (typically 10Ω or less) and a ceramic capacitor. Recommended values for this capacitor are 0.1μF to 1.0μF. In many cases a filter is not needed. NOTE: Make sure the 0-Ω resistors are populated on the board. Otherwise the input of the INA226 device will be open. R4 ≤10Ω Vin- INC1 =0.1μF to 1.0μF Vin+ INA226 IN+ R3 ≤10Ω Figure 8 Input Filter Figure 9 Location of Input Filter in the TI Design board TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 8 www.ti.com 2.2 Second Stage: ISO1541Connections and External Components 2 The second stage of the circuit uses the ISO1541. The ISO1541 is a low-power, bidirectional I C compatible bus isolator. For more information about how the ISO1541 operates refer to ISO1541 datasheet. The ISO1541 device requires pullup resistors on the SCL and SDA pins. Pull-up resistors of 10kΩ were selected for this design. Capacitors (C4, C5, C6, and C7) were also connected to match the test diagram shown in ISO1541 datasheet, but these are optional. A 0.01-μF bypass capacitor on the supply is recommended. Figure 10 illustrates how ISO1541 was incorporated in this design. The High Voltage Side 2 is connected to the INA226 Vs, GND, SCL and SDA pins. The Low Voltage Side is connected to the I C master that is going to be used to read the data collected by the INA226. HIGH VOLTAGE SIDE LOW VOLTAGE SIDE C6= 0.1µF C7= 0.1µF GND GND_INA = -48V VDUT Vs R10 10k Vs (INA226 Vs) SDA2 SDA_ISO SCL2 SCL_ISO GND (GND_INA) VDUT R11 10k ISO1541 ISOLATION R9 10k R12 10k SDA1 SDA SCL1 SCL GND C6 33pF C7 33pF C4 33pF C5 33pF GND_INA = -48V GND Figure 10 ISO1541 Connections 2.3 Third Stage: SM-USB-DIG Platform and INA226 Software The third stage uses the TI SM-USB-DIG Platform and INA226EVM Software to display the data collected by the INA226 device. Figure 11 shows the overall system setup for the TI design system. The PC runs software (INA226 Telecom Demo Software) that communicates with the SM-USB-DIG Platform. The SM-USB-DIG Platform provides the supply voltage for the Low Voltage Side of the ISO1541 and generates digital signals used to communicate with the TI Design board. Connectors on the TI Design board allow the user to connect to the system under test and monitor the power, current, and voltage. TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 9 www.ti.com SM-USB-DIG Platform TI Design Board INA226 Telecom Demo Software Figure 11 TI Design System Setup For more information about the SM-USB-Dig Platform please refer to the SM-USB-DIG Platform User Guide document. For a quick tutorial on INA226EVM Software refer to the INA226EVM User’s Guide. 3 3.1 Component Selection INA226 For this design we were looking for a current shunt monitor with wide common mode range, high accuracy, ability 2 to report current/voltage/power and capable of I C interface communications. The current shunt monitor chosen for this application is the INA226. This device not only has the resolution and accuracy needed to achieve the design goals, but also features all the internal sub-systems required to realize the current/voltage/power calculations. 2 The INA226 is a digital current shunt monitor with an I C interface. It takes two measurements, shunt voltage and bus voltage. Figure 12 shows a basic block diagram of INA226. For more information about INA226 features please refer to the INA226 datasheet. VBUS INA226 SDA X VIN+ V Power Register Current Register ADC VIN- SCL I2C Interface Voltage Register I Alert Register GND A0 A1 Figure 12 INA226 Basic Block Diagram TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 10 www.ti.com 3.2 ISO1541 In this design the INA226 device will be referenced to the -48V rail. We need a device capable to translate -48V 2 reference into ground referenced signals. Low power consumption, compatibility with I C interfaces and a +3.3V to 5V supply voltage range are also required. The device selected for this task is the ISO1541. 2 The ISO1541 is a low-power, bidirectional I C bus isolator. The ISO1541 has its logic input and output buffers separated by TI’s Capacitive Isolation technology using a silicon dioxide (SiO2) barrier. This isolation technology provides for function, performance, size and power consumption advantages when compared to opto-couplers. 2 The ISO1541 has a bidirectional data and a unidirectional clock channel. It is compatible with I C interfaces and its supply range, +3V to +5.5V, meets our supply requirements. Figure 13 shows a basic block diagram of ISO1541. For more information about ISO1541 features please refer to the ISO1541 datasheet. VS VS ISO1541 ISOLATION (High Voltage) SDA2 SCL1 GND (Low Volatge) SDA1 SCL1 GND Figure 13 ISO1541 Basic Block Diagram 4 Simulation No simulation models are available for the INA226 device, so it is currently not possible to simulate the full functionality of the system. TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 11 www.ti.com 5 PCB Design The PCB schematic and bill of materials can be found in the Appendix A. 5.1 PCB Layout The two-layer printed circuit board (PCB) used in this design measures 3.54” x 2.33”. The PCB layout of this TI Design follows the following guidelines: 1. The input signal has a simple and clean path to the INA226 Vin+ and Vin- pins. The terminal block J1 for the input current and power supply share a common ground (GND_ISO) connection at the left side of the board. This shortens the path of the load current on the PCB. VinINA226 Vin+ Figure 14 INA226 path for input pins 2. Power supply bypass capacitors have been placed close to the devices’ supply pins. Vs2 pin Vs1 pin Vs pin INA226 ISO1541 Figure 15 Bypass Capacitors 3. The terminal block J7 has all the connections needed for the SM-USB-DIG. It is placed closed to the ISO1541 SDA, SCL, Vs and GND low voltage side pins. It is possible that the user would like to use its 2 own I C interface communication and supply voltage. For this purposes, another block terminal, J2, have been placed near the ISO1541 low voltage side pins. TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 12 www.ti.com 4. The board should have two ground sides. One ground side for the high voltage (-48 V) connections and the other side for the USB DIG low voltage connections. The board has been divided in two sections and has been marked with silk screen boundaries. See Figure 16. Figure 16 PCB Layout TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 13 www.ti.com 6 Verification & Measured Performance 6.1 6.1.1 Measured DC Transfer Function Data Collected with Rshunt=100mΩ and ILOAD = 50mA to 750mA Data was collected by sweeping the load current from 50mA to 750mA and measuring the shunt voltage of the INA226 across a 100mΩ shunt resistor. Table 3 shows the data collected. Vshunt real is the actual differential voltage that is applied to the differential input, measured at the inputs of the INA226 with precision volt meter. Vshunt INA226 is the Vshunt reported by the INA226. The relative error has been calculated using Equation 11. Figure 17 shows the calculated relative error and Figure 18 shows the transfer function. % Re lative _ Error = Vshunt REAL − Vshunt INA226 × 100 Vshunt REAL ( 11 ) Table 3 Data Collected with Rshunt=100mΩ and ILOAD = 50mA to 750mA Rshunt (mΩ) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 Load Current (mA) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 TIDU361-September 2014-Revised September 2014 Vshunt Real (mV) 4.96 10.13 15.29 20.45 25.61 30.78 35.94 41.11 46.27 51.43 56.6 61.78 66.97 72.13 77.29 Vshunt INA226 (mV) 4.94 10.11 15.26 20.42 25.59 30.76 35.91 41.07 46.25 51.39 56.59 61.77 66.95 72.11 77.3 % Error (%) 0.403 0.197 0.196 0.147 0.078 0.065 0.083 0.097 0.043 0.078 0.018 0.016 0.030 0.028 0.013 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 14 www.ti.com Measured Relative Error @ Rshunt= 100mΩ; Iload = 50mA to 750mA 0.450 0.400 Relative Error (%) 0.350 0.300 0.250 0.200 0.150 0.100 0.050 0.000 0 100 200 300 400 500 600 700 800 900 800 900 Load Current (mA) Figure 17 Relative Error with Rshunt=100mΩ and ILOAD = 50mA to 750mA Vshunt vs Load Current Rshunt= 100mΩ; Iload = 50mA to 750mA 90 80 Vshunt (mV) 70 60 50 40 30 20 10 0 0 100 200 300 400 500 Load Current (mA) 600 700 Figure 18 Measured DC Transfer Function (Vshunt vs IIN) with Rshunt=100mΩ and ILOAD = 50mA to 750mA TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 15 www.ti.com 6.1.2 Data Collected with Rshunt=100mΩ and ILOAD = -50mA to -750mA New set of data was collected by sweeping the load current from -50mA to -750mA and measuring the shunt voltage of the INA226 across a 100mΩ shunt resistor. Table 4 shows the data collected. Figure 19 shows the calculated relative error and Figure 20 shows the transfer function. Table 4 Data Collected with Rshunt=100mΩ and ILOAD = -50mA to -750mA Rshunt (mΩ) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 Load Current (mA) -50 -100 -150 -200 -250 -300 -350 -400 -450 -500 -550 -600 -650 -700 -750 TIDU361-September 2014-Revised September 2014 Vshunt Real (mV) -4.95 -10.53 -15.69 -20.84 -26.01 -31.17 -36.33 -41.5 -46.66 -51.83 -57.01 -62.17 -67.33 -72.51 -77.78 Vshunt INA226 (mV) -4.93 -10.56 -15.73 -20.89 -26.07 -31.23 -36.4 -41.55 -46.73 -51.89 -57.05 -62.24 -67.42 -72.61 -77.86 % Error (%) 0.404 0.285 0.255 0.240 0.231 0.192 0.193 0.120 0.150 0.116 0.070 0.113 0.134 0.138 0.103 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 16 www.ti.com Measured Relative Error @ Rshunt= 100mΩ; Iload = -50mA to -750mA 0.450 0.400 Relative Error (%) 0.350 0.300 0.250 0.200 0.150 0.100 0.050 0.000 -800 -700 -600 -500 -400 -300 -200 -100 0 Load Current (mA) Figure 19 Measure Relative Error with Rshunt=100mΩ and ILOAD = -50mA to -750mA Vshunt vs Load Current Rshunt= 100mΩ; Iload = -50mA to -750mA 0 -10 -20 Vshunt (mV) -30 -40 -50 -60 -70 -80 -90 -800 -700 -600 -500 -400 -300 -200 -100 0 Load Current (mA) Figure 20 Measured DC Transfer Function (Vshunt vs IIN) with Rshunt=100mΩ and ILOAD = -50mA to -750mA TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 17 www.ti.com 6.2 Maximum Shunt Voltage Error Analysis In order to set our design goals we have identified the main influences of maximum shunt voltage errors. 6.2.1 • Input offset voltage of the INA226 (VOS) • Shunt voltage gain error • Common-mode rejection of the INA226 (CMR) • Power supply rejection of the INA226 (PSR) • Input offset current (IOS) • Shunt resistor tolerance Errors at Small Values of Load Current When the load current is small there is a corresponding small input voltage to the INA226. Errors will be dominated primarily by the input offset related errors. Determining the errors associated with each parameter is straightforward and described below. 6.2.1.1 Initial Offset Voltage Error The maximum error due to input offset voltage can be taken directly from the INA226 device specification. The maximum input offset voltage is given as 10µV at 25˚C. This error is calculated with respect to the ideal voltage across the shunt (Vshunt). The ideal shunt voltage is the product of the load current and ideal shunt resistor value. The system nominal current is 50mA and the ideal shunt resistor value is 100mΩ. eVos = 6.2.1.2 Vos (max) Vshunt × 100 = Vos (max ) I load × Rshunt × 100 = 10µV × 100 = 0.20% 50mV × 100mV ( 12 ) Initial CMR Error The maximum input offset error due to the common mode rejection of the INA226 (VCMR) is calculated by determining the actual common mode voltage as applied to the INA226 with reference to the ground pin of the INA226. From the INA226 device specification the common mode rejection ratio minimum is given as 126dB (0.501µV/V). The offset voltage in the datasheet is specified with a common mode voltage 12V higher that what we called GND_INA, -48V. This means that the datasheet specification of 12V bus voltage is the same as -36V in this application, Vcm-pds = -36V. The resulting common mode error is determined as: eCMRR 6.2.1.3 (V = ) cm− pds − Vcm− sys × CMRRINA 226 Vshunt × 100 = ( − 36V − (−48V ) )× 0.501 µV 50mV × 100mV V × 100 = 0.120% (13) Initial PSR Error Error due to PSRR can be calculated in a manner similar to CMRR. From the INA226 device specification the specified power supply voltage for the input offset voltage specification is given as 3.3V. Any deviation from 3.3V applied between the INA226 V+ pin and ground pin will result in an additional error. From the INA226 device specification the power supply rejection ratio minimum is given as 2.5µV/V. The PSR error is determined as: ePSRR (V = ) s − pds − Vs − sys × PSRRINA 226 Vshunt TIDU361-September 2014-Revised September 2014 × 100 = (3.3V − 4.7V )× 2.5 µV 50mV × 100mV V × 100 = 0.07% -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated ( 14 ) 18 www.ti.com 6.2.1.4 Input Offset Current Error The input offset current is given as 10µA at 25˚C. This error is calculated with respect to the ideal voltage across the shunt (Vshunt). The ideal shunt voltage is the product of the load current and ideal shunt resistor value. The system nominal current is 50mA and the ideal shunt resistor value is 100mΩ. eVos = 6.2.1.5 I os × Rshunt 10µA × 100mΩ 1µV × 100 = × 100 = × 100 = 0.02% Vshunt 50mV × 100mV 5mV ( 15 ) Shunt Voltage Gain Error From the INA226 device specification the shunt voltage gain error is given as 0.1%. 6.2.1.6 Total Error at Small Currents The worst case total error at small load currents is calculated as below: n etotal − worst −case (% ) = ∑ en = 0.20 + 0.120 + 0.07 + 0.02 + 0.1 = 0.510% ( 16 ) 1 6.2.2 Errors at Large Values of Load Current At large load currents the input voltage developed across the shunt resistor will be at its maximum. This minimizes the percentage contribution of the errors from the initial error sources described above. The dominant errors sources for large inputs are: 6.2.2.1 • Shunt voltage gain error from the INA226 • Shunt resistor accuracy INA226 Shunt Voltage Gain Error From the INA226 device specification the shunt voltage gain error is given as 0.1%. 6.2.2.2 Shunt Resistor Error In this design it is assumed that the shunt resistor tolerance (accuracy) is 1.0%. However, this value will not be considered because the differential voltage that is reported in our results has been measured at the inputs of the INA226 with a precision volt meter. Measuring at the inputs of the INA226 eliminates the shunt resistor error contribution in our results. 6.2.2.3 CMR, PSR and Vos Errors The total error at large load current will also include the errors due to CMR, PSR, VOS and Input offset current with respect to the maximum load current (750mA). The errors are calculated as below: eCMRR (V = ) cm− pds − Vcm− sys × CMRRINA 226 ePSRR Vshunt (V = eVos = ) × 100 = s − pds − Vs − sys × PSRRINA 226 Vshunt ( − 36V − (−48V ) )× 0.501 µV 750mV × 100mV × 100 = V × 100 = 0.0080% (3.3V − 4.7V )× 2.5 µV 750mV × 100mV V × 100 = 0.0047% I os × Rshunt 10µA × 100mΩ 1µV × 100 = × 100 = × 100 = 0.0013% Vshunt I load × Rshunt 750mV × 100mV TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated (17) (18) (19) 19 www.ti.com 6.2.2.4 Total Error at High Currents The worst case total error at high load currents is calculated as below: n etotal −worst −case (% ) = ∑ en = 0.1 + 0.0080 + 0.0047 + 0.0013 = 0.1140% ( 20 ) 1 6.3 Measured Results Summary Table 5 Measured Performance Results 6.4 Goal Measured Relative Error (Iload= 50mA) 0.510% 0.403% Relative Error (Iload= -50mA) 0.510% 0.404% Relative Error (Iload= 750mA) 0.114% 0.013% Relative Error (Iload= -750mA) 0.114% 0.103% Vbus Range The TI Design targeted bus voltage was -48 volts. From results shown in Table 3 and Table 4 we have proved that using this TI Design board the INA226 is able to collect data at -48V rail. The Vbus range was verified by sweeping the bus voltage from 0V to -50V. Results showed that the INA226 is not able to collect data with Vbus values from 0 to -7V. At this voltage range the potential generated by the voltage drop across the Zener diode is not enough to power the device. Using this TI Design board the INA226 device is able to measure bus voltage and shunt voltage when the Vbus is -8V to -50V. Vbus Measured by INA226 (V) Vbus Range 55 50 45 40 35 30 25 20 15 10 5 0 -5 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 Vbus Applied (V) Figure 21 Vbus range accepted by TI Design board TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 20 www.ti.com 7 Modifications 7.1 INA226EVM Software Update A modified version of the INA226EVM Software has been released, only for this TI Design demonstration. This new version is called INA226 Telecom Demo Software. It allows the user to modify the LSB step size of the bus voltage, feature not available in INA226EVM Software. The LSB step size value has to be modified because we are dividing the bus voltage by 4, with the voltage divider, to meet the INA226 input bus voltage specifications. Currently, the INA226EVM Software uses 1.25mV as the LSB step size for the bus voltage It is important to take this LSB number and multiply it by the voltage divider ratio, 4. Failure to property set the LSB step size will result in incorrect bus voltage readings. The new LSB value will be 5mV. This 5mV value has been set as default in the INA226 Telecom Demo Software. New_LSB = (Vbus_Divider) × (Old _ LSB ) = 4 × 1.25mV = 5mV (21 ) Where; New_LSB: New LSB step size (Bus Voltage) Old_LSB: Old LSB step size (Bus Voltage) Vbus_Divider: Vbus voltage divider ratio The INA226 Telecom Demo Graphical User Interface (GUI) looks like Figure 22. Please note “Step 7”. This step was not included in INA226EVM software GUI. Use Step 7 to set the bus voltage LSB step size value. This is the only modification that has been made to the INA226EVM GUI. Please refer to the INA226EVM User’s Guide for Software configuration and GUI instructions. Figure 22 INA226 Telecom Demo GUI TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 21 www.ti.com 8 About the Author Mayrim Verdejo ([email protected]) is an Applications Engineer at Texas Instruments where she supports current shunt monitors and temperature sensors. Mayrim graduated from the University of Puerto Rico, Mayagüez, where she earned a Bachelor of Science in Electrical Engineering with emphasis on Digital Signal Processing. 9 Acknowledgements & References 9.1 Acknowledgements The author wishes to acknowledge Scott Hills and Ed Mullins for their ideas, support and assistance with this TI Design. 9.2 References 1. P. Semig and C. Wells. (2012, February 8). A Current Sensing Tutorial Parts I-IV. Available: http://www.eetimes.com/design/industrial-control 2 2. High-or Low-Side Measurement, Bi-Directional CURRENT/POWER MONITOR with I C™ Interface (SBOS547) 3. INA226EVM Evaluation Board and Software Tutorial (SBOU113) 2 4. Low-Power Bidirectional I C Isolators (SLLSEB6B) 5. Power: Telecom DC/DC Module: Analog Available: http://www.ti.com/solution/power_telecom_dc_dc_module_analog TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 22 Appendix A. A.1 Electrical Schematic Figure A-1: Electrical Schematic An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. TINA-TI is a trademark of Texas Instruments WEBENCH is a registered trademark of Texas Instruments TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2014, Texas Instruments Incorporated 23 A.2 Bill of Materials Figure A-2: Bill of Materials An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. TINA-TI is a trademark of Texas Instruments WEBENCH is a registered trademark of Texas Instruments TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2014, Texas Instruments Incorporated 24 Appendix B. B.1 TI Design Board Functionality and Setup B.1.1 TI Design board kit Table B-1 details the contents of the TI Design kit, and Figure B-1 below shows all of the included hardware. Table B-1. Contents of INA226EVM kit Item Quantity TI Design Board USB SM-DIG Platform PCB USB Extender Cable SM-Dig Connector Ribbon Cable 1 1 1 1 SM-DIG Connector Ribbon Cable USB Extender Cable USB SM-DIG TI Design Board Figure B-1: Hardware needed for TI Design Evaluation An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. TINA-TI is a trademark of Texas Instruments WEBENCH is a registered trademark of Texas Instruments TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2014, Texas Instruments Incorporated 25 www.ti.com B.1.2 INA226 Telecom Demo Hardware Setup Connect the INA226 Telecom Demo and the USB SM-DIG Platform together. Make sure that the two connectors are completely pushed together; loose connections may cause intermittent operation. Please refer to figure below for connection guideline (Texas Instruments logo should be looking upside down). Figure B-2 How to connect the TI Design board and the USB SM-DIG Platform After the INA226 Telecom Demo board and SM-DIG are connected, as in Figure B-2, connect the desired bus voltage and shunt configuration intended to be measured. For this, connect an external dc power supply of -48V to the Vin- (GND_INA) pin referenced to the GND_ISO pin on terminal block J1. Also, connect a shunt resistor between the Vin+ and Vin- terminals. When connecting a load, attach it to the Vin+ pin at terminal block J1. Refer to Figure 16. B.1.3 INA226 Telecom Demo Jumper Settings 2 Jumpers 3 through 6 (J3-J6) controls the I C address pin for the INA226, these jumpers can set the address for A0 and A1 to either high, low, SCL, or SDA. Make sure to only connect one jumper at a time for each address control, for example connecting only J3 and not J4. Failure to properly connect jumpers can cause shorts or interruptions in the communication lines. For more information on the INA226 addressing, please consult the INA226 datasheet. Table B-2 summarizes the function of the TI Design board jumpers. Table B-2 TI Design Jumper Functions Jumper Default Purpose 2 J3/J4 GND This jumper selects I C AO address selection for A0. Four separate I2C addresses can be selected depending upon whether J3 is set to high or low or J4 is set to SDA/SCL. J5/J6 GND This jumper selects I2C AO address selection for A1. Four separate I2C addresses can be selected depending upon whether J5 is set to high or low or J6 is set to SDA/SCL. TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 26 www.ti.com B.1.4 INA226 Telecom Demo Features This section describes some of the hardware features present on the TI Design board. 2 B.1.4.1 J3/J4 – I C Address Hardware Setting (A0) 2 Jumper J3 and J4 are used to set the hardware settings for the A0 I C address pin on the INA226. Using J3, the A0 address can be set to either a logic “1” or a logic “0”. Using J4, the A0 address can be set to either the SCL or SDA communication line. Make sure to only have either J3 or J4 connected individually; failure to keep these lines 2 separate can lead to board shorts and problems with the I C communication lines. See the section 5.2.1, in the INA226EVM User’s Guide, on how to configure the INA226EVM software to match the J3/J4 hardware setting. B.1.4.2 2 J5/J6 – I C Address Hardware Setting (A1) 2 Jumper J5 and J6 are used to set the hardware settings for the A1 I C address pin on the INA226. Using J3, the A1 address can be set to either a logic “1” or a logic “0”. Using J4, the A1 address can be set to either the SCL or SDA communication line. Make sure to only have either J5 or J6 connected individually; failure to keep these lines 2 separate can lead to board shorts and problems with the I C communication lines. See the section 5.2.1, in the INA226EVM User’s Guide, on how to configure the INA226EVM software to match the J5/J6 hardware setting. B.1.4.3 2 External I C lines and Terminal Block J2 2 The I2C communication lines on the TI Design board are tied to two sources: The internal I C communication lines from the SM-DIG (J7) and the Terminal block J2. In the event the user wants to add external signal separate from the SM-DIG, simply disconnect the SM-DIG from the Ti design board and hook up the needed SDA, SCL, 2 and GND lines. Also, remember to apply an external DVDD to the lines that is compatible with the I C communication device being used. TIDU361-September 2014-Revised September 2014 -48V Telecom Current/Voltage/Power Sense with Isolation Copyright © 2013, Texas Instruments Incorporated 27 IMPORTANT NOTICE FOR TI REFERENCE DESIGNS Texas Instruments Incorporated ("TI") reference designs are solely intended to assist designers (“Buyers”) who are developing systems that incorporate TI semiconductor products (also referred to herein as “components”). Buyer understands and agrees that Buyer remains responsible for using its independent analysis, evaluation and judgment in designing Buyer’s systems and products. TI reference designs have been created using standard laboratory conditions and engineering practices. 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