Features • • • • • • • • • • • Pin-programmable Mode Supply Voltage Range 1.55V to 3.6V PHY IC_USB1.0 Downstream Port Bridge USB2.0 Section 7 to IC_USB1.0 Bridge IC_USB1.0 to USB2.0 Section 7 3.3V Voltage Reference Two 70mA LDO Voltage Regulators Less Than 5µA Static Current on Each Supply Slew Rate Control to Minimize Radiated EMI ESD 4kV Compliant with USB UICC Applications: – Mobile USB UICC (ETSI 102 600), PC USB UICC, Token USB Description The AT73C260 is an Inter Chip USB transceiver fully compliant with the Universal Serial Bus Specification, and more specifically with the IC_USB1.0 supplement. The AT73C260 is a bidirectional differential interface. The AT73C260 is ideal for applications in mobile devices, PCs and USB tokens making use of an USB UICC. The AT73C260’s upstream facing port may be connected to three different interfaces: Power Management and Analog Companions (PMAAC) AT73C260 • Digital • USB2.0 section 7 with or without cable • IC_USB1.0 The AT73C260’s downstream port complies with IC_USB1.0. The AT73C260’s mode is selected by three pins. When PVCC is powered by 3.3V and pull down resistors are added on PDM and PDP, the AT73C260’s downstream port complies with USB2.0 section 7. The AT73C260 includes a 3.5V Supply Monitor, a Low Power Band-Gap, a 3.3V 70mA Linear Voltage Regulator and a 1.8V-3.0V 70mA Linear Voltage Regulator SIM FTA compliant Test 27.17.2.1. The AT73C260 is specified over the industrial temperature range - 40°C to +85°C. Interchip USB Transceiver (PHY - IC_USB1.0, Voltage Class Converter, USB2.0 - IC_USB1.0 Bridges) The AT73C260 is available in a 3 X 3 mm, 0.5mm pitch, QFN16 package. Preliminary 11030A–PMAAC–13-Sep-10 1. Block Diagram Figure 1-1. AT73C260 functional block diagram 9 AT73C260 PVRF 1 12 HVCC PVCC Vref 3.3Volt 4 VBUS 13 RCV 6 10 HDMO PDM 7 HDPO 8 OE_N 2 11 HDP PDP 3 HDM M<2> M<1> M<0> GND 14 2 15 16 5 AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 2. Package and Pinout PVRF 9 10 PDM Thermal Pad (BOTTOM) 11 PDP AT73C260 QFN16 package pinout - top view 12 PVCC Figure 2-1. 8 OE_N RCV 13 M<0> 16 6 HDMO HDP 2 17 GND HVCC 1 PIN 1 INDICATOR 7 HDPO 5 GND VBUS 4 M<1> 15 C260B YYWW XXXXX HDM 3 M<2> 14 3 11030A–PMAAC–13-Sep-10 3. Pin Description Table 3-1. Pin Name AT73C260 Pin Description I/O Pin Number Type Function Output 1 Analog Host Side VCC •When pin 4 (VBUS) is grounded. The LDO on pin HVCC is in standby and its output is isolated. The Host supplies HVCC with the appropriate voltage to the AT73C260’s upstream transceiver. •When pin 4 (VBUS) is connected to a voltage source the internal voltage reference 3.3V and both LDO are activated. The LDO on pin 1 provides power at 3.3V to the AT73C260’s upstream transceiver and it may source up to 70mA. HDP I/O 2 Digital Bidirectional HDM I/O 3 Digital Bidirectional VBUS Input 4 Analog Supply, provides power to the LDOs on pin 1 and 12 GND Ground 5 Analog GND Ground for Digital and I/Os HDMO Output 6 Digital Output HDPO Output 7 Digital Output OE_N Input 8 Digital Input PVRF Input 9 Analog PVCC LDO input reference PDM I/O 10 Digital Bidirectional pad PDP I/O 11 Digital Bidirectional pad HVCC Input 12 Analog Peripheral Side VCC •When pin 4 (VBUS) is grounded. The LDO on pin PVCC is in standby and its output is isolated. The application supplies PVCC with the appropriate voltage to the AT73C260’s downstream transceiver. •When pin 4 (VBUS) is connected to a voltage source, the LDO on pin PVCC follows the voltage on pin PVRF. The LDO on pin PVCC provides power to the AT73C260’s downstream transceiver and it may source up to 70mA. RCV Output 13 Digital Output M<2> Input 14 Digital Input. For mode configuration M<1> Input 15 Digital Input. For mode configuration M<0> Input 16 Digital Input. For mode configuration GND Ground 17 Analog Analog Ground. Thermal Pad. Shall be connected to GND for electrical and power dissipation reasons. PVCC 4 AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 4. Absolute Maximum Ratings Table 4-1. Absolute Maximum Ratings Operating Temperature (Industrial)..................-40°C to + 85°C(1) *NOTICE: Storage Temperature........................................-55°C to + 150°C Power Supply Input on HVCC............................... -0.3V to + 3.6V Power Supply Input on VBUS............................. -0.3V to + 5.5V Digital I/O Input Voltage...................................... -0.3V to + 3.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Other Pins.......................................................-0.3V to + 3.6V ESD (all pins)..............................................................4 KV HBM Notes: 1. Refer to Power Dissipation Rating section) 5. Recommended Operating Conditions Table 5-1. Recommended Operating Conditions Parameter Condition Operating Ambient Temperature (1) Min Max Units -40 85 °C Power Supply Output PVCC 1.55 3.6 V Power Supply Input HVCC 1.55 3.6 V Power Supply Input VBUS 4.0 5.5 V Note: 1. Refer to Power Dissipation Rating section 6. Power Dissipation Ratings Table 6-1. Recommended Operating Conditions Parameter Condition Maximum Junction Temperature Min Typ Max Units -40 -- 125 °C RTHjA(1) Package thermal junction to ambient resistance -- -- 90 °C / W Maximum On-chip Power Dissipation Ambient temperature = 85°C -- -- 400 mW Note: 1. According to specification JESD51-5 5 11030A–PMAAC–13-Sep-10 7. Electrical Characteristics 7.1 I/Os DC Characteristics Referred to HVCC Table 7-1. Symbol HVCC Referred I/Os: HDP, HDM, RCV, HDMO, HDPO, OE_N and M<2:0> Parameter Comments (1) Min Typ Max Units 1.55 -- 3.6 V -- -- 2 mA HVCC Host Side Supply Voltage 220nF ceramic capacitor IHVCC Operating HVCC Supply Current Full Speed Transceiver / Receiver at 12Mbps, CLOAD = 18pF on HDP and HDM during transmit VIH Input High-Level Voltage VOH > VOH_MIN 0.65 x HVCC -- HVCC + 0.3 V VIL Input Low-Level Voltage VOH < VOL_MAX -0.3 -- 0.35 x HVCC V VOH Output High-Level Voltage IOH = - 2mA HVCC 0.45 -- -- V VOL Output Low-Level Voltage IOL = 2mA -- -- 0.45 V RPDP Pull-Down Resistors on HDP, HDM All Cases 30 -- 80 kΩ RPU1(2) Upstream Pull-Up Resistors on HDP M<0> = 0 M<2:1> = connected to HVCC 0.9 -- 3.09 kΩ RPU2(3) Upstream Pull-Up Resistors on HDP M<2:0> = connected to HVCC 1 -- 150 kΩ Notes: 1. A 220nF ceramic capacitor is connected between the pin HVCC and the pin GND and closest to HVCC pin. 2. RPU1 Pull Up resistor is as per the ECN “Pull-up/pull-down resistors” published by the USB-IF. RPU1 value is between 900Ω and 1575Ω when the bus is idle and between 1425Ω and 3090Ω when the upstream device is transmitting 3. RPU2 Pull Up resistor is as per the IC_USB1.0 published by the USB-IF. RPU2 value is between 1kΩ and 3kΩ to attach and between 30kΩ and 150kΩ during idle. 7.2 I/Os DC Characteristics Referred to PVCC Table 7-2. PVCC Referred I/Os: PDP, PDM Symbol Parameter Comments Min Typ Max Units PVCC Peripheral Side Supply Voltage 220nF ceramic capacitor (1) 1.55 -- 3.6 V IPVCC Operating PVCC Supply Current Full Speed Transceiver / Receiver at 12Mbps, CLOAD = 18pF on PDP and PDM during transmit -- -- 2 mA VIH Input High-Level Voltage VOH > VOH_MIN 0.65 x PVCC -- PVCC + 0.3 V VIL Input Low-Level Voltage VOH < VOL_MAX -0.3 -- 0.35 x PVCC V VOH Output High-Level Voltage IOH = - 2mA PVCC 0.45 -- -- V VOL Output Low-Level Voltage IOL = 2mA -- -- 0.45 V RPDH Pull-Down Resistors All Cases for PDP, PDM 30 -- 80 kΩ Notes: 6 1. A 220nF ceramic capacitor is connected between the pin PVCC and the pin GND and closest to PVCC pin. AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 7.3 Timing Characteristics Table Table 7-3. Timing Table Symbol Parameter TDELAY Propagation Delay Time TSLEW_R_P Slew Rate, Rise Time on PDP TSLEW_R_M Slew Rate, Rise Time on PDM Comments Min Typ Max Units HVCC = 3.3V and PVCC = 3.0V -- 37 -- ns HVCC = 3.3V and PVCC = 1.8V -- 42 -- ns 10%-90%, CLOAD=33pF, PVCC=3.0V -- 5.7 -- 10%-90%, CLOAD=33pF, PVCC=1.8V -- 10.5 -- 10%-90%, CLOAD=33pF, PVCC=3.0V -- 5.6 -- 10%-90%, CLOAD=33pF, PVCC=1.8V -- 10.6 -- 10%-90%, CLOAD=33pF, PVCC=3.0V -- 6.1 -- 10%-90%, CLOAD=33pF, PVCC=1.8V -- 7.6 -- 10%-90%, CLOAD=33pF, PVCC=3.0V -- 6.1 -- 10%-90%, CLOAD=33pF, PVCC=1.8V -- 7.7 -- ns TSLEW_F_P Slew Rate, Fall Time on PDP TSLEW_F_M Slew Rate, Fall Time on PDM TATTACH Attachment Transit Time M<2:0>=110, HVCC = 3.3V and PVCC = 3.0V -- 400 -- ns TATTACH Attachment Transit Time M<2:0>=111, HVCC = 1.8V and PVCC = 3.3V -- 400 -- ns Notes: 1. External Capacitor is a 1µF or higher ceramic capacitor connected between the pin VBUS and the pin GND and closest to VBUS pin 7.4 VBUS Supply Characteristics Table 7-4. Symbol VBUS Supply Monitor Parameter Comments Min Typ Max Units 4.0 5.0 5.5 V VBUS Input Supply Voltage Range VTP Positive Threshold 3.36 3.5 3.64 V VTN Negative Threshold 3.02 3.15 3.28 V VHYS Hysteresis 348 361 374 mV Notes: 1µF ceramic capacitor (1) 1. External Capacitor is a 1µF or higher ceramic capacitor connected between the pin VBUS and the pin GND and closest to VBUS pin . Table 7-5. Symbol VBUS IVBUS Notes: VBUS Current Consumption Parameter Comments Input Supply Voltage Range 1µF ceramic capacitor VBUS Supply Current VBUS active • HVCC= 3.3V nominal • 1.55V < PVRF < 3.6V • Loads = 0mA • Idle (1) Min Typ Max Units 4.0 5.0 5.5 V -- 100 150 µA 1. External Capacitor is a 1µF or higher ceramic capacitor connected between the pin VBUS and the pin GND and closest to VBUS pin. 7 11030A–PMAAC–13-Sep-10 7.5 HVCC and PVCC Supplies Characteristics 7.5.1 HVCC and PVCC Current Consumption Table 7-6. PVCC and HVCC Current Consumption Symbol Parameter HVCC PVCC IVCC 7.5.2 Typ Max Units Host Supply Voltage 1.55 -- 3.6 V Peripheral Supply Voltage 1.55 -- 3.6 V -- -- 5 µA Symbol (1) IO HVCC LDO Characteristics Parameter Comments Min Typ Max Units Output Voltage - Enabled when VBUS is greater than 3.5V typical. - Disabled when VBUS goes below 3.15V typical 3.0 3.3 3.6 V 0 -- 70 mA Output Current Static Load Regulation • VBUS > 4.5V • IO = 10% to 90% -- -- 10 mV Dynamic Load Regulation • VBUS > 4.5V • IO = 10% to 90% • TRISE = TFALL = 5µs -- 50 -- mV • VBUS from 4.3V to 5.5V • IO = Max -- -- 20 mV • VBUS from 4.0V to 5.5V • IO = 7 mA -- -- 20 mV • VBUS From 0V to 5.0V • TRISE = 10µs • IO = 0mA • VOUT > 3.0V -- -- 60 µs ΔVDD_IL ΔVDD_VIN TSTART Notes: 8 VBUS = 0V, PVRF = 0V • Loads = 0mA • Idle • HVCC forced at 3.6V • PVCC forced at 3.3V 3.3V Supplied on HVCC When V BUS is greater than 3.5V nominal, an internal LDO voltage regulator provides a 3.3V nominal voltage source on pin HVCC. Table 7-7. HVCC Min XVCC Supply Current Comments Static Line Regulation Start-up Time 1. When VBUS is present and greater than VTP, 10kΩ pull down is removed on HVCC and on PVCC and LDO are started. When VBUS goes below VTP, a 10kΩ pull down is connected on HVCC and PVCC and LDO are disabled. When VBUS = 0V and HVCC and PVCC within their normal range the 10kΩ pull down are disconnected. AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 7.5.3 Voltage Supplied on PVCC When VBUS is greater than 3.5V nominal, an internal LDO Follower provides a voltage source on pin PVCC. The voltage on pin PVCC is equal to the voltage on pin PVRF. PVCC LDO is in accordance with FTA Test 3GPP - 27.17.2.1 dedicated for Subscriber Identity Module (SIM) application. Table 7-8. PVCC LDO Characteristics Symbol Parameter Comments Min Typ Max Units VBUS Supply Input Voltage On pin VBUS 4.0 5.0 5.5 V PVCC(1) Output Voltage - Enabled when VBUS is greater than 3.5V typical. - Disabled when VBUS goes below 3.15V typical - 1.55V < PVRF < 3.6V 1.55 -- 3.6 V VOFF Follower Offset Voltage PVCC - PVRF -40 -- 40 mV IO Output Current 0 -- 70 mA Static Load Regulation • VBUS > 4.5V • IO = 10% to 90% -- -- 10 mV Dynamic Load Regulation • VBUS > 4.5V • IO = 10% to 90% • TRISE = TFALL = 5µs -- 30 -- mV • VBUS from 4.3V to 5.5V • IO = Max -- -- 20 mV • VBUS from 4.0V to 5.5V • IO = 7 mA -- -- 20 mV • VBUS is set at 5.0V • PVRF 0V to 1.8V with TRISE = 5µs • IO = 10mA • VOUT > 1.62V -- 20 35 µs • VBUS is set at 5.0V • PVRF 0V to 3.0V with TRISE = 5µs • IO = 10mA • VOUT > 2.7V -- 32 50 µs • VBUS is set at 5.0V • PVRF 3.0V to 0V with TFALL = 5µs • RLOAD = 1KΩ. COUT=220nF/ X5R • VOUT < 0.4V -- -- 525 µs • VBUS is set at 5.0V • PVRF 3.0V to 0V with TFALL = 5µs • IO = 7mA. COUT=220nF/ X5R • VOUT < 0.4V -- -- 225 µs ΔVDD_IL ΔVDD_VIN TSTART Start-up Time TSTOP(2) Notes: Static Line Regulation Power-Off Time 1. When VBUS is present and greater than VTP, 10kΩ pull down is removed on HVCC and on PVCC and LDO are started. When VBUS goes below VTP, a 10kΩ pull down is connected on HVCC and PVCC and LDO are disabled. When VBUS = 0V and HVCC and PVCC within their normal range the 10kΩ pull down are disconnected. 2. Off time is described in Section 9.3.4 on page 16. To reduce TSTOP time an external reisitor is recommended. This value depends on COUT and load applied on the system. 9 11030A–PMAAC–13-Sep-10 8. Components List. Table 8-1. AT73C260 External Components List Component Name Component Type Value / Tol. R 1 , R2 Resistor 33 Ω +/- 5% CRG0402J33R R3 Resistor 10 Ω +/- 5% CRG0603J10R R4 Resistor 10kΩ +/- 1% CPF0402F10KE1 R5 Resistor 100kΩ +/- 1% CPF0603F100KC1 R 6 , R7 Resistor 22kΩ +/- 5% CRG0402J22K C 1 , C2 Ceramic Capacitor COG 22pF +/- 20% C1005COG1H220J GRM1555C1H220JZ01 C3 Ceramic Capacitor X5R 1µF +/- 20% C1005X5R0J105K GRM155R60J105KE19 C4 Ceramic Capacitor X5R 220nF +/- 20% C1005X5R1C224KT GRM155R60J224KE01 C5 Ceramic Capacitor X5R 220nF +/- 20% C1005X5R1C224KT GRM155R60J224KE01 10 Reference Reference AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 9. Functional Description 9.1 AT73C260’s Upstream and Downstream Ports This section relates to either upstream or downstream ports with digital, IC_USB1.0 or USB2.0 section 7 electrical characteristics. Table 9-1 shows the configuration of the upstream and downstream ports based on pins 14, 15 and 16 voltages. • 0 is when the pin is connected to GND. • 1 is when the pin is connected to HVCC. Table 9-1. Upstream and Downstream Ports M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 Upstream Port Downstream Port 0 0 0 Digital IC_USB1.0 0 0 1 Digital IC_USB1.0 0 1 0 Digital IC_USB1.0 0 1 1 Digital IC_USB1.0 1 0 0 Not Used Not Used 1 0 1 Digital IC_USB1.0 1 1 0 Section 7 IC_USB1.0 1 1 1 IC_USB1.0 Section 7 (1) / IC_USB1.0 Notes: 1. PVCC is set to 3.3V and external pull down resistors of 22kΩ ± 5% are connected, one between PDP and GND and the other between PDM and GND. 11 11030A–PMAAC–13-Sep-10 9.2 AT73C260 Pull Up and Pull Down Resistors Pull down resistors RPDP and RPDH values and behaviors comply with the IC_USB1.0 specification published by the USB-IF. 9.2.1 9.2.2 AT73C260 Upstream Port Connectivity (HVCC, HDP, HDM): The host, IC_USB1.0 or USB2.0 section 7, is connected to the AT73C260’s upstream port. • When in IC_USB 1.0 RPU2 is selected. • When in USB2.0 section 7 RPU1 is selected. AT73C260 Downstream Port Connectivity (PVCC, PDP, PDM): The peripheral, IC_USB1.0 or USB2.0 section 7, is connected to the AT73C260’s downstream port. • An IC_USB1.0 peripheral is connected to the AT73C260’s downstream port. • An USB2.0 section 7 peripheral is connected to the AT73C260’s downstream port with external pull down resistors as per precedent note (1) (See Table 9-1 on page 11). Figure 9-1. AT73C260 Downstream and Upstream Ports HVCC PVCC SW2 SW1 RPU1 RPU2 HDP PDP HDM PDM RPDP SW3 RPDH SW4 SW5 SW6 GND 12 AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 9.3 Theory Of Operation 9.3.1 Remote Wake Up The AT73C260 does not support remote wake up. 9.3.2 Slew Rate Control When the AT73C260 drives an IC_USB bus section the output buffer on each line (Figure 9-2) drives the pin with a slew rate control to minimize radiated EMI. Figure 9-2. AT73C260 Output Buffer Output buffers TxIC_DP C T = 18pF CT TxIC_DM CT Figure 9-3. AT73C260 Output Buffer Slew Rate 90% 90% 10% 10% tR Note: tF See Table 7-3 on page 7 for timing values. 13 11030A–PMAAC–13-Sep-10 9.3.3 Attach Figure 9-4. AT73C260 Attach Sequence HDP Reset idle PDP idle T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 In the following paragraphs, two different attach sequences are described according the mode selected. Mode VCC and Mode S7_ICC_TK are explained. 9.3.3.1 Attach Sequence ”Mode VCC” The following sequence describes the AT73C260 with an IC_USB upstream connection and an IC_USB downstream connection (Mode VCC). For hardware connection refers to “Mode: Voltage Class Converter: VCC” on page 34. • HVCC and PVCC are present and are in their dedicated voltage range. • RPU1 is not used (SW1 always open). (For more information about switches, refers to Figure 9-1 on page 12) • Before T1, RPDP and RPDH are connected. RPU2 is disconnected. (For more information about resistors, refers to Figure 9-1 on page 12) • T1: Peripheral event. Beyond T1, PDP is driven high by the IC_USB peripheral’s pull-up resistor. • T2: AT73C260 event. The signal is above VIH. The AT73C260 verifies that the condition PDP is high lasts more than 200ns nominal. This information is passed to the AT73C260’s Host side. • T3: AT73C260 event. Beyond T3, RPU2 (2k nominal) is connected while RPDP on HDP is disconnected. • T4: Host event. From T4 the host drives the reset with SE0. • T5: AT73C260 event. It takes 40 ns nominal beyond T4 for PDP to be driven low. • T6: AT73C260 event. During reset the AT73C260 detects a SE0 for more than 1µs nominal. Beyond T6 both RPDH are disconnected. 14 AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 • T7: Host event. Host stops driving SE0. The AT73C260 with its 2k nominal resistor, pulls-up HDP. • T8: AT73C260 event. The signal is above VIH.(on HDP) • T9: AT73C260 event. 40ns nominal after T8. From T9, the AT73C260 drives high until VIH (on PDP) is reached plus 100ns nominal until T11. • T10: AT73C260 event. Between T7 and T10. HDP is pulled-up with 2k nominal until VIH (on HDP) is reached plus 100ns. At T10 RPU2 becomes 50k nominal. 9.3.3.2 Attach Sequence Mode S7_ICC_TK The following sequence describes the AT73C260 with an USB2.0 section 7 upstream connection and an IC_USB downstream connection (Mode S7_ICC_TK). For hardware connection refers to “Mode: USB2.0 section 7 to IC_USB1.0 with PVCC fixed by PVRF: S7_ICC_TK” on page 38. • HVCC = 3.3V and PVCC are present and are in their dedicated voltage range. • RPU2 is not used (SW2 always open). RPDP are not used (SW3 and SW4 always open).(For more information about switches, refers to Figure 9-1 on page 12) • Before T1, RPDH are connected. RPU2 is disconnected. (For more information about resistors, refers to Figure 9-1 on page 12) • T1: Peripheral event. Beyond T1, PDP is driven high by the IC_USB peripheral’s pull-up resistor. • T2: AT73C260 event. The signal is above VIH. The AT73C260 verifies that the condition PDP is high lasts more than 200ns nominal. This information is passed to the AT73C260’s Host side. • T3: AT73C260 event. Beyond T3, RPU1 1.2k nominal, is connected. • T4: Host event. From T4 the host drives the reset with SE0. • T5: AT73C260 event. RPU1 becomes 2.2k nominal. It takes 40 ns nominal beyond T4 for PDP to be driven low. • T6: AT73C260 event. During reset the AT73C260 detects a SE0 for more than 1µs nominal. Beyond T6 both RPDH are disconnected. • T7: Host event. Host stops driving SE0. The AT73C260 with its 2k nominal resistor, pulls-up HDP. • T8: AT73C260 event. The signal is above VIH.(on HDP) 15 11030A–PMAAC–13-Sep-10 • T9: AT73C260 event. 40ns nominal after T8. From T9, the AT73C260 drives high until VIH (on PDP) is reached plus 100ns nominal until T11. • T10: AT73C260 event. Between T7 and T10. HDP is pulled-up with 2.2k nominal until VIH (on HDP) is reached plus 100ns. At T10 RPU1 becomes 1.2k nominal. 9.3.4 PVRF Driving PVCC Figure 9-5. AT73C260 PVRF driving PVCC PVRF TOFF PVCC 90% 10% TSTART TSTOP When VBUS, pin 4, is providing power to the USB UICC via the LDOs, the voltage on PVCC (pin 12) is following the voltage on PVRF (pin 9). TSTART is mostly related to the capacitive load on PVCC and the strength of the LDO’s PMOS. TSTART as mentioned in Table 7-8 on page 9 is less than 50µs. TSTOP is mostly related to the load on PVCC since the LDO’s PMOS is off when starts TOFF. Certain applications may require PVCC to fall below a minimum voltage in less than TOFF and guarantee a Power On Reset sequence in the USB UICC when PVCC is set again. For these applications an extra load, such as a resistor across PVCC and GND in parallel with the USB UICC and the decoupling capacitor C5 may be required. As an example, for TOFF = 0.4ms, a decoupling capacitor C5 of 220nF and an USB UICC in standby (less than 100µA) the extra resistor shall be less than 1kΩ. 16 AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 9.3.5 Reset Signaling At the end of the Reset signaling on AT73C260’s host side and peripheral sides the pulled up data line voltage has to reach VIH_MIN in less than TDDIS, see Figure 9-6. If it is not the case, the host may see a disconnect condition. Reset is forced during T2. If a 100kΩ pull up resistor is used while the capacitive load is more than 20pF, the time constant is greater than 2µs. To avoid any disconnect condition, the AT73C260 pulls up the appropriate data line during about one bit duration with extra strength making the disconnect condition unlikely. Figure 9-6. AT73C260 Reset Signaling IC_DP VIH_MIN IC_DM Less than TDDIS min (2µs) Reset signaling T1 9.3.6 T2 Resume Signaling The AT73C260 supports resume signaling. The timings on IC_DP and IC_DM are those on HDP and HDM delayed by 40ns nominal. Figure 9-7. AT73C260 Resume Signaling One J state EOP (Two Low Speed bit time) HDP SOF TDRSMND (≥ 20ms minimum) HDM 3ms max Idle, J state The Hub signals resume to the UICC by forcing a K state during TDRSMDN (≥ 20ms) Notes: 1. J state means that HDP = 1 and HDM = 0. 2. K state means that HDP = 0 and HDM = 1. 3. SOF = Start Of Frame 17 11030A–PMAAC–13-Sep-10 9.4 General Description The AT73C260 covers four main functions: • PHY (described in Section 9.4.3 on page 20) • Bridge (described in Section 9.4.4 on page 30) • IC_USB1.0 Voltage Class Converter (described in Section 9.4.5 on page 34) • Bridge with LDOs for two specific applications (described in Section 9.4.6 on page 36), and one extra function from many described as an example where the AT73C260 is an interchip PHY in a digital implementation (FPGA) of a peripheral. 9.4.1 Application Modes The following Table 9-2 lists the applications and pin settings. Table 9-2. AT73C260 Application Modes (4) Mode Application M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 Function PHY_6_SE0 Digital six wires unidirectional DAT_SE0 to IC_USB1.0 0 0 0 PHY PHY_4_SE0 Digital four wires bidirectional DAT_SE0 to IC_USB1.0 0 0 1 PHY PHY_6_DPDM Digital six wires unidirectional DP_DM to IC_USB1.0 0 1 0 PHY PHY_4_DPDM Digital four wires bidirectional DP_DM to IC_USB1.0 0 1 1 PHY PHY_3_ULPI Digital three wires bidirectional (DAT, SE0, OE_N) to IC_USB1.0 1 0 1 PHY S7_ICC USB2.0 section 7 without cable to IC_USB1.0 1 1 0 Bridge S7_ICC_DBB USB2.0 section 7 with cable to IC_USB1.0, LDOs ON VCC driven by the Digital Base Band (2) 1 1 0 Bridge with LDOs S7_ICC_TK USB2.0 section 7 with cable to IC_USB1.0, LDOs ON VCC fixed by PVRF (3) 1 1 0 Bridge with LDOs ICC_S7 IC_USB1.0 to USB2.0 section 7 (1) 1 1 1 Bridge VCC IC_USB1.0 to IC_USB1.0 1 1 1 Voltage Class Converter Notes: 1. 22kΩ Pull down on pins 10 and 11 2. PC with Digital Base Band 3. Token 4. M<2:0> code”100” is not used 18 AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 9.4.2 Function Descriptions 9.4.2.1 Downstream Port PHY: A set of digital signals generated by an FPGA or an ASIC with I/O powered by a first power supply drive the AT73C260 which converts these signals into analog signals IC_DP and IC_DM as per IC_USB1.0 powered by a second power supply. 9.4.2.2 Bridge: Two cases are supported: USB2.0 section 7 to IC_USB1.0 and IC_USB1.0 to USB2.0 section 7. • USB2.0 section 7 to IC_USB1.0 Downstream D+ and D- signals drive the AT73C260 which converts these signals into analog signals IC_DP and IC_DM as per IC_USB1.0. • IC_USB1.0 to USB2.0 section 7 Downstream IC_USB1.0 signals drive the AT73C260 which converts these signals into analog signals D+ and D- as per USB2.0 section 7. 9.4.2.3 Voltage Class Converter: The following applications enable communications between an IC_USB1.0 compliant downstream port with a first voltage class V1 and an IC_USB1.0 compliant peripheral with a second voltage class VCC. The range of the supplies, respectively Host and Device, are: HVCC (1.55V - 3.6V) and PVCC (1.55V - 3.6V) 9.4.2.4 Bridge with LDOs: Two cases are supported: one for PC with embedded Digital Base Band and one for Token. • PC with embedded Digital Base Band The AT73C260 provides up to 70mA from VBUS to the UICC under the VCC required by the DBB. Also the AT73C260 converts D+ and D- signals into analog signals IC_DP and IC_DM as per IC_USB1.0. • Token The AT73C260 provides up to 70mA from VBUS to the UICC under VCC. This voltage is generated by PVCC LDO and set by an external resistor bridge supplied by 3.3V voltage reference (HVCC). Also the AT73C260 converts D+ and D- signals into analog signals IC_DP and IC_DM as per IC_USB1.0. 19 11030A–PMAAC–13-Sep-10 9.4.3 Downstream Port PHY In mobile applications, the USB UICC is handled by the user and special care should be taken in the ESD protection on the downstream port facing the USB UICC. The AT73C260 downstream port is protected against 4kV ESD. Also, the host and the USB UICC may not be located on the same board with a flex connecting the two PCBs. The AT73C260 should be located next to the host. The flex is between the AT73C260’s downstream port and the USB UICC upstream port. The AT73C260 downstream port has slew rate control on both PDM and PDP to minimize the radiated EMI. Pins VBUS and PVRF are connected to GND and LDO outputs are isolated and in standby. 9.4.3.1 Mode: Digital six wires unidirectional DAT_SE0 to IC_USB1.0: PHY_6_SE0 Description This application allows a Host, ASIC or FPGA, with the digital unidirectional Philips PDIUSBP11A (MODE pin = 0) six wires interface to drive an IC_USB downstream port. Figure 9-8. PHY_6_SE0 Block Diagram ASIC FPGA 6 IC_USB_1.0 AT73C260 DAT_SEO Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-3. Mode M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 PHY_6_SE0 0 0 0 Table 9-4. Pin Number 20 AT73C260 Hardware Configuration Application Digital six wires unidirectional DAT_SE0 to IC_USB1.0 AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function 1 HVCC A-Power -- Supply by ASIC FPGA I/O Ring (1.55V to 3.6V) 2 TX_DAT D-Input -- Unidirectional Transmit Data 3 TX_SEO D-Input -- Unidirectional Transmit Single Ended 0 4 VBUS A-Input -- Not Used and Connected to Ground 6 RX_DM D-Output -- Unidirectional Receiving DM 7 RX_DP D-Output -- Unidirectional Receiving DP 8 TX_ENABLE_N D-Input Low 9 PVRF A-Input -- Connected to Ground 10 PDM D-I/O -- Downstream Port for USB Device Tx Enable N AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 Table 9-4. Pin Number AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function D-I/O -- Downstream Port for USB Device 11 PDP 12 PVCC A-Power -- Same as peripheral’s power (1.8V or 3V typical) 13 RX_RCV D-Output -- Unidirectional Receiving RCV M<2:0> D-Inputs Low 14, 15, 16 Connected to Ground Application Diagram In the following figure, the hardware configuration is described. Figure 9-9. AT73C260: PHY - 6 wires DAT_SE0 to IC_USB1.0 - application diagram 9 PVRF AT73C260 1 12 HVCC PVCC C4 HVCC PVCC GND VBUS rx_dm rx_dp tx_enable_n tx_dat tx_se0 rx_rcv rx_dm 6 rx_dp 7 tx_enable_n 8 tx_dat 2 tx_se0 3 RCV VCC 10 HDMO PDM IC_DM USB UICC rx_rcv 13 HDPO OE_N 11 HDP ISO/IEC 7816-3 DIGITAL WRAPPER UTMI Vref 3.3Volt 4 ASIC/FPGA : 6 WIRES DAT_SE0 C5 IC_DP PDP HDM M<2> M<1> M<0> GND 14 Note: 15 16 5 All external components are defined in component list Table 8-1 on page 10 21 11030A–PMAAC–13-Sep-10 9.4.3.2 Mode: Digital four wires bidirectional DAT_SE0 to IC_USB1.0: PHY_4_SE0 Description This application allows a Host, ASIC or FPGA, with the digital bidirectional UTMIfs, DAT_SE0, four wires interface to drive an IC_USB downstream port. Figure 9-10. PHY_4_SE0 Block Diagram ASIC FPGA 4 DAT_SEO AT73C260 IC_USB_1.0 Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-5. Mode M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 Application PHY_4_SE0 0 0 HVCC Digital four wires bidirectional DAT_SE0 to IC_USB1.0 Table 9-6. Pin Number AT73C260 Pin description and configuration Pin Name I/O Type Polarity 1 HVCC A-Power -- Supply by ASIC FPGA I/O Ring (1.55V to 3.6V) 2 TX_DAT/RX_DP D-I/O -- Bidirectional Rx_Dp/Tx_Data 3 TX_SE0/RX_DM D-I/O -- Bidirectional Rx_DM/Tx_Single Ended 0 4 VBUS A-Input -- Not Used and Connected to Ground 6 HDMO D-Output HiZ Not Connected 7 HDPO D-Output HiZ Not Connected 8 TX_ENABLE_N D-Input Low Tx Enable N 9 PVRF A-Input -- Connected to Ground 10 PDM D-I/O -- Downstream Port for USB Device 11 PDP D-I/O -- Downstream Port for USB Device 12 PVCC A-Power -- Same as peripheral’s power (1.8V or 3V typical) 13 RX_RCV D-Output -- Unidirectional Receiving RCV M<2:1> D-Inputs Low Connected to Ground M<0> D-Input High Connected to HVCC 14, 15 16 22 AT73C260 Hardware Configuration Function AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 Application Diagram In the following figure, the hardware configuration is described. Figure 9-11. AT73C260: PHY - 4 wires DAT_SE0 to IC_USB1.0 - application diagram 9 PVRF AT73C260 1 12 HVCC GND PVCC C4 PVCC VBUS rx_rcv 13 RCV VCC rx_dm 6 nc HDMO rx_dp 7 nc HDPO tx_enable_n tx_enable_n 8 10 11 HDP tx_se0/rx_dm 3 tx_se0 ISO/IEC 7816-3 IC_DM OE_N tx_dat/rx_dp 2 tx_dat PDM USB UICC DIGITAL WRAPPER rx_rcv C5 Vref 3.3Volt 4 ASIC/FPGA : 4 WIRES DAT_SE0 UTMI HVCC IC_DP PDP HDM M<2> M<1> M<0> GND 14 15 16 5 HVCC Note: All external components are defined in component list Table 8-1 on page 10 23 11030A–PMAAC–13-Sep-10 9.4.3.3 Mode: Digital six wires unidirectional DP_DM to IC_USB1.0: PHY_6_DPDM Description This application allows a Host, ASIC or FPGA, with the digital unidirectional Philips PDIUSBP11A (MODE pin = 1) six wires interface to drive an IC_USB downstream port. Figure 9-12. PHY_6_DPDM Block Diagram ASIC FPGA 6 DP_DM AT73C260 IC_USB_1.0 Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-7. Mode M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 PHY_6_DPDM 0 HVCC 0 Table 9-8. Pin Number 24 AT73C260 Hardware Configuration Application Digital six wires unidirectional DP_DM to IC_USB1.0 AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function 1 HVCC A-Power -- Supply by ASIC FPGA I/O Ring (1.55V to 3.6V) 2 TX_DP D-Input -- Unidirectional Tx DP 3 TX_DM D-Input -- Unidirectional Tx DM 4 VBUS A-Input -- Not Used and Connected to Ground 6 RX_DM D-Output -- Unidirectional Rx DM 7 RX_DP D-Output -- Unidirectional Rx DP 8 TX_ENABLE_N D-Input Low 9 PVRF A-Input -- Connected to Ground 10 PDM D-I/O -- Downstream Port for USB Device 11 PDP D-I/O -- Downstream Port for USB Device 12 PVCC A-Power -- Same as peripheral’s power (1.8V or 3V typical) 13 RX_RCV D-Output -- Unidirectional Receiving RCV 14 M<2> D-Input Low Connected to Ground 15 M<1> D-Input High Connected to HVCC 16 M<0> D-Input Low Connected to Ground Tx Enable N AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 Application Diagram In the following figure, the hardware configuration is described. Figure 9-13. AT73C260: PHY - 6 wires DP_ DM to IC_USB1.0 - application diagram 9 PVRF AT73C260 1 HVCC C4 12 PVCC HVCC PVCC GND VBUS rx_dm rx_dp tx_enable_n tx_dat tx_se0 rx_rcv 13 rx_dm 6 rx_dp 7 tx_enable_n 8 tx_dp 2 tx_dm 3 VCC RCV 10 PDM HDMO IC_DM USB UICC rx_rcv HDPO OE_N 11 ISO/IEC 7816-3 DIGITAL WRAPPER UTMI Vref 3.3Volt 4 ASIC/FPGA : 6 WIRES DP_DM C5 IC_DP PDP HDP HDM M<2> M<1> M<0> GND 14 15 16 5 HVCC Note: All external components are defined in component list Table 8-1 on page 10 25 11030A–PMAAC–13-Sep-10 9.4.3.4 Mode: Digital four wires bidirectional DP_DM to IC_USB1.0: PHY_4_DPDM Description This application allows a Host, ASIC or FPGA, with the digital bidirectional UTMIfs, DP_DM, four wires interface to drive an IC_USB downstream port. Figure 9-14. PHY_4_DPDM Block Diagram ASIC FPGA 4 IC_USB_1.0 AT73C260 DP_DM Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-9. Mode M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 Application PHY_4_DPDM 0 HVCC HVCC Digital four wires bidirectional DP_DM to IC_USB1.0 Table 9-10. Pin Number AT73C260 Pin description and configuration Pin Name I/O Type Polarity 1 HVCC A-Power -- Supply by ASIC FPGA I/O Ring (1.55V to 3.6V) 2 TX_DP/RX_DP D-I/O -- Bidirectional Tx_Dp/Dx_DP 3 TX_DM/RX_DM D-I/O -- Bidirectional Tx_Dm/Dx_DM 4 VBUS A-Input -- Not Used and Connected to Ground 6 HDMO D-Output HiZ Not Connected 7 HDPO D-Output HiZ Not Connected 8 TX_ENABLE_N D-Input Low Tx Enable N 9 PVRF A-Input -- Connected to Ground 10 PDM D-I/O -- Downstream Port for USB Device 11 PDP D-I/O -- Downstream Port for USB Device 12 PVCC A-Power -- Same as peripheral’s power (1.8V or 3V typical) 13 RX_RCV D-Output -- Unidirectional Receiving RCV 14 M<2> D-Input Low Connected to Ground M<1:0> D-Inputs High Connected to HVCC 15,16 26 AT73C260 Hardware Configuration Function AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 Application Diagram In the following figure, the hardware configuration is described. Figure 9-15. AT73C260: PHY - 4 wires DP_ DM to IC_USB1.0 - application diagram 9 PVRF AT73C260 C4 1 12 HVCC PVCC HVCC PVCC GND VBUS RCV VCC rx_dm 6 nc HDMO rx_dp 7 nc HDPO tx_enable_n tx_enable_n 8 tx_dp/rx_dp 2 tx_dat tx_dm/rx_dm 3 tx_se0 10 PDM IC_DM OE_N 11 HDP ISO/IEC 7816-3 rx_rcv 13 rx_rcv USB UICC DIGITAL WRAPPER UTMI Vref 3.3Volt 4 ASIC/FPGA : 4 WIRES DP_DM C5 IC_DP PDP HDM M<2> M<1> M<0> GND 14 15 16 5 HVCC Note: All external components are defined in component list Table 8-1 on page 10 27 11030A–PMAAC–13-Sep-10 9.4.3.5 Mode: Digital three wires bidirectional (DAT, SE0, OE_N) to IC_USB1.0: PHY_3_ULPI Description This application allows a Host, ASIC or FPGA, with the digital bidirectional ULPI serial support, DAT, SE0, and OE_N, three wires interface to drive an IC_USB downstream port. Figure 9-16. PHY_3_ULPI Block Diagram 3 ASIC FPGA AT73C260 IC_USB_1.0 ULPI Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-11. Mode M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 Application PHY_3_ULPI HVCC 0 HVCC Digital three wires bidirectional DAT, SE0, OE_N to IC_USB1.0 Table 9-12. Pin Number 28 AT73C260 Hardware Configuration AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function 1 HVCC A-Power -- Supply by ASIC FPGA I/O Ring (1.55V to 3.6V) 2 RX_RCV/TX_DAT D-I/O -- Bidirectional Rx_RCV / Tx_Data 3 RX_SE0/TX_SE0 D-I/O -- Bidirectional Rx_SE0/Tx_SE0 4 VBUS A-Input -- Not Used and Connected to Ground 6 HDMO D-Output HiZ Not Connected 7 HDPO D-Output HiZ Not Connected 8 TX_ENABLE_N D-Input Low Tx Enable N 9 PVRF A-Input -- Connected to Ground 10 PDM D-I/O -- Downstream Port for USB Device 11 PDP D-I/O -- Downstream Port for USB Device 12 PVCC A-Power -- Same as peripheral’s power (1.8V or 3V typical) 13 RCV D-Output HiZ Not Connected 14 M<2> D-Input High Connected to HVCC 15 M<1> D-Inputs Low Connected to Ground 16 M<0> D-Inputs High Connected to HVCC AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 Application Diagram In the following figure, the hardware configuration is described. Figure 9-17. AT73C260: PHY - 3 wires DAT, SE0, OE_N to IC_USB1.0 - application diagram 9 PVRF AT73C260 1 HVCC C4 12 PVCC HVCC PVCC GND Vref 3.3Volt 4 ASIC/FPGA : 3 WIRES DAT, SE0, OE_N C5 VBUS DIGITAL WRAPPER 13 RCV VCC rx_dm 6 nc HDMO rx_dp 7 nc HDPO tx_enable_n tx_enable_n 8 rx_rcv/tx_dat 2 tx_dat rx_se0/tx_se0 3 tx_se0 10 PDM IC_DM OE_N 11 HDP ISO/IEC 7816-3 nc USB UICC UTMI rx_rcv IC_DP PDP HDM M<2> M<1> M<0> GND 14 15 16 5 HVCC Note: All external components are defined in component list Table 8-1 on page 10 29 11030A–PMAAC–13-Sep-10 9.4.4 Bridge Pins VBUS and PVRF are connected to GND and LDO outputs are isolated and in standby. Pin OE_N is connected to HVCC. The following applications enable communications between. • S7_ICC: an USB2.0 section 7 compliant downstream port and an IC_USB1.0 compliant peripheral • ICC_S7: an IC_USB1.0 compliant downstream port and an USB2.0 section 7 compliant peripheral 9.4.4.1 Mode: USB2.0 section 7 downstream port to IC_USB1.0 peripheral: S7_ICC Description This application establishes a communication path between an USB2.0 section 7 downstream port and an IC_USB peripheral. An external 3.3V voltage source is applied on HVCC. AT73C260’s D+ and D- input pins are compliant with USB2.0 core specification. This application is particularly well suited for mobile devices where the host may not have an IC_USB1.0 downstream port. Figure 9-18. S7_ICC Block Diagram USB 2.0 AT73C260 Section 7 IC_USB_1.0 Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-13. Mode M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 S7_ICC HVCC HVCC 0 Table 9-14. Pin Number 30 AT73C260 Hardware Configuration Application USB2.0 section 7 downstream port to IC_USB1.0 peripheral AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function 1 HVCC A-Power -- Supplied by host at 3.3V 2 D+ D-I/O -- Bidirectional D+ 3 D- D-I/O -- Bidirectional D- 4 VBUS A-Input -- Not Used and Connected to Ground 6 HDMO D-Output HiZ Not Connected 7 HDPO D-Output HiZ Not Connected 8 OE_N D-Input High Connected to HVCC AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 Table 9-14. AT73C260 Pin description and configuration Pin Number Pin Name I/O Type Polarity Function 9 PVRF A-Input -- Connected to Ground 10 PDM D-I/O -- Downstream Port for USB Device 11 PDP D-I/O -- Downstream Port for USB Device 12 PVCC A-Power -- Same as peripheral’s power (1.8V or 3V typical) 13 RCV D-Output HiZ Not Connected 14 M<2> D-Input High Connected to HVCC 15 M<1> D-Inputs High Connected to HVCC 16 M<0> D-Inputs Low Connected to Ground Application Diagram In the following figure, the hardware configuration is described. Figure 9-19. AT73C260: Bridge - USB2.0 section 7 downstream port to IC_USB1.0 -application diagram 9 PVRF AT73C260 1 12 HVCC C4 GND HVCC PVCC C5 PVCC Vref 3.3Volt 4 VBUS 13 RCV VCC 6 nc HDMO 7 nc HDPO 10 PDM 8 HVCC OE_N 2 D+ 11 HDP ISO/IEC 7816-3 IC_DM USB UICC nc IC_DP PDP 3 D- HDM M<2> M<1> M<0> GND 14 15 16 5 HVCC Note: All external components are defined in component list Table 8-1 on page 10 31 11030A–PMAAC–13-Sep-10 9.4.4.2 Mode: IC_USB1.0 downstream port to USB2.0 section 7 peripheral: ICC_S7 Description This application establishes a communication path between an IC_USB1.0 downstream port and an USB2.0 section 7 peripheral. Figure 9-20. ICC_S7 Block Diagram µC/ASIC IC_USB_1.0 AT73C260 USB 2.0 Section 7 Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-15. Mode M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 Application ICC_S7 HVCC HVCC HVCC IC_USB1.0 downstream port to USB2.0 section 7 peripheral Table 9-16. Pin Number 32 AT73C260 Hardware Configuration AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function 1 HVCC A-Power -- Same as host I/O Ring Power (1.8V to 3V typical) 2 IC_DP D-I/O -- Bidirectional IC_DP 3 IC_DM D-I/O -- Bidirectional IC_DM 4 VBUS A-Input -- Not Used and Connected to Ground 6 HDMO D-Output HiZ Not Connected 7 HDPO D-Output HiZ Not Connected 8 OE_N D-Input High Connected to HVCC 9 PVRF A-Input -- Connected to Ground 10 D- D-I/O -- Downstream Port for USB Device 11 D+ D-I/O -- Downstream Port for USB Device 12 PVCC A-Power -- Supplied at 3.3V 13 RCV D-Output HiZ Not Connected 14 M<2> D-Input High Connected to HVCC 15 M<1> D-Inputs High Connected to HVCC 16 M<0> D-Inputs High Connected to HVCC AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 Application Diagram In the following figure, the hardware configuration is described. Figure 9-21. AT73C260: Bridge - IC_USB1.0 downstream port to USB2.0 section 7 - application diagram 9 PVRF HVCC AT73C260 1 12 PVCC C4 HVCC C5 PVCC GND Vref 3.3Volt 4 VBUS 13 nc 6 nc RCV 10 D- PDM HDMO R6 7 nc HVCC IC_DP HDPO 8 OE_N 11 2 D+ PDP HDP R7 IC_DM 3 HDM M<2> M<1> M<0> GND 14 15 16 5 HVCC Note: R6 and R7 are defined in component list Table 8-1 on page 10 33 11030A–PMAAC–13-Sep-10 9.4.5 Mode: Voltage Class Converter: VCC Description Pins VBUS and PVRF are connected to GND and LDO outputs are isolated and in standby. Pin OE_N is connected to HVCC. The following applications enable communications between an IC_USB1.0 compliant downstream port with a first voltage class HVCC and an IC_USB1.0 compliant peripheral with a second voltage class PVCC. Figure 9-22. Voltage Class Converter Block Diagram ASIC IC_USB_1.0 IC_USB_1.0 AT73C260 Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-17. Mode M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 Application VCC HVCC HVCC HVCC IC_USB1.0 to IC_USB1.0 Voltage Class Converter Table 9-18. Pin Number 34 AT73C260 Hardware Configuration AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function 1 HVCC A-Power -- Same as host I/O Ring Power (1.8V to 3V typical) 2 IC_DP D-I/O -- Bidirectional IC_DP 3 IC_DM D-I/O -- Bidirectional IC_DM 4 VBUS A-Input -- Connected to Ground 6 HDMO D-Output HiZ Not Connected 7 HDPO D-Output HiZ Not Connected 8 OE_N D-Input High Connected to HVCC 9 PVRF A-Input -- Connected to Ground 10 PDM D-I/O -- Downstream Port for USB Device 11 PDP D-I/O -- Downstream Port for USB Device 12 PVCC A-Power -- Same as peripheral’s power (1.8V or 3V typical) 13 RCV D-Output HiZ Not Connected 14 M<2> D-Input High Connected to HVCC 15 M<1> D-Inputs High Connected to HVCC 16 M<0> D-Inputs High Connected to HVCC AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 Application Diagram In the following figure, the hardware configuration is described. Figure 9-23. AT73C260: Voltage Class Converter - IC_USB1.0 to IC_USB1.0 - application diagram 9 PVRF AT73C260 1 12 HVCC PVCC C4 HVCC PVCC GND C5 Vref 3.3Volt 4 VBUS 13 VCC RCV 10 HDMO 7 nc HDPO PDM IC_DM 8 HVCC OE_N 11 2 IC_DP ISO/IEC 7816-3 6 nc USB UICC nc IC_DP PDP HDP 3 IC_DM HDM M<2> M<1> M<0> GND 14 15 16 5 HVCC Note: All external components are defined in component list Table 8-1 on page 10 35 11030A–PMAAC–13-Sep-10 9.4.6 Bridge With LDOs LDOs are enabled. AT73C260’s pin VBUS is connected to the USB signal VBUS through a low pass filter. 9.4.6.1 Mode: PC’s USB2.0 section 7 to IC_USB1.0 with VCC driven by the DBB: S7_ICC_DBB Description The PC’s Digital Base Band may not provide enough power to a USB UICC with mass storage. The VBUS power supply voltage will make available that extra power, up to 70mA, through the AT73C260’s LDO if needed by the USB UICC. The PC’s Digital Base Band supplies on pin 9 the power sequence required by ETSI. The AT73C260 buffers the signal on PVRF to PVCC. PVCC sources power from VBUS to VCC. On the Host side HVCC generates 3.3V from VBUS. Figure 9-24. S7_ICC_DBB Block Diagram ISO7816 DBB VBUS Phone µC/ASIC PVRF USB 2.0 AT73C260 PVCC IC_USB_1.0 Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-19. Mode M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 S7_ICC_DBB HVCC HVCC 0 Table 9-20. Pin Number 36 AT73C260 Hardware Configuration Application PC’s USB2.0 section 7 to IC_USB1.0 with VCC driven by DBB AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function 1 HVCC A-Output -- Delivered by AT73C260 from VBUS at 3.3V 2 D+ D-I/O -- Bidirectional D + 3 D- D-I/O -- Bidirectional D - 4 VBUS A-Input -- Supplied by USB Power Line 6 HDMO D-Output HiZ Not Connected 7 HDPO D-Output HiZ Not Connected 8 OE_N D-Input High Connected to HVCC 9 PVRF A-Input -- Control by Digital Base Band AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 Table 9-20. AT73C260 Pin description and configuration Pin Number Pin Name I/O Type Polarity Function 10 PDM D-I/O -- Downstream Port for USB Device 11 PDP D-I/O -- Downstream Port for USB Device 12 PVCC A-Output -- Delivered by AT73C260 from VBUS and control by DBB 13 RCV D-Output HiZ Not Connected 14 M<2> D-Input High Connected to HVCC 15 M<1> D-Inputs High Connected to HVCC 16 M<0> D-Inputs Low Connected to Ground Application Diagram In the following figure, the hardware configuration is described. Figure 9-25. AT73C260: Bridge with LDO - USB2.0 section 7 to IC_USB1.0 with VCC driven by DBB - application diagram RST Digital Base Band CLK I/O 9 PVRF AT73C260 1 12 HVCC C4 HVCC PVCC GND R3 C5 Vref 3.3Volt 4 VBUS VBUS C3 13 VCC RCV 10 HDMO 7 nc HDPO PDM IC_DM 8 HVCC OE_N R1 2 D+ 11 ISO/IEC 7816-3 6 nc USB UICC nc IC_DP PDP HDP C1 3 DR2 HDM C2 M<2> M<1> M<0> GND 14 15 16 5 HVCC Notes: 1. PVCC LDO regulator is compliant with SIM FTA 27.17.2.1 Tests Series. 2. All external components are defined in component list Table 8-1 on page 10 37 11030A–PMAAC–13-Sep-10 9.4.6.2 Mode: USB2.0 section 7 to IC_USB1.0 with PVCC fixed by PVRF: S7_ICC_TK Description This is a token application where an USB UICC is connected to an USB2.0 section 7 downstream port. The AT73C260’s LDOs supply HVCC set at 3.3V and P VCC set at the power supply voltage required by the USB UICC. This application establishes a communication path between a USB2.0 section 7 downstream port and the USB UICC’s. The power to the USB UICC is provided by VBUS using an LDO able to source up to 70mA. This is the typical electrical schematic for a USB UICC used in a USB Token to be connected to a USB2.0 series A receptacle. The voltage divider R4/R5 generates for example 3.0V buffered by the LDO to the downstream side of the transceiver and to the USB UICC PVCC. This set up allows passing USB CV tests to the USB UICC under tests. HVCC=3.3V Figure 9-26. S7_ICC_TK Block Diagram (Token Application) VBUS USB 2.0 PVRF PVCC AT73C260 IC_USB_1.0 Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-21. Mode M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 S7_ICC_TK HVCC HVCC 0 Table 9-22. Pin Number 38 AT73C260 Hardware Configuration Application USB2.0 section 7 to IC_USB1.0 with PVCC fixed by PVRF AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function 1 HVCC A-Output -- Delivered by AT73C260 from VBUS at 3.3V 2 D+ D-I/O -- Bidirectional D + 3 D- D-I/O -- Bidirectional D - 4 VBUS A-Input -- Supplied by USB Power Line 6 HDMO D-Output HiZ Not Connected 7 HDPO D-Output HiZ Not Connected AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 Table 9-22. AT73C260 Pin description and configuration Pin Number Pin Name I/O Type Polarity Function 8 OE_N D-Input High 9 PVRF A-Input -- Fixed by external resistor bridge divider 10 PDM D-I/O -- Downstream Port for USB Device 11 PDP D-I/O -- Downstream Port for USB Device 12 PVCC A-Output -- Delivered by AT73C260 from VBUS according external resistor ratio 13 RCV D-Output HiZ Not Connected 14 M<2> D-Input High Connected to HVCC 15 M<1> D-Inputs High Connected to HVCC 16 M<0> D-Inputs Low Connected to Ground Connected to HVCC Application Diagram In the following figure, the hardware configuration is described. Figure 9-27. AT73C260: Bridge with LDO - USB2.0 section 7 to IC_USB1.0 with VCC fixed by PVRF - application diagram PVRF = PVCC = HVCC * R5/(R5+R4) R4 R5 9 PVRF AT73C260 1 12 HVCC HVCC C4 PVCC GND R3 C5 Vref 3.3Volt 4 VBUS VBUS C3 13 VCC RCV 10 HDMO 7 nc HDPO PDM IC_DM From Host USB2.0 section 7 with cable 8 HVCC OE_N R1 D+ 2 11 ISO/IEC 7816-3 6 nc USB UICC nc IC_DP PDP HDP C1 3 D- HDM C2 R2 M<2> M<1> M<0> GND 14 15 16 5 HVCC Notes: 1. PVCC LDO regulator is compliant with SIM FTA 27.17.2.1 Tests Series. 2. All external components are defined in component list Table 8-1 on page 10 39 11030A–PMAAC–13-Sep-10 3. External resistors shall be in the following range: 100KΩ < R4 + R5 < 330KΩ in order to minimize current consumption and to reach a good accuracy on PVCC. The bias current of PVRF follower is less than +/-100nA. 40 AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 9.4.7 Example of an Extra Function For an FPGA implementation of a USB device, there is a need for an upstream IC_USB 1.0 PHY. For this requirement the AT73C260 product can be configured as described below. Pins VBUS and PVRF are connected to GND and LDO outputs are isolated and in standby. 9.4.7.1 Mode: Digital six wires unidirectional DAT_SE0 to IC_USB1.0 upstream: Extra Function Description This application allows a peripheral based on an ASIC or an FPGA with the digital unidirectional six wires interface to be connected to an IC_USB 1.0 downstream port. Here below, an example is shown. Other digital interfaces are compatible with this upstream IC_USB 1.0 port. Figure 9-28. PHY_6_SE0 Block Diagram pull-up Control HOST 6 AT73C260 IC_USB_1.0 ASIC FPGA DAT_SEO Hardware Configuration In the following tables, the pin and the hardware configuration are described. Table 9-23. Mode Extra Mode (as an example) Table 9-24. Pin Number AT73C260 Hardware Configuration M<2> Pin 14 M<1> Pin 15 M<0> Pin 16 0 0 0 Application Digital six wires unidirectional DAT_SE0 to IC_USB1.0 upstream AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function 1 HVCC A-Power -- Same as peripheral I/O ring (1.55V to 3.6V typical) 2 TX_DAT D-Input -- Unidirectional Transmit Data 3 TX_SEO D-Input -- Unidirectional Transmit Single Ended 0 4 VBUS A-Input -- Not Used and Connected to Ground 6 RX_DM D-Output -- Unidirectional Receiving DM 7 RX_DP D-Output -- Unidirectional Receiving DP 8 TX_ENABLE_N D-Input Low Tx Enable N 41 11030A–PMAAC–13-Sep-10 Table 9-24. Pin Number AT73C260 Pin description and configuration Pin Name I/O Type Polarity Function 9 PVRF A-Input -- Connected to Ground 10 PDM D-I/O -- Downstream Port for USB Device 11 PDP D-I/O -- Downstream Port for USB Device 12 PVCC A-Power -- Same power as host VCC (1.8 or 3V typical) 13 RX_RCV D-Output -- Unidirectional Receiving RCV M<2:0> D-Inputs Low 14, 15, 16 Connected to Ground Application Diagram In the following figure, the hardware configuration is described. Figure 9-29. AT73C260: Extra Mode - PHY of a 6-wire FPGA peripheral implementation - application diagram 9 PVRF AT73C260 1 HVCC C4 12 HVCC PVCC GND 4 ASIC/FPGA : Peripheral 6 WIRES DAT_SE0 rx_dm UTMI rx_dp tx_enable_n tx_dat tx_se0 PVCC VBUS DIGITAL WRAPPER rx_rcv C5 Vref 3.3Volt rx_rcv 13 rx_dm 6 rx_dp 7 VCC RCV 10 PDM HDMO IC_DM PVCC HDPO tx_enable_n 8 tx_dp 2 tx_dm 3 HOST REXT OE_N 11 HDM M<2> M<1> M<0> GND 14 Pull-Up Control IC_DP PDP HDP 15 16 Pull-Up Control 5 HVCC Notes: 1. All external components are defined in component list Table 8-1 on page 10 2. In Upstream port configuration, the software must drive the REXT pull-up resistor. 42 AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 10. Package Information Figure 10-1. Mechanical Package Drawing for 16-lead Quad Flat No Lead Package Note: All the dimensions are in mm 43 11030A–PMAAC–13-Sep-10 11. Ordering Information Table 11-1. 44 Ordering Information Ordering Code Package Package Type Temperature Operating Range AT73C260 QFN16 3 x 3 mm Green -40°C to +85°C AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 12. Revision History Doc. Rev Date Comments 11030A 13-Sep-10 First revision Change Request Ref. 45 11030A–PMAAC–13-Sep-10 46 AT73C260 11030A–PMAAC–13-Sep-10 AT73C260 1 Block Diagram .......................................................................................... 2 2 Package and Pinout ................................................................................. 3 3 Pin Description ......................................................................................... 4 4 Absolute Maximum Ratings .................................................................... 5 5 Recommended Operating Conditions .................................................... 5 6 Power Dissipation Ratings ...................................................................... 5 7 Electrical Characteristics ........................................................................ 6 7.1I/Os DC Characteristics Referred to HVCC ...............................................................6 7.2I/Os DC Characteristics Referred to PVCC ...............................................................6 7.3Timing Characteristics Table .....................................................................................7 7.4VBUS Supply Characteristics ....................................................................................7 7.5HVCC and PVCC Supplies Characteristics ...............................................................8 8 Components List. ................................................................................... 10 9 Functional Description .......................................................................... 11 9.1AT73C260’s Upstream and Downstream Ports .......................................................11 9.2AT73C260 Pull Up and Pull Down Resistors ...........................................................12 9.3Theory Of Operation ................................................................................................13 9.4General Description .................................................................................................18 10 Package Information .............................................................................. 43 11 Ordering Information ............................................................................. 44 12 Revision History ..................................................................................... 45 i 11030A–PMAAC–13-Sep-10 ii AT73C260 11030A–PMAAC–13-Sep-10 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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