36 V, 1 A SPI Controlled Power Supply with

Adam Rozenberg, Daniel Kimmitt, Bill Eisenhower
TI Designs – Precision: Verified Design
36 V, 1 A SPI Controlled Power Supply with Integrated
Current Shunt
TI Designs – Precision
Circuit Description
TI Designs – Precision are analog solutions created
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are also discussed.
Simple power supplies are often required when
constructing test hardware. This version offers 16-bits
of programmable accuracy using a Serial Peripheral
Interface protocol while providing a maximum voltage
of 36 V with a maximum current load of 1 A. This
supply can also interface with a simple SAR or Δ-Ʃ
analog to digital converter (ADC) for continuous
output current monitoring.
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INA146
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OPA2277
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R3
36kΩ
SW1
R2
R6
36kΩ
1kΩ
R1
DACOUT
OPA140
10kΩ
LF411
100Ω
C1
1000pF
100kΩ
SW2
Force Out
OPA549
1000pF
R7
R8
R9
100Ω
100Ω
R10
R11
1Ω
1Ω
SW3
INA146
DAC8871
C2
R4
Sense Out
Current Out
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and
other important disclaimers and information.
TINA-TI is a trademark of Texas Instruments
WEBENCH is a registered trademark of Texas Instruments
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36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
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1
Design Summary
The design requirements are as follows:

Supply voltage for amplifying and power stages of 43 V dc. The negative supply requires -3 V dc and
the positive supply requires 40 V dc

Supply Current Limit of 1A @ 40 V

Supply voltage for other components: -15 V to 15 V dc

Input: Two 3-wire Serial-Peripheral Interfaces (SPIs) for DAC and Relay configuration control

Current Monitor Output: Scaled to ±1 V to easily fit inside a typical precision analog-to-digital (ADC)
range
The design goals and performance are summarized in Table 1. Figure 1 depicts the measured transfer
function of the design.
Table 1. Comparison of Design Goals, Simulation, and Measured Performance
VOUT Gain Error
(%FSR)
INA146 Gain
(V/V)
Current Shunt (Ω)
Goal
Simulated
Measured
1 or 100
1 or 100
0.1%
-0.006716
-0.079
1
100
1
100
50
50
50
50
-0.016680
-1.088813
-0.013118
-1.088727
2.92
2.61
2.45
N/A
1 or 100
50
4.2205615
8.2301825
1
100
1
100
1
1
1
1
-1.998930
-2.007920
-1.988344
-1.997240
1.001730
-0.030363
1.003658
-0.141955
1
100
1
100
70
70
70
70
68.999155
69.008537
69.091690
69.101018
92.278229
89.456711
92.317234
89.538604
1
VOUT Load
Regulation
(µV/mA)
100
VOUT Offset (mV)
1 or 100
1
INA Gain Error
(%FSR)
100
1
INA CMRR (dB)
100
40
35
VOUT (V)
30
y = -3.5971x + 0.0124
25
20
15
10
5
0
-10
-8
-6
-4
-2
0
DAC Voltage (V)
Figure 1: Measured Transfer Function
2
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
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2
Theory of Operation
A schematic for the circuit is shown in Figure 2.
R3
36kΩ
SW1
R2
R6
36kΩ
1kΩ
R1
DAC8871
DACOUT
OPA140
C2
R4
10kΩ
LF411
100Ω
C1
1000pF
Sense Out
R7
100kΩ
Force Out
OPA549
1000pF
SW2
R8
R9
100Ω
100Ω
R10
R11
1Ω
1Ω
INA146
SW3
Current Out
Figure 2: Simplified Schematic
2.1
DAC Reference Buffer Design
A DAC8871 (U3) is used to provide the control voltage for the power supply. Using a SPI bus the user
communicates to the DAC to program the new voltage at the DAC output. This voltage is amplified in later
stages to the desired levels. The range of voltage the DAC can output is determined by the voltages at its
reference pins. For example, if the VREFH pin is connected to 10 V and the VREFL pin was connected to 0 V
the DAC would have a range of 0 to 10 V. The design contains an on board voltage reference that sets
VREFH to 10 V and VREFL to -10 V shown in Figure 3. There is also a secondary option for the user to
choose external reference voltages via the J13 and J14 jumpers.
U3 VREFH Sense
C3
1 nF
U3 VREFH Force
REF102
U9
REFOUT
OPA2277 U8A
U3 VREFL Sense
R18
R17
1 kΩ
C4
U3 VREFL Force
1 kΩ
OPA2277 U7A
1 nF
OPA2277 U8B
OPA2277 U7B
Figure 3: DAC Voltage Reference
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To create the DAC references first we need a stable voltage source. The REF102 (U9) produces a stable
voltage of 10 V. All that is missing is a -10 V reference. To create the low voltage reference (VREFL) the
REF102 10 V output is inverted using an op amp (U7B) with an inverting configuration of -1 and then
buffered (U8B) to prevent interaction between the DAC8871 R-2R ladder and the OPA2277 feedback
network. The buffer U7A between the inverting amplifier and U9 prevents R17 from loading the output of U9
and causing the voltage to drop.
2.2
DAC Output Buffer Design
The DAC8871 architecture is a R-2R back-DAC. A consequence of the back-DAC architecture is that the
DAC output impedance (ZO) is always approximately 6.25 kΩ. This is listed in the product datasheet
specification table. Any load the DAC drives must take this constant large ZO into account as it will be a
large source of error in any design. By buffering the DAC output with an OPA140 (U10) we significantly limit
the contribution of ZO to the overall error in the design. Without the buffer the DAC output voltage would be
divided between the ZO and R1, preventing the DAC from reaching its full output range. The OPA140 is a
JFET input op amp has a maximum 10 pA bias current at room temperature. Its contribution to the error is
And far below the threshold of the DAC’s least significant bit (LSB)
2.3 Buffer and Power Amplifier Design
The output of the DAC8871 needs to be amplified to achieve the desired voltage range of 0 – 36 V. The
LF411A (U2) is chosen for its high voltage power rail compliance that is necessary to achieve the 36V
output with a 40 V supply. The DAC output range spans ±10 V so U2 is configured in a gain of -3.6 V/V to
meet the specification. This configuration gives a possible ±36 V of span at the output of U 2. Our initial
design only calls for a 0 – 36 V span. This is compensated by losing 1-bit of precision in the DAC range,
effectively rendering our DAC as a 15-bit DAC and not a 16-bit DAC. It will be seen in the Modifications
section that we can recover this resolution with a minor change to the DAC voltage reference.
The LF411A inverting configuration was chosen to keep the input common mode fixed at ground (GND)
and reduce the common mode error in the design. However, the negative gain means the DAC must be
configured to output a negative voltage.
VOUT  
RFEEDBACK
VIN
RIN
(1)
R2 (or R2||R3 for bipolar operation) is the feedback resistor, R1 is the input resistor, and the buffered DAC
voltage from the OPA140 is VIN.
The OPA549 (O1) power amplifier is used to buffer the LF411A output to increase the output current drive
to meet the design specifications of 1 A. A Kelvin connection is provided to allow for remote sensing at the
load power amplifier’s load. R7 prevents the amplifier from railing when the Kelvin connection is not being
utilized.
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36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
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2.4
Output Current Sense Design
In conjunction with the shunt resistors (R8 – R11) the INA146 (I1) acts as a high side current shunt monitor
as shown in Figure 4. The shunt resistor converts the load current into a voltage that is amplified by the
INA146. The INA146 is a two op-amp instrumentation amplifier as opposed to the more common 3 op-amp
configuration. There is a 0.1 V/V resistive divider at each input and the current shunt R 9 or R11 is in series
with the divider on the non-inverting input. In order to balance the bias current offset generated by the
shunt a matching resistor R8 or R10 is added in series with the inverting input. If these resistors were not
present the INA would see an unbalanced resistance and the resulting bias current would cause the
common mode rejection to decrease. When SW 3 is closed the shunt voltage is equal to the shunt current,
otherwise it’s 100 times the shunt current. The shunt voltage is amplified by the INA146 where it is scaled
to match a ±1V ADC range.
Out from
OPA549 (U5)
R8
R9
100 Ω
100 Ω
R10
R11
1Ω
R13
1Ω
SW4
SW3
R12
100 kΩ 11 kΩ
R15
RG
Vout
INA146 (I1)
To ADC
100 kΩ
R14
10 kΩ
R16
100 Ω
REF
Figure 4: INA Gain Settings
When SW 4 is in the reset position (as shown in Figure 4) the gain of the INA146 is 1 V/V. In the second position it
is 100 V/V. The voltage output from the INA146 is 1, 100, or 10000 times the shunt current depending on the
shunt resistor used and INA gain settings. This voltage can easily be read by an ADC and used to monitor the
current draw from the power supply.
Table 2: INA Gain Configurations
SW3 Setting
Open
Closed
TIDU001A-Sept. 2013-Revised July 2014
SW4 Setting
Shunt Resistor (Ω)
INA Gain (V/V)
Reset
100
1
Total Gain (V/V)
100
Set
100
100
10000
Reset
1
1
1
Set
1
100
100
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3
Component Selection
3.1 Passive Component Selection
The amplification portion of this circuit is used to gain the voltage from the DAC to the desired range.
Equation 2 shows how the output voltage of the op amp relates to the input voltage.
In the power supply circuit R1 is the input resistor and R2 is the feedback resistor. The max VOUT for the
circuit is 36 V and VIN, the voltage coming from the DAC, was chosen to be a maximum of 10 V. This
information is used to calculate the ratio of the feedback resistors to the input resistor in the power supply
circuit. It is shown explicitly in the following equations:
R2
10V
R1
(2)
R2  3.6 * R1
(3)
36V 
Using standard resistor values the easiest way to get these ratios is to use a 10kΩ resistor for R 1 and
36kΩ resistors for R2.
R4 and C1 are used as a low pass filter to attenuate high frequency noise. Equation 3 shows the formula to
find cutoff frequency:
f CUTOFF 
1
2 * * R * C
(4)
We selected a cutoff frequency of 1.5 MHz and a resistance of 100Ω. The equation was solved for
capacitance. This resulted in the following:
1
2 *  *100 * C
C  1000 pF
1.5MHz 
(5)
(6)
R6 was chosen as 1kΩ to be able to provide adequate protection from feedback current should the outputs
ever short circuit. As an example Equation 7 shows what the device would be current limited to in the
worst case scenario of a 36 V input while the output is shorted.
I IN 
VOUT
36V

 36mA
R6
1000
(7)
R7 was chosen to be 100kΩ so that when SW 2 is closed for the Kelvin connection all the current would flow
through the force/sense lines. R7 also ensures that the OPA549 does not run open loop when the Kelvin
lines are open.
Since the shunt resistors R8 through R11 make a voltage proportional to the current based on their value
they were selected to be either 1Ω or 100Ω for simple software calculations. Special consideration for
these resistors was necessary, however, since they could potentially have 1 amp of current through them.
For that reason 3 W power resistors are selected.
R12 through R16 were selected to give the INA146 a 1 V/V and 100 V/V gain configurations. Their values
are specified by the INA146’s datasheet (see page 8 of the INA146 datasheet).
R17 and R18 were used to create an inverting op-amp with a gain of -1. The value of 1 kΩ was a tradeoff
between noise and power dissipation.
C3 and C4 serve provide high frequency compensation for the VREF buffers to ensure stability.
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3.2 DAC Selection
In order to achieve the maximum voltage of 36 V in the chosen circuit configuration, a DAC capable of
producing -10 V is required. There are a number of options to achieve negative voltage outputs using
back-DAC architectures. The DAC8871 is chosen because it is a native high voltage DAC capable of
accepting 39.6 V between VREFH and VREFL. This makes DAC8871 very flexible to meet the specifications
of this unipolar design to output +10 V while being adaptable for other configurations discussed in the
Modifications section
Briefly mentioned in 2.3, this 16-bit DAC is only being used as a 15-bit DAC. This is because the output of
the DAC8871 is gained by -3.6 V/V in the U2 stage. The DAC8871 output requirements are only -10V to
0V but the output can span -10 V to 10 V. This means that half the DAC’s code span from 0x8000 to
0xFFFF is not utilized for the unipolar design. This trade off was made in order to allow for the bipolar
options discussed later.
3.3 DAC Reference Selection
A voltage reference was needed to produce a very stable value of 10 V. The only two references capable
of producing such a voltage are the REF5010 and the REF102. Of the two devices REF102 was
ultimately chosen because it has lower noise of 5 µVPP, a lower drift of 2.5 ppm/○C, and a better initial
accuracy of ±2.5 mV.
3.4 Reference Buffer Selection
The reference buffers need to be precision amplifiers with low offset voltage and low offset drift along with
low voltage noise and be stable at unity gain. The OPA2277 is an excellent choice with 12 nV/√Hz at 10
Hz, a maximum 25 μV of dc offset and a maximum offset drift of 0.25 μV/C. Even with the large heat sink
required in the design the power op amp will create a change in the ambient temperature so searching for
a very low offset drift coefficient is important to maintain accuracy as the output power increases.
3.5 DAC Buffer Selection
For the DAC buffer an op amp that is stable at unity gain is required. A JFET op amp is desired because
they have a high output impedance and low voltage noise density. The OPA140 meets both these features
as well as having low offset voltage and low bias current.
3.6 Amplifier Selection
The amplification section of the power supply requires a precision op amp capable of handling rail-to-rail
voltage difference of 44 V. This component must have a low offset to meet the low offset specifications.
The LF411A meets these requirements with a maximum of 500 μV offset, no more than 10 μV/C of offset
drift. Also, this stage also must remain low noise because the input of the final stage sees the root sum of
squares of the DAC8871, OPA140, and LF411A noise gained by -3.6 V/V. The LF411A has a typical
voltage noise of 25 nV/√Hz.
3.7 Power Amplifier Selection
Since the LF411A cannot sustain an output current of 1 A, it is necessary to have a buffer amplifier
capable of sourcing that current for an extended period of time. Rail-to-rail swing is also a careful
consideration for this output power stage because the closer the power stage can swing to the rails the
less head room the power rails must provide. Of the op amps available the OPA549 was the best fit.
The OPA549 specifications are good enough for this design: 500 μV max offset, 20 μV/C offset drift, 9V/μs
slew rate, and 70 nV/√Hz noise. The OPA549 is capable of sustaining 1 A indefinitely while used in
conjunction with the Thermalloy 6399B heat sink (which is recommended in the data sheet).
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3.8 Instrumentation Amplifier Selection
The INA146 was chosen as the instrumentation for the power supply because it was the only
instrumentation amplifier capable of working in the bi-polar case (which is discussed more in depth in the
modification section).
The INA146, however, does present its own difficulties since it is composed of two op amps as opposed to
the more common three op amp configuration. The inputs have an input resistor divider and higher bias
current than a 3-amp INA. This meant that it would have a poor CMRR unless compensated for. This
problem was overcome by having pairs of shunt resistors and arranging them in the way shown in Figure 2
(see Figure 7 on page 11 of the INA146 datasheet).
3.9 Relay Driver Selection
To make using the switches easier it was decided to use a relay driver in the power supply circuit. The
relay driver needs a minimum of 6 channels. The TLP9202 (U6) was chosen because it has 8 channels
and a built in 5 V LDO for powering the relays, thus eliminating the need for another component.
3.10 Protection Diode Selection
There is also a protection diode (D1) in the design. This diode connects between the negative power rail
and the output providing low side protection to the output of the design should there be a short below the
power rail. A fast switching BAS116 diode is used to clamp to the negative rail.
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4
Simulation
Figure 5 shows the TINA-TI™ schematic used to simulate the circuit.
TM
Figure 5: TINA-TI
Schematic
Since TINA-TI™ does not have a model for the DAC8871, the circuit only consists of the portion of the
power supply after the DAC buffer. In the simulation VS1 is used to represent the DAC8871 output
voltage. The equivalent output impedance is added to the source for better simulation accuracy.
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4.1 Transfer Function
The result of the transfer function is shown in Figure 6.
Figure 6: Transfer Function
4.2 VOUT Gain Error
To calculate gain error, measurements were taken at the voltage output of the power supply while there
was no current load. This data was then exported into a spreadsheet and the gain error was calculated
using Equation 8.
% FSR 
V
OUT ( MAX )
 VOUT ( MIN )   GIDEAL * VIN ( MAX )  VIN ( MIN ) 
GIDEAL * VIN ( MAX )  VIN ( MIN ) 
*100 %
(8)
The gain error was calculated for each shunt resistor and INA gain setting and results can be seen in
Table 3: Simulated VOUT Gain Error.
Table 3: Simulated VOUT Gain Error
INA Gain (V/V)
1 or 100
Shunt Resistor (Ω)
1 or 100
Gain Error (%FSR)
-0.006716
4.3 VOUT Offset
The offset of the power supply output is simply the simulated output when the input voltage was 0 V. It was
measured for each shunt resistor and INA gain settings and the results can be seen in Table 4: Simulated
VOUT Offset.
Table 4: Simulated VOUT Offset
INA Gain (V/V)
1 or 100
10
Shunt Resistor (Ω)
1 or 100
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VOUT Offset (mV)
4.2205615
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4.4 VOUT Load Regulation
For calculating the load regulation, the input voltage was made constant so that the output would ideally be
18 V. Then the current load on the power supply was swept from -1 A to 1 A, -10 mA to 10 mA, or -100 µA
to 100 µA depending on the shunt resistor and INA gain settings. Figure 7 through Figure 10 are graphical
representations of the simulated data.
Figure 7: Load Regulation 1 V/V, 1 Ω
Figure 8: Load Regulation 1 V/V, 100 Ω
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Figure 9: Load Regulation 100 V/V, 1 Ω
Figure 10: Load Regulation 100 V/V, 100 Ω
After simulations, the load regulation was calculated using Equation 9.
Load Regulation V / A 
VOUT ( MAX )  VOUT ( MIN )
CurrentMAX  CurrentMIN
*106
(9)
The results of the calculation are listed in Table 5.
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Table 5: Simulated Load Regulation
INA Gain (V/V)
1
100
Shunt Resistor (Ω)
1
100
VOUT Load Regulation (µV/A)
-0.016680
1
100
-0.013118
-1.088813
-1.088727
4.5 INA Gain Error
For calculating this gain error simulations were taken at the current output of the power supply while there
was no voltage output and the current was swept. Figure 11 through Load Regulation 100 V/V, 100
Figure 13 are graphical representations of the data.
Figure 11: INA Output 1 V/V, 1 Ω
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Figure 12: INA Output 1 V/V, 100 Ω
Figure 13: INA Output 100 V/V, 1 Ω
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Figure 14: INA Output 100 V/V, 100 Ω
From the simulated data the gain error was then calculated with Equation 8, substituting VOUT with Current
Out and VIN with Current Load. The results of the calculation are listed in Table 6.
Table 6: INA Gain Error
INA Gain (V/V)
1
100
TIDU001A-Sept. 2013-Revised July 2014
Shunt Resistor (Ω)
1
100
INA Gain Error (%FSR)
-1.998930
1
100
-1.988344
-2.007920
-1.997240
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4.6 INA CMRR
The simulations for the common-mode rejection ratio (CMRR) of the INA146 were taken at the current
output while sweeping the power supply output from 0 V to 36 V with a current draw of zero amps. Figure
15 through Figure 18 represent a graphical representation of the data.
Figure 15: INA CMRR 1 V/V, 1 Ω
Figure 16: INA CMRR 1 V/V, 100 Ω
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Figure 17: INA CMRR 100 V/V, 1 Ω
Figure 18: INA CMRR 100 V/V, 100 Ω
Because the CMRR used is input referred, two equations were necessary. Equation 10 was used to
calculate the CMRR while the INA was in the 1 V/V setting and Equation 11 was used to calculate the
CMRR when the INA was in the 100 V/V setting.
 CurrentOUT ( MAX )  CurrentOUT ( MIN ) 

CMRR  20 * log10 


V

V
OUT
(
MAX
)
OUT
(
MIN
)


TIDU001A-Sept. 2013-Revised July 2014
( 10 )
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 CurrentOUT ( MAX )  CurrentOUT ( MIN ) 

log10 


V

V
OUT
(
MAX
)
OUT
(
MIN
)


CMRR  20 *
100
( 11 )
The results of the calculations are listed in Table 7.
Table 7: INA CMRR
INA Gain (V/V)
1
100
Shunt Resistor (Ω)
1
100
1
100
INA CMRR (dB)
68.999155
69.008537
69.091690
69.101018
4.7 Bandwidth
The bandwidth of the circuit was simulated by running an AC frequency sweep at the input of the OPA140.
Figure 19 shows the bode plot of the AC sweep. The -3 dB point is at 728 kHz.
Figure 19: Simulated Bode Plot
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36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
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5
PCB Design
The PCB schematic and bill of materials can be found in the Appendix.
5.1 PCB Layout
Figure 20: PCB Layout
The board is a six layer board made up of the top and bottom layer, two ground planes, and two power
planes. The power planes are split planes with both a positive and negative voltage on them.
The Force Out traces are 50 mils wide because they have to potential to have 1 amp of current flowing
through them. In order for the kelvin connection to be active U5 must be closed.
The layout of the circuit is as follows:

Region A features a PXI connector, a serial data capture card (SDCC) connector (ERF8-025-01-L-DRA-L-TR in the bill of materials), and a set of 100 mil spaced headers for connecting to the board if
the user doesn’t have the male version of the PXI or SDCC connector.

Region B of the board contains the DAC and its references, the LF411A, and the relay driver.

Region C has big block within it for the OPA549 and its heat sink. Above it are the power supply
inputs for the circuit.

Region D is the current shunt monitor and the relays to change its gain.

Region E has the outputs of the circuit.
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6
Verification & Measured Performance
The measured data was collected and the results were calculated using the same methods as the
simulation section.
6.1 Transfer Function
40
35
VOUT (V)
30
y = -3.5971x + 0.0124
25
20
15
10
5
0
-10
-8
-6
-4
-2
0
DAC Voltage (V)
Figure 21: Measured Transfer Function
6.2 VOUT Gain Error
Equation 8 shows the gain error calculation.
Table 8: Measured VOUT Gain Error
INA Gain (V/V)
1 or 100
Shunt Resistor (Ω)
1 or 100
VOUT Gain Error (%FSR)
-0.07962175
6.3 VOUT Offset
Table 9: Measured VOUT Offset
INA Gain (V/V)
1 or 100
20
Shunt Resistor (Ω)
1 or 100
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
VOUT Offset (mV)
8.2301825
TIDU001A-Sept. 2013-Revised July 2014
www.ti.com
6.4 VOUT Load Regulation
1.0047
1.0046
y = 3E-06x + 1.0042
Vout (V)
1.0045
1.0044
1.0043
1.0042
1.0041
1.004
1.0039
-100
-50
0
50
100
150
Current Out (mA)
Figure 22: Load Regulation 1 V/V, 1 Ω
1.004310
1.004300
y = 3E-06x + 1.0043
Vout (V)
1.004290
1.004280
1.004270
1.004260
1.004250
1.004240
1.004230
-10
-5
0
5
10
Output Current (mA)
Figure 23: Load Regulation 1 V/V, 100 Ω
TIDU001A-Sept. 2013-Revised July 2014
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
21
www.ti.com
1.004330
1.004320
y = 3E-06x + 1.0043
Vout (V)
1.004310
1.004300
1.004290
1.004280
1.004270
1.004260
1.004250
-10
-5
0
5
10
Output Current (mA)
Figure 24: Load Regulation 100 V/V, 1 Ω
1.00429
1.004288
1.004286
y = 4E-08x + 1.0043
Vout (V)
1.004284
1.004282
1.00428
1.004278
1.004276
1.004274
1.004272
-100
-80
-60
-40
-20
0
20
40
60
80
100
Current Out (uA)
Figure 25: Load Regulation 100 V/V, 100 Ω
Equation 9 shows how the load regulation was calculated. The ability of the HP3458 meter to resolve the
changes between each current decreased as the current range is decreased. The calculation for the ±100
μA range is omitted because the HP3458 could not resolve the correct value due to the noise of the
system even with 100 power line cycles (PLC) of averaging.
Table 10: Measured VOUT Load Regulation
INA Gain (V/V)
1
100
22
Shunt Resistor (Ω)
1
VOUT Load Regulation (µV/A)
2.92
100
2.61
1
100
2.45
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
N/A
TIDU001A-Sept. 2013-Revised July 2014
www.ti.com
6.5 INA Gain Error
1
0.8
Current Shunt Out (V)
0.6
y = 1x - 5E-07
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1
-0.5
0
0.5
1
Current Load (A)
Figure 26: INA Output 1 V/V, 1 Ω
1
0.8
Current Shunt Out (V)
0.6
y = 0.1x - 6E-05
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-10
-5
0
5
10
Current Load (mA)
Figure 27: INA Output 1 V/V, 100 Ω
TIDU001A-Sept. 2013-Revised July 2014
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
23
www.ti.com
1
0.8
Current Shunt Out (V)
0.6
y = 0.1x - 5E-05
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-10
-5
0
5
10
Current Load (mA)
Figure 28: INA Output 100 V/V, 1 Ω
Current Shunt Out (V)
1
0.5
y = 0.01x - 0.0003
0
-0.5
-1
-100
-50
0
50
100
Current Load (μA)
Figure 29: INA Output 100 V/V, 100 Ω
See Equation 8 to see how the gain error was calculated.
INA Gain (V/V)
1
100
24
Table 11: Measured INA Gain Error
Shunt Resistor (Ω)
1
100
1
100
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
INA Gain Error (%FSR)
1.001730
-0.030363
1.003658
-0.141955
TIDU001A-Sept. 2013-Revised July 2014
www.ti.com
6.6 INA CMRR
1000
800
Current Shunt Out (uV)
600
400
100 Ω
1Ω
200
0
0
5
10
15
20
25
30
35
40
-200
-400
Power Supply Vout (V)
Figure 30: INA CMRR 1 V/V
100
80
Current Shunt Out (uV)
60
40
100 Ω
20
1Ω
0
0
5
10
15
20
25
30
35
40
-20
-40
-60
Power Supply Vout (V)
Figure 31: INA CMRR 100 V/V
See Equations 10 and 11 to see how the CMRR was calculated.
TIDU001A-Sept. 2013-Revised July 2014
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
25
www.ti.com
Table 12: Measured INA CMRR
INA Gain
1 V/V
Shunt Resistor
1Ω
INA CMRR (dB)
92.278229
100 Ω
89.456711
1Ω
100 Ω
92.317234
100 V/V
89.538604
6.7 Bandwidth
Figure 16 shows the measured bode plot of the circuit. The 3 dB point is at 500 kHz.
20
500 kHz, 8.11 dB
10
0
Gain (dB)
-10
-20
-30
-40
-50
-60
-70
100
1000
10000
100000
1000000
10000000
Frequency (Hz)
Figure 32: Bode Plot
26
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
TIDU001A-Sept. 2013-Revised July 2014
www.ti.com
7
Modifications
There are a number of modifications that can be applied to this circuit depending on the requirements of
the user.
If the user requires a bipolar output, switching SW 1 to the closed position will change the gain of the
LF411A from -3.6 V/V to -1.8 V/V. The DAC8871 is already set-up to span ±10 V because VREFH is 10 V
and VREFL is -10 V. By changing the gain to -1.8 V/V the design will now have an output range of ±18 V
with the same current load available.
The INA output can be modified to interface with an analog to digital converter (ADC) that has a 5 V
unipolar supply. To make this change, connect I1, pin 1 to 2.5 V instead of 0 V. This will bias the output of
I1 around 2.5 V while maintaining a voltage swing of ±1 V.
If the ±1 V swing is too small for the dynamic range of the user’s ADC then changing the resistors to 5Ω
and 500Ω pairs, the gain of the current shunt monitor would be increased from 1 or 100 V/V to 5 or 500
V/V. This would result in an INA output range of -5 V to 5 V. Similar changes can be made to match the
input span of any ADC.
Another option to customize the output voltage would be to modify the V REFH and VREFL voltages.
Remember, the DAC8871 will span any voltage applied to these pins up to a maximum difference of 39.6
V. Using a REF5050 to generate a 5 V reference instead of the REF102’s 10 V would result in a ±5 V
difference between VREFH and VREFL. This would result in a unipolar operation of 18 V and a bipolar
operation of ±9 V.
8
About the Author
Adam Rozenberg is an undergraduate electrical engineering student at the University of Florida. He will be
graduating with a BSEE in December 2013. Prior to interning with the High Performance Analog group in
Texas Instruments he participated in medical and communications research.
Daniel Kimmitt is the Validation Manager in the Precision Digital to Analog Converters group. Prior to his
current position he was a test engineer in the Linear Products group focusing on signal conditioning and
temperature sensors. He joined TI in 2006 after receiving MSECE from the University of Florida in
Gainesville, FL.
Bill Eisenhower is Test and Characterization Engineer in the Precision Digital to Analog Converters group.
He joined TI in 2009 after completing his MSECE at the University of Illinois at Urbana-Champaign.
TIDU001A-Sept. 2013-Revised July 2014
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
27
www.ti.com
Appendix A.
A.1 Electrical Schematic
Figure A-1: Electrical Schematic
28
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
TIDU001A-Sept. 2013-Revised July 2014
www.ti.com
A.2 Bill of Materials
Description
QTY
Ref Des
Manufacturer
Manufacturer Part Number
CAP, CERM, 1000pF, 50V, +/-1%, C0G/NP0, 0805
2
C1, C2
AVX Corporation
08055A102FAT2A
CAP, CERM, 0.1uF, 25V, +/-5%, X7R, 0603
17
C3, C5, C13, C14, C15,
C16, C17, C18, C19,
C20, C21, C22, C23,
C27, C28, C29, C30
AVX Corporation
06033C104JAT2A
Not Placed
4
C4, C6, C24, C25
CAP, TA, 10uF, 50V, +/-10%, 0.4 ohm, SMD
6
C7, C8, C9, C10, C11,
C12
AVX Corporation
TPSE106K050R0400
CAP, CERM, 1uF, 25V, +/-10%, X5R, 0805
1
C26
Murata Electronics
GRM216R61E105KA12D
Diode, Low Leakage, 215-mA, 85-V
IC, High-Voltage, Programmable Gain difference
Amp.
2.54mm Pitch KK® Solid Header, Right Angle, with
Friction Lock, 6 Circuits, 0.51µm Gold (Au) Plating
Receptacle, D-Sub 68 Pos, R/A, TH
Receptacle, Micro High Speed Socket Strip, 0.8mm,
25x2, RA, SMT
1
D1
Diodes Inc.
BAS116-7-F
1
I1
Texas Instruments
INA146UA
2
J1, J2
Molex Inc.
22-12-2064
1
J9
Molex Inc.
1
J10
SAMTEC
0714300012
ERF8-025-01-L-D-RA-LTR
Header, Male 2-pin, 100mil spacing,
2
J11, J12
Header, Male 3-pin, 100mil spacing,
4
J13, J14, J15, J18
Header, 8-pin, 100mil spacing,
IC, High Voltage, high Currnet OpAmp
1
1
J16
O1
Sullins Connector
Solutions
Sullins Connector
Solutions
TE Connectivity
Texas Instruments
RES, 1.82k ohm, 1%, 0.25W, 1206
RES, 36.0k ohm, 0.1%, 0.125W, 0805
RES, 1.00k ohm, 0.5%, 0.1W, 0805
RES, 42.2k ohm, 0.1%, 0.125W, 0805
RES, 100k ohm, 0.1%, 0.125W, 0805
2
2
3
1
3
R1, R20
R2, R4
R3, R23, R24
R5
R6, R14, R19
Vishay Dale
Susumu
Susumu
Yageo
Susumu
CRCW12061K82FKEA
RG2012P-363-B-T5
RR1220P-102-D
RT0805BRD0742K2L
RG2012P-104-B-T5
RES, 10.0k ohm, 0.1%, 0.125W, 0805
2
R7, R15
Susumu
RG2012P-103-B-T5
RES, 100 ohm, 0.1%, 0.125W, 0805
2
R8, R16
Susumu
RG2012P-101-B-T5
RES, 100 ohm, 1%, 3W, TH
2
R9, R10
Vishay Dale
CMF50100R00FHEB
PEC02SAAN
PEC03SAAN
87224-8
OPA549T
RES, 1.0 ohm, 1%, 3W, TH
2
R11, R12
Vishay Dale
RS02B1R000FE70
RES, 11.0k ohm, 0.1%, 0.125W, 0805
1
R13
Susumu
RG2012P-113-B-T5
RES, 5.97k ohm, 0.1%, 0.125W, 0805
RES, 18.0k ohm, 0.1%, 0.125W, 0805
RES, 0 ohm, 5%, 0.125W, 0805
RES, 1.00k ohm, 0.1%, 0.125W, 0805
2
1
1
2
R17, R18,
R21
R17, R18, R22, R23, R24
R29, R30
RT0805BRD075K97L
RG2012P-183-B-T5
CRCW08050000Z0EA
RG2012P-102-B-T5
8A Polarized Relay
1
SW1
Very High Sensitivity, 50 mW (nominal operating)
Relay with LT style pin layout
1
SW2
Vishay Dale
Susumu
Vishay Dale
Susumu
Panasonic Electric
Works
Panasonic Electric
Works
Low Offset, Low Drift JFET Input Op Amp
1
U2
Texas Instruments
LF411AACN
1
U3
Texas Instruments
DAC8871SPW
2
1
2
1
U4, U5
U6
U7, U8
U9
Texas Instruments
Texas Instruments
Texas Instruments
VOL618A-2T
TPL9202
OPA2277U
REF102AU
1
U10
Texas Instruments
OPA140AID
IC, 16-bit Single Channel, ±18V o/p, Unbuffered,
Serial Interface D-A Converter
OPTOCOUPLR PHOTOTRANS 125% 4LSOP
8-Channel Relay Driver with Integrated 5-V LDO
IC, High Precision Op Amp
IC, 10V Precision Voltage Reference
IC, High-Precision, Low-Noise, R-R Output, 11MHz
JFET Op Amp
ST2-L2-DC5V
TXS2-L2-4.5V
Figure A-2: Bill of Materials
TIDU001A-Sept. 2013-Revised July 2014
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
29
www.ti.com
Appendix B.
B.1 Thermal Images
WARNING: Avoid touching the OPA549 and shunt resistor during circuit operation. They can reach high temperatures.
Figure B-1: OPA549 and its Heat Sink
Figure B-1: Shunt Resistor R11, 1 A load
30
36 V, 1 A SPI Controlled Power Supply with Integrated Current Shunt
Copyright © 2013, Texas Instruments Incorporated
TIDU001A-Sept. 2013-Revised July 2014
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