PGA309 User`s Guide (Rev. B)

PGA309
Voltage Output Programmable Sensor Conditioner
User's Guide
Literature Number: SBOU024B
August 2004 – Revised January 2011
2
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Contents
....................................................................................................................................... 9
Introduction ...................................................................................................................... 11
1.1
PGA309 Functional Description ......................................................................................... 12
1.2
Sensor Error Adjustment Range ......................................................................................... 13
1.3
Gain Scaling ................................................................................................................ 13
1.4
Offset Adjustment ......................................................................................................... 13
1.5
Voltage Reference ......................................................................................................... 13
1.6
Sensor Excitation and Linearization .................................................................................... 14
1.7
ADC for Temperature Sensing .......................................................................................... 14
1.8
External EEPROM and Temperature Coefficients .................................................................... 14
1.9
Fault Monitor ............................................................................................................... 14
1.10 Over-Scale and Under-Scale Limits .................................................................................... 15
1.11 Power-Up and Normal Operation ....................................................................................... 15
1.12 Digital Interface ............................................................................................................ 16
1.13 Pin Configuration .......................................................................................................... 16
Detailed Description .......................................................................................................... 19
2.1
Gain Scaling ................................................................................................................ 20
2.1.1 PGA309 Transfer Function ...................................................................................... 22
2.2
Offset Scaling .............................................................................................................. 24
2.3
Zero DAC and Gain DAC Architecture ................................................................................. 25
2.4
Output Amplifier ............................................................................................................ 26
2.5
Reference Voltage ......................................................................................................... 29
2.6
Linearization Function ..................................................................................................... 30
2.6.1 System Definitions ................................................................................................ 33
2.6.2 Key Linearization Design Equations ........................................................................... 33
2.6.3 Key Ideal Design Equations ..................................................................................... 34
2.7
Temperature Measurement .............................................................................................. 37
2.7.1 Temp ADC Start-Convert Control .............................................................................. 42
2.7.2 External Temperature Sensing with an Excitation Series Resistor ........................................ 43
2.8
Fault Monitor ............................................................................................................... 45
2.9
Over/Under Scale ......................................................................................................... 48
2.10 Noise and Coarse Offset Adjust ......................................................................................... 53
2.11 General AC Considerations .............................................................................................. 58
Operating Modes ............................................................................................................... 59
3.1
Power-On Sequence and Normal Stand-Alone Operation ........................................................... 60
3.2
EEPROM Content and Temperature Lookup Table Calculation .................................................... 62
3.2.1 Temperature Lookup Table Calculation ....................................................................... 65
3.3
Checksum Error Event .................................................................................................... 70
3.4
Test Pin ..................................................................................................................... 70
3.5
Power-On Initial Register States ........................................................................................ 71
Digital Interface ................................................................................................................. 73
4.1
Description ................................................................................................................. 74
4.2
Two-Wire Interface ........................................................................................................ 74
4.2.1 Device Addressing ............................................................................................... 75
Preface
1
2
3
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4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
5
Application Background
5.1
5.2
5.3
6
4.2.2 Two-Wire Access to PGA309 ...................................................................................
One-Wire Interface ........................................................................................................
One-Wire Interface Timeout ..............................................................................................
One-Wire Interface Timing Considerations ............................................................................
Two-Wire Access to External EEPROM ................................................................................
One-Wire Interface Initiated Two-Wire EEPROM Transactions .....................................................
PGA309 Stand-Alone Mode and Two-Wire Transactions ............................................................
PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations ......................................
One-Wire Operation with PRG Connected to VOUT ....................................................................
Four-Wire Modules and One-Wire Interface (PRG) ...................................................................
75
77
80
81
81
83
83
86
88
91
..................................................................................................... 97
Bridge Sensors ............................................................................................................ 98
System Scaling Options for Bridge Sensors ......................................................................... 100
5.2.1 Absolute Scale .................................................................................................. 100
5.2.2 Ratiometric Scale ............................................................................................... 101
Trimming Real World Bridge Sensors for Linearity .................................................................. 102
Register Descriptions
....................................................................................................... 103
Internal Register Overview ..............................................................................................
Internal Register Map ....................................................................................................
6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000) ......................
6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001) ........
6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010) .........
6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011) .
6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register
(Read/Write, Address Pointer = 00100) ......................................................................
6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address
Pointer = 00101) ................................................................................................
6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110) .....................
6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111) .......
6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000) .............................
104
104
104
106
107
108
External EEPROM Example
...............................................................................................
.................................................................................
B
Detailed Block Diagram ....................................................................................................
B.1
Detailed Block Diagram .................................................................................................
C
Glossary .........................................................................................................................
Revision History .......................................................................................................................
119
A.1
120
6.1
6.2
A
4
PGA309 External EEPROM Example
Contents
109
111
113
116
117
125
126
127
131
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List of Figures
1-1.
Simplified Diagram of the PGA309 ...................................................................................... 12
1-2.
PGA309 Pin Assignments ................................................................................................ 16
2-1.
Gain Blocks of the PGA309 .............................................................................................. 20
2-2.
Front-End PGA Gain—Internal Node Calculations
2-3.
Fine Gain Adjust of the PGA309 ........................................................................................ 22
2-4.
Coarse and Fine Offset Adjust........................................................................................... 24
2-5.
Output Amplifier in a Common 3-Terminal Sensor Application...................................................... 26
2-6.
Output Amplifier Using External Feedback Resistors RFOEXT and RGOEXT
27
2-7.
Output Amplifier Minimum Gain at Low Supply
28
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
2-23.
2-24.
2-25.
2-26.
...................................................................
...........................................
.......................................................................
PGA309 Reference Circuit ...............................................................................................
Bridge Pressure Nonlinearity Correction ...............................................................................
Bridge Excitation Linearization Circuit ..................................................................................
Linearization Circuit .......................................................................................................
Bridge Output vs Pressure ...............................................................................................
Bridge Nonlinearity (%FSR) vs Pressure ...............................................................................
Corrected Bridge Parabolic Nonlinearity vs Pressure ................................................................
Temperature Sense Block ................................................................................................
Temp ADC Input Mux Options ...........................................................................................
ITEMP for External Temperature Measurement ..........................................................................
Temp ADC Continuous Start-Convert Control .........................................................................
Temp ADC Single Start-Convert Control ...............................................................................
External Temperature Sensing of Bridge Sensor with Top-Side Series Resistor .................................
External Temperature Sensing of Bridge Sensor with Bottom-Side Series Resistor .............................
PGA309 Fault Monitor Circuitry .........................................................................................
Fault Monitor Comparator Logic .........................................................................................
Over-Scale and Under-Scale Limit Circuit .............................................................................
Absolute Scale System—PGA309 Connected to a System ADC ...................................................
System ADC Range Budget for Over-Scale, Under-Scale, and Linear Output ...................................
21
29
30
30
31
32
32
35
38
40
41
42
43
44
44
45
48
49
51
52
2-27.
Voltage Noise Power Spectrum Referred to Input (RTI), Coarse Offset Adjust = 0mV, Gain = 1152,
CLK_CFG = ‘00’ (default) ................................................................................................ 53
2-28.
VOUT Noise, 0.1Hz to 10Hz Peak-to-Peak Noise ....................................................................... 54
2-29.
Unfiltered VOUT Clock Feedthrough, Coarse Offset Adjust = 0mV, Gain = 1152, CLK_CFG = ‘00’
(default) ..................................................................................................................... 54
2-30.
Unfiltered VOUT Clock Feedthrough Glitch, Coarse Offset Adjust = −59mV, Gain = 1152, VIN = +61mV,
CLK_CFG = ‘00’ (default). VOUT Glitch (RTI) = 347µVPP .............................................................. 55
2-31.
Filtered 0.1Hz to 10Hz VOUT Peak-to-Peak Noise, Coarse Offset Adjust = −59mV, Gain = 1152, VIN =
+61mV, CLK_CFG = ‘00’ (default) ...................................................................................... 55
2-32.
Voltage Noise Spectrum (RTI), Coarse Offset Adjust = −59mV, Gain = 1152, VIN = +61mV, CLK_CFG =
‘00’ (default) ................................................................................................................ 55
2-33.
0.1Hz to 10Hz VOUT Peak-to-Peak Noise for Coarse Offset Adjust = −56mV, Gain = 1152, VIN = +57mV,
CLK_CFG = ‘01’, VNPP (RTI) = 4.44 VPP ................................................................................. 56
2-34.
VOUT Noise Spectrum for Coarse Offset Adjust = −56mV, Gain = 1152, VIN = +57mV, CLK_CFG = ‘01’ ...... 56
2-35.
0.1Hz to 10Hz VOUT Peak-to-Peak Noise for Coarse Offset Adjust = −56mV, Gain = 1152, VIN = +57mV,
CLK_CFG = ‘10’, VNPP (RTI) = 18.4µVPP ................................................................................ 57
2-36.
VOUT Noise Spectrum for Coarse Offset Adjust = −56mV, Gain = 1152, VIN = +57mV, CLK_CFG = ‘10’ ...... 57
2-37.
0.1Hz to 10Hz VOUT Peak-to-Peak Noise for Coarse Offset Adjust = −56mV, Gain = 1152, VIN = +57mV,
CLK_CFG = ‘11’, VNPP (RTI) = 42µVPP .................................................................................. 57
2-38.
VOUT Noise Spectrum for Coarse Offset Adjust = −56mV, Gain = 1152, VIN = +57mV, CLK_CFG = ‘11’ ...... 57
2-39.
Input Filtering............................................................................................................... 58
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6
3-1.
State Machine—Power-On Sequence and Operation in Stand-Alone Mode ...................................... 61
3-2.
PGA309 Internal Registers Map to External EEPROM Addresses ................................................. 62
3-3.
Desired Gain DAC Values ................................................................................................ 65
3-4.
Desired Zero DAC Values ................................................................................................ 65
3-5.
Signal Path Functional Check with Test = ‘1’ on Power-Up ......................................................... 72
4-1.
Two-Wire Timing Diagram................................................................................................ 74
4-2.
Two-Wire Start and Acknowledge ....................................................................................... 75
4-3.
External EEPROM and Control Byte Allocation ....................................................................... 75
4-4.
Two-Wire Access to PGA309 Timing ................................................................................... 76
4-5.
Typical PGA309 PRG To Controller Connection ...................................................................... 77
4-6.
One-Wire (PRG) Access to PGA309 and External EEPROM Timing .............................................. 78
4-7.
One-Wire Access to PGA309 Registers ................................................................................ 79
4-8.
One-Wire Access to External EEPROM ................................................................................ 80
4-9.
One-Wire Through PGA309 Timing Diagram .......................................................................... 81
4-10.
Two-Wire Access to External EEPROM Timing ....................................................................... 82
4-11.
First Part of External EEPROM Timing for Stand-Alone Mode ...................................................... 84
4-12.
Second Part of External EEPROM Timing for Stand-Alone Mode .................................................. 85
4-13.
Two-Wire Bus Relinquish by PGA309 in Master Mode
4-14.
Two-Wire Bus Master Algorithm ......................................................................................... 87
4-15.
One-Wire Operation with PRG Tied to VOUT ............................................................................ 88
4-16.
Output Enable/Disable State Machine .................................................................................. 90
4-17.
Four-Wire Sensor Module Application .................................................................................. 91
4-18.
SCR ESD Cell
4-19.
Severe EMI/RFI Disturbance............................................................................................. 93
4-20.
PRG Circuit Protection Logic Levels .................................................................................... 94
4-21.
PRG Circuit EMI/RFI Filtering............................................................................................ 95
5-1.
Typical Bridge Sensor
5-2.
Example of Span and Offset ............................................................................................. 98
5-3.
Ideal Span and Offset vs Temperature ................................................................................. 99
5-4.
Effect of Nonlinearity on Bridge Sensor Span Over Temperature .................................................. 99
5-5.
Effect of Nonlinearity on Bridge Sensor Offset Over Temperature ................................................. 99
5-6.
Non-Ideal Curves for Both a Positive and Negative Nonlinear Bridge Sensor Output with Applied
Pressure ................................................................................................................... 100
5-7.
Absolute Scaling Conditions ............................................................................................ 100
5-8.
Ratiometric Configuration, 5V .......................................................................................... 101
5-9.
Ratiometric Configuration, 3V .......................................................................................... 101
5-10.
Typical Trim Configuration .............................................................................................. 102
5-11.
PGA309 Trim Configuration ............................................................................................ 102
6-1.
Internal Temperature Mode; Register 6[9] = ‘1’ ...................................................................... 104
6-2.
External Signal Mode; Register 6 = ‘0000 0100 0011 0000’ ....................................................... 105
6-3.
Internal Temperature Mode (Register 6 [9] = ‘1’) .................................................................... 114
6-4.
External Signal Mode (Register 6 [9], TEN = ‘0’) .................................................................... 114
6-5.
Temp ADC Mux Configurations ........................................................................................ 115
A-1.
PGA309 Circuit for External EEPROM Example .................................................................... 120
A-2.
Gain and Offset Scaling for External EEPROM Example .......................................................... 121
B-1.
Detailed Block Diagram ................................................................................................. 126
..............................................................
.............................................................................................................
....................................................................................................
List of Figures
86
92
98
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List of Tables
1-1.
PGA309 Adjustment Capability .......................................................................................... 13
1-2.
................................................................................................
Output Amplifier Typical Gain Resistor Values ........................................................................
Output Amplifier Gain Selections—Register 4 .........................................................................
Register 3 Reference Control Bits.......................................................................................
PGA309 Recommended Operating Conditions .......................................................................
Range 0—Typical System Applications and Maximum Nonlinearity Correction ..................................
Range 1—Typical System Applications and Maximum Nonlinearity Correction ..................................
Internal Temperature Mode Configuration—Register 6 ..............................................................
Internal Temperature Mode Resolution—Register 6..................................................................
Internal Temperature Mode Data —Register 0 ........................................................................
Temp ADC PGA Gain Select—Register 6 .............................................................................
Temp ADC Reference Select—Register 6 .............................................................................
Temp ADC Resolution (Conversion time)—Register 6 ...............................................................
Temp ADC Start-Convert Control—Register 6 ........................................................................
Temp ADC Conversion Speed Options for External Temperature Mode ..........................................
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
PGA309 Pin Descriptions
17
26
28
29
36
37
37
38
39
39
40
41
41
42
43
2-15.
Bridge Sensor Faults and Fault Comparator States—VIN1 and VIN2 Have No Pull-Up or Pull-Down
Resistors .................................................................................................................... 46
2-16.
Bridge Sensor Faults and Fault Comparator States—VIN1 and VIN2 are connected by 10MΩ Pull-Up
Resistors to VEXC ........................................................................................................... 47
2-17.
16.Bridge Sensor Faults and Fault Comparator States—VIN1 and VIN2 are connected by 10MΩ Pull-Down
Resistors to GND .......................................................................................................... 47
2-18.
Over-Scale Threshold Selections (Register 5 Bits [5:3]). VREF = +5V ............................................... 49
2-19.
Under-Scale Threshold Selections (Register 5 Bits [2:0]). VREF = +5V ............................................. 49
2-20.
Electrical Characteristics for Over-Scale and Under-Scale Comparators and VREF ............................... 51
2-21.
Over-Scale and Under-Scale Min and Max Trip Point Calculations ................................................ 52
2-22.
PGA309 VOUT Limits for System ADC Range Budget ................................................................. 52
2-23.
PGA309 Clocking Schemes.............................................................................................. 56
3-1.
1k-Bit External EEPROM Contents ..................................................................................... 63
3-2.
Temp ADC Temperature vs Counts
3-3.
Gain DAC Temperature Coefficient Calculation ....................................................................... 67
3-4.
Zero DAC Temperature Coefficient Calculation ....................................................................... 68
3-5.
Lookup Table Contents ................................................................................................... 68
3-6.
Gain DAC vs Temperature ............................................................................................... 69
3-7.
Gain DAC Lookup Table Calculation Algorithm ....................................................................... 69
3-8.
POR States for Key Parameters
4-1.
Two-Wire Timing Diagram Definitions .................................................................................. 74
4-2.
One-Wire Timing Diagram Definitions .................................................................................. 81
4-3.
Temp ADC—Delay After VOUT Enable (Register 7).................................................................... 89
4-4.
Output Enable Counter for One-Wire Interface/VOUT Multiplexed Mode (Register 7) ............................. 89
6-1.
Internal Register Overview.............................................................................................. 104
6-2.
Internal Temperature Mode−Data Format (12-Bit Resolution). TEN = 1; R1, R0 = ‘11’ ........................ 105
6-3.
External Signal Mode—Data Format Example (Register 6 = ‘0000 0100 0011 0011’), 15-Bit + Sign
Resolution. REN = 1, RS = 1 ........................................................................................... 105
6-4.
Zero DAC—Data Format Example (VREF = +5V) ..................................................................... 106
6-5.
Gain DAC—Data Format................................................................................................ 107
6-6.
Linearization DAC—Data Format Example (Range 1: −0.166VFB < Linearization DAC Range <
+0.166VFB)................................................................................................................. 108
....................................................................................
........................................................................................
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71
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6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
A-1.
A-2.
8
.........................................................................................
Front End PGA—Gain Select ..........................................................................................
Front End PGA—MUX Select ..........................................................................................
Coarse Offset Adjust on Front-End PGA—Data Format Example (VREF = +5V) .................................
Clock Configuration (Front End PGA Auto-Zero and Coarse Adjust DAC Chopping) ..........................
Over-Scale Threshold Select (VREF = +5V) ...........................................................................
Under-Scale Threshold Select (VREF = +5V) ..........................................................................
Temp ADC Reference Select ..........................................................................................
Temp ADC Input Mux Select ...........................................................................................
Temp ADC PGA Gain Select ...........................................................................................
Temp ADC—Resolution (Conversion Time) Select .................................................................
Temp ADC—Delay After VOUT Enable .................................................................................
Output Enable Counter for One-Wire Interface/VOUT Multiplexed Mode ..........................................
PGA309 Configuration for External EEPROM Example ............................................................
Final Values for External EEPROM Example ........................................................................
Output Amplifier—Gain Select
List of Tables
109
109
110
110
111
112
112
113
114
114
115
116
117
120
122
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Preface
SBOU024B – August 2004 – Revised January 2011
Read This First
About This Manual
This user’s guide describes the function and operation of the PGA309.
Related Documentation from Texas Instruments
Current versions of all documentation can be obtained from the TI website at http://www.ti.com/, or by
calling the Texas Instruments Literature Response Center at (800) 477-8924 or the Product Information
Center (PIC) at (972) 644-5580. When ordering, identify the document by both title and literature number
(shown in parentheses).
Data Sheets:
PGA309 (SBOS292)
User's Guides:
PGA309EVM User’s Guide (SLOR087)
Sensor-Emulator-EVM Reference Guide (SBOA102)
USB DAQ Platform User’s Guide (SBOU056)
Universal Serial Bus General-Purpose Device Controller (SLLS466)
Tools:
PGA309EVM Software (SLOR088)
PGA309EVM Source Code (SBOC070)
PGA309EVM Evaluation Module
If You Need Assistance
If you have questions about the PGA309 or the PGA309 evaluation module, join the discussion with the
Linear Amplifiers Applications Team in the e2e™ forum at e2e.ti.com. Include PGA309 as the subject
heading of your posting.
Information About Cautions and Warnings
This document contains caution statements.
CAUTION
This is an example of a caution statement. A caution statement describes a
situation that could potentially damage your software or equipment.
The information in a caution or a warning is provided for your protection. Please read each caution and
warning carefully.
e2e is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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9
FCC Warning
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FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense is required to
take whatever measures may be required to correct this interference.
10
Read This First
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© 2004–2011, Texas Instruments Incorporated
Chapter 1
SBOU024B – August 2004 – Revised January 2011
Introduction
This user’s guide describes the function and operation of the PGA309, a programmable analog signal
conditioner designed for bridge sensors.
Topic
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
...........................................................................................................................
PGA309 Functional Description ..........................................................................
Sensor Error Adjustment Range ..........................................................................
Gain Scaling .....................................................................................................
Offset Adjustment .............................................................................................
Voltage Reference .............................................................................................
Sensor Excitation and Linearization ....................................................................
ADC for Temperature Sensing ............................................................................
External EEPROM and Temperature Coefficients ..................................................
Fault Monitor ....................................................................................................
Over-Scale and Under-Scale Limits .....................................................................
Power-Up and Normal Operation .........................................................................
Digital Interface .................................................................................................
Pin Configuration ..............................................................................................
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Introduction
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13
13
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11
PGA309 Functional Description
1.1
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PGA309 Functional Description
The PGA309 is a smart programmable analog signal conditioner designed for resistive bridge sensor
applications. It is a complete signal conditioner with bridge excitation, initial span and offset adjustment,
temperature adjustment of span and offset, internal/external temperature measurement capability, output
over-scale and under-scale limiting, fault detection, and digital calibration. The PGA309, in a calibrated
sensor module, can reduce errors to the level approaching the bridge sensor repeatability. Figure 1-1
shows a block diagram of the PGA309. Following is a brief overview of each major function.
+5V
VSD
VSA
REFIN/REFOUT
PGA309
VREF
Power-On
Reset
KREF
Band-Gap
Voltage
Reference
VEXC
S
VOUT
KLIN
Linearization
DAC
VFB
SDA
Interface and Control
Circuitry
Internal
Temp Sense
VTEMP
TEMPIN
Temp ADC
Signals Mux
+5V
SCL
Two-Wire
EEPROM
(SOT23-5)
Temperature
ADC
Temperature ADC
Input Select
SpanTC and OffsetTC Adjust Lookup
Table with interpolation
Coarse
Offset Adjust
PRG
Fine Offset
Adjust
Zero
DAC
VOS
Over-/UnderScale Limits
Bridge
Sensor
2x2 Multiplexer
VIN1
VIN2
Front-End
PGA Out
Front-End PGA
(Gain 4 to 128)
VOUT
Fault Out
VOUT FILT
Fine Gain
Adjust
Gain
DAC
VOUT
Output
Amp
RISO
100W
CL
10nF
RTEMP
TEST
Fault Conditions
Monitoring Circuit
Fault
Out
Int/Ext
Feedback
VFB
VFB
RFB
100W
Test Logic
Output Coarse
Gain Adjust
(2 to 9)
CF
150pF
VSJ
GNDA
GNDD
Figure 1-1. Simplified Diagram of the PGA309
12
Introduction
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Sensor Error Adjustment Range
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1.2
Sensor Error Adjustment Range
The adjustment capability of the PGA309 is summarized in Table 1-1.
Table 1-1. PGA309 Adjustment Capability
Parameter
1mV/V to 245mV/V
Span TC
Over ±3300ppmFS/°C (1)
Span TC nonlinearity
> 10%
Zero offset
±200%FS (2)
Zero offset TC
Over ±3000ppmFS/°C (2)
Zero offset TC nonlinearity
> 10%
Sensor impedance
Down to 200Ω (3)
(1)
(2)
(3)
1.3
Value/Range
FSS (full-scale bridge sensitivity)
Depends on the temperature sensing scheme.
Combined coarse and fine offset adjust.
Lower impedance possible by using a dropping resistor in series with
the bridge.
Gain Scaling
The core of the PGA309 is the precision low-drift and no 1/f noise Front-End Programmable Gain Amplifier
(Front-End PGA). The overall gain of the Front-End PGA + Output Amplifier can be adjusted from 2.7V/V
to 1152V/V. The polarity of the inputs can be switched through the 2x2 input mux to accommodate
sensors with unknown polarity output.
The Front-End PGA provides initial coarse signal gain using a no 1/f noise, auto-zero instrumentation
amplifier. The fine gain adjust is accomplished by the 16-bit attenuating Gain Digital-to-Analog Converter
(Gain DAC). The Gain DAC is controlled by the data in the Temperature Compensation Lookup Table
driven by the Temperature Analog-to-Digital Converter (Temp ADC). In order to compensate for
second-order and higher drift nonlinearity, the span drift can be fitted to piecewise linear curves during
calibration with the coefficients stored in an external nonvolatile EEPROM lookup table.
Following the fine gain adjust stage is the Output Amplifier that provides additional programmable gain.
Two key Output Amplifier connections, VFB and VSJ, are brought out on the PGA309 for application
flexibility. These connections allow for an accurate conditioned signal voltage while also providing a
means for PGA309 output overvoltage and large capacitive loading for RFI/ EMI filtering required in many
end applications.
1.4
Offset Adjustment
The sensor offset adjustment is performed in two stages. The input referred Coarse Offset Adjust DAC
has approximately a ±60mV offset adjustment range for a selected VREF of 5V. The fine offset and the
offset drift are canceled by the 16-bit Zero DAC that sums the signal with the output of the Front-End
PGA. Similar to the Gain DAC, the input digital values of the Zero DAC are controlled by the data in the
Temperature Compensation Lookup Table, stored in external EEPROM, driven by the Temp ADC. The
programming range of the Zero DAC is 0 to VREF, with an output range of 0.1V to VSA − 0.1V.
1.5
Voltage Reference
The PGA309 contains a precision low-drift voltage reference (selectable for 2.5V or 4.096V) that can be
used for external circuitry through the REFIN/REFOUT pin. This same reference is used for the Coarse
Offset Adjust DAC, Zero DAC, Over/Under-Scale Limits and sensor excitation/linearization through the
VEXC pin. When the internal reference is disabled, the REFIN/REFOUT pin should be connected to an
external reference or to VSA for ratiometric-scaled systems.
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Sensor Excitation and Linearization
1.6
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Sensor Excitation and Linearization
A dedicated circuit with a 7-bit + sign DAC for sensor voltage excitation and linearization is provided on
the PGA309. This block scales the reference voltage and sums it with a portion of the PGA309 output to
compensate the positive or negative bow-shaped nonlinearity exhibited by many sensors over their
applied pressure range. Sensors not requiring linearization can be connected directly to the supply (VSA) or
to the VEXC pin with the Linearization DAC (Lin DAC) set to zero.
1.7
ADC for Temperature Sensing
The compensation for the sensor span and offset drifts is driven by the temperature sense circuitry. Either
internal or external temperature sensing is possible. The temperature can be sensed in one of the
following ways:
• Bridge impedance change (excitation current sense, in the positive or negative part of the bridge), for
sensors with large temperature coefficient of resistance (TCR > 0.1%/°C)
• On-chip PGA309 temperature, when the chip is located sufficiently close to the sensor
• External diode, thermistor, or RTD placed on the sensor membrane. An internal 7mA current source
may be register-enabled to excite these types of temperature sensors.
The temperature signal is digitized by the onboard Temp ADC. The output of the Temp ADC is used by
the control digital circuit to read data from the Lookup Table in an external EEPROM, and set the output of
the Gain DAC and the Zero DAC to the calibrated values as temperature changes.
An additional function provided through the Temp ADC is the ability to read the VOUT pin back through the
Temp ADC input mux. This provides flexibility for a digital output through either One-Wire or Two-Wire
interface, as well as the possibility for an external microcontroller to perform real-time custom calibration of
the PGA309.
1.8
External EEPROM and Temperature Coefficients
The PGA309 uses an industry-standard Two-Wire external EEPROM (typically, a SOT23-5 package). A
1k-bit (minimum) EEPROM is needed when using all 17 temperature coefficients. Larger EEPROMs may
be used to provide user space for serial number, lot code, or other data.
The first part of the external EEPROM contains the configuration data for the PGA309, with settings for:
• Register 3—Reference Control and Linearization
• Register 4—PGA Coarse Offset and Gain/Output Amplifier Gain
• Register 5—PGA Configuration and Over/Under-Scale Limit
• Register 6—Temp ADC Control
This section of the EEPROM contains its own individual checksum (Checksum1).
The second part of the external EEPROM contains up to 17 temperature index values and corresponding
temperature coefficients for the Zero DAC and Gain DAC adjustments with measured temperature and
contains its own checksum (Checksum2). The PGA309 lookup logic contains a linear interpolation
algorithm for accurate DAC adjustments between stored temperature indexes. This approach allows for a
piecewise linear temperature compensation of up to 17 temperature indexes and associated temperature
coefficients.
If either Checksum1, Checksum2, or both are incorrect, the output of the PGA309 is set to
high-impedance.
1.9
Fault Monitor
To detect sensor burnout or a short-circuit, a set of four comparators are connected to the inputs of the
Front-End PGA. If any of the inputs are taken to within 100mV of ground or VEXC, or violate the input CMR
of the Front-End PGA, then the corresponding comparator sets a sensor fault flag that causes the
PGA309 VOUT to be driven within 100mV of either VSA or ground, depending upon the alarm configuration
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Over-Scale and Under-Scale Limits
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setting (Register 5—PGA Configuration and Over/Under-Scale Limit). This will be well above the set
over-scale limit level or well below the set under-scale limit level. The state of the fault condition can be
read in digital form in Register 8—Alarm Status Register. If the Over/Under-Scale Limit is disabled, the
PGA309 output voltage will still be driven within 100mV of either VSA or ground, depending upon the alarm
configuration setting.
There are five other fault detect comparators that help detect subtle PGA309 front-end violations that
could otherwise result in linear voltages at VOUT that would be interpreted as valid states. These are
especially useful during factory calibration and setup and are configured through Register 5—PGA
Configuration and Over/Under-Scale Limit. Their status can also be read back through Register 8—Alarm
Status Register.
1.10 Over-Scale and Under-Scale Limits
The over-scale and under-scale limit circuitry combined with the fault monitor circuitry provides a means
for system diagnostics. A typical sensor-conditioned output may be scaled for 10% to 90% of the system
ADC range for the sensor normal operating range. If the conditioned pressure sensor is below 4%, it is
considered under-pressure; if over 96%, it is considered over-pressure.
The PGA309 over/under-scale limit circuit can be programmed individually for under-scale and over-scale
that clip or limit the PGA309 output. From a system diagnostic view, 10% to 90% of ADC range is normal
operation, < 4% is under-pressure, and > 96% is over-pressure. If the fault detect circuitry is used, a
detected fault will cause the PGA309 output to be driven to positive or negative saturation. If this fault flag
is programmed for high, then > 97% ADC range will be a fault; if programmed for low, then < 3% ADC
range will be a fault. Now the system software can be used to distinguish between over- or under-pressure
condition, which indicates an out-of-control process, or a sensor fault.
1.11 Power-Up and Normal Operation
The PGA309 has circuitry to detect when the power supply is applied to the PGA309, and reset the
internal registers and circuitry to an initial state. This reset also occurs when the supply is detected to be
invalid, so that the PGA309 is in a known state when the supply becomes valid again. The rising threshold
for this circuit is typically 2.2V and the falling threshold is typically 1.7V. After the power supply becomes
valid, the PGA309 waits for approximately 33ms and then attempts to read the configuration data from the
external EEPROM device.
If the EEPROM has the proper flag set in address location 0 and 1, then the PGA309 continues reading
the EEPROM; otherwise, the PGA309 waits for 1.3 seconds before trying again. If the PGA309 detects no
response from the EEPROM, the PGA309 waits for 1.3 seconds and tries again; otherwise, the PGA309
tries to free the bus and waits for 33ms before trying to read the EEPROM again. If successful (including
valid checksum data), the PGA309 triggers the Temp ADC to measure temperature. For 16-bit resolution
results the converter takes approximately 125ms to complete a conversion. Once the conversion is
complete, the PGA309 begins reading the Lookup Table information from the EEPROM to calculate the
settings for the Gain DAC and Zero DAC. This process is detailed in the flowchart shown in Figure 3-1.
The PGA309 reads the entire Lookup Table so that it can determine if the checksum for the Lookup Table
is correct. Each entry in the Lookup Table requires approximately 500ms to read from the EEPROM. Once
the checksum is determined to be valid, the calculated values for the Gain and Zero DACs are updated
into their respective registers, and the Output Amplifier is enabled. The PGA309 then begins looping
through this entire procedure, starting with reading the EEPROM configuration registers, then starting a
new conversion on the Temp ADC, which then triggers reading the Lookup Table data from the EEPROM.
This loop continues indefinitely.
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Digital Interface
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1.12 Digital Interface
There are two digital interfaces on the PGA309. The PRG pin uses a One-Wire, UART-compatible
interface with bit rates from 4.8Kbits/s to 38.4Kbits/s. The SDA and SCL pins together form an industry
standard Two-Wire interface at clock rates from 1kHz to 400kHz. The external EEPROM uses the
Two-Wire interface. Communication to the PGA309 internal registers, as well as to the external EEPROM,
for programming and readback can be conducted through either digital interface.
It is also possible to connect the One-Wire communication pin, PRG, to the VOUT pin in true three-wire
sensor modules and still allow for programming. In this mode, the PGA309 Output Amplifier may be
enabled for a set time period and then disabled again to allow sharing of the PRG pin with the VOUT
connection. This allows for both digital calibration and analog readback during sensor calibration in a
three-wire sensor module.
The Two-Wire interface has timeout mechanisms to prevent bus lockup from occurring. The Two-Wire
master controller in the PGA309 has a mode that attempts to free up a stuck-at-zero SDA line by issuing
SCL pulses, even when the bus is not indicated as idle after the timeout period has expired. The timeout
will only apply when the master portion of the PGA309 is attempting to initiate a Two-Wire communication.
1.13 Pin Configuration
VEXC
1
16 REFIN/REFOUT
GNDA
2
15 TEMPIN
VSA
3
14 SDA
VIN1
4
13 SCL
VIN2
5
12 PRG
VFB
6
11 GNDD
VOUT
7
10 VSD
VSJ
8
9
TEST
Figure 1-2. PGA309 Pin Assignments
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Pin Configuration
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Table 1-2. PGA309 Pin Descriptions
Pin
Name
Description
1
VEXC
Bridge sensor excitation. Connect to bridge if linearization and/or internal reference for bridge
excitation is to be used.
2
GNDA
Analog ground. Connect to analog ground return path for VSA. Should be same as GNDD.
3
VSA
Analog voltage supply. Connect to analog voltage supply. To be within 200mV of VSD.
4
VIN1
Signal input voltage 1. Connect to + or – output of sensor bridge. Internal multiplexer can
change connection internally to Front-End PGA.
5
VIN2
Signal input voltage 2. Connect to + or – output of sensor bridge. Internal multiplexer can
change connection internally to Front-End PGA.
6
VFB
VOUT feedback pin. Voltage feedback sense point for over/under-scale limit circuitry. When
internal gain set resistors for the Output Amplifier are used, this is also the voltage feedback
sense point for the Output Amplifier.
VFB in combination with VSJ allows for ease of external filter and protection circuits without
degrading the PGA309 VOUT accuracy. VFB must always be connected to either VOUT or the
point of feedback for VOUT, if external protection is used.
7
VOUT
Analog output voltage of conditioned sensor.
8
VSJ
Output Amplifier summing junction. Use for Output Amplifier compensation when driving large
capacitive loads (> 100pF) and/or for using external gain setting resistors for the Output
Amplifier.
9
TEST
10
VSD
Test/External Controller Mode pin. Pull to GNDD in normal mode.
11
GNDD
Digital ground. Connect to digital ground return path for VSD. Should be same as GNDA.
12
PRG
Single-wire interface program pin. UART-type interface for digital calibration of the PGA309
over a single wire. Can be connected to VOUT for a three-lead (VS, GND, VOUT) digitally
programmable sensor assembly.
13
SCL
Clock input/output for Two-Wire, industry-standard compatible interface for reading and
writing digital calibration and configuration from external EEPROM. Can also communicate
directly to the registers in the PGA309 through the Two-Wire, industry-standard compatible
interface.
14
SDA
Data input/output for Two-Wire, industry-standard compatible interface for reading and writing
digital calibration and configuration from external EEPROM. Can also communicate directly to
the registers in the PGA309 through the Two-Wire, industry-standard compatible interface.
15
TEMPIN
External temperature signal input. PGA309 can be configured to read a bridge current sense
resistor as an indicator of bridge temperature, or an external temperature sensing device
such as diode junction, or RTD, or thermistor. This input can be internally gained up by 1, 2,
4, or 8. In addition, this input can be read differentially with respect to VGNDA, VEXC, or the
internal VREF. There is also an internal, register-selectable, 7µA current source (ITEMP) that can
be connected to TEMPIN as an RTD, thermistor, or diode excitation source.
16
REFIN/REFOUT
Reference input/output pin. As an output, the internal voltage reference (selectable as 2.5V or
4.096V) is avail-able for system use on this pin. As an input, the internal voltage reference
may be disabled and an external voltage reference can then be applied as the reference for
the PGA309.
Digital voltage supply. Connect to digital voltage supply. To be within 200mV of VSA.
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Chapter 2
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Detailed Description
This chapter provides a detailed description of the PGA309.
Topic
...........................................................................................................................
.....................................................................................................
...........................................................................
2.2
Offset Scaling ...................................................................................................
2.3
Zero DAC and Gain DAC Architecture ..................................................................
2.4
Output Amplifier ................................................................................................
2.5
Reference Voltage .............................................................................................
2.6
Linearization Function .......................................................................................
2.6.1 System Definitions .....................................................................................
2.6.2 Key Linearization Design Equations ................................................................
2.6.3 Key Ideal Design Equations ..........................................................................
2.7
Temperature Measurement .................................................................................
2.7.1 Temp ADC Start-Convert Control ...................................................................
2.7.2 External Temperature Sensing with an Excitation Series Resistor .............................
2.8
Fault Monitor ....................................................................................................
2.9
Over/Under Scale ..............................................................................................
2.10 Noise and Coarse Offset Adjust ..........................................................................
2.11 General AC Considerations ................................................................................
2.1
Gain Scaling
2.1.1
PGA309 Transfer Function
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20
22
24
25
26
29
30
33
33
34
37
42
43
45
48
53
58
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Gain Scaling
2.1
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Gain Scaling
The PGA309 contains three main gain blocks for scaling differential input bridge sensor signals, as shown
in Figure 2-1. The Front-End PGA contains the highest gain selection to allow for the highest
signal-to-noise ratio by applying the largest gain at the front of the signal chain before the addition of other
noise sources. The Front-End PGA gain select has eight gain settings (4, 8, 16, 23.27, 32, 42.67, 64, and
128) and is set by Register 4 bits (11:8). Bit 11 selects the polarity of the input mux.
PGA309 Differential Gain Range
2.6666 to 1152
Zero
DAC
VINN
VIN2
VDIFF
VIN1
Gain
Network
Input
Mux
VINP
VOUT
Gain
DAC
Front-End PGA
4, 8, 16, 23.27,
Fine Gain Adjust
32, 42.64,
0.3333 to 1
64, 128
16-Bit Resolution
Output Amplifier
2, 2.4, 3, 3.6,
4.5, 6, 9
NOTE: VOUT = [(VDIFF + VCOARSE OFFSET)(Front-End PGA Gain) + VZERO DAC][Gain DAC][Output Amplifier Gain]
Figure 2-1. Gain Blocks of the PGA309
The Front-End PGA is followed by the Gain DAC. The fine gain adjust is controlled by the 16-bit Gain
DAC and is adjustable from 0.3333 to 1. Register 2 is used only for the Gain DAC setting.
Final signal gain is applied through the Output Amplifier, which has an internal select of seven gain
settings (2, 2.4, 3, 3.6, 4.5, 6, 9). The Output Amplifier has a selection to disable the internal gain and
allow user-supplied external resistors to set the Output Amplifier gain. Register 4 bits (14:12) select the
internal Output Amplifier gains, except when programmed with ‘111’ when the internal feedback is
disabled. The combined gain blocks allow for a VOUT/VDIFF signal gain of 2.666 (400kHz bandwidth) to 1152
(60kHz bandwidth).
The Front-End PGA of the PGA309 is a three op amp instrumentation amplifier for optimum rejection of
common-mode voltages. This instrumentation amplifier is constructed using op amps with auto-zero
front-ends to virtually eliminate 1/f noise.
As with any instrumentation amplifier, there are limitations on the output voltage swing and input
common-mode voltage range. The circuit in Figure 2-2 is representative of the Front-End PGA inside of
the PGA309 and is used to evaluate critical internal node voltages to ensure that output voltage swing and
common-mode limits are not violated. It is possible to violate the limits of these internal nodes and still
have apparently valid output voltages at VOUT of the PGA309. There are internal comparators that can be
set to monitor these internal nodes to indicate an out-of-limit condition during sensor calibration (see
Section 2.8, Fault Monitor).
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VDIFF = VINP - VINN
VDIFF = 2.550V - 2.450V
VDIFF = 100mV
VZERO DAC = 0.290875V
ZeroDAC = 3813 counts
(VREF = +5V)
VCM = (VINP + VINN)/2
VCM = (2.550V - 2.450V)/2
VCM = 2.5V
+5V
Front-End PGA Gains
VFRONT/VDIFF
G = 1 + 2 RF/RG
4
8
16
23.27
32
42.67
64
128
1
2
4
5.8175
8
10.6675
16
32
VFRONT/VDIFF = 23.27
G = 5.8175
VS = +5V
1.96kW
2.04kW
2.550V
2.04kW
1.96kW
+5V
VREF
0.1V < VOA2 < VS - 0.12V
VOA2 = VCM + G(VDIFF/2)
VDIFF
2.450V
VZERO DAC
16-Bit
DAC
+5V
4R
VINP
2.55V
Converts
to
VIN1
A2
AutoZero
A3
Front-End
PGA Gain
VDIFF
VCM
2.5V
PGA
Difference
Amplifier
RF
VDIFF/2
50mV
Zero DAC
R
RF
A1
VDIFF/2
50mV
VINN
AutoZero
RG
R
4R
VFRONT =
VDIFF(Front-End PGA Gain) +
VZERO DAC
= 2.327V + 0.290875V
= 2.617875V
(2)
AutoZero
VIN2
2.45V
Input Mux
VOA1 = VCM - G(VDIFF/2)
0.1V < VOA1 < VS - 0.12V
(1)
(1)
Input mux allows for sensor output polarity reversal.
(2)
PGA difference amplifier gain of 4 allows full range out of Zero DAC and full voltage swing out of A1 and A2
without common-mode violation on A3 input.
Figure 2-2. Front-End PGA Gain—Internal Node Calculations
After choosing appropriate scaling for the PGA309 gain blocks, a simple hand analysis can check for
internal node limit violations. It is important to convert the PGA309 input voltages (VINP, VINN) to
common-mode and differential components for the maximum sensor output. The model for this conversion
is illustrated in Figure 2-2. The Front-End PGA has a gain of 4 in difference amplifier A3. To analyze
important internal nodes VOA1 and VOA2, it is necessary to assign the proper gain factor (G) to op amps A1
and A2. This is detailed in Figure 2-2 with the respective equations for the output voltages shown at the
appropriate nodes. For maximum VDIFF output of the sensor, VOA1 and VOA2 are within the allowed voltage
swing of: 0.1V < (VOA1 or VOA2) < VS − 0.12. Or, for this example: 0.1V < (VOA1 or VOA2) < 4.88V.
Other applications may yield different results that require different gain scaling or a resistor in the positive
or negative leg of the sensor excitation path to adjust the common-mode input voltage of the PGA309.
The maximum allowable input voltage range (IVR) of the PGA309 is specified as 0.2V < IVR < VSA − 1.5V,
which for this application translates to 0.2V < IVR < 3.5V. In Figure 2-2 we see VINP = 2.550V and VINN =
2.450V, which is within the acceptable IVR specification.
The output (VFRONT) of difference amplifier A3 has a gain of 4 in it for voltages out of A2 and A1, but a gain
of 1 for voltages out of the Zero DAC. VFRONT is shown with the contribution from VDIFF times the Front-End
PGA gain plus the Zero DAC output voltage. The VFRONT signal is further processed through the Gain DAC
and Output Amplifier gain blocks.
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Gain Scaling
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Figure 2-3 depicts the Gain DAC and Output Amplifier gain blocks inside the PGA309. For this example
the Gain DAC was set to 0.859475571 and the Output Amplifer to a gain of 2. As shown in Figure 2-3, the
net output voltage, VOUT, is 4.5V for the maximum VDIFF output of the sensor.
For VOUT MIN, the sensor output of 0V:
VOUT MIN = VZERO DAC [(Gain DAC)(Output Amplifier Gain)]
For this example:
VOUT
MIN
= 0.290908813V [(0.859475571)(2)] = 0.5000V
The Output Amplifier has external connections, which allow the end-user maximum flexibility in Output
Amplifier configurations for a variety of applications. The use of the VFB and VSJ pins, are described in
Section 2.4, Output Amplifier.
Example 2-1 shows the procedure for solving for gain settings.
VOUT = [VFRONT (Gain DAC)] [Output Amplifier Gain]
+5V
Front-End
PGA
2.327V + 0.290875V = 2.617875V
VFRONT
Fine Gain Adjust
0.333333 < Fine Gain < 1
16-Bit DAC
51,722 counts = (0.859476725)
Output Amplifier
Gain DAC
4.5V
VOUT
RISO
100W
0.1 < VOUT < VS - 0.1V
INT/EXT FB Select
Allows for Other Output Amplifier
External Gain Settings
RFO
Output Gain Select
2, 2.4, 3, 3.6, 4.5, 6, 9
RGO
VFB
Allows for accurate
dc feedback when
using RISO
RFB
100W
CL
> 100pF
RLOAD
CF
VSJ
Allows for CL compensation,
external gain resistors, and filtering
NOTE: VOUT = [(VDIFF + VCOARSE OFFSET)(Front-End PGA Gain) + VZERO DAC][Gain DAC][Output Amplifier Gain]
Figure 2-3. Fine Gain Adjust of the PGA309
2.1.1 PGA309 Transfer Function
Equation 1 shows the mathematical expression that is used to compute the output voltage, VOUT. This
equation can also be rearranged algebraically to solve for different terms. For example, during calibration,
this equation is rearranged to solve for VIN.
(
(
VOUT = [ mux_sign ? VIN + VCoarse_Offset ? GI + VZero_DAC ] ? GD ? GO
(1)
Where:
mux_sign: This term changes the polarity of the input signal; value is ±1.
VIN: The input signal for the PGA309; VIN1 = VINP, VIN2 = VINN.
VCoarse_Offset: The coarse offset DAC output voltage.
GI: Input stage gain.
VZero_DAC: Zero DAC output voltage.
GD: Gain DAC.
GO: Output stage gain.
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Example 2-1. Solving For Gain Settings
An example bridge sensor application will be used to examine internal nodes of the PGA309 that are related
to the gain blocks (refer to Figure 2-2 and Figure 2-3).
Given:
Full-Scale Bridge Sensitivity (FSS) = 20mV/V (sensor span)
VOS = 0mV (sensor offset)
VREF = +5V (sensor excitation)
VB = +5V, VS = +5V
RBRG = 2kΩ
VOUT MIN = +0.5V
VOUT MAX= +4.5V
Find:
Front-End PGA Gain
Gain DAC Setting
Zero DAC Setting
Output Amplifier Gain
Solution:
1. Maximum Sensor Output:
VBRmax = (FSS)(VB)
VBRmax = (20mV/V)(5V)
VBRmax = 100mV
2. Total Desired Gain:
GT = (VOUT MAX − VOUT MIN)/VBRmax
GT = (4.5V − 0.5V)/100mV
GT = 40
3. Partition the Gain; Determine the Desired Gain DAC Setting:
Choose Front-End PGA Gain = 23.27
Choose Output Amplifier Gain = 2
Gain DAC = 0.859475719
Gain DAC = GT/[(Front-End PGA)(Output Amplifier Gain)]
Gain DAC = 40/[(23.27)(2)]
Gain DAC = 0.859475719
4. Calculate exact programmable Gain DAC value:
Decimal # counts = (Gain DAC − 1/3)(3/2)(65536)
Decimal # counts = (0.859475719 − 1/3)(3/2)(65536) = 51,721.90133
Use 51,722 counts→CA0Ah→1100 1010 0000 1010 →0.859476725
Gain DAC = (# counts/65536)(2/3)+(1/3)
5. Calculate Zero DAC value
VZERO DAC = VOUT MIN/[(Gain DAC)(Output Amplifier Gain)]
VZERO DAC = 0.5V/[(0.859475571)(2)] = 0.29087505V
Decimal # counts = VZERO DAC/(VREF/65536)
Decimal # counts = 0.29087505/(5/65536) = 3812.55746
Use 3813 counts→0EE5h→0000 1110 1110 0101 →0.290908813V
VZERO DAC = (# counts/65536)(VREF)
6. Calculate VCM and VDIFF for Maximum Sensor Output (see Figure 2-2): VDIFF = VINP − VINN
VDIFF = 2.550 − 2.450
VDIFF = 100mV; VDIFF/2 = 50mV
VCM = (VINP + VINN)/2
VCM = (2.550V + 2.450V)/2
VCM = 2.5V
7. Check Internal Nodes VOA2 and VOA1: Front-End PGA Gain = 23.27
G = 5.8175 (see Figure 2-2)
VOA1 = VCM − G(VDIFF/2)
VOA1 = 2.5V − 5.8175(50mV)
VOA1 = 2.209125
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Offset Scaling
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Example 2-1. Solving For Gain Settings (continued)
VOA2 = VCM + G(VDIFF/2)
VOA2 = 2.5V + 5.8175(50mV)
VOA2 = 2.790875
0.1V ≤ VOA1 and VOA2 ≤ VS − 0.12V
0.1V ≤ VOA1 and VOA2 ≤ 4.88V
Therefore, VOA1 and VOA2 are valid.
8. Check Internal Nodes VOA3 (VFRONT):
VFRONT = VDIFF (Front-End PGA Gain) + VZERO DAC
VDIFF MIN = 0V
VDIFF MAX = 100mV
Front-End PGA Gain = 23.27
VZERO DAC = 0.290908813V
VFRONT MIN = (0)(23.27) + 0.290908813V = 0.290908813V
VFRONT MAX = (100mV)(23.27) + 0.290908813V = 2.6179V
0.05V < VFRONT MIN and VFRONT MAX < VSA − 0.1V
0.05V < 0.290908813V and 2.6179V < VSA − 0.1V
VFRONT OK!
2.2
Offset Scaling
The coarse offset adjust is implemented before the Front-End PGA gain to allow for maximum dynamic
range. Many bridge sensors have initial offsets comparable to their maximum scale outputs. The coarse
offset adjust can be applied as positive or negative. It is implemented in a 4-bit DAC + sign and contains
14 positive selections, 14 negative selections, and zero.
The resolution in either the positive or negative range is VREF/1200. For a +5V reference, this translates to
4.2mV steps. Figure 2-4 depicts the PGA309 with the gain settings used for the example bridge sensor
application detailed in Section 2.1, Gain Scaling.
+5V
VREF
+5V
2.0136kW
1.9864kW
2.483V
-34mV
1.9864kW
2.0136kW
2.517V
VCOS
34mV
10LSBs =
34mV + sign
VIN1
2.483V
VZERO DAC RTO = (VZERO DAC)(Gain DAC)(Output Amplifier Gain)
VZERO DAC
+sign/-sign
17mV
VCOS/2
VINP
2.5V
R
VCOS/2
RG
RF
VCM
2.5V
VDIFF/2
17mV
Sensor at 0 psi
Offset = -34mV
Common-Mode = +2.5V
A1
VCOS/2
AutoZero
VINN
2.5V
VIN2
2.517V
Zero DAC
4R
PGA
Differential
Amplifier
A3
RF
Front-End
PGA
Fine Offset Adjust
2%VREF < RANGE < 98%VREF
1LSB = VREF/65536
16-Bit
DAC
A2
AutoZero
VDIFF/2
17mV
+5V
VREF
Coarse Offset Adjust
-3
1LSB = (VREF)(0.85e )
4-Bit + Sign
DAC
AutoZero
R
Zero DAC (VZERO DAC) = 0.290875V
(VREF = +5V, 3813 counts)
VZERO DAC RTO (referred to output) = 0.5V
(VREF = +5V, 3813 counts)
Fine
Gain
Adjust
Output
Amplifier
Gain
Gain DAC =
0.859475571
Output
Amplifier
Gain = 2
4R
VOUT
Front-End PGA
Gain = 23.27
VCOS/2
17mV
NOTE: VOUT = [(VDIFF + VCOARSE OFFSET)(Front-End PGA Gain) + VZERO DAC][Gain DAC][Output Amplifier Gain]
Figure 2-4. Coarse and Fine Offset Adjust
24
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The conversion of the bridge initial differential offset plus its common-mode to the differential plus
common-mode voltage source model is shown in Figure 2-4 for an initial bridge sensor offset of −34mV
(VINP – VINN). Conceptually, this divides into two 17mV offset voltages with polarities as shown. If the
coarse offset adjust is set for +34mV offset (VINP – VINN), then the initial bridge offset is cancelled exactly.
Any residual initial bridge offset not cancelled by the coarse offset adjust will be gained up by the
Front-End PGA gain and needs to be accounted for when setting the fine offset adjust by using the Zero
DAC.
The coarse offset adjust is set by Register 4 bits (4:0), with bit 4 determining the coarse offset polarity as
negative for a ‘1’ and positive for a ‘0’. The internal architecture of the coarse offset adjust does yield
duplicate digital codes for both −7(VREF)(0.85e−3) and +7(VREF)(0.85e–3). See Section 6.2.5, Register 4, for
a complete mapping of the coarse offset adjust settings.
The fine offset adjust is set by the Zero DAC. The Zero DAC setting is gained by the Gain DAC and the
Output Amplifier gain and is referred-to-output (RTO). The Zero DAC is a unipolar, 16-bit DAC, with its
reference being the VREF setting of the PGA309. The range of the Zero DAC is ensured to be linear from
2%VREF to 98%VREF, for VREF = +5V (for VREF < +5V, the upper end of the Zero DAC range can extend to
VREF). The Zero DAC analog range is 0.1V ≤ Zero DAC analog range ≤ (VSA − 0.1V). The Zero DAC
programming range is 0V ≤ Zero DAC programming range ≤ VREF. The data format is 16-bit unsigned.
Register 1 bits (15:0) are used for the Zero DAC setting.
2.3
Zero DAC and Gain DAC Architecture
Two 16-bit DACs are incorporated into the PGA309 for fine adjustment of the Zero DAC and Gain DAC.
These DACs are based on a Resistor String (R-String) architecture with very low integral and differential
nonlinearities.
The Zero DAC incorporates a buffer amplifier in a gain of 2V/V. The DAC resistor string is connected
between the REFIN/REFOUT (VREF voltage) pins and GNDA. The input digital value adjusts the point on the
resistor string where the noninverting amplifier input is connected between 0 × VREF to 0.5 × VREF, thus
adjusting the Zero DAC output voltage from 0V to VREF. Due to the device output saturation of the buffer
amplifier, the linearity of the Zero DAC is specified from 2% to 98% of the digital scale with VREF = VSA.
However, for cases when VREF < VSA (for example, when using the PGA309 internal reference), the Zero
DAC is linear to 100% of full-scale.
The Gain DAC uses a similar R-String architecture. However, the Output Amplifier is performing the
function of the buffer amplifier. The R-String of the DAC is connected between the output of the Front-End
PGA, VFRONT, and GNDA (see Figure 2-3). The input digital value adjusts the value of the noninverting
amplifier input between 1/3 × VFRONT to 1 × VFRONT, thus setting the attenuation factor of the Gain DAC from
0.333V/V to 1V/V with 16-bit precision.
The output of both the Zero and Gain DACs are calculated and adjusted on every Temp ADC
measurement according to the Lookup Table stored in EEPROM (see Section 3.2, EEPROM Content and
Lookup Table Calculation). This leads to DAC code adjustments on small temperature changes. Unlike
some string DACs, the proprietary switch architecture of the PGA309 Zero and Gain DACs allows
switching with very low glitch energy and essentially no dependency on the code being changed. The
glitch energy is normally lower than the voltage noise level at the output of the PGA309.
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Output Amplifier
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Output Amplifier
The Output Amplifier section of the PGA309 is configured to allow maximum flexibility and accuracy in the
end application. Figure 2-5 depicts the Output Amplifier in a common three-terminal sensor application. In
this application, it is desired to provide overvoltage protection due to mis-wires on the output of the
PGA309, as well as a 10nF capacitor on the sensor module output for EMI/RFI filtering. In this
configuration, RISO and RFB provide overvoltage protection on VOUT FILT to 16V by limiting the current into
VOUT and VFB to about 150mA [(16V − 0.7V)/100Ω]. The 0.7V drop results from the internal ESD structure
to GND or VSA. In addition, RISO serves to isolate the 10nF RFI/ EMI capacitive load from VOUT. RFB adds a
slight gain error that is calibrated out with the PGA309 + sensor calibration. Note that the point of
feedback around the Output Amplifier is taken from VOUT FILT and as such, after PGA309 + sensor
calibration, the Output Amplifier will accurately scale VOUTFILT to match the desired conditioned sensor
voltage. CF provides a second feedback path around the Output Amplifier for stability. With the
configuration shown, the Output Amplifier is stable for internal Output Amplifier gains from 2 (125kHz
bandwidth, 63° loop gain phase margin, typical values) to 9 (64kHz bandwidth, 86° loop gain phase
margin, typical values). Table 2-1 details the typical Output Amplifier resistor values for RFO and RGO, as
well as open-loop output resistance. These values, combined with the typical Output Amplifier open-loop
gain curve and standard op amp stability techniques, allow the Output Amplifier to be tailored and
configured for the specific sensor application.
VSA
PGA309
Output
Amplifier
VSD
Interface
and
Control
Circuitry
SDA
SCL
Two-Wire
EEPROM
PRG
Front-End
PGA Out
VS
Fine Gain Adjust
(Gain DAC)
VOUT
Output
Amp
RISO
100W
~150mA
VOUT FILT
16V
INT/EXT FB Select
RFO
VFB
RFB
100W
~150mA
Mis-wire
Fault
Condition
GND
CL
10nF
Output Gain Select
(1-of-7)
Range of 2 to 9
CF
150pF
RGO
Shows current in case of
output mis-wiring or
overvoltage.
VSJ
GNDA
GNDD
Figure 2-5. Output Amplifier in a Common 3-Terminal Sensor Application
Table 2-1. Output Amplifier Typical Gain Resistor Values (1)
(1)
26
Gain
RFO
Typical
(kΩ)
RGO
Typical
(kΩ)
2
18
18
2.4
21
15
3
24
12
3.6
26
10
4.5
28
8
6
30
6
9
32
4
RO = open-loop output impedance = 675Ω, typical at f = 1MHz, IOUT = 0.
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In addition to using its own internal gain setting resistors, RFO and RGO, the Output Amplifier may use
external feedback resistors RFOEXT and RGOEXT, as shown in Figure 2-6. Table 2-2 details the bits used in
Register 4 for the desired Output Amplifier gain configurations. To use the external feedback resistors, set
GO2, GO1, and GO0 to all 1s. In addition to allowing external feedback resistors to be used, this
configuration provides a handy mechanism for testing the Output Amplifier stability, even if internal gain
settings are to be used. As shown in Figure 2-6, external feedback resistors RFOEXT and RGOEXT are both
set to 18kΩ, equivalent to the typical resistor values used for an internal gain setting of 2. If VOUT is biased
to mid-scale (+2.5V for VSA = +5V) through the Zero DAC and by setting VDIFF = 0V, a signal generator
may be used to inject a 200mVPP square wave (1kHz) into the end of RGOEXT and a response measured at
VOUT. This provides a transient response for the Output Amplifier in a given configuration. Standard
stability transient response criteria for a dominant two-pole system may be used to determine suitable
phase margin based upon the measured overshoot and ringing on VOUT.
VOUT
VSA
PGA309
Output
Amplifier
VSD
Interface
and
Control
Circuitry
SDA
SCL
t
Two-Wire
EEPROM
PRG
Front-End
PGA Out
VS
Fine Gain Adjust
(Gain DAC)
Output
Amp
RISO
100W
VOUT
VOUT FILT
RFO
Output Gain Select
(1-of-7)
Range of 2 to 9
CL
10nF
RFB
100W
INT/EXT FB Select
VFB
GND
RFOEXT
18kW
CF
150pF
RGO
VSJ
GNDA
RGOEXT
18kW
GNDD
VTEST
+100mV
-100mV
f = 1kHz
Figure 2-6. Output Amplifier Using External Feedback Resistors RFOEXT and RGOEXT
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Output Amplifier
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Table 2-2. Output Amplifier Gain Selections—Register 4
GO2
[14]
GO1
[13]
GO0
[12]
Output Amplifier Gain
0
0
0
2
0
0
1
2.4
0
1
0
3
0
1
1
3.6
1
0
0
4.5
1
0
1
6
1
1
0
9
1
1
1
Disable Internal Feedback
For low-supply applications, the minimum gain for the Output Amplifier is related to its IVR and output
voltage swing. In Figure 2-7, the supply is lowered to +2.7V. The tested IVR of the Output Amplifier is 0V
to VSA−1.5V, as reflected in Figure 2-7. The output voltage swing is tested to be 0.1V to +2.6V for a 10kΩ
load, as shown. This calculates to a minimum gain of 2.08. For best performance, the Output Amplifier
should be scaled for a minimum gain of 2.4 for this application. Usually, this is only a factor at lower
voltages but is easily checked for each individual application.
VSA
+2.7V
+1.2V
+2.6V
IVR
VIN+
VOUT
0V
+0.1V
RGO
RFO
Output Amplifier Gain Minimum = VOUT/VIN+ = +2.5V/+1.2V = 2.08
Use 2.4
Figure 2-7. Output Amplifier Minimum Gain at Low Supply
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Reference Voltage
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2.5
Reference Voltage
The PGA309 can be configured for use with an internal or external voltage reference. The reference
voltage is used by the Zero DAC, Over/Under-Scale Limit, Coarse Offset Adjust DAC, Temp ADC, and
Bridge Excitation Linearization Circuit. Figure 2-8 depicts the PGA309 reference circuit. If internal
reference is selected, either 2.5V or 4.096V can be chosen. In this mode, a typically better than 2% initial
accuracy, low drift, ±10ppm/°C reference is available for internal and external use. Up to 5mA can be
supplied through the REFIN/REFOUT pin in internal reference mode. If external reference mode is chosen,
then an external reference from +2.0V to +VSA may be applied to the REFIN/REFOUT pin. During power-on,
the external reference mode is selected. Table 2-3 details the Register 3 bits (9:8) used for the reference
mode selections.
VS
VS
Supply
External
Reference
REFIN/REFOUT
VREF Enable/Disable Select
VREF
Bandgap
Reference
RFB
RSET
VREF Internal Set
(2.5V or 4.096V)
PGA309
Figure 2-8. PGA309 Reference Circuit
Table 2-3. Register 3 Reference Control Bits
D9
D8
RS
REN
VREF
Reference Configuration
X
0
REFIN/REFOUT
External Reference
(disable internal reference)
0
1
4.096V
Internal Reference
1
1
2.5V
Internal Reference
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Linearization Function
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Linearization Function
Many bridge sensors have an inherently nonlinear output with applied pressure. Figure 2-9 illustrates a
typical nonlinearity correction using the PGA309 linearization circuit.
2.7
Uncorrected
Bridge Output
2.4
Nonlinearity (%FSR)
2.1
1.8
1.5
1.2
0.9
0.6
Corrected
Bridge Output
0.3
0
-0.3
0
1
2
3
4
5
6
7
8
9
10
Bridge Output (mV)
Figure 2-9. Bridge Pressure Nonlinearity Correction
The PGA309 contains a dedicated circuit for sensor voltage excitation and linearization, as shown in
Figure 2-10. The Linearization Circuit scales the selected VREF and sums it together with a portion of the
output voltage (VOUT) through the feedback pin (VFB) to compensate for the bow-shaped nonlinearity of the
bridge sensor output versus pressure. Using this technique, it is possible to compensate for parabolic
nonlinearity resulting in up to to a 20:1 improvement over an uncompensated bridge output, as shown in
Figure 2-9. KLIN is a bipolar scale factor of VOUT produced by the Lin DAC. KEXC is a set attenuation factor
of VREF to allow for increases or decreases to VEXC, as required. There are two ranges available in the
Linearization Circuit, with a different respective range and a different respective fixed attenuation for KLIN.
KLIN
VEXC
(3)
PGA309
Bridge Excitation
Linearization Circuit
S
KEXC
VREF
Fine
Offset
DAC
(1)
P
FSS
and
(2)
PNL
Pressure
Sensor
+Sensor Out
VIN1
-Sensor Out
VIN2
VFB
VOUT
(4)
GT
NOTE:
1.
FSS = Full-Scale bridge Sensitivity of sensor.
2.
PNL = Pressure Nonlinearity of sensor.
3.
KLIN = Linearization coefficient set by the Lin DAC.
4.
GT = (Front-End PGA Gain)(Gain DAC)(Output Amplifier Gain).
Figure 2-10. Bridge Excitation Linearization Circuit
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If no sensor voltage excitation linearization is needed, there are several options for the bridge excitation.
In ratiometric systems, the bridge should be tied directly to VSA. In systems that provide an external
reference for VREF, the sensor should be tied to this external sensor. For systems that use the PGA309
internal reference, it is recommended that VEXC be used for sensor excitation, and Lin DAC be set to zero.
The reason for this is to minimize any large current draws from the REFIN/REFOUT pin that could affect the
internal VREF value used by the internal circuits.
In systems that do not use VEXC, both the Lin DAC and VEXC may be disabled by setting the appropriate
Register 3 bits (10, 7:0) to ‘0’. This results in 50mA to 100mA of lower total quiescent current.
The typical bandwidth of the Linearization Circuit from the VFB pin to VEXC is 35kHz.
The output signal-dependence (VOUT dependence) of the bridge excitation (VEXC) adds a second-order term
to the overall system transfer function (PGA309 + bridge sensor). The Lin DAC shown in Figure 2-11
scales a portion of VOUT that is then summed with a scaled version of the reference voltage, VREF. The Lin
DAC code can be set to compensate for each individual bridge sensor nonlinearity. As illustrated in
Figure 2-11, there are two ranges available in the PGA309 Linearization Circuit to accommodate a variety
of sensor nonlinearities and VREF combinations.
x0.166
(-0.166VFB < VLIN_DAC < +0.166VFB)
7-Bit + Sign
DAC
KLIN
KEXC
S
REFIN/REFOUT
LinDAC
x0.83
4.096V
Range 0
2.5V
Internal Select
VFB
VEXC
x1
Output
Amplifier
VOUT
x0.124
(-0.124VFB < VLIN_DAC < +0.124VFB)
S
7-Bit + Sign
DAC
KLIN
KEXC
REFIN/REFOUT
LinDAC
x0.52
Range 1
4.096V
2.5V
Internal Select
Figure 2-11. Linearization Circuit
To determine the value for the Lin DAC, also called the linearization coefficient KLIN, the nonlinearity of the
bridge sensor with constant excitation voltage must be known. The PGA309 linearization circuitry can only
compensate for the parabolic-shaped portions of a sensor’s nonlinearity with applied pressure. This
nonlinearity is assumed to be constant over temperature or the temperature variations are assumed to be
an insignificant contribution to the system error budget. For the typical PGA309 application, the KLIN factor
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is not adjusted with temperature changes. Optimum correction occurs when maximum deviation from a
linear output occurs at mid-scale, as shown in Figure 2-12 and Figure 2-13. Sensors with nonlinearity
curves similar to that of Figure 2-12, but not peaking at exactly mid-scale, can still be substantially
improved. A sensor with an S-shaped nonlinearity curve (equal positive and negative nonlinearity) cannot
be improved by using the PGA309 Linearization Circuit.
10
9
Bridge Output (mV)
8
Positive Bridge Nonlinearity
BV = +0.025 (+2.5% FSR)
7
6
5
4
Negative Bridge Nonlinearity
BV = -0.025 (-2.5% FSR)
3
2
1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Normalized Stimulus (PIN/PMAX)
Figure 2-12. Bridge Output vs Pressure
3.0
2.4
Nonlinearity (% FSR)
1.8
Positive Bridge Nonlinearity
BV = +0.025 (+2.5% FSR)
1.2
0.6
0
-0.6
Negative Bridge Nonlinearity
BV = -0.025 (-2.5% FSR)
-1.2
-1.8
-2.4
-3.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Normalized Stimulus (P/PMAX)
Figure 2-13. Bridge Nonlinearity (%FSR) vs Pressure
Either positive or negative bridge nonlinearities can be compensated by the proper setting of the Lin DAC
polarity. To correct for positive bridge nonlinearity (upward bowing—shown in Figure 2-13), the Lin DAC
value should be set positive. For negative bridge nonlinearity (downward bowing—shown in Figure 2-13),
set the Lin DAC value negative.
The excitation voltage (VEXC) directly scales the bridge sensor output, and therefore, must be accounted
for in the gain and offset setting of the PGA309 when the linearization circuit is used.
Key definitions and design equations for the linearization circuit are given in the following sections.
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2.6.1 System Definitions
BV: Bridge Nonlinearity with Applied Pressure. Maximum error at mid-scale input range given as a decimal
equivalent of % of full-scale range (%FSR). For Example, %FS: +2.5% FS = 0.025, −2.5% = −0.025.
FSS: Full-Scale Bridge Sensitivity for Sensor at PMAX (i.e., 5mV/V)
GL: Total PGA309 Gain of VOUT/VIN when using the Linearization Circuit.
GT: Total PGA309 Gain of VOUT/VIN.
GT = (Front-End PGA Gain)(Gain DAC)(Output Amplifier Gain).
KEXC: PGA Excitation Coefficient. Scale factor on VREF.
KLIN: PGA309 Linearization Coefficient
KP: Pressure Constant. Converts linear input pressure to nonlinear pressure detected by sensor.
Referenced to full-scale input pressure.
P: Pressure Input to Sensor
PMIN: Minimum Sensor Input Pressure
PMAX: Maximum Sensor Input Pressure
PNL: Nonlinear Pressure Output of Bridge with Linear Pressure Input P
VEXC: Bridge Voltage Excitation (generated by PGA309 based on VREF, KLIN, KEXC, VOUT)
VOUT
MIN
: Minimum PGA309 VOUT Voltage for PMIN Bridge Sensor Input
VOUT
MAX
: Maximum PGA309 VOUT Voltage for PMAX Bridge Sensor Input
VREF: PGA309 Reference Voltage
2.6.2 Key Linearization Design Equations
The focus of this section is to define the design equations used to scale the PGA309 when using the
Linearization Circuit.
Nonlinear Pressure Conversion for Bridge Sensor Parabolic Nonlinearity
PNL = P + 4(BV) · PMAX ·
(
P
P
PMAX
PMAX
( (
2
(
BV = positive for a positive parabolic nonlinearity, BV = negative for a negative parabolic nonlinearity; see
Figure 2-13)
(2)
space
Pressure Constant (PNL referenced to full-scale input pressure)
KP =
KP =
PNL
PMAX
(
P + 4(BV) · PMAX ·
(
P
P
PMAX
PMAX
( (
2
(
(
PMAX
(3)
Linearization Coefficient
KLIN =
4 · BV · VREF · KEXC
(VOUT_MAX - VOUT_MIN) - 2 · BV · (VOUT_MAX + VOUT_MIN)
(4)
Total PGA309 Gain Required When Using Linearization Circuit
GL =
(VOUT_MAX - VOUT_MIN)
(VREF · KEXC · FSS) + (KLIN · VOUT_MAX · FSS)
(5)
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PGA309 VOUT
VOUT =
(FSS · GL · KP · VREF · KEXC) + VOUT_MIN
1 - (FSS · GL · KP · KLIN)
(6)
PGA309 VEXC
VEXC = VREF · KEXC + KLIN · VOUT
(7)
Lin DAC Counts Conversion
Decimal # Counts =
|KLIN|
(Full-Scale Ratio / 127)
where Full-Scale Ratio = 0.166 (Range 0) or 0.124 (Range 1)
(8)
Example 2-2. Lin DAC Counts Conversion
Given:
Range 0: −0.166VFB < Lin DAC < +0.166VFB
Find:
Lin DAC value for KLIN = −0.082
Solution:
1. Absolute value of KLIN = |−0.082| = 0.082
2. Decimal # Counts = 0.082 / (0.166/127) = 62.7349
3. Use 63 counts → 3Fh → 0011 1111
4. However, −0.082 is needed. Add 1 in the sign bit (MSB, Bit 7) for negative ratio
5. Final Lin DAC setting: 1011 1111 → BFh
space
2.6.3 Key Ideal Design Equations
Ideal Gain, G
GIDEAL =
VOUT_MAX - VOUT_MIN
VREF · FSS
(9)
VOUT Ideal as a Function of Pressure, P
VOUT_IDEAL = FSS · GIDEAL ·
( PP ( · V
MAX
REF
+ VOUT_MIN
(10)
Full-Scale Range of Output
FSR = VOUT_MAX - VOUT_MIN
(11)
VOUT Error (%FSR)
VOUT_ERR_FSR = VOUT - VOUT_IDEAL · 100
FSR
(
(
(12)
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Example 2-3. Linearization Design
Value
Units
PMIN
System Inputs
0
psi
PMAX
100
psi
FSS
BV
0.005
V/V
+0.025 (+0.025 = +2.5%)
%FSR
VOUT
MAX
4.5
V
VOUT
MIN
0.5
V
VREF
5
V
KEXC
0.83
PGA309 Calculations for Using Linearization Circuit
KLIN
+0.110667
V/V
GL
172.117
V/V
GIDEAL
160
V/V
FSR
4
V
VOUT
IDEAL
P
(psi)
KP
VOUT
(V)
VEXC
(V)
VOUT IDEAL
(V)
VOUT Error
(%FSR)
0
0.0000
0.5000
4.2053
0.5000
0
10
0.1090
0.8986
4.2494
0.9000
−0.03464537
20
0.2160
1.2981
4.2937
1.3000
−0.04667445
30
0.3210
1.6983
4.3380
1.7000
−0.04126142
40
0.4240
2.0990
4.3823
2.1000
−0.02381898
50
0.5250
2.5000
4.4267
2.5000
1.1102E−14
60
0.6240
2.9010
4.4710
2.9000
0.02430134
70
0.7210
3.3017
4.5154
3.3000
0.04294918
80
0.8160
3.7020
4.5597
3.7000
0.04956629
90
0.9090
4.1015
4.6039
4.1000
0.03753519
100
1.0000
4.5000
4.6480
4.5000
2.2204E−14
space
0.05
0.04
VOUT Error (% FSR)
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
0
10
20
30
40
50
60
70
80
90
100
Pressure (psi)
Figure 2-14. Corrected Bridge Parabolic Nonlinearity vs Pressure
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In each end application, the Linearization Circuit limits should be checked for operation within the allowed
range.
Table 2-5 and Table 2-6 illustrate the linearization range for several typical system applications. These
tables account for the internal limits of the PGA309 linearization circuit and assume that VOUT scaling is to
account for over-scale and under-scale limits and fault detection. For specific end applications not listed,
the following equations may be used to calculate critical design values, once the system design choices
for VREF, VOUTMAX,VOUTMIN and linearization range, are made:
1. VEXC MAX: Use Equation 7 at VOUT MAX
2. VEXC MIN: Use Equation 7 at VOUT MIN
3. BVMAX (maximum nonlinearity that can be compensated): Use KLIN+MAX to calculate +BVMAX and KLIN–MAX to
calculate –BVMAX by Equation 4 solved for BV as:
VOUT_MAX - VOUT_MIN
BV =
4 · VREF · KEXC
+ 4 · (VOUT_MAX + VOUT_MIN)
KLIN
(
(
•
For Range 0:
KLIN −MAX = −0.166
KLIN +MAX = +0.166
• For Range 1:
KLIN −MAX = −0.124
KLIN +MAX = +0.124
4. VLin DAC MAX = ((VREF/4) – VOUT MAX/10) ≥ 300mV
5. VEXC MAX ≤ VSA − 0.5V
6. KLIN −MAX ≤ KLIN ≤ KLIN +MAX
When using the Linearization Circuit, to ensure that the bridge sensor output common-mode voltage
remains within the PGA309 input specifications, Equation 7 can be used to calculate VEXC at full-scale
signal (VOUT MAX). The common-mode voltage (VCM) of the bridge sensor output is one-half of VEXC if no
common-mode or temperature sensing additional resistor is used in series with the bridge sensor.
During the sensor calibration process using the PGA309, a two-step process can be employed. First, the
nonlinearity of the sensor bridge is measured with an initial gain and offset and with KLIN = 0 (Lin DAC set
to Zero). Using the resulting sensor nonlinearity (BV), values for KLIN, Gain, and Offset are calculated. A
second calibration measurement can be taken to adjust KLIN, to account for any offsets and mismatches in
the Linearization Circuit. This calibration procedure is most easily performed using the PGA309 Designer’s
Kit and associated software and calibration spreadsheets, which can be downloaded from www.ti.com.
Table 2-4. PGA309 Recommended Operating
Conditions
Case1
Case2
Case3
Case4
0.057
0.075
0.112
0.075
KLIN
+MAX
SPACE
Range 0
KEXC
KLIN
+MAX
KLIN –MAX
36
0.83
FSS
0.005
V/V
–0.166
0.166
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Table 2-5. Range 0—Typical System Applications and Maximum Nonlinearity Correction
RANGE 0
+BV MAX
(1)
RANGE 0
−BV MAX
RANGE
0
VSA MIN
(V)
VSA MAX
(V)
VREF
(V)
ADC
REF
(V)
G
LinDAC
MAX
> 0.3V?
(V)
2.7
5.5
2.5
2.5
0.175
2.225
0.0136
2.202
2.104
167.73
−0.0454
2.046
1.706
240.38
0.4025
2.7
5.5
2.5
2.048
0.123
1.761
0.0143
2.207
2.095
138.38
−0.0354
2.055
1.783
183.77
0.4489
4.5
5.5
4.096
2.5
0.175
2.175
0.0231
3.761
3.429
106.36
−0.0259
3.371
3.039
131.64
0.8065
4.5
5.5
4.096
4.096
0.246
3.564
0.0371
3.991
3.441
166.26
−0.0447
3.359
2.808
236.32
0.6676
4.5
5.5
4.096
2.048
0.143
1.782
0.0191
3.695
3.423
88.70
−0.0210
3.376
3.104
105.61
0.8458
4.7
5.5
4.5
4.5
0.27
4.185
0.0275
4.204
3.780
176.76
−0.0483
3.690
3.040
257.54
0.7065
5
5.5
5
5
0.3
4.65
0.0188
4.499
4.200
176.76
−0.0483
4.100
3.378
257.54
0.785
VOUT MIN
(V)
VEXC MAX
VOUT MAX
(V)
+BV
(0.025=
2.5%)
(V)
VEXC MIN
(V)
(1)
G
−BV
(−0.025=
−2.5%)
VEXC MAX
(V)
VEXC MIN
(V)
Limited by VEXC saturation voltage of 0.5V.
Table 2-6. Range 1—Typical System Applications and Maximum Nonlinearity Correction (1) (2) (3)
PGA309
VSA
Operating Range
VSA MIN
(V)
(1)
(2)
(3)
2.7
VSA MAX
(V)
PGA309
VREF
VREF
(V)
System
ADC
REF
PGA309
VOUT
Linear Range
PGA309
+BV MAX
PGA309
VEXC Range
for +BV MAX
PGA309
Gain
VOUT/
VDIFF IN
for +BV
MAX
PGA309
−BV MAX
RANGE 0
+BV MAX
ADC
REF
(V)
VOUT MIN
(V)
VOUT MAX
(V)
PGA309
VEXC Range
for −BV MAX
PGA309
Gain
VOUT/
VDIFF IN
for −BV
MAX
RANGE 0
−BV MAX
PGA309
LinDAC
Max
Check
RANGE
0
+BV
(0.025=
2.5%)
VEXC MAX
(V)
VEXC MIN
(V)
GT
−BV
(−0.025=
−2.5%)
VEXC MAX
(V)
VEXC MIN
(V)
GT
LinDAC
MAX
> 0.3V?
(V)
2.7
5.5
2.5
2.5
0.175
2.225
0.0439
1.576
1.322
260.17
−0.0552
1.278
1.024
400.35
0.4025
2.7
5.5
2.5
2.048
0.123
1.761
0.0358
1.518
1.315
215.76
−0.0429
1.285
1.082
302.87
0.4489
4.5
5.5
4.096
2.5
0.175
2.175
0.0272
2.400
2.152
166.69
−0.0312
2.108
1.860
215.03
0.8065
4.5
5.5
4.096
4.096
0.246
3.564
0.0435
2.572
2.160
258.02
−0.0543
2.099
1.688
393.13
0.6676
4.5
5.5
4.096
2.048
0.143
1.782
0.0226
2.351
2.148
139.44
−0.0253
2.112
1.909
171.72
0.8458
4.7
5.5
4.5
4.5
0.27
4.185
0.0464
2.859
2.373
273.88
−0.0588
2.307
1.821
429.97
0.7065
5
5.5
5
5
0.3
4.65
0.0464
3.177
2.637
273.88
−0.0588
2.563
2.023
429.97
0.785
Over-scale and under-scale limits and fault detection desired.
FSS used to calculate a representative gain value (GT) for completeness.
Range 1, KEXC = 0.52, KLIN −MAX = −0.124, KLIN +MAX = 0.124, FSS = 0.005V/V
Temperature Measurement
The center of the PGA309 temperature measurement circuitry is the Temp ADC. The Temp ADC and its
associated PGA, input mux, and REF mux provide a flexible and configurable temperature sensing block
for reading either on-chip or external temperatures. Figure 2-15 illustrates the PGA309 temperature sense
block.
The internal temperature sensing is accomplished by using on-chip diode junctions. The Internal
Temperature Mode is configured through setting the bits in Register 6 to the values shown in Table 2-7
and Table 2-8. The Temp ADC output is presented in Register 0 in 12-bit + sign extended, right-justified,
two’s complement data format (see Table 2-9). The resolution, for the Temp ADC in Internal Temperature
Mode, is 0.0625°C/count and the accuracy is ±2°C. The temperature accuracy is a relative error that is
calibrated out with the PGA309 + sensor calibration to the accuracy of the calibration temperature
measurement equipment.
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REFIN/REFOUT
VREF INT/EXT Select
VSA
Temp ADC
Internal VREF
(2.048V)
ITEMP
7mA
TEMPIN
VEXC
VOUT
VREF Internal Set
(2.5V or 4.096V)
VREFT
Temp
ADC
Input
Mux
15-Bit + Sign
ADC
xG
Temp ADC
Input Mux
Select
RFB
Temp ADC
REF Select
TEMPIN
VREF
Bandgap
Reference
VEXC
VSA
INT Temperature
(on-chip diodes)
ITEMP Enable
VREF
Temp ADC
REF Mux
VREF
Temp ADC
PGA
(1, 2, 4, or 8)
Temperature
Source
Select
RSET
Digital
Controls
Control Registers
Alarm Register
Interface
and
Control
Circuitry
Offset TC Adjust and Span TC Adjust
Lookup Logic with Interpolation Algorithm
SDA
SCL
PRG
PGA309 Temperature Sense Block
Figure 2-15. Temperature Sense Block
Table 2-7. Internal Temperature Mode Configuration—Register 6
38
Bit
Bit Name
Bit State
Configuration
15
RFB
0
Reserved Factory Bit—set to 0 for proper operation
14
RFB
0
Reserved Factory Bit—set to 0 for proper operation
13
ADC2X
0
12
ADCS
0
11
ISEN
0
10
CEN
1
Enable the Temp ADC
9
TEN
1
Internal Temperature Mode selected
8
AREN
0
7
RV1
0
6
RV0
0
5
M1
0
4
M0
0
3
G1
0
2
G0
0
1
R1
1
See Table 2-8.
0
R0
1
See Table 2-8.
Unused for Internal Temperature Mode; set to zero.
Unused for Internal Temperature Mode; set to zero.
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Table 2-8. Internal Temperature Mode Resolution—Register 6
Temp ADC Resolution (Conversion Time) Select
TEN = ‘1’
R1
R0
0
0
9-Bit + Sign, Right-Justified, Sign-Extended, Twos Complement,
0.5°C (3ms)
0
1
10-Bit + Sign, Right-Justified, Twos Complement, Sign-Extended,
0.25°C (6ms)
1
0
11-Bit + Sign, Right-Justified, Twos Complement, Sign-Extended,
0.125°C (12ms)
1
1
12-Bit + Sign, Right-Justified, Twos Complement, Sign-Extended,
0.0625°C (24ms)
Table 2-9. Internal Temperature Mode Data —Register 0 (1)
(1)
Temperature
(°C)
Digital Output (Binary)
AD15…………AD0
Digital Output
(Hex)
128
0000 1000 0000 0000
0800
127.9375
0000 0111 1111 1111
07FF
100
0000 0110 0100 0000
0640
80
0000 0101 0000 0000
0500
75
0000 0100 1011 0000
04B0
50
0000 0011 0010 0000
0320
25
0000 0001 1001 0000
0190
0.25
0000 0000 0000 0100
0004
0.0
0000 0000 0000 0000
0000
−0.25
1111 1111 1111 1100
FFFC
−25
1111 1110 0111 0000
FE70
−55
1111 1100 1001 0000
FC90
−128
1111 1000 0000 0000
F800
The resolution for the Temp ADC in Internal Temperature Mode is 0.0625°C/count.
For Positive Temperatures (for example, +50°C):
Twos Complement is not performed on positive numbers. Therefore, simply convert the number to
binary code with the 16-bit, right-justified format, and MSB = 0 to denote a positive sign. Extend this
sign into the upper 4 bits.
Example: (50°C)/(0.0625°C/count) = 800 = 320h = 0011 0010 0000 Twos Complement 16-bit,
right-justified, sign-extended format = 0000 0011 0010 0000 = 0320h.
For Negative Temperatures (for example, −25°C):
Generate the Twos Complement of a negative number by complementing the absolute value binary
number and adding 1. Extend the sign, denoting a negative number with MSB = 1. Extend the sign to
the upper 4 bits to form the 16-bit word.
Example: (| −25°C|)/(0.0625°C/count) = 400 = 190h = 0001 1001 0000 Twos Complement format: 1110
0111 0000 Extend the sign and create the 16-bit word: 1111 1110 0111 0000 = FE70h
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There are several configurations possible for the Temp ADC when External Temperature Mode is
selected. In this mode, the TEMPIN pin is read to determine temperature. TEMPIN may be referenced to
GND, VEXC, or VREF. VOUT may also be selected to be read relative to GND through the Temp ADC.
Figure 2-16 shows the allowable Temp ADC input mux configurations.
NOTE: In Configuration #3, the VOUT pin is read, not the VFB pin. Therefore, this value may be
different from VOUT FILT. Refer to Figure 1-1 and Figure 2-5.
Temp ADC Input Mux Configuration #2
Register 6[5:4] = '01'
Register 6[M1,M0] = '01'
Temp ADC Input Mux Configuration #1
Register 6[5:4] = '00' (default)
Register 6[M1,M0] = '00' (default)
Positive Input
Positive Input
VEXC
TEMPIN
GNDA
TEMPIN
Negative Input
Negative Input
Temp ADC
PGA
Temp ADC Input Mux Configuration #4
Register 6[5:4] = '11'
Register 6[M1,M0] = '11'
Temp ADC Input Mux Configuration #3
Register 6[5:4] = '10'
Register 6[M1,M0] = '10'
Positive Input
Positive Input
VREF
VOUT
GNDA
Temp ADC
PGA
TEMPIN
Negative Input
Negative Input
Temp ADC
PGA
Temp ADC
PGA
Figure 2-16. Temp ADC Input Mux Options
Table 2-10. Temp ADC PGA Gain Select—Register 6
40
G1
[3]
G0
[2]
Temp ADC
PGA Gain
0
0
1
0
1
2
1
0
4
1
1
8
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The temperature sense block also contains a 7µA (typ) current source, ITEMP, that is enabled by a logic ‘1’
written to Register 6, bit 11, ISEN. A logic ‘0’ disables ITEMP from the TEMPIN pin. This current source can
be used to excite an external resistive temperature device or diode for bridge sensor temperature
measurement, as shown in Figure 2-17.
VSA
PGA309 ITEMP Block
ITEMP
7mA
ITEMP Enable
TEMPIN
TEMPIN
VREF
°C
VEXC
VOUT
Temp
ADC
Input Mux
Temp ADC
Input Mux Select
Figure 2-17. ITEMP for External Temperature Measurement
The Temp ADC has several choices for its reference voltage for analog-to-digital conversions when used
in External Temperature mode; these are illustrated in Table 2-11 and Figure 2-15. The resolution of the
Temp ADC when used in External Temperature mode is also register-selectable (see Table 2-12).
Table 2-11. Temp ADC Reference Select—Register 6
(1)
AREN
[8]
RV1
[7]
RV0
[6]
Temp ADC Reference
(VREFT)
0
0
0
VREF
0
0
1
VEXC
0
1
0
VSA
0
1
1
Factory Reserved
1
X (1)
X (1)
Temp ADC Internal REF (2.048V)
‘X’ = don’t care.
Table 2-12. Temp ADC (1) Resolution (Conversion time)—Register 6
(1)
R1
[1]
R0
[0]
External Signal Mode [TEN=0],
External Reference [AREN=0]
External Signal Mode [TEN=0],
Internal Reference [2.048V, AREN=1]
0
0
11-Bit + Sign, Right-Justified,
Sign-Extended (6ms)
11-Bit + Sign, Right-Justified,
Sign-Extended (8ms)
0
1
13-Bit + Sign, Right-Justified,
Sign-Extended (24ms)
13-Bit + Sign, Right-Justified,
Sign-Extended (32ms)
1
0
14-Bit + Sign, Right-Justified,
Sign-Extended (50ms)
14-Bit + Sign, Right-Justified,
Sign-Extended (64ms)
1
1
15-Bit + Sign, Right-Justified,
Sign-Extended (100ms)
15-Bit + Sign, Right-Justified,
Sign-Extended (128ms)
Temp ADC uses Twos Complement data format.
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2.7.1 Temp ADC Start-Convert Control
The Temp ADC has two conversion modes: Single and Continuous. In Continuous Conversion mode
(CEN = ‘1’), the Temp ADC initiates the next conversion cycle immediately after a conversion is complete.
In Single Conversion mode (CEN = ‘0’) the Temp ADC start-convert bit (ADCS) acts as a
start-convert/busy bit and must be set to ‘1’ before a conversion is initiated. Setting ADCS to ‘1’ occurs
when the register configuration section of the EEPROM (part one) contains ADCS = ‘1’ and the EEPROM
is read. Furthermore, ADCS will be reset to ‘1’ for each successive EEPROM read. After ADCS is set to
‘1’, it will be a ‘1’ if read immediately and can be polled until it returns to a ‘0’, indicating the conversion is
complete. The Start-Convert modes are shown in Table 2-13.
Table 2-13. Temp ADC Start-Convert Control—Register 6
CEN
[10]
ADCS
[12]
Conversion
Mode
0
0
Single
Temp ADC mode—no conversions.
0
1
Single
Temp ADC starts conversion and ADCS acts as
busy bit with it changing to a '0' at end of
conversion.
1
X
Continuous
Comments
ADCS bit excercises no control—typically ADCS =
'1' since conversions are continuous
In Figure 2-18 continuous start-convert control is selected. After an initial power-on reset timeout of
typically 33ms, the register configuration section of the EEPROM (part one) is read. Immediately after this,
a Temp ADC conversion is started. At the end of this first conversion, the temperature coefficients section
of the EEPROM (part two) are read, and Zero and Gain DAC settings are adjusted. Since CEN = ‘1’, the
end of each conversion will start the next conversion. After the temperature coefficients section of the
EEPROM (part two) has been read, the register configuration values are read. Note that reading of the
second half of the EEPROM (temperature coefficients) is triggered by a valid register configuration read of
the EEPROM. This operation yields the most temperature updates over a given time period.
Internal or External Temperature Mode
CEN = '1', ADCS = 'x' (don't care)
VOUT
EEPROM
Read
Temp ADC
Start
Conversion
Disabled
Reg Config and
Checksum1
Initial POR
Conversion
Temp ADC
End
Conversion t t = 25ms
0
Enabled
Temp Coeff and
Checksum2
Reg Config and
Checksum1
Update Zero and Gain DACs
Temp Coeff and
Checksum2
Update Zero and Gain DACs
ADC Results Ignored
ADC Results Will Be Used for Zero and Gain DACs
Update Based on Temp Coefficient
Reg Config and
Checksum1
ADC Results Ignored
ADC Results Will Be Used for Zero and Gain DACs
Update Based on Temp Coefficient
Figure 2-18. Temp ADC Continuous Start-Convert Control
In Figure 2-19, Single Conversion mode is selected (CEN = ‘0’). After an initial power-on reset timeout of
typically 33ms, the register configuration (part one) of the EEPROM is read. Immediately after this, a
Temp ADC conversion is started if CEN = ‘0’ and ADCS = ‘1’. At the end of this first conversion, the
temperature coefficients (part two) of the EEPROM are read, and Zero and Gain DAC settings are
adjusted. When CEN = ‘0’ and ADCS = ‘1’, a new start conversion occurs only after reading the register
configuration part of the EEPROM. At the end of this conversion, the second part of the EEPROM
(temperature coefficients) is read, the Gain and Zero DAC temperature calculations are done, and each
respective DAC updated. Note that in the Single Start-Convert mode, if CEN = ‘0’ and ADCS = ‘0’ (no
Temp ADC conversions), the PGA309 will wait 33ms after power-on, read the register configuration part of
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the EEPROM, and without an ADC conversion, read the Lookup Table and calculate Gain and Zero DAC
values. These values are based on the current ADC output register (all zero on power-up). The PGA309
output will then be enabled and will wait about 25ms, and read the register configuration part of the
EEPROM. The output remains enabled with a continuous loop of reading the register configuration part of
the EEPROM, waiting 33ms, and read again.
One final control option for External Temperature Mode is the ADC2X bit, Register 6 bit [13]. This bit
allows the conversion speed of the Temp ADC to be increased for external temperature readings only.
Table 2-14 shows the typical settings and the effect of the ADC2X bit.
Internal or External Temperature Mode
TEN = '0', CEN = '0', ADCS = '1'
VOUT
EEPROM
Read
Temp ADC
Start
Conversion
Disabled
Reg Config and
Checksum1
Enabled
Temp Coeff and
Checksum2
Reg Config and
Checksum1
Temp Coeff and
Checksum2
Update Zero
and Gain DACs
Initial POR
Conversion
Temp ADC
End
Conversion
Update Zero
and Gain DACs
ADC Idle
t0 t = 25ms
ADC Results Will Be Used for Zero and Gain DAC
Update Based on Temp Coeff
ADC Results Will Be Used for Zero and Gain DAC
Update Based on Temp Coeff
Figure 2-19. Temp ADC Single Start-Convert Control
Table 2-14. Temp ADC (1) Conversion Speed Options for External Temperature Mode
(1)
TEN=0],
[AREN=0],
[ADC2X=0]
[TEN=0],
[AREN=0],
[ADC2X=1]
[TEN=0]
[2.048V, AREN=1],
[ADC2X=0]
[TEN=0]
[2.048V, AREN=1],
[ADC2X=1]
R1
[1]
R0
[0]
0
0
11-Bit + Sign (6ms)
11-Bit + Sign (3ms)
11-Bit + Sign (8ms)
11 Bit + Sign (4ms)
0
1
13-Bit + Sign (24ms)
13-Bit + Sign (12ms)
13-Bit + Sign (32ms)
13 Bit + Sign (16ms)
1
0
14-Bit + Sign (50ms)
14-Bit + Sign (25ms)
14-Bit + Sign (64ms)
14 Bit + Sign (32ms)
1
1
15-Bit + Sign (100ms)
15-Bit + Sign (50ms)
15-Bit + Sign (128ms)
15 Bit + Sign (64ms)
Temp ADC data uses a 16-bit, sign-extended, right-justified Twos Complement data format.
2.7.2 External Temperature Sensing with an Excitation Series Resistor
Some bridge sensor applications measure the temperature of the bridge sensor by the change in the
bridge resistance. This is accomplished by adding a series resistor in either the top or the bottom of the
bridge excitation connections. When this is done, the common-mode voltage range of the PGA309 inputs
must be observed over the operating temperature range of the application.
Figure 2-20 shows a top-side series resistor (RT+) used to monitor the change in bridge resistance with
temperature. For simplification of analysis, the effective bridge resistance is converted to one resistor
(RBT), as shown. For a given temperature, RBT will be a fixed value; for this example, 1.8kΩ at 70°C. Since
RT has a negligible change in temperature (50ppm/°C) compared with RBT (3500ppm/°C), RT is used to
detect a change in RBT. For this application, the Temp PGA is configured for VEXC on the +input, and
TEMPIN on the –input. The Temp ADC uses VEXC as its reference, VREFT. The Temp PGA is set to a gain of
8. Notice that two different values for VEXC will be analyzed to emulate the changing voltage on VEXC due to
the linearization block adjusting VEXC to minimize error on the bridge sensor output with applied pressure.
The squareboxed values show numerical results for VEXC = 2.9V and the oval-ringed values for VEXC =
2.4V. The final Temp ADC reading will be the same value regardless of what value VEXC is used by the
linearization block.
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Figure 2-21 shows a bottom-side series resistor (RT−) used to monitor the change in bridge resistance with
temperature. Again, for simplification of analysis, the effective bridge resistance is converted to one
resistor (RBT) as shown. For 70°C, RBT is 1.8kΩ for this example. RT is used to measure the change in RBT.
The Temp PGA is configured for TEMPIN on the +input and GND on the –input. VEXC is selected as the
Temp ADC reference, VREFT. The PGA gain is 8. The square-boxed values are results for VEXC = 2.9V and
the oval-ringed values for VEXC = 2.4V. It is seen that the final Temp ADC reading will be the same
regardless of the VEXC value.
If the linearization block is not used in the application, the bridge sensor top excitation connection is made
to either VSA or VREF, instead of VEXC. In either of these cases, top-side (Figure 2-20) or bottom-side
(Figure 2-21), external temperature sensing can be done by adding a series resistor, RT. The Temp ADC
reference (VREFT) should be changed to the bridge excitation voltage (VSA or VREF) for the specific
application. This yields a constant Temp ADC output at a given temperature independent of changes in
the bridge excitation voltage.
PGA309 External Temperature Mode
2.9V
VEXC
VEXC
2.4V
Linearization
Block
VREF
2.9V
VFB
VEXC
2.4V
RT+
100W
2.273684211V
RB
VREFT
Temp PGA
2.747368421V
RBT
°C 1.8kW
at 70°C
Temp ADC
x8
TEMPIN
Temp ADC Out
(% Full-Scale Range)
0.152631579V
1.221052632V
42.1052631%
0.126315789V
1.010526316V
42.1052631%
Figure 2-20. External Temperature Sensing of Bridge Sensor with Top-Side Series Resistor
2.9V
PGA309 External Temperature Mode
2.4V
VEXC
RB
VEXC
Linearization
Block
VREF
VFB
2.9V
VEXC
RBT
°C 1.8kW
at 70°C
TEMPIN
2.4V
VREFT
Temp PGA
Temp ADC
x8
RT100W
Temp ADC Out
(% Full-Scale Range)
0.152631579V
1.221052632V
42.1052631%
0.126315789V
1.010526316V
42.1052631%
Figure 2-21. External Temperature Sensing of Bridge Sensor with Bottom-Side Series Resistor
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2.8
Fault Monitor
Fault monitoring of external bridge sensors is provided on the PGA309 through nine internal comparators.
Refer to Figure 2-22. These comparators are grouped into two sets: Internal Fault Comparators and
External Fault Comparators. In Figure 2-22, these are denoted as EXT for those in the External Fault
Comparator group and by INT for those in the Internal Fault Comparator group.
VEXC
VEXC
Circuit
Min Ref Select
VSA - 1.2V
(1)
(VEXC - 100mV)
INP_HI
(ALM1)
EXT
INT
A2SAT_LO
(ALM5)
INT
A2SAT_HI
(ALM6)
100mV
VSA - 120mV
Optional
Pull-Up
Resistors
1MW to 10MW
INP_LO
(ALM0)
EXT
100mV
Fine Offset
DAC
MUXCNTL
VSA - 1.2V
4R
VINP
A3_VCM
(ALM4)
INT
R
A2
VIN2
RF
RB2
RB1
Bridge
Sensor
RB3
VIA_OUT
RG
A3
RF
Fine
Gain Adjust
DAC
VOUT
RB4
R
VINN
VIN1
RFO
4R
A1
RGO
Optional
Pull-Down
Resistors
1MW to 10MW
EXT
INN_LO
(ALM2)
EXT
INN_HI
(ALM3)
INT
A1SAT_LO
(ALM7)
INT
A1SAT_HI
(ALM8)
100mV
100mV
Min Ref Select
VSA - 1.2V
(VEXC - 100mV)(1)
VSA - 120mV
NOTE:
1.
When VEXC is enabled, a minimum reference selector circuit becomes the reference for the INN_HI and INP_HI
comparator threshold. This minimum reference selector circuit uses VEXC − 100mV and VSA − 1.2V, and compares
the VINX pin to the lower of the two references. This ensures accurate fault monitoring in conditions where VEXC
might be higher or lower than the input voltage range of the Front-End PGA amplifier relative to VSA.
2.
All comparator outputs are high for fault condition.
Figure 2-22. PGA309 Fault Monitor Circuitry
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The external fault comparators are used to monitor proper operation of the bridge sensor and report input
fault conditions. Table 2-15 enumerates the possible fault cases for a bridge sensor and the associated
fault comparator outputs for each fault condition. Due to the extremely low input bias currents of the
PGA309, if fault detection of floating inputs (sensor disconnected entirely from one or both of the PGA309
inputs) is to be accurately reported, it is necessary to add either pull-up or pull-down resistors to each of
these inputs (VIN1 and VIN2), shown in Figure 2-22 as optional. The value of these resistors can be between
1MΩ and 10MΩ in order to minimize signal loading of the bridge sensor’s output. Offset and other errors
from these optional resistors will be cancelled out during the PGA309 + sensor calibration. Table 2-16
itemizes the special cases for floating inputs on the PGA309 when using pull-up resistors. Table 2-17 lists
the special cases for floating inputs on the PGA309 when using pull-down resistors. All other fault cases
not listed as special cases are the same as those detailed in Table 2-15.
Table 2-15. Bridge Sensor Faults and Fault Comparator States—VIN1 and VIN2 Have No Pull-Up or
Pull-Down Resistors (1)
VIN1
(VINP)
(V)
VIA_OUT
(V)
INN_HI
(ALM3)
INN_LO
(ALM2)
INP_HI
(ALM1)
INP_LO
(ALM0)
Normal
1.7
1.7
Linear
0
0
0
0
RB1 Open
1.7
0
~0
0
0
0
1
RB2 Open
0
1.7
~VSA
0
1
0
0
RB3 Open
3.4
1.7
~0
1
0
0
0
RB4 Open
1.7
3.4
~VSA
0
0
1
0
RB1 Short
1.7
3.4
~VSA
0
0
1
0
RB2 Short
3.4
1.7
~0
1
0
0
0
RB3 Short
0
1.7
?
0
1
0
0
RB4 Short
1.7
0
~0
0
0
0
1
Open Sensor GND
3.4
3.4
~0
1
0
1
0
Open Sensor VEXC
0
0
~0
0
1
0
1
VEXC Short GND
0
0
~0
1 (2)
1
1 (2)
1
VIN1 (VINP) Open (3)
1.7
~VSA−0.7
~VSA
0
0
0
0
Under-scale limit on
VOUT, no fault
detect—Int or Ext
VIN2 (VINN) Open (3)
~VSA−0.7
1.7
~0
0
0
0
0
Over-scale limit on
VOUT, no fault
detect—Int or Ext
Case
VIN1 (VINP) Short GND
1.7
0
~0
0
0
0
1
VIN2 (VINN) Short GND
0
1.7
~VSA
0
1
0
0
VIN1 (VINP) Short VEXC
1.7
3.4
~VSA
0
0
1
0
VIN2 (VINN) Short VEXC
3.4
1.7
~0
1
0
0
0
VIN1 (VINP),
VIN2 (VINN) Open (3)
~VSA−0.7
~VSA−0.7
Linear?
0
0
0
0
VIN1 (VINP),
VIN2 (VINN) Short GND
0
0
~VSA
0
1
0
1
VIN1 (VINP),
VIN2 (VINN) Short VEXC
3.4
3.4
~0
1
0
1
0
(1)
(2)
(3)
46
Logic Level Outputs
VIN2
(VINN)
(V)
Comments
Typically drifts to
over-scale limit slowly;
no Ext Fault detect
(ALM7), Int Fault set =
A1 Sat Low
VSA = +5V, VREF = +4.096V, KEXC = 0.83, KLIN = 0, and VEXC = 3.4V.
Typically, a logic 1, but not ensured by design and nature of fault.
Accurate detection of these faults requires a pull-up or pull-down resistor on each input (VIN1 and VIN2).
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Table 2-16. Bridge Sensor Faults and Fault Comparator States—VIN1 and VIN2 are connected by
10MΩ Pull-Up Resistors to VEXC (1)
Special Case
(1)
(2)
(2)
Logic Level Outputs
VIN2
(VINN)
(V)
VIN1
(VINP)
(V)
VIA_OUT
(V)
INN_HI
(ALM3)
INN_LO
(ALM2)
INP_HI
(ALM1)
INP_LO
(ALM0)
VIN1 (VINP) Open
1.7
VEXC
~VSA
0
0
1
0
VIN2 (VINN) Open
VEXC
1.7
~0
1
0
0
0
VIN1 (VINP), VIN2 (VINN) Open
VEXC
VEXC
~0
1
0
1
0
VSA = +5V, VREF = +4.096V, KEXC = 0.83, KLIN = 0, and VEXC = 3.4V.
All other cases not listed are the same as those in Table 2-15.
Table 2-17. 16.Bridge Sensor Faults and Fault Comparator States—VIN1 and VIN2 are connected by
10MΩ Pull-Down Resistors to GND (1)
Logic Level Outputs
VIN2 (VINN)
(V)
VIN1 (VINP)
(V)
VIA_OUT
(V)
INN_HI
(ALM3)
INN_LO
(ALM2)
INP_HI
(ALM1)
INP_LO
(ALM0)
VIN1 (VINP) Open
1.7
~0
~VSA
0
0
0
1
VIN2 (VINN) Open
~0
1.7
~0
0
1
0
0
VIN1 (VINP), VIN2 (VINN) Open
~0
~0
~0
0
1
0
1
Special Case
(1)
(2)
(2)
VSA = +5V, VREF = +4.096V, KEXC = 0.83, KLIN = 0, and VEXC = 3.4V.
All other cases not listed are the same as those in Table 2-15.
When VEXC is enabled, external fault comparators INP_HI and INP_LO have a minimum reference selector
circuit that selects between a typical trip point of either VEXC – 100mV or VSA – 1.2V. This ensures accurate
fault monitoring in conditions where the Linearization Circuit increases VEXC, and the bridge sensor has
fault conditions that violate the IVR, relative to VSA, of the Front-End PGA in the PGA309. If VEXC is
disabled, these comparators default to the VSA – 1.2V threshold.
The internal fault comparators are used to monitor the Front-End PGA internal nodes of the PGA309 (see
Figure 2-22). When PGA309 + Sensor calibration is in process, it is crucial to have the internal comparator
group enabled because it can alert the user to an internal node violation. Such a violation may still yield an
output voltage within the expected linear range, but it will not be an accurate one. Each of the front-end
amplifiers, A1 and A2, of the Front-End PGA have their outputs monitored for both saturation to the
positive supply or to ground. If either of these comparators trips during calibration, it is an indication of an
out-of-range scaling condition due either to the incorrect Front-End PGA gain select or coarse offset
adjust. The A3 amplifier in the Front-End PGA is also monitored for common-mode violations that can
occur if the Zero DAC is combined incorrectly with the Front-End PGA gain select.
Each individual internal and external fault comparator can be read through one of the digital interfaces:
Two-Wire or One-Wire. The current results are stored in Register 8—Alarm Status Register. When the
PGA309 output is enabled, the value of the Alarm Status Register reflects the current state of the fault
comparators. When VOUT is disabled, the value in the register is the comparator status immediately before
the output was disabled. This allows for easier identification and debugging of a three terminal sensor
module (PRG shorted to VOUT). See Section 4.10, One-Wire Operation with PRG Connected to VOUT, for
details. In addition, each group of comparators, internal fault and external fault, can be programmed such
that if any comparator in their respective group is logic high, indicating a fault, the PGA309 output (VOUT)
will be forced to a fault indicating voltage level of either positive (VSA − 0.1V max with a 10kΩ load) or
negative (0.1V max with a 10kΩ load). The logic for this is shown in Figure 2-23.
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EXTPOL
1 = Force VOUT High
0 = Force VOUT Low
External Comparator
Fault Flag
1 = fault
INP_HI
INP_LO
External
INN_HI
Comparators
INN_LO
VSA
1 = Close
0 = Open
'0'
'1'
EXTEN
1 = enable
0 = disable
ALM2
ALM3
ALM0
ALM1
ALM8
ALM7
ALM4
ALM6
ALM5
Alarm
Status
Register
Output
Amp
VOUT
A2SAT_LO
A2SAT_HI
Internal
A3_VCM
Comparators A1SAT_LO
A1SAT_HI
1 = Close
0 = Open
1 = fault
Internal Comparator
Fault Flag
INTEN
1 = enable
0 = disable
INTPOL
1 = Force VOUT High
0 = Force VOUT Low
VSA
'0'
'1'
Figure 2-23. Fault Monitor Comparator Logic
Configuration for the fault monitor comparator logic is provided in Register 5—PGA Configuration and
Over/Under Scale Limit. The individual comparator outputs in each group are combined to generate an
Internal Comparator Fault flag and an External Comparator Fault flag. For the External Comparator group,
EXTEN, Register 5 (bit 11) enables or disables whether the External Comparator Fault flag will be sent
forward to force VOUT to a fault indication state. For the Internal Comparator group, INTEN, Register 5 (bit
10), enables or disables whether the Internal Comparator Fault flag will be sent forward to force VOUT to a
fault indication state. For each of the comparator groups, there is programmability of the fault indication
state on VOUT (either VSA or GND). INTPOL, Register 5 (bit 8), selects this state for the Internal Comparator
group and EXTPOL, Register 5 (bit 9) selects for the External Comparator group. The External
Comparator Fault flag has priority over the Internal Comparator.
Fault flag, as shown in Figure 2-23. For example, if the Internal Fault Comparator group is set to force
VOUT low and the External Fault Comparator group is set to force VOUT high, and both groups detect a fault
(which is possible if both are enabled), then the External Fault Comparator group prevails and VOUT is
forced high. This is to ensure that for most real-world applications, a critical sensor fault would be reported
as priority over an internal node violation. Assuming there is a valid linear output on VOUT at the time of a
detected fault, the fault logic always prevails (if enabled), and will override the linear output to indicate a
fault on VOUT as positive or negative VOUT saturation.
2.9
Over/Under Scale
The Over-Scale and Under-Scale Limit circuit provides a programmable upper and lower clip limit for the
PGA309 output voltage. This circuit can be enabled by setting Register 5, bit D6 to ‘1’. When combined
with the Fault Monitor circuitry, system diagnostics can be performed to determine if a conditioned sensor
is defective or if the process being monitored by the sensor is out of range. Figure 2-24 details the key
sections of the Over-Scale and Under-Scale Limit circuit. The selected PGA309 VREF is divided down by a
precision resistor string to form the over-scale and under-scale thresholds, as shown in Table 2-18 and
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Table 2-19. Register 5 bits [5:0] set the desired thresholds. These resistor ratios are extremely accurate
and produce no significant initial or temperature errors. As shown in Figure 2-24, there are two separate
comparators: over-scale and under-scale, which use the over-scale or under-scale threshold, respectively,
and determine where the PGA309 output (VOUT) will be clipped. The dominant errors in the Over-Scale
and Under-Scale Limit circuit are due to the comparators offset and offset temperature drift.
VREF
x1
On = '1'
Over-Scale
Comparator
Over-Scale
Threshold
(Select 1-of-7)
Output Amplifier
Output Stage
Over-Scale
Limit
VOUT
Output
Amplifier
RGO
Under-Scale
Limit
RFO
VFB
(Select 1-of-8)
On = '1'
Under-Scale
Threshold
Under- Scale
Comparator
x1
Figure 2-24. Over-Scale and Under-Scale Limit Circuit
Table 2-18. Over-Scale Threshold Selections (Register 5 Bits [5:3]). VREF = +5V
HL2
[5]
HL1
[4]
HL0
[3]
Over-Scale Threshold
(V)
Over-Scale Threshold
0
0
0
4.854
0.9708 VREF
0
0
1
4.805
0.9610 VREF
0
1
0
4.698
0.9394 VREF
0
1
1
4.580
0.9160 VREF
1
0
0
4.551
0.9102 VREF
1
0
1
3.662
0.7324 VREF
1
1
0
2.764
0.5528 VREF
1
1
1
Reserved
—
Table 2-19. Under-Scale Threshold Selections (Register 5 Bits [2:0]). VREF = +5V
LL2
[2]
LL1
[1]
LL0
[0]
Under-Scale Threshold
(V)
Under-Scale Threshold
0
0
0
0.127
0.02540 VREF
0
0
1
0.147
0.02930 VREF
0
1
0
0.176
0.03516 VREF
0
1
1
0.196
0.03906 VREF
1
0
0
0.225
0.04492 VREF
1
0
1
0.254
0.05078 VREF
1
1
0
0.274
0.05468 VREF
1
1
1
0.303
0.06054 VREF
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The design considerations in using the Over-Scale and Under-Scale Limit circuit are best understood
through a definition by example, as shown in Example 2-4.
Example 2-4. Over/Under-Scale Calculation
Given:
Absolute Scale System—PGA309 connected to a system ADC (see Figure 2-25)
System ADC Reference: VREF ADC = 4.096V
PGA309 Reference: VREF = 4.096V (use PGA309 internal reference)
Operating Temperature Range: −40°C to +125°C
PGA309 VSA, VSD = +5V
External Fault Monitor; Trip High when Fault Detected
Find:
Recommended levels to allow for Over/Under-Scale Limits as well as Fault Detection.
(A) Over-Scale Limit
(B) Under-Scale Limit
(C) Useable Linear PGA309 Output Range
(D) System ADC Trip Points: Over-Scale, Under-Scale, Fault Detect
Solution:
1. Analyze the worst case offset errors on the over-scale and under-scale comparators over the operating
temperature range. Table 2-20 contains key electrical characteristics needed for this computation.
Over-Scale Comparator Offset Calculation:
Over-Scale Temperature Drift:
−40°C to 25°C: −24.05mV = (+0.37mV/°C)(−40°C − 25°C)
25°C to +125°C: +37.00mV = (+0.37mV/°C)(+125°C − 25°C)
Over-Scale Offset Min and Max:
VOS min = +6mV −24.05mV = −18.05mV
VOS max = +114mV + 37.00mV = +151.00mV
Under-Scale Comparator Offset Calculation:
Under-Scale Temperature Drift:
−40°C to 25°C: +9.75mV = (−0.15mV/°C)(−40°C − 25°C)
25°C to +125°C: −15.00mV = (−0.15mV/°C)(+125°C − 25°C)
Under-Scale Offset Min and Max:
VUS min = −7mV + 9.75mV = −2.75mV
VUS max = −93mV −15.00mV = −108mV
2. Analyze the worst-case change in VREF over the operating temperature range.
VREF Temperature Drift:
−40°C to +125°C: [(+10ppm/°C)/(1e6)][+125°C − (−40°C)]VREF = +0.00165 VREF
VREF Min and Max:
VREF min = 4.00V – (0.00165)(4.00V) = 3.9934V
VREF max = 4.14V + (0.00165)(4.00V) = 4.1466V
3. Calculate the over-scale and under-scale min and max trip points over the operating temperature range for
each overscale and under-scale threshold (refer to Table 2-21).
Over-Scale (OS) Min and Max Trip Points:
OS min = VREF min (OS ratio) + VOS min
OS max = VREF max (OS ratio) + VOS max
Under-Scale (US) Min and Max Trip Points:
US min = VREF min (US ratio) + VUS max
US max = VREF max (US ratio) + VUS min
4. From the over-scale and under-scale min and max trip point calculations, choose the best selection that
will allow for the optimum system ADC range budget (see Figure 2-26). For this example, the PGA309 is
scalable for a linear output of 8% to 80.8% of the system ADC reference. In addition, we can set
reasonable trip points for detecting over-scale limit, under-scale limit, and fault detect.
5. Check that the PGA309 VOUT can support the voltage swings defined in the System ADC range budget.
Table 2-22 confirms that for our example the PGA309 VOUT can meet the limiting conditions for our desired
scaling.
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Example 2-4. Over/Under-Scale Calculation (continued)
Since the PGA309 + sensor is usually calibrated together as a system, the over-scale and under-scale limits
can be measured per device at the operating temperature extremes, and the final limits adjusted as desired
for optimum scaling. In a ratiometrically scaled system, the reference error will not need to be included in the
over-scale and under-scale trip point calculations.
+5V
+5V
VREF ADC
(4.096V)
+5V
+5V
VSD
0.1mF
REFIN/REFOUT
VSA
Sensor
Out
SDA
Two-Wire
EEPROM
+5V
PRG
SCL
1 0 1 0 1
GND
(1)
VOUT
System ADC
RISO
100W
(2)
VEXC
VIN2
ADC
(1)
VFB
PGA309
RFB
100W
CL
10nF
(3)
CF
150pF
Bridge
Sensor
VIN1
VSJ
TEMPIN
Test
GNDA
GNDD
NOTE: (Although not needed in all applications):
1.
RISO and RFB provide the PGA309 with overvoltage protection on Sensor Out.
2.
CL provides EMI/RFI filtering.
3.
CF provides the PGA309 with stability for capacitive load of CL.
Figure 2-25. Absolute Scale System—PGA309 Connected to a System ADC
Table 2-20. Electrical Characteristics for Over-Scale and Under-Scale Comparators and VREF
Parameter
Over-Scale Comparator Offset
Min
Typ
Max
+6
+60
+114
Over-Scale Comparator Offset Drift
Under-Scale Comparator Offset
+0.37
−7
VREF2
−50
4.00
VREF2 Drift
4.096
+10
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mV
mV/°C
−93
−0.15
Under-Scale Comparator Offset Drift
Units
mV
mV/°C
4.14
V
ppm/°C
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Table 2-21. Over-Scale and Under-Scale Min and Max Trip Point Calculations
(1)
(1)
Threshold
U = Under-Scale
O = Over-Scale
Threshold
Ratio to VREF
Min Trip
(V)
Min Trip
(%VREF ADC)
Max Trip
(V)
Max Trip
(%VREF ADC)
Typ Trip
(V)
Typ Trip
(%VREF ADC)
U7
0.0605
0.1338
3.2656
0.2483
6.0616
0.1910
4.6636
U6
0.0547
0.1104
2.6943
0.2240
5.4684
0.1672
4.0814
U5
0.0508
0.0948
2.3141
0.2078
5.0736
0.1513
3.6938
U4
0.0449
0.0714
1.7428
0.1835
4.4804
0.1274
3.1116
U3
0.0391
0.0480
1.1714
0.1592
3.8871
0.1036
2.5293
U2
0.0352
0.0324
0.7912
0.1430
3.4923
0.0877
2.1418
U1
0.0293
0.0090
0.2199
0.1187
2.8991
0.0639
1.5595
U0
0.0254
−0.0066
−0.1603
0.1026
2.5042
0.0480
1.1719
O6
0.5528
2.1895
53.4546
2.4432
59.6494
2.3164
56.5520
O5
0.7324
2.9067
70.9648
3.1880
77.8313
3.0473
74.3980
O4
0.9102
3.6167
88.2994
3.9252
95.8309
3.7710
92.0652
O3
0.9160
3.6399
88.8649
3.9493
96.4181
3.7946
92.6415
O2
0.9394
3.7333
91.1462
4.0463
98.7870
3.8898
94.9666
O1
0.9610
3.8196
93.2521
4.1359
100.9737
3.9777
97.1129
O0
0.9708
3.8587
94.2076
4.1765
101.9658
4.0176
98.0867
VREF MIN = 3.9934V, VREF MAX = 4.1466V, VREF ADC = 4.096V, VOS min = −0.01805V, VOS max = 0.151V,
VUS min = −0.00275V, VUS max = −0.108V. Bold Italics indicate final choice for Example 2-4.
100% of VREF ADC
ADC Upper Headroom
98.4% of VREF ADC
97.4% VREF ADC¾ Fault-Flag Trip Point
96.4% of VREF ADC¾ Over-Scale Limit (max)
92.6% of VREF ADC¾ Over-Scale Limit (typ)
88.9% of VREF ADC¾ Over-Scale Limit (min)
87.8% VREF ADC¾ Over-Scale Trip Point
86.8% of VREF ADC
Real-World Usable
ADC Range
PGA309 Linear Output Range
8% of VREF ADC
7% VREF ADC¾ Under-Scale Trip Point
6.1% of VREF ADC¾ Under-Scale Limit (max)
4.7% of VREF ADC¾ Under-Scale Limit (typ)
3.3% of VREF ADC¾ Under-Scale Limit (min)
2% of VREF ADC
0% of VREF ADC
ADC Lower Headroom
Figure 2-26. System ADC Range Budget for Over-Scale, Under-Scale, and Linear Output
Table 2-22. PGA309 VOUT Limits for System ADC Range Budget (1)
(1)
52
Limiting Condition
PGA309 VOUT (V)
PGA309 VOUT Limit (V)
96.4% VREF ADC—Over-Scale Limit (max)
3.9493
4.9
3.3% VREF ADC—Under-Scale Limit (min)
0.1338
0.1
VREF ADC = 4.096V, VSA = 5V.
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2.10 Noise and Coarse Offset Adjust
The PGA309 Front-End PGA contains auto-zero operational amplifiers that allow precision, low-noise
measurements free from flicker, or 1/f noise, that is typically present in regular low-voltage CMOS op
amps.
This auto-zero topology operates by canceling amplifier low-frequency noise and offset during each clock
cycle of an internal oscillator. This flattens the lowfrequency noise voltage spectrum of the PGA309,
leaving only a small residual clock feedthrough component at ~7kHz and its multiples. Figure 2-27 details
the PGA309 voltage noise spectrum for coarse offset adjust = 0mV. This auto-zero method allows higher
precision measurement by filtering the output of the PGA309 proportionally. Conventional CMOS
operational amplifiers that use averaging do not improve the signal-to-noise ratio in the 1/f noise region. In
addition, the auto-zero technique allows the PGA309 input offset voltage to achieve very good
temperature and time stability.
eND (mV/?Hz), RTI
1
0.1
0.01
1
10
100
1k
10k
100k
Frequency (Hz)
Figure 2-27. Voltage Noise Power Spectrum Referred to Input (RTI), Coarse Offset Adjust = 0mV, Gain =
1152, CLK_CFG = ‘00’ (default)
The PGA309 low-frequency voltage noise density (RTI) is ~210nV/√Hz. To convert this to a peak-to-peak
amplitude for oscilloscope measurements, the following equation is supplied:
VNPP = (eND)(√BW)(crest factor)
where:
• VNPP = voltage noise peak-to-peak (nVPP)
• eND = voltage noise density (nV/√Hz)
• BW = bandwidth of interest (Hz)
• Crest Factor = probability factor for conversion of rms noise to peak-topeak noise (crest factor of 6
reduces probability of seeing a larger peak-topeak amplitude to < 0.3%).
PGA309 peak-to-peak noise, RTI, BW = 10Hz:
VNPP = (210nV/√Hz)(√10Hz)(6) = 3984nVPP = 3.98mVPP (RTI)
For a PGA309 total gain of 1152, this implies the noise at VOUT will be 4.58mVPP , as shown in Figure 2-28.
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1mV/div
G = 1152
Coarse Offset = -59mV
VIN = +61mV
Measured After Bandpass Filter:
0.1Hz Second-Order High-Pass
10Hz Fourth-Order Low-Pass
1s/div
Figure 2-28. VOUT Noise, 0.1Hz to 10Hz Peak-to-Peak Noise
To compensate for bridge sensors with a large initial offset, the input stages of the PGA309 Front-End
PGA incorporate a patented circuit for the coarse offset adjust based on the auto-zero topology. For each
clock cycle of the internal auto-zero oscillator, the offsets and noise of the input amplifier stages are
subtracted from the input signal, and the result is summed with a small voltage produced by the Coarse
Offset Adjust DAC. This resulting value becomes the input-referred offset of the PGA309. This value can
be positive or negative as described Section 2.2, Offset Scaling. This operation does not increase the low
frequency 1/f noise of the PGA309. However, the mismatches of internal elements in the Coarse Offset
DAC can produce temperature and long-term stability errors on the same order of magnitude as regular,
traditional CMOS op amps (that is, temperature drift of input offset voltage of up to 10mV/°C).
To produce a value that is temperature- and time-stable, the Coarse Offset DAC circuitry incorporates a
chopping circuit that rotates internal components, averaging the mismatch error on the output of the
Coarse Offset Adjust DAC. This produces a very time- and temperature-stable coarse offset adjust.
100mV/div
The design compromise of the Coarse Offset DAC chopping technique is a clock feedthrough glitch that
can be seen at VOUT, the output of the PGA309, due to the rotating elements. With the Coarse Offset
Adjust set to 0mV the clock feedthrough components are practically negligible on the VOUT signal of the
PGA309, as shown in Figure 2-29.
Time (100ms/div)
Figure 2-29. Unfiltered VOUT Clock Feedthrough, Coarse Offset Adjust = 0mV, Gain = 1152, CLK_CFG =
‘00’ (default)
As the Coarse Offset Adjust DAC value increases the amplitude of the clock, feedthrough glitch also
increases. For VREF = +5V and a full-scale Coarse Offset DAC value of −59mV, the clock feedthrough
glitch is shown in Figure 2-30. This scope photo is for the PGA309 set in its maximum internal gain of
1152, with the Coarse Offset Adjust DAC set to −59mV and VIN set to +61mV. Referred to input (RTI), this
VOUT glitch is only 347mVPP (0.4VPP/1152). This glitch occurs at half of the internal auto-zero clock; typically,
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100mV/div
3.5kHz. This glitch does not reflect back into the low-frequency range and can be filtered out if the signal
of interest is at or below 1kHz. Figure 2-31 is a scope photo of VOUT peak-to-peak noise for this case.
Figure 2-32 shows the voltage noise spectrum for the case where the Coarse Offset Adjust DAC is set to
−59mV and VIN = +61mV. In Figure 2-32, the baseband noise is about the same as when the coarse offset
adjust was set to zero, as in Figure 2-27, but with an additional spike at about 3.5kHz.
Time (100ms/div)
1mV/div
Figure 2-30. Unfiltered VOUT Clock Feedthrough Glitch, Coarse Offset Adjust = −59mV, Gain = 1152, VIN =
+61mV, CLK_CFG = ‘00’ (default). VOUT Glitch (RTI) = 347µVPP
Measured After Bandpass Filter:
0.1Hz Second-Order High-Pass
10Hz Fourth-Order Low-Pass
Time (1s/div)
Figure 2-31. Filtered 0.1Hz to 10Hz VOUT Peak-to-Peak Noise, Coarse Offset Adjust = −59mV, Gain = 1152,
VIN = +61mV, CLK_CFG = ‘00’ (default)
eND (mV/?Hz), RTI
10
1
0.1
0.01
1
10
100
1k
10k
50k
Frequency (Hz)
Figure 2-32. Voltage Noise Spectrum (RTI), Coarse Offset Adjust = −59mV, Gain = 1152, VIN = +61mV,
CLK_CFG = ‘00’ (default)
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For applications where the clock feedthrough glitch from the Coarse Offset Adjust DAC chopping circuitry
is an issue, there are alternate modes that can be selected for the Coarse Offset DAC clocking and the
auto-zero clocking of the Front-End PGA. Register 5 bits (13:12) are referenced as CLK_CFG1 and
CLK_CFG0, respectively. Table 2-23 outlines the clocking schemes available using these bits. Up to this
point, CLK_CFG = ‘00’ has been discussed.
Table 2-23. PGA309 Clocking Schemes
CLK_CFG
Mode
CLK_CFG1
Bit D13
CLK_CFG0
Bit D12
Auto-Zero
PGA Front-End
Chopping
Coarse Offset DAC
00 (default)
0
0
7kHz typical
3.5kHz typical
01
0
1
7kHz typical
Off (none)
10
1
0
7kHz typical,
Random Clocking
3.5kHz typical,
Random Clocking
11
1
1
7kHz typical
3.5kHz typical,
Random Clocking
In the CLK_CFG = ‘01’ mode, the Coarse Offset Adjust DAC chopping is turned off. The clock feedthrough
glitch is no longer present (Figure 2-33 shows the 0.1Hz to 10Hz VOUT peak-to-peak noise) and the VOUT
noise spectrum is clean, as shown in Figure 2-34. However, the input Coarse Offset Adjust DAC is no
longer temperature-stable. Typical span drift is generally linear with temperature and may be acceptable in
applications where the PGA309 is located close to the bridge sensor and they are both calibrated
together. The drift of the Coarse Offset Adjust DAC simply sums with the bridge sensor offset drift, and
they are both calibrated out.
1mV/div
Measured After Bandpass Filter:
0.1Hz Second-Order High-Pass
10Hz Fourth-Order Low-Pass
1s/div
Figure 2-33. 0.1Hz to 10Hz VOUT Peak-to-Peak Noise for Coarse Offset Adjust = −56mV, Gain = 1152, VIN =
+57mV, CLK_CFG = ‘01’, VNPP (RTI) = 4.44 VPP
eND (mV/?Hz), RTI
10
1
0.1
0.01
1
10
100
1k
10k
100k
500k
Frequency (Hz)
Figure 2-34. VOUT Noise Spectrum for Coarse Offset Adjust = −56mV, Gain = 1152, VIN = +57mV, CLK_CFG
= ‘01’
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CLK_CFG = ‘10’ mode and CLK_CFG = ‘11’ mode turn on different clock randomization schemes for the
Front-End PGA auto-zero and Coarse Offset DAC chopping. Although this does not reduce the amplitude
of the clock feedthrough glitch (see Figure 2-30), it does spread the glitch energy over a wider frequency
range. This removes the fixed spike at half of the input auto-zero clock frequency, but raises the noise
floor in the lower frequency range, thus increasing the baseband noise. CLK_CFG = ‘11’ mode simply
whitens the peak-to-peak noise from the 1Hz region to about the 7kHz region by modulating both the
auto-zero and chopping clocks. In CLK_CFG = ‘10’ mode, the Coarse Offset DAC chopping clock is
modulated but not the auto-zero clock. The results of these two modes are shown in both voltage noise
spectrum and peak-to-peak noise plots in Figure 2-35, Figure 2-36, Figure 2-37, and Figure 2-38.
space
5mV/div
VOUT Noise (mV/?Hz)
10
1
0.1
Measured After Bandpass Filter:
0.1Hz Second-Order High-Pass
10Hz Fourth-Order Low-Pass
0.01
100
1s/div
Figure 2-35. 0.1Hz to 10Hz VOUT Peak-to-Peak Noise
for Coarse Offset Adjust = −56mV, Gain = 1152, VIN
= +57mV, CLK_CFG = ‘10’, VNPP (RTI) = 18.4µVPP
10k
1k
100k
Frequency (Hz)
Figure 2-36. VOUT Noise Spectrum for Coarse Offset
Adjust = −56mV, Gain = 1152, VIN = +57mV,
CLK_CFG = ‘10’
space
10mV/div
Measured After Bandpass Filter:
0.1Hz Second-Order High-Pass
10Hz Fourth-Order Low-Pass
VOUT Noise (mV/?Hz)
10
VOS RTI = -56mV
VIN = 57mV
1
0.1
0.01
100
Time (100ms/div)
Figure 2-37. 0.1Hz to 10Hz VOUT Peak-to-Peak Noise
for Coarse Offset Adjust = −56mV, Gain = 1152, VIN
= +57mV, CLK_CFG = ‘11’, VNPP (RTI) = 42µVPP
10k
1k
100k
Frequency (Hz)
Figure 2-38. VOUT Noise Spectrum for Coarse Offset
Adjust = −56mV, Gain = 1152, VIN = +57mV,
CLK_CFG = ‘11’
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2.11 General AC Considerations
In addition to normal good analog layout and design practices, there are a few key items to check when
designing with the PGA309.
1. REFIN/REFOUT, pin 16: Keep capacitive loading to 200pF or less.
2. VEXC, pin 1: Keep capacitive loading to 200pF or less.
3. VSA, pin 3 and VSD, pin 10: Keep these within 200mV of each other. Internally, the PGA309 separates
its digital and analog power supplies to minimize cross-talk between the two. Externally, tie the two
together and bypass, directly at the pins, with a 0.1mF capacitor. If an RC filter is used between the two
supplies, ensure that maximum drop is never more than 200mV.
4. GNDA, pin 2 and GNDD, pin11: Ensure that these are both tied directly together and connected to the
same ground point.
5. VSJ, pin 8: This is the negative input to the Output Amplifier and as such, it is high-impedance. Route
low-impedance traces, such as VOUT, and noisy traces away from VSJ. Minimize trace lengths to avoid
unwanted additional capacitance on VSJ.
6. VIN1, pin 4 and VIN2, pin 5: For source resistances greater than or equal to 10kΩ, add a capacitor of 1nF
to 2nF between VIN1 and VIN2 to minimize noise coupling.
7. VIN1, pin 4 and VIN2, pin 5: RFI filtering is always a concern for instrumentation amplifier applications.
RFI signals injected into instrumentation amplifiers become rectified and appear on the output as a DC
drift or offset; high-gain circuits amplify this effect. Figure 2-39 depicts input filtering for the PGA309.
Depending upon the distance of the bridge sensor from the PGA309 and the sensor module shielding,
R1 and R2 may be required. C1 should be equal to C2, and C3 should be ten times larger than C1 to
attenuate any common-mode signals that become differential due to the mismatch in C1 and C2. All
input filter components should be located directly at the PGA309 inputs to avoid and trace lengths from
becoming receiving RFI antennas.
VEXC
R1
VIN1
Front-End
PGA
C1
(1)
C3
R2
(2)
Mux
C2
VIN2
PGA309
(1)
Figure 2-39. Input Filtering
58
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Chapter 3
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Operating Modes
This chapter describes the operating modes of the PGA309.
Topic
...........................................................................................................................
Page
3.1
3.2
Power-On Sequence and Normal Stand-Alone Operation ....................................... 60
EEPROM Content and Temperature Lookup Table Calculation ............................... 62
3.3
3.4
3.5
Checksum Error Event ....................................................................................... 70
Test Pin ............................................................................................................ 70
Power-On Initial Register States .......................................................................... 71
3.2.1
Temperature Lookup Table Calculation
............................................................
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59
Power-On Sequence and Normal Stand-Alone Operation
3.1
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Power-On Sequence and Normal Stand-Alone Operation
The PGA309 internal state machine controls the operations of the part in Stand-Alone Mode, without any
external digital controller. In this mode, the PGA309 performs the functions of a Two-Wire interface master
to read the data from the EEPROM.
The PGA309 has power-on reset (POR) circuitry to reset the internal registers and subcircuits to their
initial states. This power-on reset also occurs when the supply is detected to be too low so that the
PGA309 is in a known state when the supply becomes valid again. The threshold for the POR circuit is
typically 2.2V for VSA rising and 1.7V for VSA falling.
After the power supply becomes valid, the PGA309 waits for approximately 33ms and then attempts to
read the configuration register data (Register 3—Register 6 bit settings) from the first part of the external
EEPROM device. If the EEPROM has the proper programmed flag word (0x5449, “TI” ASCII) in address
locations 0 and 1, the PGA309 will continue reading the EEPROM. Otherwise, the PGA309 will wait for
1.3 seconds before trying again. If the PGA309 detects that there was no response from the EEPROM
and the TwoWire bus was in a valid idle state (SCL = ‘1’, SDA = ‘1’), then the PGA309 will wait for 1.3
seconds and try again. If the Two-Wire bus is stuck with SDA = ‘0’, the PGA309 will try to free the bus by
sending extra clocks down SCL (see Chapter 4, Digital Interface, for details), and wait for 33ms before
trying to read the EEPROM again. If the EEPROM configuration read is successful (including valid
Checksum1 data) and either bits ADCS or CEN in Register 6 are set to ‘1’, the PGA309 will trigger the
Temp ADC to measure the temperature information as configured in the configuration registers. For 16-bit
resolution results, the converter takes approximately 125ms to complete a conversion. Once the
conversion is complete, the PGA309 begins reading the Lookup Table from EEPROM address locations
16 and higher, to calculate the settings for the Gain and Zero DACs using the piecewise linear
interpolation algorithm. The PGA309 reads the entire Lookup Table and determines if the checksum for
the Lookup Table (Checksum2) is correct. Each entry in the Lookup Table requires approximately 500ms
to read from the EEPROM. Once Checksum2 is determined to be valid, the calculated value for the Gain
and Zero DACs is updated into their respective registers, and the Output Amplifier (VOUT) is enabled. The
PGA309 then begins looping through this entire procedure, starting again with reading the configuration
data from the first part of the EEPROM. This loop continues indefinitely.
NOTE: For PRG Pin Connected to VOUT
During the entire initial power-on sequence, the PGA309 VOUT is disabled (high-impedance)
until valid EEPROM contents are verified and an ADC conversion is complete, as described
above and illustrated in Figure 3-1. In true three-wire connection (VS, GND, and VOUT with
PRG pin shorted to VOUT), with OWD = ‘1’ (Register 4, bit D15), the time interval after
power-up is the only opportunity that an external communications controller can initiate digital
communication with the PGA309 and trigger a one second delay in the internal state
machine. After VOUT is enabled no further digital communication is possible, unless power is
cycled.
If the PGA309 detects that there is no EEPROM device present (that is, it does not receive an
acknowledge to a slave address byte sent to the EEPROM), the PGA309 will wait for approximately one
second and try again. It will continue in this loop indefinitely with VOUT disabled.
At any time, if the PGA309 is addressed through the Two-Wire or One-Wire interface with OWD = ‘0’
(Register 4, bit D15), the internal state machine aborts its cycle and initiates a 1s delay. After the 1s delay
has timed out, a EEPROM read is started. The 1s delay is reset every time the PGA309 is addressed.
This allows an external microcontroller to control the function of the PGA309, as long as some
communication activity is addressed to the PGA309 at least once per second. VOUT will stay in the state
(enabled or disabled) that it was in before the PGA309 was addressed. If full microcontroller control of the
PGA309 is desired from initial power-on, then the Test pin should be brought high to enable the output
after the internal PGA309 registers have been configured to their desired states.
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Power-On
Disable
VOUT
Power
Valid
?
No
Yes
Wait
33ms
Begin
EEPROM
Read
Wait
1 second
No
EEPROM
Acknowledge
?
No
Two-Wire
Bus Stuck
Yes
Try to Free
Two-Wire Bus
Yes
Wait
1 second
No
Programmed
Flag Values
Correct
?
Yes
Read
First Part
of EEPROM
Wait
25ms
Disable
VOUT
No
Checksum1
Correct
?
No
Start Temp ADC
Single Conversion
Temp ADC
Yes
Continuous Conversion
(CEN = '1')
?
Read
Second Part
of EEPROM
Wait for
Conversion
Complete
Yes
ADCS = '1'
or
CEN = '1'
?
125ms Delay
(16-Bit
resolution)
No
No
Wait
25ms
Yes
Update
Gain and Zero
DACs
Yes
Set Configuration
Registers to
EEPROM Values
Checksum2
Correct
?
Set Gain and
Zero DACs
to POR Values
Enable
VOUT
Figure 3-1. State Machine—Power-On Sequence and Operation in Stand-Alone Mode
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EEPROM Content and Temperature Lookup Table Calculation
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EEPROM Content and Temperature Lookup Table Calculation
The PGA309 uses an industry standard, Two-Wire, external EEPROM (typically, a SOT23 package). A
1k-bit minimum EEPROM is needed if all 17 temperature coefficients are used. Larger EEPROMs may be
used to provide additional user space for serial number, lot code, or other product data.
The 16-bit data words used by the PGA309 are stored in the external EEPROM, least significant 8-bit byte
first, as shown in Figure 3-2.
PGA309 Internal Registers
D15 D14 D13 D12 D11 D10 D9
Location '1'
Upper Byte
D8
D7
D6
D5
D4
D3
D2
D1
D0
Location '0'
Lower Byte
External EEPROM
EEPROM Address
D7
D6
D5
D4
D3
D2
D1
D0
00h
D15 D14 D13 D12 D11 D10 D9
D8
01h
Figure 3-2. PGA309 Internal Registers Map to External EEPROM Addresses
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Table 3-1 outlines the external EEPROM contents for a 1k−bit EEPROM. For a detailed External
EEPROM Example refer to Appendix A.
The first part of the EEPROM (16 8-bit bytes), address location 1/0 through address location 15/14,
contains the EEPROM Programmed Flag and the PGA309 configuration data for Registers 3, 4, 5, and 6.
Included at the end of this section is Checksum1, at address location 15/14.
The second part of the EEPROM (108 8-bit bytes), address location 17/16 through address location
123/122, contains the temperature coefficient Lookup Table for the Zero DAC (Fine Offset Adjust) and
Gain DAC (Fine Gain Adjust). There can be up to 17 temperature index values with corresponding scale
factors for the Gain DAC and Zero DAC. The temperature values in the Lookup Table represent points on
the piecewise linear curves that compensate for sensor span and offset temperature drifts. Each
temperature value corresponds to respective slope factors for the Gain DAC and Zero DAC. The DAC
values are linearly interpolated for a measured temperature that does not fall directly on a stored
temperature value.
Second Part
First Part
Table 3-1. 1k-Bit External EEPROM Contents
EEPROM
Address
Location ‘1’
(Decimal)
EEPROM
Address
Location ‘0’
(Decimal)
1
0
EEPROM Programmed Flag; 5449h = “TI” ascii
3
2
Not used, but include in Checksum1 calculation; available for user data.
5
4
Not used, but include in the Checksum1 calculation; available for user
data.
7
6
Value for PGA309 Register 3, Reference Control and Linearization
9
8
Value for PGA309 Register 4: PGA Coarse Offset and Gain/Output
Amplifier Gain
11
10
Value for PGA309 Register 5: PGA Configuration and Over/Under-Scale
Limit
13
12
Value for PGA309 Register 6: Temp ADC Control
15
14
Checksum1= FFFFh − sum(hex values of location 1/0 thru 13/12)
Checksum1 truncated above 16 bits
17
16
T0 (Temperature Index Value for Temp ≤ T0)
19
18
Z0 (Zero DAC Value for Temp ≤ T0)
21
20
G0 (Gain DAC Value for Temp ≤ T0)
23
22
T1 (Temperature Index Value T1)
25
24
ZM1 (Zero DAC Multiplying Slope Factor for T1 ≤ Temp ≤ T0)
27
26
GM1 (Gain DAC Multiplying Slope Factor for T1 ≤ Temp ≤ T0)
...
...
...
...
...
...
...
...
...
113
112
T16 (Temperature Index Value T1)
115
114
ZM16 (Zero DAC Multiplying Slope Factor for T15 ≤ Temp ≤ T16)
117
116
GM16 (Gain DAC Multiplying Slope Factor for T15 ≤ Temp ≤ T16)
119
118
TEND (End of Lookup Table → 7FFFh)
121
120
ZMEND (End of Lookup Table; value ignored but included in Checksum2)
123
122
GMEND (End of Lookup Table; value ignored but included in Checksum2)
Checksum2 = FFFFh − sum(Hex values of location 17/16 thru 123/122)
Checksum2 truncated above 16 bits
125
124
Not used; available for user data
127
126
Not used; available for user data
Content (All data are stored as two 8-bit bytes)
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T0, T1, T2 ... Tx (where x ≤ 16) are the temperature index values in the Lookup Table. These are output
results from the Temp ADC. The values must be monotonically increasing from minimum to maximum for
the Lookup Table to function correctly. Note that this does not necessarily correspond to increasing
temperature. For example, if a diode voltage is being measured by the Temp ADC, its readings will be
decreasing with temperature. However, the Lookup Table must still be built from minimum Temp ADC
reading to the maximum Temp ADC reading. The data format for Tx is 16-bit data with a format
dependent upon which Temp ADC mode is selected (see Section 6.2.7, Register 6: Temp ADC Control
Register).
Z0 is the value of the Zero DAC setting for temperatures T0 and below. Z0 data format is unsigned 16-bit
data. The equation for the Zero DAC value is:
VZdesired
· 65,536
Zx =
VREF
(
(
(13)
where 0 ≤ Zx ≤ 65535 (programmable range) and 0.1V ≤ Zero DAC ≤ VSA − 0.1V (analog limits).
G0 is the value of the Gain DAC setting for temperatures T0 and below. G0 data format is unsigned 16−bit
data. The equation for the Gain DAC value is:
1
3
Gx = Gaindesired · · 65,536
3
2
(
(
(14)
where 0.3333333 ≤ Gain DAC ≤ 0.9999898 and 0 ≤ Gx ≤ 65535.
ZM1, ZM2 … ZMi are multiplying slope factors for each piecewise linear segment for the Zero DAC
adjustment. They are calculated based on the desired values Z1, Z2 … Zx (calculated same as Z0) of the
Zero DAC for T1, T2 … Tx respectively. The equation for calculating the ZMi slope factors is:
ZMi = 256
Zx - Z(x - 1)
Tx - T(x - 1)
(15)
The ZMi scale factor of 256 is to format the decimal value for PGA309 internal binary arithmetic. These
numbers are 16-bit, Twos Complement data format. See Table 3-2 for an example of the Lookup Table.
GM1, GM2 … GMi are multiplying slope factors for each piecewise linear segment for the Gain DAC
adjustment. They are calculated based on the desired values G1, G2 … Gx (calculated the same as G0)
of the Gain DAC for T1, T2, T3 …Tx, respectively. The equation for calculating the GMi slope factors is:
GMi = 256
Gx - G(x - 1)
Tx - T(x - 1)
(16)
The GMi scale factor of 256 is to format the decimal value for PGA309 internal arithmetic. These numbers
are 16-bit, Two’s-Complement data format.
The end of the Lookup Table is flagged by temperature index value TEND = 7FFFh in the temperature index
data. The ZMEND value of this entry is ignored but is included in Checksum2. The ZMEND value should be
set to zero. The GMEND value of this entry becomes Checksum2, the checksum for the second part of the
EEPROM.
Example 3-1 details the calculation of Lookup Table values and how the PGA309 lookup table linear
interpolation algorithm works.
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3.2.1 Temperature Lookup Table Calculation
Example 3-1. Temperature Lookup Table Calculation
In Figure 3-3, G0−G7 are the exact desired settings at T0−T7, respectively, for the Gain DAC. GM1−GM7 are
the slopes of the piecewise linear curves that connect G0 to G1, G1 to G2, G2 to G3, G3 to G4, G4 to G5, G5
to G6, and G6 to G7. This example demonstrates how the Lookup Table is constructed and how the Lookup
Logic with Linear Interpolation Algorithm accurately calculates the setting for the Gain DAC at TREAD = 25°C.
Note that TREAD = 25°C does not fall on an exact data point (Tx, Gx). Temperature coefficients for both the
Gain DAC and the Zero DAC are calculated to complete the Lookup Table.
Given:
1. Desired Gain DAC values as in Figure 3-3 and Zero DAC values as in Figure 3-4.
2. Internal Temperature Mode with resolution set to 12-bit (16-bit data format: 12-bit, sign-extended,
right-justified, Twos Complement).
3. VREF = +5V.
Find:
Gain DAC slope factors (GMi) and Zero DAC slope factors (ZMi).
G0
1.0
Gain DAC Value (decimal)
Temp
(°C)
G1
GM1
0.9
0.8
GM2
G2
0.7
G7
G5
0.6
GM7
0.5
GM6
GM3
G3
0.4
G6
GM5
-40
-30
-20
-10
0
10
20
30
Gain
DAC
1
0.9
0.7
0.4
0.3333
0.6
0.4756
0.6543
G4
GM4
0.3
-40
-30
-20
-10
0
10
20
T0
T1
T2
T3
T4
T5
T6
Temperature (°C)
30
T7
TREAD
Figure 3-3. Desired Gain DAC Values
Z4
2.0
Z7
Zero DAC Value (decimal)
1.8
ZM5
1.6
Zero
DAC
Z5
1.4
ZM7
ZM4
1.2
Z3
Z2
1.0
ZM6
Z6
ZM3 = 0
0.8
0.6
ZM2
0.4
0.2
Temp
(°C)
Z1
Z0
0
-40
T0
-40
-30
-20
-10
0
10
20
30
0.1
0.2
1
1
2
1.5
1
2
ZM1
-30
-20
-10
0
10
20
30
T1
T2
T3
T4
T5
T6
T7
Temperature (°C)
Figure 3-4. Desired Zero DAC Values
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Step 1:
Calculate Temp ADC counts for the temperature range of interest using Table 3-2.
Table 3-2. Temp ADC Temperature vs Counts
Temperature
(°C)
Temp ADC
(Counts)
Temp ADC
(Hex)
−40
−640
FD80
−30
−480
FE20
−20
−320
FEC0
−10
−160
FF60
0
0
0000
10
160
00A0
20
320
0140
25
400
0190
30
480
01E0
The resolution for the Temp ADC in Internal Temperature Mode is 0.0625°C/count.
For positive temperatures (for example, 20°C):
(20°C)/(0.0625°C/count) = 320 → 140h → 0001 0100 0000
Twos Complement is not performed on positive numbers. Simply convert the number to binary code
with 16-bit, right-justified format, and MSB = ‘0’ to denote a positive sign. Extend the sign to the upper
4 bits.
20°C will be read by the Temp ADC as 0000 0001 0100 0000 → 140h
For negative temperatures (that is, −20°C):
(|−20|)/(0.0625°C/count) = 320 → 140h → 0001 0100 0000
Generate the Twos Complement of a negative number by complementing the absolute value binary
number and adding 1. Extend the sign, denoting a negative number by MSB = ‘1’. Extend the sign to
the upper 4 bits to form the 16-bit word.
−20°C will be read by the Temp ADC as 1111 1110 1100 0000 → FEC0h.
Step 2:
Calculate Gain DAC temperature coefficients using Table 3-3.
For the Gain DAC desired counts (that is, G3 = 0.4):
Gx = (GainDESIRED − 1/3)(3/2)(65536)
G3 = (0.4 − 1/3)〈3/2)(65536) = 6553.6
0 ≤ Gx ≤ 65535
0.3333333 ≤ Gain DAC ≤ 0.9999898
For positive slopes (that is, GM5):
GM5 = [(G5 − G4)/(T5 − T4)][256]
GM5 = [(26214.4 − 0)/(160 − 0)][256] = 41943.04
Integer [41943.04] = 41943
GM5 = 41943 → A3D7h → 1010 0011 1101 0111
For negative slopes (that is, GM2):
GM2 = [(G2 − G1)/(T2 − T1)][256]
GM2 = [(36044.8 − 55705.6)/(−320 − {−480})][256] = −31457.28
Integer [−31457.28] = −31457
Generate the Twos Complement of −31457:
GM2 = 851Fh → 1000 0101 0001 1111
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NOTE: Gain DAC Slopes
If the Gain DAC slope computes to a count > 65535, there is a problem. The Temp ADC
must be reconfigured for lower resolution or the number of points in the Lookup Table must
be increased to bring the slopes within the PGA309 computation region.
Table 3-3. Gain DAC Temperature Coefficient Calculation
(1)
Temp
(°C)
Temp
Index
Temp
ADC
(Counts)
Gain
DAC
Desired
Value
Gain
DAC
Desired
Index
Gain DAC
Desired
(Counts)
Gain
DAC
Slope
Gain DAC Slope Formula
Gain
DAC
Slope (1)
(Counts)
Gain
DAC
Slope
(Hex)
−40
T0
−640
1
G0
65535
G0
G0 = G0
65535
FFFF
−30
T1
−480
0.9
G1
55705.6
GM1
GM1 = [(G1 − G0)/T1 − T0)][256]
−15727
C291
−20
T2
−320
0.7
G2
36044.8
GM2
GM2 = [(G2 − G1)/T2 − T1)][256]
−31457
851F
−10
T3
−160
0.4
G3
6553.6
GM3
GM3 = [(G3 − G2)/T3 − T2)][256]
−47104
4800
0
T4
0
0.3333
G4
0
GM4
GM4 = [(G4 − G3)/T4 − T3)][256]
−10496
D700
10
T5
160
0.6
G5
26214.4
GM5
GM5 = [(G5 − G4)/T5 − T4)][256]
41943
A3D7
20
T6
320
0.4756
G6
13985.4
GM6
GM6 = [(G6 − G5)/T6 − T5)][256]
−19566
B392
30
T7
480
0.6543
G7
31552.3
GM7
GM7 = [(G7 − G6)/T7 − T6)][256]
28107
6DCB
Integer [Gain DAC Slope Formula].
Step 3:
Calculate Zero DAC temperature Coefficients using Table 3-4.
For the Zero DAC desired counts (for example, Z5 = 1.5):
Zx = (VZDESIRED/VREF)(65536)
Z5 = (1.5/5)(65536) = 19660.8
0 ≤ Zx ≤ 65535
0.1V ≤ Zero DAC Analog Range ≤ (VSA − 0.1V)
0V ≤ Zero DAC Programming Range ≤ VREF
For positive slopes (for example, ZM4):
ZM4 = [(Z4 − Z3)/(T4 − T3)][256]
ZM4 = [(26214.4 − 13107.2)/(0 − {−160})][256] = 20971.52
Integer [20971.52] = 20972
ZM4 = 20972 → 51ECh → 0101 0001 1110 1101
For negative slopes (for example, ZM6):
ZM6 = [(Z6 − Z5)/(T6 − T5)][256]
ZM6 = [(13107.2 − 19660.8)/(320 − 160)][256] = −10485.76
Integer [−10485.76] = −10486
Generate the Twos Complement of −10486:
ZM6 = D70Ah → 1101 0111 0000 1010
NOTE: Zero DAC Slopes
If the Zero DAC slope computes to a count > 65535, there is a problem. The Temp ADC
must be reconfigured for lower resolution or the number of points in the Lookup Table must
be increased to bring the slopes within the PGA309 computation region.
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Table 3-4. Zero DAC Temperature Coefficient Calculation
(1)
Temp
(°C)
Temp
Index
Temp
ADC
(Counts)
Zero
DAC
Desired
Value
Zero
DAC
Desired
Index
Zero DAC
Desired
(Counts)
Zero
DAC
Slope
Zero DAC Slope Formula
Zero
DAC
Slope (1)
(Counts)
Zero
DAC
Slope
(Hex)
−40
T0
−640
0.1
Z0
1310.7
Z0
Z0 = Z0
1311
051F
−30
T1
−480
0.2
Z1
2621.4
ZM1
ZM1 = [(Z1 − Z0)/T1 − T0)][256]
2097
0831
−20
T2
−320
1
Z2
13107.2
ZM2
ZM2 = [(Z2 − Z1)/T2 − T1)][256]
16777
4189
−10
T3
−160
1
Z3
13107.2
ZM3
ZM3 = [(Z3 − Z2)/T3 − T2)][256]
0
0000
0
T4
0
2
Z4
26214.4
ZM4
ZM4 = [(Z4 − Z3)/T4 − T3)][256]
20972
51EC
10
T5
160
1.5
Z5
19660.8
ZM5
ZM5 = [(Z5 − Z4)/T5 − T4)][256]
−10486
D70A
20
T6
320
1
Z6
13107.2
ZM6
ZM6 = [(Z6 − Z5)/T6 − T5)][256]
−10486
D70A
30
T7
480
2
Z7
26214.4
ZM7
ZM7 = [(Z7 − Z6)/T7 − T6)][256]
20972
51EC
Integer [Zero DAC Slope Formula].
Step 4:
Assemble the Lookup Table, as shown in Table 3-5.
Table 3-5. Lookup Table Contents
Temp
(°C)
Temp
Index
Zero DAC
Slope
Gain DAC
Slope
EEPROM Tx
(Hex)
EEPROM ZMi
(Hex)
EEPROM
GMi
(Hex)
−40
T0
Z0
G0
FD80
051F
FFFF
−30
T1
ZM1
GM1
FE20
0831
C291
−20
T2
ZM2
GM2
FEC0
4189
851F
−10
T3
ZM3
GM3
FF60
0000
4800
0
T4
ZM4
GM4
0000
51EC
D700
10
T5
ZM5
GM5
00A0
D70A
A3D7
20
T6
ZM6
GM6
0140
D70A
B392
30
T7
ZM7
GM7
01E0
51EC
6DCB
—
TEND
ZMEND
GMEND
7FFF
0000
B5D8
Use the calculated values from Step 2 and Step 3.
Set TMEND to 7FFFh to indicate the end of the Lookup Table.
Set ZMEND to 0000h.
Calculate GMEND as Checksum2 (truncate results above 16-bit):
GMEND = Checksum2 = FFFFh − sum(Hex values of all entries in the Lookup Table except GMEND)
GMEND = FFFFh − C4A27h
GMEND = FFFFF4B5D8h
GMEND = Checksum2 = B5D8h
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Step 5:
Calculate Ideal value for Gain DAC at TREAD = +25°C using Table 3-6.
Table 3-6. Gain DAC vs Temperature
Tx
Temp (°C)
Gx
Gain DAC
T0
−40
G0
1
T1
−30
G1
0.9
T2
−20
G2
0.7
T3
−10
G3
0.4
T4
0
G4
0.3333
T5
10
G5
0.6
T6
20
G6
0.4756
TREAD
25
GREAD
Calculated
T7
30
G7
0.6543
Linear Interpolation for Gain DAC (TREAD = 25°C):
GREAD = {[(G7 − G6)/(T7 − T6)] [TREAD − T6]} + G6
GREAD = {[(0.6543 − 0.4756)/(30 − 20)] [25 − 20]} +0.4756
GREAD = 0.56495
Step 6:
Reference calculation algorithm for Gain DAC using Lookup Table.
Table 3-7 outlines the calculation algorithm used inside the PGA309 for linear interpolation and calculation
of the Gain DAC setting for TREAD = 25°C. From Table 3-3 the computations for GM1-GM7 at T1-T7, for
given values at G1-G7, are known. In addition, the starting values (T0 and G0) were defined. Step 5
shows the Actual Gain DAC value for TREAD = 25°C should be 0.56495 V/V if the linear interpolation part of
the calculation algorithm is working properly.
Table 3-7. Gain DAC Lookup Table Calculation Algorithm
(1)
Temp
(°C)
Tx
Temp
ADC
(Counts)
GAC Calculation
Running
GAC Value (1)
(Counts)
Actual Gain
DAC (V/V)
−40
T0
−640
G0
−30
T1
−480
GM1
65535
GAC0 = G0
65535
0.9999898
−15727
GAC1 = GAC0 + [GM1(T1 − T0)/256]
55706
−20
T2
−320
GM2
0.9000041
−31457
GAC2 = GAC1 + [GM2(T2 − T1)/256]
36045
−10
T3
−160
0.7000020
GM3
−47104
GAC3 = GAC2 + [GM3(T3 − T2)/256]
6605
0
T4
0.4005229
0
GM4
−10496
GAC4 = GAC3 + [GM4(T4 − T3)/256]
45
10
0.3337911
T5
160
GM5
41943
GAC5 = GAC4 + [GM5(T5 − T4)/256]
26259
0.6004537
20
T6
320
GM6
−19566
GAC6 = GAC5 + [GM6(T6 − T5)/256]
14030
0.4760539
30
T7
480
GM7
28107
T7 > TREAD → YES!
—
—
25
TREAD
400
—
—
GAC_TREAD = GAC6 + [GM7(TREAD − T6)/256]
22813
0.565399169
—
TEND
32767 (7FFFh)
—
—
The Lookup Table is read to the end to verify
Checksum2
—
—
GMi
Gain DAC
Slope (1)
(Counts)
Integer [GAC Calculation].
Each time the Temp ADC does a conversion, it reads the entire external EEPROM. The first part of the
EEPROM is dedicated to fixed setup parameters for the PGA309 that do not change with temperature. As
the PGA309 reads the second half of the EEPROM, it begins a running calculation of the Gain DAC
setting with temperature (the PGA309 runs a similar calculation for the Zero DAC setting). The model in
Table 3-7 includes an accumulator named GAC (G Accumulator). When the PGA309 reads T0, the initial
Gain DAC setting (G0) is stored in GAC0 (GAC at T0READ). Next, T1 is read and slope GM1 is multiplied
by the difference between T1 and T0 (a scale divisor of 256 is used to convert back to decimal counts for
our model) and added to GAC0 to form the new accumulator value, GAC1 (GAC at T1READ). This
process continues in a sequential fashion as the PGA309 reads through the entire Lookup Table. As each
temperature index value (Tx) is read, it is compared against TREAD, the current Temp ADC conversion
result. If Tx > TREAD, it is known that TREAD is between Tx and T(x − 1). In this example, it occurs after T7 is
read. The accumulator contents, GAC6 (GAC at T6), are modified by the addition of (TREAD − T6)(GM7).
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The resulting GAC_TREAD is the linearly interpolated setting for the Gain DAC at TREAD = 25°C. The
actual Gain DAC value is slightly different than the theoretical value calculated in Step 5 due to Gain DAC
resolution and computation rounding. The rest of the EEPROM is read through TEND for error checking with
Checksum2 at the end of the Lookup Table. If Checksum2 is valid then the Gain DAC is updated with the
computed value GAC_TREAD = 0.565399169.
GAC Calculation (for example, GAC2):
GAC1 = 55706; GM2 = −31457; T2 = −320; T1 = −480
GAC2 = GAC1 + [GM2(T2 − T1)/256]
GAC2 = 55706 + [−31457(−320−{−480})/256] = 36045.375
Integer [GAC2] = Integer [36045.375] = 36045
GAC2 = 36045
Actual Gain DAC (for example, GAC2):
GAC2 = 36045
Gain DAC = [(GACx/65536)(2/3)] + 1/3
Gain DAC = [(36045 / 65536)(2/3)] + 1/3 = 0.7000020
Gain DAC at GAC2 = 0.7000020
3.3
Checksum Error Event
If at any time the PGA309 detects an invalid Checksum1 from the first part of the EEPROM, the PGA309
will disable VOUT, wait for approximately 33ms, and try to read the EEPROM again from the beginning. It
will continue to reread the EEPROM indefinitely.
If at any time the PGA309 detects an invalid Checksum2 from the second part of the EEPROM (the
Lookup Table data), it will disable VOUT, set the Gain and Zero DACs to their POR values, return to the
read configuration register portion (first part of the EEPROM) of the loop, and then try to read the
EEPROM Lookup Table again when the next temperature conversion completes.
3.4
Test Pin
The PGA309 has a user-accessible test pin (Test, pin 9), which stops the internal state machine cycle and
enables the output drive (VOUT) when it is brought high (logic ‘1’). This mode can be used for ease of
troubleshooting or initial configuration diagnostics during the system design. During normal (stand-alone)
operation, the Test pin must be connected to GND (logic ‘0’).
If the Test pin is brought high at any time, the following happens:
• The state machine described previously is interrupted and reset to its initial state. Any EEPROM
transactions are interrupted and the Two-Wire bus is released.
• The PGA309 output (VOUT) is enabled.
• All internal registers are kept to their current values. If the Test pin is high when the supply becomes
valid, the registers stay in the initial (POR) state and output is enabled immediately.
• An external controller can modify any of the writable PGA309 registers using either a One-Wire or
Two-Wire digital interface.
In this mode, a test signal can be applied to the front end of the PGA309, which quickly verifies if the
signal path through the PGA309 is functioning correctly.
Test mode (Test pin = high) is recommended during initial calibration because the values in the external
EEPROM are ignored and the PGA309 registers can be individually set as desired.
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3.5
Power-On Initial Register States
In a power-up or low-voltage event, the POR circuit resets all the PGA309 registers to their initial state. All
registers are set to zeros except for the Gain and Zero DACs, which both are set to 4000h.
Table 3-8 summarizes the key settings for the POR states.
Table 3-8. POR States for Key Parameters
Parameter
POR State
Coarse Offset
0V
Front-End PGA Gain
4 (VIN1 = VINP, VIN2 = VINN)
Gain DAC
0.5
Output Amplifier Gain
2
Zero DAC
0.25VREF
VREF Select
External Reference
Lin DAC
0
Fault Monitor
Disabled
Over/Under-Scale
Disabled
VEXC
Disabled
ITEMP
Disabled
Temp ADC
External Signal Mode
Example 3-2 and Figure 3-5 show by example how the PGA309 functions on power-up with the Test pin
high.
Example 3-2. PGA309 Power-Up State
For a +5V supply and configuration as shown in Figure 3-5 with Test pin high, the gain and offset scaling
through the PGA309 on power-up becomes:
VOUT = VDIFF (Front-End PGA Gain)(Output Amplifier Gain)(Fine Gain) + 0.25VREF(Fine Gain)(Output Amplifier
Gain)
VOUT = VDIFF (4)(2)(0.5) + (0.25(5)(0.5)) × 2
VOUT = 4 VDIFF + 1.25V
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+5V
+5V
VSD
VSA
REFIN/REFOUT
SDA
Two-Wire
EEPROM
PRG
SCL
RTEST = 0W
VOUT = 1.25V
VOUT
+5V
VOUT
VEXC
RTEST = 446.5W
VOUT = 4.9V
1kW
VIN2
RTEST = 0W
VDIFF = 0V
PGA309
VFB
VDIFF
RTEST
500W
RTEST = 446.5W
VDIFF = 0.9125V
1kW
VSJ
VIN1
+5V
TEMPIN
Test
GNDA
10kW
GNDD
NOTE: Two conditions for VDIFF and the resulting VOUT are shown in this figure. Condition one is in a dashed,
square box. Condition two is shown in a dashed oval.
Figure 3-5. Signal Path Functional Check with Test = ‘1’ on Power-Up
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Chapter 4
SBOU024B – August 2004 – Revised January 2011
Digital Interface
This chapter describes the digital interface of the PGA309.
Topic
4.1
4.2
...........................................................................................................................
Page
Description ....................................................................................................... 74
Two-Wire Interface ............................................................................................ 74
.....................................................................................
........................................................................
4.3
One-Wire Interface .............................................................................................
4.4
One-Wire Interface Timeout ................................................................................
4.5
One-Wire Interface Timing Considerations ...........................................................
4.6
Two-Wire Access to External EEPROM ................................................................
4.7
One-Wire Interface Initiated Two-Wire EEPROM Transactions ................................
4.8
PGA309 Stand-Alone Mode and Two-Wire Transactions ........................................
4.9
PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations ..............
4.10 One-Wire Operation with PRG Connected to VOUT ..................................................
4.11 Four-Wire Modules and One-Wire Interface (PRG) .................................................
4.2.1
Device Addressing
75
4.2.2
Two-Wire Access to PGA309
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Description
4.1
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Description
There are two digital interfaces on the PGA309. The PRG pin uses a One-Wire, UART-compatible
interface, with bit rates from 4.8kbits/s (4800 baud) to 38.4kbits/s (38400 baud). The SDA and SCL pins
together form an industry standard Two-Wire interface at clock rates from 1kHz to 400kHz. The external
EEPROM uses the Two-Wire interface for programming and reading. Communication to the PGA309
internal registers can be conducted through either digital interface, One-Wire or Two-Wire. Additionally,
the external EEPROM can be programmed either through the PGA309 One-Wire interface pin, PRG, or by
direct connection to the SDA and SCL lines of the Two-Wire interface.
4.2
Two-Wire Interface
The industry standard Two-Wire timing diagram is shown in Figure 4-1, with the timing diagram definitions
in Table 4-1. The key operating states are:
• Bus Idle: Both SDA and SCL lines remain high.
• START Condition: A START condition is defined by a change from high to low in the state of the SDA
line, while the SCL line is high. Each data transfer is initiated with a START condition (see Figure 4-1).
• STOP Condition: A STOP condition is defined by a change from low to high in the state of the SDA
line, while the SCL line is high. Each data transfer is terminated with a repeated START or STOP
condition (see Figure 4-1).
• Data Transfer: The number of data bytes transferred between a START and a STOP condition is not
limited and is determined by the master device. The receiver acknowledges the transfer of each 8-bit
byte of data.
• Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A
device acknowledges by pulling down the SDA line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold
times must be taken into account. On a master receive, the master may terminate the transaction by
generating a Not Acknowledge on the last byte that has been transmitted by the slave (see Figure 4-2).
Table 4-1. Two-Wire Timing Diagram Definitions
Parameter
Min
Max
Units
400
kHz
SCL Operating Frequency
fSCL
1
Bus Free Time Between STOP and START Conditions
tBUF
600
ns
Hold Time After Repeated START Condition.
After this period, the first clock is generated.
tHDSTA
600
ns
Repeated START Condition Setup Time
tSUSTA
600
ns
STOP Condition Setup Time
tSUSTO
600
ns
Data Hold Time
tHDDAT
0
ns
Data Setup Time
tSUDAT
100
ns
SCL Clock LOW Period
tLOW
1300
ns
SCL Clock HIGH Period
tHIGH
600
ns
Clock/Data Fall Time
tF
300
ns
Clock/Data Rise Time
tR
300
ns
tLOW
tF
tR
tHDSTA
SCL
tHDSTA
tHIGH
tHDDAT
tSUSTO
tSUSTA
tSUDAT
SDA
tBUF
P
S
P = STOP Condition, S = START Condition
P
S
Figure 4-1. Two-Wire Timing Diagram
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Data from
Transmitter
Not Acknowledge
Data from
Receiver
Acknowledge
SDA
SCL From
Master
1
2
8
9
S
Acknowledge
Clock Pulse
START
Condition
Figure 4-2. Two-Wire Start and Acknowledge
4.2.1 Device Addressing
Following a START condition issued by the master, a control byte is the first byte received. The seven
most significant bits (MSBs) of the control byte are the slave address for the part being addressed. The
last bit of the control byte is a Read/Write control bit (Read = ‘1’, Write = ‘0’). The slave addresses for the
PGA309 and supported external EEPROM are shown in Figure 4-3.
START
READ/WRITE
S
R/W ACK
SLAVE ADDRESS
1
0
1
0
EEPROM
Slave ID
P10
P9
P8
START
READ/WRITE
S
R/W ACK
SLAVE ADDRESS
1
0
0
0
0
0
0
EEPROM
Block Address
External EEPROM Control Byte Allocation
PGA309 Control Byte Allocation
Figure 4-3. External EEPROM and Control Byte Allocation
4.2.2 Two-Wire Access to PGA309
Figure 4-4 shows the Two-Wire read and write timing supported for interfacing directly with the PGA309
internal registers.
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S 1
0
0
0
0
Control Byte
0
1
0
0
0
0
Control Byte
0
0
0
0
R/W
0
R/W
A
P
A
P
0
0
0
0
Digital Interface
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A = Acknowledge from PGA309
P
A = Not Acknowledge from Controller
C
A
= Acknowledge from Controller
C
NOTES: S = START Condition of Two-Wire Protocol
P = STOP Condition of Two-Wire Protocol
SDA S
Slave ID
Read Timing: Two-Wire
SDA
Slave ID
Write Timing: Two- Wire
Register Address
A
0 P4 P3 P2 P1 P0 P S
Register Address
1
0
0
0
0
Control Byte
0
Slave ID
Register Data (8 LSBs)
0
1
R/W
P
Register Data (8 LSBs)
Register Data (8 MSBs)
A
A
A
P D7 D6 D5 D4 D3 D2 D1 D0 C D15D14D13D12 D11D10 D9 D8 C P
Register Data (8 MSBs)
A
A
A
0 P4 P3 P2 P1 P0 P D7 D6 D5 D4 D3 D2 D1 D0 P D15D14D13D12D11D10 D9 D8 P
Two-Wire Interface
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Figure 4-4. Two-Wire Access to PGA309 Timing
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4.3
One-Wire Interface
The PGA309 may be configured through a One-Wire UART-compatible interface (PRG pin). This interface
also allows programming of the external industry-standard Two-Wire EEPROM device. There are six
possible communication transactions. These transactions allow the internal register pointer to be updated,
the external EEPROM pointer to be updated, internal registers to be read, internal registers to be written,
EEPROM data to be read, and EEPROM data to be written. It is possible to connect the PRG pin, which
uses the One-Wire interface, to the VOUT pin in true three-wire sensor module applications and still allow
for digital programming.
Each transaction consists of several bytes of data transfer. Each byte consists of 10 bit periods. The first
bit is the start bit and is always zero. The PRG pin should always be high when no communication is in
progress. The one-to-zero (high-to-low) transition of the PRG pin signals the start of a byte transfer and all
timing information for the current byte is referenced to this transition. Bits 2 thru 9 are the eight data bits
for the byte and are transferred least significant bit (LSB) first. The tenth bit is the stop bit and is always
‘1’. The recommended circuit implementation to interace to the PRG pin uses a pull-up resistor and/or
pull-up current source with an open drain (or open collector) driver connected to the PRG pin. (The PRG
pin is also an open drain output. The PRG pin may be driven high by the digital programmer (controller)
during transmit from the controller, but some form of pull-up will be required to allow the signal to go high
during a receive transaction, since the PGA309 can only pull the output low. Figure 4-5 shows a typical
connection between the PGA309 PRG pin and the controller.
VS
Controller
VSA
VSD
RPU
PRG
Logic
and
Control
PGA309
GNDA
GNDD
Figure 4-5. Typical PGA309 PRG To Controller Connection
All communication transactions start with an initialization byte transmitted by the controller. This byte (55h)
is used to sense the baud rate used for the communication transaction. The baud rate is sensed during
the initialization byte of every transaction. This baud rate is used for the entire transaction. Each
transaction may use a different baud rate if desired. Baud rates of 4800 to 38400 are supported. The
second byte is a command byte transmitted by the controller.
There are six possible commands:
• Set PGA309 Register Address Pointer (01h)
• Set EEPROM Address Pointer (02h)
• Write PGA309 Register (04h)
• Write EEPROM (08h)
• Read PGA309 Register (10h)
• Read EEPROM (20h)
See Figure 4-6 for timing details of these transactions.
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S
1
1
0
1
0
1
0
Initialization Byte (55h)
0
S
1
1
0
1
0
1
0
Initialization Byte (55h)
0
S
1
1
0
1
0
1
0
Initialization Byte (55h)
0
P
P
P
S
S
S
1
S
1
1
0
1
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S
1
S
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Initialization Byte (55h)
0
P
P
P
S
S
S
0
0
0
0
0
0
0
0
1
0
0
0
0
0
P
P
0
0
0
1
0
0
0
P
0
0
0
0
0
0
P
0
0
1
0
0
0
0
P
0
0
0
0
1
0
0
P
EEPROM Read Command (20h)
0
EEPROM Write Command (08h)
0
X
X
P
S P8 P9 P10 X
X
X
X
P
EEPROM Data (8 LSBs)
For EEPROM Address + 0
EEPROM Write Cycle
(5.6ms, typ)
S
EEPROM Data (8 MSBs)
For EEPROM Address + 1
S D8 D9 D10 D11D12 D13 D14 D15 P
Driven by PGA309
EEPROM Data (8 MSBs)
For EEPROM Address + 1
No Communication
Allowed to EEPROM
Register Data (8 MSBs)
S D8 D9 D10 D11D12 D13 D14 D15 P
X
S D0 D1 D2 D3 D4 D5 D6 D7 P
EEPROM Data (8 LSBs)
For EEPROM Address + 0
S D0 D1 D2 D3 D4 D5 D6 D7 P
EEPROM Address Pointer
S P0 P1 P2 P3 P4 P5 P6 P7 P
Register Data (8 LSBs)
S D8 D9 D10 D11 D12 D13 D14 D15 P
Driven by PGA309
Register Data (8 MSBs)
D8 D9 D10 D11 D12 D13 D14 D15 P
S D0 D1 D2 D3 D4 D5 D6 D7 P
One-Byte Period Delay
Allows for Bus Direction Change
Register Data (8 LSBs)
S D0 D1 D2 D3 D4 D5 D6 D7 P
Register Address Pointer
S P0 P1 P2 P3 P4 X
One-Byte Period Delay
Allows for Bus Direction Change
Plus 600ms for EEPROM Access
EEPROM Address Command (02h)
0
1
Register Read Command (10h)
0
Register Write Command (04h)
NOTES: S = START Condition of One- Wire Protocol
P = STOP Condition of One- Wire Protocol
Unless otherwise noted, all transactions are driven by the controller.
PRG
1
Initialization Byte (55h)
0
Read EEPROM Timing
PRG
0
Initialization Byte (55h)
0
Write EEPROM Timing
PRG
0
Register Address Command (01h)
Set EEPROM Address Pointer Timing
PRG
Read PGA309 Register Timing
PRG
Write PGA309 Register Timing
PRG
Set PGA309 Register Address Pointer Timing
One-Wire Interface
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Figure 4-6. One-Wire (PRG) Access to PGA309 and External EEPROM Timing
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Data transfer occurs after the command byte. The number of bytes and direction of data transfer depend
on the command byte.
For the Set PGA309 Register Address Pointer (01h) command, one additional byte is required to be
transmitted by the controller. This is used to select the PGA309 internal register for the next PGA309
Write Register (04h) or PGA309 Read Register (10h) command. For the PGA309 Write Register
command, two additional bytes are required to be transmitted by the controller. These two bytes,
transmitted least significant byte first, are stored in the PGA309 internal register pointed to by the register
address pointer. The addressed register will be updated with all 16 bits simultaneously at the completion
of the transfer of the second byte. For the PGA309 Read Register (10h) command, two additional bytes
are transmitted by the PGA309. The PGA309 waits for eight bit periods after the completion of the
command byte before beginning transmission. This allows time for the controller to ensure that the
PGA309 will be able to control the One-Wire interface. The first byte transmitted is the least significant
byte of the register and the second byte is the most significant byte of the register.
For a One-Wire PGA309 sequence, the transactions may be repeated immediately one after the other, as
shown in Figure 4-7. For a One-Wire PGA309 register read sequence, the transactions may be repeated
after the data has been received from the PGA309, also shown in Figure 4-7.
Set PGA309
Register Address
with Initialization Byte
Set PGA309
Register Address
with Initialization Byte
Send PGA309
Register Read
Command
with Initialization Byte
Send PGA309
Register Write
Command
with Initialization Byte
Wait for PGA309
to Send Start
(~1 Byte Period)
Send Register Data
to PGA309
Receive Register
Data from
PGA309
One-Wire
PGA309 Register Write
Continuous Sequence
One-Wire
PGA309 Register Read
Continuous Sequence
Figure 4-7. One-Wire Access to PGA309 Registers
For the Set EEPROM Address Pointer (02h) command, two additional bytes must be transmitted by the
controller. These are used for the EEPROM address for the next Write EEPROM (08h) or Read EEPROM
(20h) command. For the Write EEPROM (08h) command, two additional bytes are transmitted by the
controller. These two bytes are written to the EEPROM and stored at the address contained in the
EEPROM address pointer. The first byte (least significant byte) is written to the address in the EEPROM
address pointer. The second byte (most significant byte) is written to the address in the EEPROM address
pointer plus one. To avoid any confusion, the EEPROM address pointer is always set to a value that is
even. The first byte is written to the even address and the second byte is written to the next consecutive
odd address.
The controller is responsible for ensuring that the EEPROM device has enough time to successfully
complete the write operation before additional EEPROM communication occurs. For a typical EEPROM,
this will be about 5.6ms (0.6ms for the PGA309 to write a 16-bit byte into the EEPROM and 5ms for the
EEPROM nonvolatile internal write cycle). For the Read EEPROM (20h) command, two additional bytes
are transmitted by the PGA309. The PGA309 waits for eight bit periods after the completion of the
command byte to allow time for data direction change. The PGA309 also waits for a read communication
from the EEPROM device to occur. This will typically be 600ms of additional delay. The first byte
transmitted is the least significant byte (from EEPROM address) and the second byte transmitted is the
most significant byte (from EEPROM address + 1).
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For continuous One-Wire PGA309 EEPROM writes, the controller must insert a typical 5.6ms delay
between transactions, as shown in Figure 4-8. For continuous One-Wire PGA309 EEPROM reads,
transactions may be repeated after the data has been received from the PGA309, as shown in Figure 4-8.
Set EEPROM
Address
with Initialization Byte
Send PGA309
EEPROM Write
Command
with Initialization Byte
Send Data
to
EEPROM
Set EEPROM
Address
with Initialization Byte
Send
EEPROM Read
Command
with Initialization Byte
Wait for PGA309
to Send Start
(~1 Byte Period)
Wait EEPROM
Write Cycle
(5.6ms, typ)
Receive Data
from
EEPROM
One-Wire
EEPROM Write
Continuous Sequence
One-Wire
EEPROM Read
Continuous Sequence
Figure 4-8. One-Wire Access to External EEPROM
If there is an invalid communication transaction or disconnect with the EEPROM, a One-Wire EEPROM
Read will be all 1s.
4.4
One-Wire Interface Timeout
A timeout mechanism is implemented to allow for resynchronization of the One-Wire interface, or if
synchronization between the controller and the PGA309 is lost for any reason. The timeout period is set to
approximately 25ms to 35ms. If the timeout period expires between the initialization byte and the
command byte, between the command byte and any data byte, or between any data bytes, the PGA309
will reset the One-Wire interface circuitry to expect an initialization byte. Every time a byte is transmitted
on the One-Wire interface, this timeout period is restarted.
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4.5
One-Wire Interface Timing Considerations
Figure 4-9 illustrates the key timing and jitter considerations for the One-Wire interface and Table 4-2
contains the specifications for ensured, reliable operation. During a transaction, the baud rate must remain
within ±1% of its initialization byte value; however, the baud rate can change from transaction to
transaction.
BaudTYP
Jitter+
tF
tR
Jitter-
Figure 4-9. One-Wire Through PGA309 Timing Diagram
Table 4-2. One-Wire Timing Diagram Definitions
Parameter
Baud
Typ
Units
38.4K
Bits/s
0.5
%Baud
Fall Time, tF
0.5
%Baud
(1)
±1
%Baud
Jitter
4.8K
Max
Rise Time, tR
(1)
4.6
Min
Transmit jitter from controller to PGA309. Standard UART interfaces will accept data sent from the
PGA309 during One-Wire transactions.
Two-Wire Access to External EEPROM
Figure 4-10 shows the read and write timing for the PGA309 interface to the external EEPROM when the
PGA309 receives commands through the One-Wire interface (PRG pin). All manufacturer reading and
writing modes are allowed when direct Two-Wire access is made to the external EEPROM. Note that full
10-bit EEPROM addressing mode is supported by the PGA309 One-Wire access to the external EEPROM
through the PGA309 Two-Wire interface. A 1k-bit EEPROM minimum is needed for the PGA309
Configuration Register and 17 Lookup Table coefficients. A larger EEPROM can be used to store other
configuration information such as serial number, date code, lot code, etc. In addition, note that the
PGA309 SCL and SDA pins have light internal pull-up current sources to VSD (85mA typical on each pin).
This is more than adequate for most applications that involve placing only the external EEPROM close to
the PGA309 on the same printed circuit board (PCB). Other applications that add load and capacitance to
the SDA and SCL lines may need additional external pull-up resistors to VSD to ensure rise timing
requirements are met at all times. At the end of a EEPROM write cycle, there is a typical 5ms EEPROM
write cycle during which the data is stored in a nonvolatile fashion internally to the EEPROM. During this
time, if Two-Wire direct access is attempted, there will be no acknowledge from the EEPROM. If
communicating to the external EEPROM through the PGA309 One-Wire interface, this EEPROM write
cycle time is a No Communication Allowed time period.
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S
1
0
1
Block Address
Control Byte
0 P10 P9 P8
0
R/W
A
E
Word Address
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S
Block Address
Control Byte
Word Address
A
A
1 0 1 0 P10 P9 P8 0 E P7 P6 P5 P4 P3 P2 P1 P0 E
R/W
A = Acknowledge from EEPROM
E
A = Not Acknowledge from PGA309
P
A
= Acknowledge from PGA309
P
NOTES: S = START Condition of Two-Wire Protocol
P = STOP Condition of Two-Wire Protocol
SDA
Slave ID
S
R/W
Block Address
Control Byte
1 0 1 0 P10 P9 P8 1
Slave ID
EEPROM Data (8 MSBs)
for EEPROM Address + 1
EEPROM Write Cycle
(5ms, typ)
No Communication
Allowed to EEPROM
A
A
A
E D7 D6 D5 D4 D3 D2 D1 D0 P D15 D14 D13 D12 D11 D10 D9 D8 P P
EEPROM Data (8 MSBs)
EEPROM Data (8 LSBs)
for EEPROM Address + 1
for EEPROM Address + 0
EEPROM Data (8 LSBs)
for EEPROM Address + 0
A
A
A
P7 P6 P5 P4 P3 P2 P1 P0 E D7 D6 D5 D4 D3 D2 D1 D0 E D15 D14 D13 D12 D11 D10 D9 D8 E P
EEPROM Read Timing: Two-Wire Through PGA309 One-Wire
EEPROM Random Read Timing: Two-Wire Direct
SDA
Slave ID
EEPROM Write Timing: Two-Wire Through PGA309 One-Wire
EEPROM Write Timing: Two-Wire Direct
S
Two-Wire Access to External EEPROM
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Figure 4-10. Two-Wire Access to External EEPROM Timing
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4.7
One-Wire Interface Initiated Two-Wire EEPROM Transactions
One-Wire Interface Initiated Two-Wire EEPROM Transactions
The Write EEPROM and Read EEPROM One-Wire commands initiate a communication transaction on
the Two-Wire bus between the PGA309 and the EEPROM device (see Figure 4-10).
The Write EEPROM command causes the PGA309 to generate a Two-Wire start condition and send a
Two-Wire slave address byte to the EEPROM device with the four MSBs set to ‘1010’ and the three LSBs
set to bits 10−8 of the EEPROM address pointer. The R/W bit is set to ‘0’ to indicate a write instruction. If
the PGA309 receives an acknowledge from the EEPROM device, it then sends a byte with eight LSBs of
the EEPROM address pointer. If the PGA309 receives an acknowledge from this byte, the PGA309 sends
the least significant byte of the data to the EEPROM. Upon successful receipt of an acknowledge to this
byte, the PGA309 transmits the most significant byte. After the acknowledge bit of this byte, the PGA309
generates a Two-Wire stop condition to terminate data transfer to the EEPROM.
The Read EEPROM command causes the PGA309 to generate a Two-Wire start condition and send a
Two-Wire slave address byte to the EEPROM with the four MSBs set to ‘1010’, the three LSBs set to bits
10−8 of the EEPROM Address Pointer, and the R/W bit set to ‘0’ to indicate a write instruction. If the
PGA309 receives an acknowledge from the EEPROM device, it will then send a byte with the eight LSBs
of the EEPROM address pointer. If the PGA309 receives an acknowledge from this byte, the PGA309
generates another Two-Wire START condition, send another slave address byte but this time with the
R/W bit set to ‘1’ to indicate a read instruction. If the PGA309 receives an acknowledge, it continues to
clock the SCL line to receive the first byte from the EEPROM, acknowledge this byte, receive the second
byte, not acknowledge the second byte to terminate data transfer, and then generate a Two-Wire STOP
condition.
4.8
PGA309 Stand-Alone Mode and Two-Wire Transactions
In Stand-Alone Mode (see Chapter 3, Operating Modes), the PGA309 accesses the external EEPROM in
a different fashion than that presented for the One-Wire Interface Initiated Two-Wire Transactions. If all
other POR conditions have been met to allow a PGA309 to allow access to a properly programmed
external EEPROM, the PGA309 will first access the first part of the external EEPROM (configuration
register data) as shown in Figure 4-11.
If the Checksum1 is correct and the PGA309 is triggered by the Temp ADC to read the second part of the
EEPROM, it will proceed as shown in Figure 4-12. If the One-Wire disable bit, OWD, bit 15, in Register 4
is set to ‘1’, initial POR is completed, and a valid Checksum2 is received, the One-Wire interface will be
disabled, the PRG pin becomes high impedance, and One-Wire communication cannot take place unless
power is cycled. This is necessary to allow for direct connection of the PRG pin to VOUT.
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0
0
0
Block Address
Control Byte
1 0
0
R/W
A
E
0
0
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A = Acknowledge from EEPROM
E
A = Not Acknowledge from PGA309
P
A
= Acknowledge from PGA309
P
NOTES: S = START Condition of Two-Wire Protocol
P = STOP Condition of Two-Wire Protocol
SDA S 1 0
Slave ID
0
0
0
Word Address
0
0
EEPROM Read Timing: Two-Wire by PGA309 Master
First Part of EEPROM: Configuration Registers
0
A
E S
0
0
0
Programmed Flag Value (MSBs)
Checksum1 (LSBs)
Address 00Eh
Checksum1 (MSBs)
Address 00Fh
A
A
D7 D6 D5 D4 D3 D2 D1 D0 P D15 D14 D13 D12 D11 D10 D9 D8 P
Register 3, 4, 5, 6 Configuration Data
Programmed Flag Value (LSBs)
P
A
A
A
1 E D7 D6 D5 D4 D3 D2 D1 D0 P D15 D14 D13 D12 D11 D10 D9 D8 P
R/W
Block Address
Control Byte
1 0 1 0
Slave ID
PGA309 Stand-Alone Mode and Two-Wire Transactions
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Figure 4-11. First Part of External EEPROM Timing for Stand-Alone Mode
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0
0
0
Block Address
Control Byte
1 0
0
R/W
A
E
0
0
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A = Acknowledge from EEPROM
E
A = Not Acknowledge from PGA309
P
A
= Acknowledge from PGA309
P
NOTES: S = START Condition of Two-Wire Protocol
P = STOP Condition of Two-Wire Protocol
SDA S 1 0
Slave ID
1
0
0
Word Address
0
0
0
EEPROM Read Timing: Two-Wire by PGA309 Master
Second Part of EEPROM: Lookup Table Coefficients
A
E S
0
0
0
Temperature Index Value T0 (MSBs)
Checksum2 (LSBs)
Checksum2 (MSBs)
A
A
D7 D6 D5 D4 D3 D2 D1 D0 P D15 D14 D13 D12 D11 D10 D9 D8 P
Lookup Table Coefficients
Temperature Index Value T0 (LSBs)
P
A
A
A
1 E D7 D6 D5 D4 D3 D2 D1 D0 P D15 D14 D13 D12 D11 D10 D9 D8 P
R/W
Block Address
Control Byte
1 0 1 0
Slave ID
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PGA309 Stand-Alone Mode and Two-Wire Transactions
Figure 4-12. Second Part of External EEPROM Timing for Stand-Alone Mode
Digital Interface
85
PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
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PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
Whenever the PGA309 is called upon to communicate to the external EEPROM, the PGA309 must
become the master on the Two-Wire interface bus. In order to do this in a reliable and orderly fashion, the
PGA309 contains fault diagnostics to attempt to free a stuck bus. Several monitors and algorithms check
for bus availability, prevent bus contention in case other devices are connected in parallel with the
External EEPROM.
If the PGA309 is ever addressed on its Two-Wire or One-Wire interface, with the PGA309 providing a
successful acknowledge, the PGA309 will cease all transactions as a master on the Two-Wire bus and
give up control for 1.3 seconds. Each time the PGA309 is addressed on the Two-Wire bus, the 1.3 second
timeout is reset, as shown in Figure 4-13.
POR
Wait 33ms
PGA309 is Master
on Two-Wire Bus
PGA309
Addressed?
(One-Wire or
Two-Wire)
No
Yes
Release Bus
and
Stop as Master
Wait 1.3 Second
Figure 4-13. Two-Wire Bus Relinquish by PGA309 in Master Mode
Figure 4-14 details the algorithms used by the PGA309 when it must become master on the Two-Wire
bus. A 33ms timer is started. Now SCL is monitored for being low. If SCL is not low, the PGA309 checks
to see if communication on the Two-Wire bus is between a START and a STOP. If the bus communication
is between a START and a STOP, the PGA309 waits for the 33ms timer to time out, and then checks if
SDA is low. If SDA is not low and SCL is high, the PGA309 becomes bus master. If there is any SCL
activity during the 33ms interval, the 33ms timer will restart.
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PGA309 wants
to be Master
Start 33ms Timer
SCL = 0
?
Yes
Timer > 33ms
?
Yes
No
Between
Start and Stop
?
Yes
Timer > 33ms
?
No
SDA = 0?
Wait 33ms
No
No
Yes
Yes
Timer > 33ms
?
No
Yes
No
No
PGA309
Becomes
Master
SDA = 1
?
Yes
Send START
Send STOP
Bus Free?
SDA = SCL = 1
?
Yes
No
10 SCL Clocks
Sent
?
Yes
No
Send SCL Clock
Figure 4-14. Two-Wire Bus Master Algorithm
If SCL remains low for the entire 33ms timer countdown, the PGA309 waits 33ms before starting the 33ms
timer again to begin to check the bus for an idle state (SDA = SCL = ‘1’).
If SDA is low after the 33ms timer counts down, the PGA309 interprets this as a stuck-bus condition. The
PGA309 attempts to free the stuck bus by sending up to ten clocks down SCL to free up SDA. If it is
successful in causing SDA to go high, the PGA309 sends a START and then STOP sequence to ensure a
complete reset of whichever device was causing the stuck bus. Now the bus should be in an idle state
(SDA = SCL = ‘1’) and the PGA309 can become the master on the bus.
If the PGA309 is communicating on the bus as a master and it sees contention, the PGA309 will release
the bus and retry in 33ms. Contention is defined as the PGA309 wanting SCL high and SCL is low, or
wanting SDA high and SDA is low.
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One-Wire Operation with PRG Connected to VOUT
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4.10 One-Wire Operation with PRG Connected to VOUT
Some sensor applications, require the end-user access to three pins, VS, GND, and Sensor Out. It is also
desired in these applications to digitally calibrate the sensor module after its final assembly of sensor and
electronics. The PGA309 has a mode that allows the One-Wire interface pin (PRG) to be tied directly to
the PGA309 output pin (VOUT), as shown in Figure 4-15.
For the PGA309 + sensor calibration, it is necessary to configure and reconfigure internal registers on the
PGA309 and then measure the analog voltage on VOUT as a result of these register value settings. To do
this while VOUT is tied to PRG requires the ability to enable and disable VOUT. This allows a multiplexing
operation between PRG using the connection as a bidirectional digital interface and VOUT driving the
connection as a conditioned sensor output voltage. In addition, it is convenient to configure the Temp ADC
for Single Start Convert mode and delay the start of the Temp ADC until after VOUT is enabled and internal
circuitry has had a chance to settle to accurate final values. This is especially important in applications that
use the Linearization Circuit, tie the sensor to VEXC, and measure temperature external to the PGA309
(that is, a temperature sense series resistor in the upper or lower excitation leg of the bridge sensor).
Register 7 (Output Enable Counter Control Register) contains the control bits for setting both the amount
of time VOUT is active on the common connection and also the delay from the time VOUT is enabled to the
start of a Temp ADC conversion. These individual bits are defined in Table 4-3 and Table 4-4.
+5V
Three-Wire Sensor Module
Easy-to-use
Calibration
+5V
+5V
VSD
VSA
REFIN/REFOUT
0.1mF
Sensor
Out
SDA
Two-Wire
EEPROM
Power Supply
+ -
PRG
SCL
VOUT
RISO
100W
VFB
RFB
100W
VEXC
VIN2
PGA309
GND
VCC
1-Wire
GND
PC
RS232
SDA
SCL
CL
10nF
PGA309
EVM Interface Board
CF
150pF
Bridge
Sensor
VIN1
VSJ
TEMPIN
Test
GNDA
GNDD
Figure 4-15. One-Wire Operation with PRG Tied to VOUT
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Table 4-3. Temp ADC—Delay After VOUT Enable (Register 7)
(1)
Temp ADC
Delay
(ms) (1)
DLY3
[11]
DLY2
[10]
DLY1
[9]
DLY0
[8]
Decimal Equivalent
(Initial Counter Value)
0
0
0
0
0
0
0
0
0
1
1
10
0
0
1
0
2
20
0
0
1
1
3
30
0
1
0
0
4
40
0
1
0
1
5
50
0
1
1
0
6
60
0
1
1
1
7
70
1
0
0
0
8
80
1
0
0
1
9
90
1
0
1
0
10
100
1
0
1
1
11
110
1
1
0
0
12
120
1
1
0
1
13
130
1
1
1
0
14
140
1
1
1
1
15
150
Temp ADC delay = intial counter value x 10ms.
Table 4-4. Output Enable Counter for One-Wire Interface/VOUT Multiplexed Mode (Register 7)
Digital In put (Binary)
OEN7......OEN0
[7......0]
Decimal Equivalent
(Initial Counter Value)
VOUT Enable Timeout
(ms)
0000 0000
0
0 (VOUT Disabled)
0010 0000
32
320
0100 0000
64
640
0110 0000
96
960
1000 0000
128
1280
1010 0000
160
1600
1100 0000
192
1920
1110 0000
224
2240
1111 1111
255
2550
Figure 4-16 details the output enable/disable state machine. Upon initial POR, there is a 25ms wait for
communication through either digital interface to prevent the PGA309 from going through its POR
sequence and reaching Stand-Alone Mode. The output enable/disable state machine can be forced to run
at any time the PGA309 is powered and either digital interface (One-Wire or Two-Wire) can write to
Register 7. Writing a non-zero value to OEN7:OEN0 will cause VOUT to be immediately enabled and the
Output Enable Counter to be loaded with the OEN7:OEN0 value (decimal equivalent x 10ms = initial
Output Enable Counter value). VOUT remains enabled until this initial Output Enable Counter value is
decremented to 0 by 10ms increments. VOUT is then disabled and a one second timeout begins waiting for
bus activity on either digital interface (PRG pin for three-wire sensor application). As long as there is
activity on the PRG pin, the one second timeout will be continually reset. After one second of no bus
activity, the PGA309 stops and the state machine will try to read the EEPROM. It is important to store
invalid data in the programmed flag values of the EEPROM for this calibration process, to prevent it from
being read, which could change the register settings in the PGA309. This will also force the one second
timeout to be reset and allow as long as needed for communication to start and stop on PRG. Once all
registers in the PGA309 have been set to their desired values, another write to Register 7 will start the
process all over again so a new analog value of VOUT can be measured.
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Wait for
Register 7 Write
One-Wire or
Two-Wire
Valid
Write to
Register 7
?
No
Yes
VOUT =
Disable
Yes OEN7:OEN0
Yes
Temp ADC
Conversion
Complete
Load
Temp ADC
Delay Counter
(DLY3:DLY0)
Start Single
Temp ADC
Conversion
all 0's
?
No
Wait 10ms
VOUT = Enable
Load
Output Enable
Counter
(OEN7:OEN0)
Yes
No
Decrement
Temp ADC
Delay Counter
Temp ADC
Delay Count
=0?
PGA309
Stand-Alone
(2)
Mode
Yes
CEN = 0
?
Read
EEPROM
No
No
Valid
EEPROM
(1)
Flag Values?
Wait 10ms
No
Decrement
Output Enable
Counter
Output Enable Yes
Counter = 0
?
Yes
VOUT = Disable
Sample
Alarm Bits
Start
1 Second
Timeout
Bus Activity?
One-Wire or
Two-Wire
Yes
No
1 Second
Timeout
Expired?
No
NOTE:
1.
For calibration using PRG tied to VOUT, set EEPROM programmed flag values to invalid values to prevent
PGA309 registers from having their values changed by EEPROM register configuration and lookup table data.
2.
In PGA309 Stand−Alone mode, if OWD (Register 4 [15]) is set to ’1’ in the first part of EEPROM (configuration
part), then the One−Wire interface is disabled and the only way to communicate over the One−Wire interface is to
cycle power on the PGA309 and begin communication over the One−Wire interface within 25ms of power on.
Figure 4-16. Output Enable/Disable State Machine
The second part of the output enable/disable state machine is the Temp ADC delay. During calibration,
the Temp ADC conversion results will be needed at different calibration temperatures. These readings
combined with measured VOUT at the respective calibration temperatures are used to calculate the final
temperature coefficients to be stored in the Lookup Table part of the external EEPROM. To use this
function, the Temp ADC must be set to Single Start Convert mode (CEN = 0, Register 6 [10]). After a write
to Register 7, the Temp ADC delay counter is loaded with the DLY3:DLY0 value (decimal equivalent x
10ms = initial Temp ADC delay counter value). This initial Temp ADC delay counter value is decremented
to 0 by 10ms increments. When it reaches 0, a single Temp ADC conversion is triggered. No additional
write to Register 6 [12] (the ADCS bit) is needed to initiate the conversion. Upon completion of the
conversion, this branch of the state machine returns to waiting for the next valid Register 7 write.
The output enable/disable state machine allows three-wire sensor applications to measure temperature
through the PGA309, against the calibration standard, for the PGA309 + sensor combination. It also
allows PGA309 + sensor characteristics over pressure and temperature to be measured through the
PGA309. These real-world results allow for accurate calculation of temperature coefficients for the Lookup
Table and, therefore, accurate PGA309 + sensor digital calibration on a module-by-module basis.
The values of the Fault Monitor Alarm bits are latched immediately before the output is disabled to allow
their values to be read through the One-Wire interface during factory calibration.
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Once the final values are to be programmed into the EEPROM, it is desirable to have the One-Wire
Interface disabled in three-wire sensor applications. This prevents VOUT changes in the final end-use from
being read back into the PGA309 through the One-Wire interface (PRG pin) and potentially misinterpreted
as bus activity, which could then cause VOUT to become disabled. To disable the One-Wire Interface, set
the OWD bit to ‘1’ during the final EEPROM program write. The OWD (One-Wire Disable) bit is located in
Register 4 [15]. After this final programming, the only way to communicate to the One-Wire Interface (PRG
pin) is to cycle power on the PGA309 and begin communication within 33ms.
4.11 Four-Wire Modules and One-Wire Interface (PRG)
In four-wire module applications, it is essential that the OWD Bit (Register 4 [D15]) be set to '1' to disable
the One-Wire interface after final programming is complete and before the final sensor module is sent out
to the end application. In a four-terminal module, the PRG pin is connected directly to the outside world
and is even more susceptible to noise coupled into it from periodic noise generators. Repetitive noise,
such as a commutating motor or a switching power supply, can cause the PRG circuitry to misinterpret
this noise as valid communication and put the PGA309 into an unpredicted state or, worse, cause
EEPROM corruption.
Even if the OWD bit is set to '1' to disable the One-Wire interface, a 33ms window remains open on
power-up, where periodic noise can be coupled into the PRG pin and be interpreted as coherent
communication. The four-terminal module application, as show in Figure 4-17, requires detailed discussion
and consideration when bringing the PRG pin directly to the outside world.
Power Supply
+ VCC
PC
RS232
PRG
VCC
RP
4.7kW
Customer
Sensor
PRG
VOUT
VIN
GND
GND
SDA
SDA
SCL
SCL
PGA309
10nF
EEPROM
PGA309
PC Interface Board
PGA309
Sensor Interface Board
Temperature
Chamber
-40°C < Temperature < +125°C
Pressure
Input
Figure 4-17. Four-Wire Sensor Module Application
Figure 4-20 depicts details of the PRG circuitry within the PGA309. Additional external protection
components and electromagnetic interferences/radio frequency interference (EMI/RFI) filtering are
included in this discussion. Considerations for programming the PGA309 four-terminal sensor module are
presented with reference to Figure 4-20.
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The PGA309 contains electrostatic discharge (ESD) cells, D2 and D1/SCR1, on the PRG pin to prevent
ESD damage when the device is being handled before installation on a printed circuit board. These same
ESD cells may not be adequate when the PGA309 is installed in a complete circuit with regards to
electrical overstress. The ESD diodes D1 and D2 can handle up to 10mA continuous load. However,
SCR1 will trigger with a 14V level and then drop to 3V at 80mA of sustaining current, as Figure 4-18
shows. If the current is not limited, the voltage will increase again; this increase, combined with higher
currents, may cause permanent damage to the ESD cells and make the PRG circuitry unusable.
SCR with Snap-back Effect
14V Trip Threshold
3V on at 80mA Sustaining
200
IC (mA)
160
120
80
40
0
0
5
10
15
VCE (V)
Figure 4-18. SCR ESD Cell
If miswiring is or external electrical overstresses are anticipated, the PRG pin must be protected by using
external devices. SD1 and SD2 are signal Schottky diodes that steer current away from the internal ESD
cells on the PRG pin during electrical overstress events. R7 will limit the current through SD1 and SD2. Z1
is a zener diode to clamp the energy passed through SD1. The selection of R7 can impact the valid logic
levels at PRG_PGA309 and PRG_ Programmer. SW1 and RON represent the MOSFET switch and
on-resistance used on the PGA309EVM or customer programmer that configures and calibrates the
PGA309 over the One-Wire interface. For the PGA309, logic high is 0.7VSD (3.5V for VSD = 5V) or greater;
logic low is 0.2VSD (1V for VSD = 5V) or less. Logic high is not a concern because there are pull-up
resistors on the PGA309 module and on the programmer. The worst-case condition for logic low is shown
in Figure 4-20; this figure illustrates the condition at approximately 610mV, which is less than the specified
0.2VSD (1V for VSD = 5V) maximum logic low. This configuration will be adequate for up to ±50V of
miswiring on the 1W pin, based on current flow and the power dissipation of the components shown up to
a temperature of +75°C.
Each individual application should be analyzed for electrical overstress and proper programming logic
levels on the PRG pin.
Refer to Figure 4-21 for an illustration of common EMI/RFI filtering and the PRG pin configuration. Most
EMI/RFI filter schemes typically involve connecting the chassis ground to the signal ground via capacitors
in the range of 1nF to 10nF. These capacitors are connected on every pin into and out of the module. In
Figure 4-21, we connect the signal ground to the chassis ground with capacitor C2 (1nF). VCC is
connected to the chassis ground through capacitor C4 (100nF) and capacitor C2 (1nF). We also add
capacitor C1 (10nF) from the PRG pin at the module output and tie it directly to VCC. This configuration is
optimal for rejecting any switching disturbances between the chassis ground and the signal ground.
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EMI/RFI is often seen as disturbance referenced to the chassis ground, as shown in Figure 4-19. A
common source impedance of 50Ω (through R11) is assumed. The disturbance is injected into the PRG
pin of the module, and will then flow through capacitors C3 (10nF), C4 (100nF), and C2 (1nF) as it returns
to chassis ground. A severe disturbance of ±5V at 100kHz will only degrade the logic high voltage on the
PRG pin from 5V to 4.27V, as shown in Figure 5-4. The minimum logic high is 0.7VSD (3.5V for VSD = 5V) ,
and thus there will be no PRG miscommunication caused by this severe disturbance between chassis
ground and signal ground.
5.26
1W
PGA309
4.27
0
10
20
30
20
30
Time (ms)
5.00
VG1
-5.00
0
10
Time (ms)
Figure 4-19. Severe EMI/RFI Disturbance
As a final note, consider Figure 4-20 once more, and observe that in order to program a PRG pin on a
module with large capacitance (for example, with C1 = 10nF) on the PRG pin, the customer programmer
must use a PRG speed-up circuit, which detects a rising edge on the PRG signal. Based on this rising
edge, a switch connects the PRG line to +5V through a 200Ω resistor for 5ms in order to quickly charge
capacitor C1 (10nF) and obtain a reasonable rising edge in logic '0' to logic '1' transitions. The
PGA309EVM has this PRG speed-up circuit already installed in the PC Programmer Interface Board.
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R9
50W
MMSZ4690T1
VCC
+
VS
5V
C3
1nF
C4
100nF
Z1
Chassis
Ground
PGA309 PRG Circuit Equivalent
Shown with ESD Cells
ID1 10mA (max)
-1.004378nA
U1
C1
10nF
R5
10kW
D2
PRG
In
50mV
AM2
-1.417279mA
+
VOL = 0.4V at 4mA
+
U2
SW2
100mW
5V
-
PRG
Out
R4
4.7kW
R6
100W
+
R7
500W
A
SCR1
D1
VF1
ID2 10mA (max)
-963.225037pA
0V
SW
SPST2
SD1
BAT54S
SCR with Snap-back Effect
14V Trip Threshold
3V on, at 80mA Sustaining
SD2
BAT54S
GND
PRG PGA309
143.144277mV
VPGA
5V
C2
1nF
PRG Speed-up Circuit
Greater than 0.7V
Comparator
PGA309 Four-Wire Module
1W Interface
R8
100MW
5ms Pulse on
Rising Edge Trigger
Chassis Ground
R2
200W
+
R10
4.7kW
+
SW3
100mW
-
V1
5V
PRG Programmer
610.151343mV
SW1
100mW
VOL = 0.4V at 4mA
SW
SPST1
+
-
R3
4.7kW
+
VPGM
5V
RON
100W
SN74LVC1G07
PGA309EVM or
Customer Programmer
Figure 4-20. PRG Circuit Protection Logic Levels
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R9
50W
MMSZ4690T1
VCC
+
VS
5V
C4
100nF
Z1
PGA309 PRG Circuit Equivalent
Shown with ESD Cells
ID1 10mA (max)
C3
10nF
R5
10kW
U1
D2
PRG
In
SD1
BAT54S
AM2
+
VOL = 0.4V at 4mA
+
U2
SW2
100mW
-
PRG
Out
SW
SPST2
R4
4.7kW
+
PRG
Programmer
A
SCR1
D1
VF1
ID2 10mA (max)
R6
100W
R7
500W
SCR with Snap-back Effect
14V Trip Threshold
3V on, at 80mA Sustaining
SD2
BAT54S
PRG PGA309
R11
50W
GND
VPGA
5V
+
C2
1nF
PGA309 Four-Wire Module
PRG Interface
R8
100MW
Chassis Ground
Figure 4-21. PRG Circuit EMI/RFI Filtering
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Chapter 5
SBOU024B – August 2004 – Revised January 2011
Application Background
This chapter describes the application background of the PGA309.
Topic
...........................................................................................................................
Page
5.1
5.2
Bridge Sensors ................................................................................................. 98
System Scaling Options for Bridge Sensors ....................................................... 100
5.3
........................................................................................ 100
.................................................................................... 101
Trimming Real World Bridge Sensors for Linearity .............................................. 102
5.2.1
Absolute Scale
5.2.2
Ratiometric Scale
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Bridge Sensors
A typical bridge pressure sensor is shown in Figure 5-1. For a given bridge excitation voltage (VEXC), the
output voltage of the bridge (VP − VN) is a voltage proportional to the pressure applied to the sensor.
VBR+
2kW
2kW
RBRG
2kW
VP
2kW
VEXC
RBRG
2kW
2kW
VN
VBR-
Figure 5-1. Typical Bridge Sensor
Span is the scale factor for VP − VN at full-scale pressure input relative to the bridge excitation (VBR+ −
VBR−). Span is also called FSO (Full-Scale Output), FSS (Full-Scale Sensitivity), Sensitivity, or Gain. For
example, with a bridge excitation voltage of 5V, a 2mV/V FSS implies that the bridge output will be 10mV
at full-scale pressure.
Offset, also known as Zero, is the output of the bridge (VP − VN) with zero pressure applied. Often a bridge
sensor’s Zero may be equal to or greater than its FSS for a given excitation voltage. Figure 5-2 graphically
illustrates the definition of Span and Offset.
0.06
(VP - VN)/VEXC
0.05
0.04
0.03
Span
0.02
Offset
0.01
0
0
0.1
0.2
0.3
0.4
0.5 0.6
P/PMAX
0.7
0.8
0.9
1.0
Figure 5-2. Example of Span and Offset
An ideal sensor would have span and offset curves over temperature, as shown in Figure 5-3. Real-world
sensors have span and offset changes that change over temperature. Both span and offset have
variations at +25°C, linear changes with temperature, and nonlinear changes with temperature. Figure 5-4
and Figure 5-5 illustrate span and offset changes over temperature for a bridge sensor with second-order
nonlinearities. TC1 coefficients represent a linear change with temperature, and TC2 a second-order
change with temperature.
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0.08
Span/VEXC
Offset/VEXC
0.06
Span
0.04
0.02
Offset
0
-0.02
-40
125
Temperature (°C)
Span Error (% of Span at Room Temp)
Figure 5-3. Ideal Span and Offset vs Temperature
20
15
10
5
0
-5
-10
-15
-20
-25
Span at +25°C = 0.5%VEXC
-3
SpanTC1 = -2 ´ 10 %Span/°C
-6
2
SpanTC2 = -2.9 ´ 10 %Span/°C
-30
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Offset Error (% of Span at Room Temp)
Figure 5-4. Effect of Nonlinearity on Bridge Sensor Span Over Temperature
30
25
20
Offset at +25°C = 2%VEXC
-3
OffsetTC1 = 2 ´ 10 %Span/°C
-6
2
OffsetTC2 = 4.4 ´ 10 %Span/°C
15
10
5
0
-5
-10
-15
-20
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 5-5. Effect of Nonlinearity on Bridge Sensor Offset Over Temperature
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System Scaling Options for Bridge Sensors
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Many bridge sensors have a nonlinear output with applied pressure. Figure 5-6 shows the non-ideal
curves for both a positive and negative nonlinear bridge sensor output with applied pressure. The PGA309
provides calibration over temperature for both span and offset, and has dedicated linearization circuitry to
linearize many types of bridge sensors whose outputs are not linear with applied pressure.
10
9
Bridge Output (mV)
8
Positive Bridge Nonlinearity
BV = +0.025 (+2.5% FSR)
7
6
5
4
Negative Bridge Nonlinearity
BV = -0.025 (-2.5% FSR)
3
2
1
0
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7 0.8
Normalized Stimulus (P/PMAX)
0.9
1.0
Figure 5-6. Non-Ideal Curves for Both a Positive and Negative Nonlinear Bridge Sensor Output with
Applied Pressure
5.2
System Scaling Options for Bridge Sensors
There are two system scaling options for bridge sensor outputs: Absolute Scale and Ratiometric Scale.
5.2.1 Absolute Scale
Absolute Scale scales the output range as a percentage of a reference voltage, VREF. For example, the
absolute-scaled output of a bridge sensor can be set to the range of 10% to 90% of VREF. Figure 5-7
illustrates such a case.
+5V
+5V
VREF ADC
(4.096V)
+5V
+5V
VSD
VSA
0.1mF
REFIN/REFOUT
Sensor
Out
SDA
Two-Wire
EEPROM
+5V
PRG
SCL
1 0 1 0 1
GND
(1)
VOUT
RISO
100W
VFB
RFB
100W
System ADC
(2)
VEXC
VIN2
ADC
(1)
PGA309
CL
10nF
(3)
CF
150pF
Bridge
Sensor
VIN1
VSJ
TEMPIN
Test
GNDA
GNDD
Figure 5-7. Absolute Scaling Conditions
100
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5.2.2 Ratiometric Scale
Ratiometric Scale scales the output range as a percentage of the supply voltage. For example, the
ratiometric-scaled output of a bridge sensor can be set to the range of 10% to 90% of VS, shown in
Figure 5-8. Figure 5-9 shows that as the supply voltage, VS, is lowered from +5V to +3V the range for VOUT
of 10% to 90% of VS remains the same. The PGA309 accommodates both Absolute and Ratiometric
scaling of bridge sensors.
+5V
+5V
2kW
2kW
0psi
1 V
DIFF = 0V
4.5kW
2.5V
VP
VDIFF
2.5V
R
500W
R
2kW
2kW
VOS = 0.1VS
VOS = 0.5V
Instrumentation
Amplifier
G = 40
VOUT
R
VN
R
+5V
1 VOUT = 0.5V, 10% VS
2 VOUT = 4.5V, 90% VS
2.040kW
1.960kW
2.550V
2.040kW
1.960kW
2.450V
100psi
2 FSS = 20mV/V
VDIFF = 100mV
Figure 5-8. Ratiometric Configuration, 5V
+3V
+3V
2kW
2kW
0psi
1 V
DIFF = 0V
4.5kW
1.5V
VP
VDIFF
1.5V
R
500W
R
2kW
2kW
VOS = 0.1VS
VOS = 0.3V
Instrumentation
Amplifier
G = 40
VOUT
R
VN
R
+3V
1 VOUT = 0.3V, 10% VS
2 VOUT = 2.7V, 90% VS
2.040kW
1.960kW
1.530V
1.960kW
2.040kW
1.470V
100psi
2 FSS = 20mV/V
VDIFF = 60mV
Figure 5-9. Ratiometric Configuration, 3V
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Trimming Real World Bridge Sensors for Linearity
5.3
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Trimming Real World Bridge Sensors for Linearity
Traditional methods for trimming nonlinear, real-world bridge sensors to a linear, useful function require
additional resistors to be added around the base bridge sensor, as shown in Figure 5-10. This approach
often requires special prepackaged fixtures and special laser trim or manual trim resistors. The trims are
interactive with each other, which requires multiple test/trim/test/trim passes; this only allows for a finite
number of trims and range for a particular bridge sensor.
VBR+
Offset
Drift Trim
VP
Sensitivity
Drift Trim
VN
Zero
Trim1
Zero
Trim2
VBR-
Figure 5-10. Typical Trim Configuration
The PGA309 provides a modern digital trim approach for bridge sensors, as shown in Figure 5-11. This
technique allows for post-package trim of both the bridge sensor and its signal conditioning electronics.
The digital trimming is simplified through the use of a computer interface and spreadsheet analysis
computation tools. A near-infinite number of trim cycles can be performed with finer resolution, wider
range, and less interaction between trimmed parameters than the traditional trim method. Packaging shifts
are eliminated.
VS
Nonlinear
Bridge
Transducer
VEXC
Reference
Linearization
Circuit
Lin DAC
Fault
Monitor
Over/Under-Scale
Limiter
Auto-Zero
PGA
Linear VOUT
Digital Calibration
Internal
Temperature
External
Temperature
Lookup and Interpolation
Logic
EEPROM
(SOT23-5)
1K Bit
Temp ADC
External Temperature
PGA309
Figure 5-11. PGA309 Trim Configuration
102
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Chapter 6
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Register Descriptions
This chapter describes the PGA309 registers and their contents.
Topic
6.1
6.2
...........................................................................................................................
Page
Internal Register Overview ................................................................................ 104
Internal Register Map ....................................................................................... 104
............
6.2.1
Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
6.2.2
Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer =
00001) ................................................................................................. 106
6.2.3
Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer =
00010) ................................................................................................. 107
6.2.4
Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer
= 00011) ............................................................................................... 108
6.2.5
Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select
Register (Read/Write, Address Pointer = 00100) ................................................ 109
6.2.6
Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write,
Address Pointer = 00101) ........................................................................... 111
6.2.7
Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
6.2.8
Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer =
00111) ................................................................................................. 116
6.2.9
Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
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..................
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104
113
117
103
Internal Register Overview
6.1
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Internal Register Overview
Table 6-1. Internal Register Overview
Address Pointer
P3
P2
P1
P0
0
0
0
0
0
Register 0—Temp ADC Output
0
0
0
0
1
Register 1—Fine Offset Adjust (Zero DAC)
R/W
Fine Offset Adjust (Zero DAC)
Setting
0
0
0
1
0
Register 2—Fine Gain Adjust (Gain DAC)
6.2
Type
Register Controls
R/W
Fine Gain Adjust (Gain DAC) Setting
R/W
Reference Configuration Settings;
VEXC Enable; Linearization Setting
R
Temp ADC Output Data
0
0
0
1
1
Register 3—Reference Control and
Linearization Register
0
0
1
0
0
Register 4—Front End PGA Coarse Offset
Adjust and Gain Select; Output Amplifier
Gain Select
R/W
Front End PGA Coarse Offset
Setting; PGA Gain Select; Output
Amplifier Gain Select; One-Wire
Disable
0
0
1
0
1
Register 5—PGA Configuration and
Over/Under Scale Limit
R/W
Over/Under Scale Limits, Polarities,
Enable; Fault Comparator Select
0
0
1
1
0
Register 6—Temp ADC Control Register
R/W
Temp ADC Conversion Speed, Ref
Select; Int/Ext Temp Mode Select;
Ext Temp PGA Configuration;
TEMPIN Current Source Enable
0
0
1
1
1
Register 7—Output Enable Counter Control
R/W
Temp ADC Delay Setting; One-Wire
Interface Output Enable Setting
1
0
0
0
Register 8—Alarm Status
0
(1)
Register Description
(1)
P4
R
Fault Monitor Comparator Outputs
Type: R = Read-only, R/W = Read/Write
Internal Register Map
6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
Bit #
Bit Name
POR Value
D15
D14
D13
D12
D11
D10
AD15 AD14 AD13 AD12 AD11 AD10
0
0
0
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
0
0
0
0
0
0
0
0
0
0
Bit Descriptions:
AD[15:0] Temp ADC Output
Internal Temperature Mode: 12-bit + sign extended, right justified, Twos Complement data format
External Temperature Mode: 15-bit + sign extended, right-justified, Twos Complement data format
Temp ADC
Internal REF
On-Chip
Diodes
DS
ADC
16-Bit Digital Output:
12-Bit + Sign Extended, Right-Justified,
Twos Complement Data Format
Resolution/Update Rate
Register 6[1,0]
Figure 6-1. Internal Temperature Mode; Register 6[9] = ‘1’
104
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Table 6-2. Internal Temperature Mode−Data Format (12-Bit Resolution). TEN = 1;
R1, R0 = ‘11’ (1)
(1)
Temperature (°C)
Digital Output AD15............AD0
(Binary)
Digital Output (Hex)
150
0000 1001 0110 0000
960
128
0000 1000 0000 0000
800
127.9375
0000 0111 1111 1111
07FF
100
0000 0110 0100 0000
640
80
0000 0101 0000 0000
500
75
0000 0100 1011 0000
04B0
50
0000 0011 0010 0000
320
25
0000 0001 1001 0000
190
0.25
0000 0000 0000 0100
4
0
0000 0000 0000 0000
0
−0.25
1111 1111 1111 1100
FFFC
−25
1111 1110 0111 0000
FE70
−55
1111 1100 1001 0000
FC90
The resolution for the Temp ADC in Internal Temperature Mode is 0.0625°C/count.
For positive temperatures (for example, +50°C):
(50°C)/(0.0625°C/count) = 800 → 320h → 0011 0010 0000
50°C will be read by the Temp ADC as 0000 0011 0010 0000 → 0320h
For negative temperatures (for example, −25°C):
(|[−25]|)/(0.0625°C/count) = 400 → 190h → 0001 1001 0000
Convert to Twos Complement notation.
−25°C will be read by the Temp ADC as 1111 1110 0111 0000 → FE70h
VREF = 2.5V
Positive
Input
VREF = 2.5V
0V
+5V
+2.5V
-2.5V
x1
TEMPIN
Negative
Input
DS
ADC
16-Bit
Temp
PGA
+FS Digital Out
-FS Digital Out
Temp
ADC
Figure 6-2. External Signal Mode; Register 6 = ‘0000 0100 0011 0000’
Table 6-3. External Signal Mode—Data Format Example (Register 6 = ‘0000 0100 0011 0011’), 15-Bit
+ Sign Resolution. REN = 1, RS = 1
(1)
TEMPIN
(V)
Temp ADC Input
(V)
Temp ADC Input
(Ratio to Full Scale)
(1)
Digital Output
AD15............AD0
(Binary)
Digital Output
(Hex)
0.0001
2.49992371
+0.999969 VREFT
0111 1111 1111 1111
7FFF
+0.625
+1.875
+0.75 VREFT
0110 0000 0000 0000
6000
+1.25
+1.25
+0.5 VREFT
0100 0000 0000 0000
4000
+1.925
+0.575
+0.23 VREFT
0001 1101 0111 0001
1D71
+2.4999
+0.00007629
+(1/32768) VREFT
0000 0000 0000 0001
0001
+2.5
0
+0 VREFT
0000 0000 0000 0000
0000
+2.50007629
−0.00007629
−(1/32768) VREFT
1111 1111 1111 1111
FFFF
+3.075
−0.575
−0.23 VREFT
1110 0010 1000 1111
E28F
+3.75
−1.25
−0.5 VREFT
1100 0000 0000 0000
C000
+4.375
−1.875
−0.75 VREFT
1010 0000 0000 0000
A000
+5
−2.5
−1 VREFT
1000 0000 0000 0000
8000
VREFT can be VSA, VEXC, or VREF.
Register Descriptions 105
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6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
Bit #
D15
Bit Name
POR Value
D14
D13
D12
D11
D10
ZD15 ZD14 ZD13 ZD12 ZD11 ZD10
0
1
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ZD9
ZD8
ZD7
ZD6
ZD5
ZD4
ZD3
ZD2
ZD1
ZD0
0
0
0
0
0
0
0
0
0
0
0
Bit Descriptions:
ZD[15:0]: Zero DAC control, 16-bit unsigned data format
Table 6-4. Zero DAC—Data Format Example (VREF = +5V)
(1)
Digital Input
(Hex)
Digital Input
ZD15............ZD0
(Binary)
Zero DAC Output
(V)
Zero DAC Output
0000
0000 0000 0000 0000
0
0 VREF
0001
0000 0000 0000 0001
0.00007629
(1/65536) VREF
051F
0000 0101 0001 1111
0.100021362
0.02 VREF (1)
4000
0100 0000 0000 0000
1.25
0.25 VREF
0.50 VREF
8000
1000 0000 0000 0000
2.5
C000
1100 0000 0000 0000
3.75
0.75 VREF
FAE1
1111 1010 1110 0001
4.899978638
0.98 VREF (1)
FFFF
1111 1111 1111 1111
4.999923706
0.9999847 VREF
Ensured by design Zero DAC Range of Adjustment (0.02VREF to 0.98VREF)
Zero DAC Equation:
Decimal # Counts = (VZERO DAC/VREF)(65536)
0.1V ≤ Zero DAC Analog Range ≤ VSA − 0.1V
0 ≤ Zero DAC Programming Range ≤ VREF
Zero DAC Example:
Want: VZERO DAC = 0.5V
Given: VREF = 5V
Decimal # Counts = 0.5 / (5/65536) = 6553.6
Use 6554 counts → 199Ah → 0001 1001 1001 1010
106
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6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
Bit #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
GD15
GD14
GD13
GD12
GD11
GD10
GD9
GD8
GD7
GD6
GD5
GD4
GD3
GD2
GD1
GD0
POR Value
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Descriptions:
GD[15:0]: Gain DAC control, 16-bit unsigned data format
Table 6-5. Gain DAC—Data Format
Digital Input
(Hex)
Digital Input
ZD15............ZD0
(Binary)
Gain Adjust
0000
0000 0000 0000 0000
0.333333333
0001
0000 0000 0000 0001
0.333343505
32F2
0011 0010 1111 0010
0.466003417
4000
0100 0000 0000 0000
0.500000000
6604
0110 0110 0000 0100
0.598999023
9979
1001 1001 0111 1001
0.733001708
CC86
1100 1100 1000 0110
0.865997314
FFFF
1111 1111 1111 1111
1.000000000
Gain DAC Equation:
1 LSB = (1.000000000 – 0.333333333) / 65536 = (2/3)/65536
Decimal # Counts = (Desired Gain – 1/3)/(3/2)(65.536)
0.3333333 ≤ Gain DAC ≤ 0.9999898
0 ≤ Gain DAC Counts ≤ 65535
Gain DAC Example:
Want: Fine Gain = 0.68
Decimal # Counts = (0.68 − 1/3)(3/2)(65536) = 34078.72
Use 34079 counts → 851Fh → 1000 0101 0001 1111
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6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address
Pointer = 00011)
Bit #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
RFB
RFB
RFB
RFB
EXS
EXEN
RS
REN
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
POR Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Descriptions:
RFB: Reserved Factory Bit: Set to zero for proper operation
EXS: Linearization Adjust and Excitation Voltage (VEXC) Gain Select (Range1 or Range2)
0 = Range 1 (−0.166VFB < Linearization DAC Range < +0.166VFB, VEXC Gain = 0.83VREF)
1 = Range 2 (−0.124VFB < Linearization DAC Range < +0.124VFB, VEXC Gain = 0.52VREF)
EXEN: VEXC Enable
1 = Enable VEXC
0 = Disable VEXC
RS: Internal VREF Select (2.5V or 4.096V)
0 = 4.096V
1 = 2.5V
REN: Enable/Disable Internal VREF (disable for external VREF—connect external VREF to
REFIN/REFOUT pin)
0 = External Reference (disable internal reference)
1 = Internal Reference (enable internal reference)
LD[7:0]: Linearization DAC setting, 7-bit + sign
Table 6-6. Linearization DAC—Data Format Example (Range 1: −0.166VFB <
Linearization DAC Range < +0.166VFB)
Digital Input
(Hex)
Digital Input
LD7......LD0
FF
1111 1111
−0.166 VFB
E0
1110 0000
−0.12548 VFB
C0
1100 0000
−0.08365 VFB
A0
1010 0000
−0.04183 VFB
81
1000 0001
−0.00131 VFB
80
1000 0000
0 VFB
00
0000 0000
0 VFB
01
0000 0001
+0.00131 VFB
20
0010 0000
+0.04183 VFB
40
0100 0000
+0.08365 VFB
60
0110 0000
+0.12548 VFB
7F
0111 1111
+0.166 VFB
Linearization Adjust
Linearization DAC Equation:
Decimal # Counts = |Desired VFB Ratio| / (Full-Scale Ratio/127)
Linearization DAC Example:
Given: (Range 1: −0.166VFB < Linearization DAC Range < +0.166VFB)
Want: VFB Ratio = −0.082
Decimal # Counts = 0.082/(0.166/127) = 62.7349
Use 63 counts → 0x3F → 0011 1111
Add a ‘1’ in the Sign Bit (MSB, bit 7) to denote the negative ratio:
Final Linearization DAC Setting: 1011 1111 → BFh
108
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6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select
Register (Read/Write, Address Pointer = 00100)
Bit #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
0WD
GO2
GO1
GO0
GI3
GI2
GI1
GI0
RFB
RFB
RFB
OS4
OS3
OS2
OS1
OS0
POR Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Descriptions:
OWD: One-Wire Disable (only valid while VOUT is enabled, for use when PRG is connected to VOUT)
1 = Disable
0 = Enable
GO[2:0]: Output Amplifier Gain Select, 1-of-7 plus internal feedback disable
GI[3:0]: Front-End PGA Gain Select, 1-of-8, and Input Mux Control
GI[3] = Input Mux Control
GI[2:0] = Gain Select
RFB: Reserved Factory Bit: Set to zero for proper operation
OS[4:0]: Coarse Offset Adjust on Front-End PGA, 4-bit + sign
1LSB = (VREF)(0.85E − 3)
Table 6-7. Output Amplifier—Gain Select
GO2
[14]
GO1
[13]
GO0
[12]
Output Amplifier Gain
0
0
0
2
0
0
1
2.4
0
1
0
3
0
1
1
3.6
1
0
0
4.5
1
0
1
6
1
1
0
9
1
1
1
Disable Internal Feedback
Table 6-8. Front End PGA—Gain Select
GI2
GAIN SEL2
[10]
GI1
GAIN SEL1
[9]
GI0
GAIN SEL0
[8]
Front-End PGA Gain
0
0
0
4
0
0
1
8
0
1
0
16
0
1
1
23.27
1
0
0
32
1
0
1
42.67
1
1
0
64
1
1
1
128
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Table 6-9. Front End PGA—MUX Select
GI3
MUX CNTL
(1)
Input MUX State
(1)
0
VIN1 = VINP, VIN2 = VINN
1
VIN1 = VINN, VIN2 = VINP
VIN1 = Pin 4, VIN2 = Pin 5, VINP = positive input to Front-End PGA, VINN
= negative input to Front-End PGA; see detailed block diagram
(Figure B-1).
Table 6-10. Coarse Offset Adjust on Front-End PGA—Data Format Example (VREF = +5V)
110
OS4
[4]
OS3
[3]
OS2
[2]
OS1
[1]
OS0
[0]
Coarse Offset
(mV)
1
1
1
1
1
−59.5
−14(VREF)(0.85E − 3)
1
1
1
1
0
−55.25
−13 (VREF)(0.85E − 3)
1
1
1
0
1
−51
−12 (VREF)(0.85E − 3)
1
1
1
0
0
−46.75
−11 (VREF)(0.85E − 3)
1
1
0
1
1
−42.5
−10 (VREF)(0.85E − 3)
1
1
0
1
0
−38.25
−9 (VREF)(0.85E − 3)
1
1
0
0
1
−34
−8(VREF)(0.85E − 3)
1
1
0
0
0
−29.75
−7 (VREF)(0.85E − 3)
1
0
1
1
1
−29.75
−7 (VREF)(0.85E − 3)
1
0
1
1
0
−25.5
−6 (VREF)(0.85E − 3)
1
0
1
0
1
−21.25
−5 (VREF)(0.85E − 3)
1
0
1
0
0
−17
−4 (VREF)(0.85E − 3)
1
0
1
0
1
−12.75
−3 (VREF)(0.85E − 3)
1
0
0
1
0
−8.5
−2 (VREF)(0.85E − 3)
1
0
0
0
1
−4.25
−1 (VREF)(0.85E − 3)
1
0
0
0
0
0
0VREF
0
0
0
0
0
0
0VREF
0
0
0
0
1
+4.25
+1 (VREF)(0.85E − 3)
0
0
0
1
0
+8.5
+2 (VREF)(0.85E − 3)
0
0
0
1
1
+12.75
+3 (VREF)(0.85E − 3)
0
0
1
0
0
+17
+4 (VREF)(0.85E − 3)
0
0
1
0
1
+21.25
+5 (VREF)(0.85E − 3)
0
0
1
1
0
+25.5
+6 (VREF)(0.85E − 3)
0
0
1
1
1
+29.75
+7 (VREF)(0.85E − 3)
0
1
0
0
0
+29.75
+7 (VREF)(0.85E − 3)
0
1
0
0
1
+34
+8 (VREF)(0.85E − 3)
0
1
0
1
0
+38.25
+9 (VREF)(0.85E − 3)
0
1
0
1
1
+42.5
+10 (VREF)(0.85E − 3)
0
1
1
0
0
+46.75
+11 (VREF)(0.85E − 3)
0
1
1
0
1
+51
+12 (VREF)(0.85E − 3)
0
1
1
1
0
+55.25
+13 (VREF)(0.85E − 3)
0
1
1
1
1
+59.5
+14 (VREF)(0.85E − 3)
Register Descriptions
Coarse Offset
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6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write,
Address Pointer = 00101)
Bit #
D15
D14
Bit Name
RFB
RFB
POR Value
0
0
D13
D12
CLK_ CLK_
CFG CFG
1
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EXT
EN
INT
EN
EXT
POL
INT
POL
RFB
OU
EN
HL2
HL1
HL0
LL2
LL1
LL0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Descriptions:
RFB: (Reserved Factory Bit): Set to zero for proper operation
CLK_CFG[1:0]: Clocking scheme for Front-End PGA auto-zero and Coarse Offset DAC Chopping
EXTEN: Enable External Fault Comparator Group (INP_HI, INP_LO, INN_LO, INN_HI)
1 = Enable External Fault Comparator Group
0 = Disable External Fault Comparator Group
INTEN: Enable Internal Fault Comparator Group (A2SAT_LO, A2SAT_HI, A1SAT_LO, A1SAT_HI,
A3_VCM)
1 = Enable Internal Fault Comparator Group
0 = Disable Internal Fault Comparator Group
EXTPOL: Selects VOUT output polarity when External Fault Comparator Group detects a fault, if EXTEN
=1
1 = Force VOUT high when any comparator in the External Fault Comparator Group detects a fault
0 = Force VOUT low when any comparator in the External Fault Comparator Group detects a fault
INTPOL: Selects VOUT output polarity when Internal Fault Comparator Group detects a fault, if INTEN =
1
1 = Force VOUT high when any comparator in the Internal Fault Comparator Group detects a fault
0 = Force VOUT low when any comparator in the Internal Fault Comparator Group detects a fault
OUEN: Over/Under-Scale Limit Enable.
1 = Enable Over/Under-Scale limits
0 = Disable Over/Under-Scale limits
HL[2:0]: Over-Scale Threshold Select
LL[2:0]: Under-Scale Threshold Select
Table 6-11. Clock Configuration (Front End PGA Auto-Zero and Coarse Adjust
DAC Chopping)
ClK_CFG1
[13]
CLK_CFG0
[12]
PGA Front End
Auto-Zero
Coarse Adjust DAC
Chopping
0
0
7kHz typical
3.5kHz typical
0
1
7kHz typical
Off (none)
1
0
7kHz typical, Random Clocking
3.5kHz typical, Random Clocking
1
1
7kHz typical
3.5kHz typical, Random Clocking
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Table 6-12. Over-Scale Threshold Select (VREF = +5V)
HL2
[5]
HL1
[4]
HL0
[3]
Over-Scale Threshold
(V)
Over-Scale Threshold
0
0
0
4.854
0.9708 VREF
0
0
1
4.805
0.9610 VREF
0
1
0
4.698
0.9394 VREF
0
1
1
4.580
0.9160 VREF
1
0
0
4.551
0.9102 VREF
1
0
1
3.662
0.7324 VREF
1
1
0
2.764
0.5528 VREF
1
1
1
Reserved
—
Table 6-13. Under-Scale Threshold Select (VREF = +5V)
112
LL2
[2]
LL1
[1]
LL0
[0]
Under-Scale Threshold
(V)
Under-Scale Threshold
0
0
0
0.127
0.02540 VREF
0
0
1
0.147
0.02930 VREF
0
1
0
0.176
0.03516 VREF
0
1
1
0.196
0.03906 VREF
1
0
0
0.225
0.04492 VREF
1
0
1
0.254
0.05078 VREF
1
1
0
0.274
0.05468 VREF
1
1
1
0.303
0.06054 VREF
Register Descriptions
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6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
Bit #
D15
D14
D13
Bit Name
RFB
RFB
ADC2X
D12
POR Value
0
0
0
D11
D10
ADCS ISEN CEN
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TEN
AREN
RV1
RV0
M1
M0
G1
G0
R1
R0
0
0
0
0
0
0
0
0
0
0
0
Bit Descriptions:
RFB: Reserved Factory Bit: Set to zero for proper operation
ADC2X: Temp ADC runs 2x faster (not for internal Temp Sense Mode)
0 = 1x conversion speed (6ms typical, R1, R0 = ‘00’, TEN = ‘0’, AREN = ‘0’)
1 = 2x conversion speed (3ms typical, R1, R0 = ‘00’, TEN = ‘0’, AREN = ‘0’)
ADCS: Start (restart) the Temp ADC (single conversion control if CEN = 0)
0 = No Start/Restart Temp ADC
1 = Start/Restart Temp ADC (each write of a ‘1’ causes single conversion; when conversion is
completed ADCS = ‘0’)
ISEN: TEMPIN Current source (ITEMP) Enable
1 = Enable 7µA current source, ITEMP
0 = Disable 7µA current source, ITEMP
CEN: Enable Temp ADC Continuous Conversion Mode
1 = Continuous Conversion mode
0 = Noncontinuous Conversion mode
TEN: Internal Temperature Mode Enable
1 = Enable Internal Temperature Mode
0 = External Signal Mode
For TEN = 1, set the following bits as shown:
ADC2X = 0
ADCS = set as desired
CEN = set as desired
AREN = 0
RV[1:0] = 00
M[1:0] = 00
G[1:0] = 00
R[1:0] = Set for desired Temp ADC resolution.
AREN: Temp ADC internal reference enable
1 = Enable Temp ADC internal reference (internal reference is 2.048V typical)
0 = Disable Temp ADC internal reference (use external ADC reference; see RV[1:0])
RV[1:0]: Temp ADC External Reference Select (VSA, VEXC, VREF)
M[1:0]: Temp ADC Input Mux Select
G[1:0]: Temp ADC PGA Gain Select (x1, 2, 4, or 8)
R[1:0]: Temp ADC Resolution (Conversion time) Select
Table 6-14. Temp ADC Reference Select
AREN
[8]
RV1
[7]
RV0
[6]
0
0
0
VREF
0
0
1
VEXC
0
1
0
VSA
0
1
1
Factory Reserved
X
Temp ADC Internal REF
(2.048V)
1
X
Temp ADC Reference
(VREFT)
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Table 6-15. Temp ADC Input Mux Select
M1
[5]
M0
[4]
Temp ADC PGA
+Input
Temp ADC PGA
−Input
0
0
TEMPIN
GNDA
0
1
VEXC
TEMPIN
1
0
VOUT
GNDA
1
1
VREF
TEMPIN
Table 6-16. Temp ADC PGA Gain Select
G1
[3]
G0
[2]
Temp ADC PGA Gain
0
0
1
0
1
2
1
0
4
1
1
8
Temp ADC
Internal REF
On-Chip
Diodes
16-Bit Digital Output:
12-Bit + Sign Extended, Right-Justified,
Twos Complement Data Format
DS
ADC
Resolution/Update Rate
Register 6[1,0]
Figure 6-3. Internal Temperature Mode (Register 6 [9] = ‘1’)
VREF
Temp ADC
Internal REF
VREFT = 2.048V
VEXC
VREF
VOUT
TEMPIN
GNDA
VEXC
VSA
Temp ADC REF Mux
VREFT
Temp
ADC
Input
Mux
DS
Temp
ADC
Temp ADC PGA
(x1, 2, 4, or 8)
Register 6[3,2]
Register 6[G1,G0]
16-Bit Digital Output:
Twos Complement, Signed Value
(13 to 16 significant bits, right-justified)
Resolution/Update Rate
Register 6[1,0]
Register 6[R1,R0]
Figure 6-4. External Signal Mode (Register 6 [9], TEN = ‘0’)
114
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Temp ADC Input Mux Configuration #1
Register 6[5:4] = '00' (default)
Register 6[M1,M0] = '00' (default)
Temp ADC Input Mux Configuration #2
Register 6[5:4] = '01'
Register 6[M1,M0] = '01'
Positive Input
Positive Input
VEXC
TEMPIN
GNDA
TEMPIN
Negative Input
Negative Input
Temp ADC
PGA
Temp ADC Input Mux Configuration #3
Register 6[5:4] = '10'
Register 6[M1,M0] = '10'
Temp ADC Input Mux Configuration #4
Register 6[5:4] = '11'
Register 6[M1,M0] = '11'
Positive Input
Positive Input
VREF
VOUT
GNDA
Temp ADC
PGA
TEMPIN
Negative Input
Negative Input
Temp ADC
PGA
Temp ADC
PGA
Figure 6-5. Temp ADC Mux Configurations
Table 6-17. Temp ADC—Resolution (Conversion Time) Select
R1
[1]
R0
[0]
Internal
Temperature Mode
[TEN = 1]
External Signal Mode [TEN = 0],
External Reference [AREN = 0]
External Signal Mode [TEN = 0],
Internal Reference [2.048V, AREN = 1]
0
0
9-Bit + Sign, 0.5°C, (3ms)
11-Bit + Sign (6ms)
11-Bit + Sign (8 ms)
0
1
10-Bit + Sign, 0.25°C,
(6ms)
13-Bit + Sign (24ms)
13-Bit + Sign (32ms)
1
0
11-Bit + Sign, 0.125°C,
(12ms)
14-Bit + Sign (50 ms)
14-Bit + Sign (64 ms)
1
1
12-Bit + Sign, 0.0625°C,
(24ms)
15-Bit + Sign (100 ms)
15-Bit + Sign (128 ms)
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6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer =
00111)
Bit #
D15
D14
D13
D12
Bit
Name
RFB
RFB
RFB
RFB
POR
Value
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DLY3 DLY2 DLY1 DLY0 OEN7 OEN6 OEN5 OEN4 OEN3 OEN2 OEN1 OEN0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Descriptions:
RFB: Reserved Factory Bit: Set to zero for proper operation
DLY[3:0]: Temp ADC Delay
Temp ADC begins conversion after DLY[3:0] x 10ms after valid WRITE to this register. Initial
count, DLY[3:0] is decremented every 10ms to zero count and then Temp ADC is enabled. This
allows for linearization and excitation analog circuitry to settle before applying temperature
compensation.
OEN[7:0]: Output Enable Counter for One-Wire Interface/VOUT Multiplexed Mode.
VOUT is enabled after a valid WRITE to this register. Any non-zero value = VOUT Enable initial
count, decremented every 10ms to zero count, and then VOUTis disabled. After VOUT is disabled,
a one-second internal timer is set. If serial communication takes place from an outside controller
on either the One-Wire interface (PRG pin) or Two-Wire interface, then VOUT will remain disabled
as long as the PGA309 is addressed at least once per second.
Table 6-18. Temp ADC—Delay After VOUT Enable
(1)
DLY3
[11]
DLY2
[10]
DLY1
[9]
DLY0
[8]
Decimal Equivalent
(Initial Counter Value)
Temp ADC Delay
(ms)
0
0
0
0
0
0
0
0
0
1
1
14
0
0
1
0
2
28
0
0
1
1
3
42
0
1
0
0
4
56
0
1
0
1
5
70
0
1
1
0
6
84
0
1
1
1
7
98
1
0
0
0
8
112
1
0
0
1
9
126
1
0
1
0
10
140
1
0
1
1
11
154
1
1
0
0
12
168
1
1
0
1
13
182
1
1
1
0
14
196
1
1
1
1
15
210
(1)
Temp ADC Delay = Initial Counter Value x 14ms
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Table 6-19. Output Enable Counter for One-Wire Interface/VOUT Multiplexed Mode
(1)
Digital Input
OEN7……OEN0 [7……0]
(Binary)
Decimal Equivalent
(Initial Counter Value)
0000 0000
0
0 (VOUT disabled)
0010 0000
32
448
0100 0000
64
896
0110 0000
96
1344
1000 0000
128
1792
1010 0000
160
2240
1100 0000
192
2688
1110 0000
224
3136
1111 1111
255
3570
VOUT Enable Timeout
(1)
(ms)
VOUT Enable Timeout = Initial Counter Value x 14ms
6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
Bit #
D15
D14
D13
D12
D11
D10
D9
Bit Name
X
X
X
X
X
X
X
POR Value
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALM8 ALM7 ALM6 ALM5 ALM4 ALM3 ALM2 ALM1 ALM0
X
X
X
X
X
X
X
X
X
Bit Descriptions:
ALM[8:0]: Fault Monitor Comparator Outputs (1 = Fault Condition)
See Section 2.8, Fault Monitor. ALM8 — A1SAT_HI
ALM7 — A1SAT_LO
ALM6 — A2SAT_HI
ALM5 — A2SAT_LO
ALM4 — A3_VCM
ALM3 — INN_HI
ALM2 — INN_LO
ALM1 — INP_HI
ALM0 — INP_LO
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Register Descriptions
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Appendix A
SBOU024B – August 2004 – Revised January 2011
External EEPROM Example
This appendix uses an example to illustrate the mapping of PGA309 internal registers to external
EEPROM register Configuration Data and Lookup Table coefficients.
Topic
A.1
...........................................................................................................................
PGA309 External EEPROM Example
Page
.................................................................. 120
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PGA309 External EEPROM Example
A.1
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PGA309 External EEPROM Example
The PGA309 circuit configuration in Figure A-1 is used in the PGA309EVM (Evaluation Module) to check
proper functionality of the PGA309. Table A-1 details the desired configuration for the PGA309. The Gain
and Offset Scaling are shown in Example A-1. Figure A-2 shows how the internal PGA309 16-bit data is
mapped into the external EEPROM 8-bit address locations. The external EEPROM values are displayed in
Table A-2, which also details how Checksum1 and Checksum2 are computed for this example.
+5V
REFIN/
REFOUT
SDA
Two-Wire
EEPROM
VSD
VSA
SCL
PRG
VOUT
VEXC
VOUT
R2
1kW
VIN2
VFB
PGA309
RTEST
VDIFF
20W
10 Turn
VIN1
VSJ
R2
1kW
TEMPIN
TEST
GNDA
GNDD
Figure A-1. PGA309 Circuit for External EEPROM Example
Table A-1. PGA309 Configuration for External EEPROM Example
Parameter
Comments
VDIFF
0V to 33.67mV
VREF
4.096V
Use Internal PGA309 Reference
VEXC
3.4V
Use Linearization Circuit, Range
0 (KEXC = 0.83), Lin DAC = 0
Coarse Offset
Adjust RTEST from 0Ω to 20Ω
−3.277mV
Front-End PGA Gain
64
Gain DAC
1
Output Amplifier Gain
120
Desired Setting
2.4
Zero DAC
100mV
Over-Scale
3.876V
Under-Scale
0.245V
VOUT Ideal
−0.263V to +4.908V
With Over-Scale and Under-Scale
Disabled
VOUT Final
0.245V to 3.876V
With Over-Scale and Under-Scale
Enabled
External EEPROM Example
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Table A-1. PGA309 Configuration for External EEPROM Example (continued)
Parameter
Desired Setting
Comments
External Comparators
Enable
Fault Detect Polarity
Positive
Internal Comparators
Disable
Fault Detection
Temperature ADC
Internal Mode
Output Enable Counter
Set To All Zeroes
Set so all temperatures ≤ +128°C
use same Gain DAC and Zero
DAC settings
EEPROM Temperature
Coefficients
Example A-1. Gain and Offset Scaling for External EEPROM
VOUT = VDIFF (Front-End PGA Gain)(Gain DAC)(Output Amplifier Gain) + Coarse Offset (Front-End PGA
Gain)(Gain DAC)(Output Amplifier Gain) + Zero DAC (Gain DAC)(Output Amplifier Gain)
VOUT = VDIFF (64)(1)(2.4) + −3.277mV (64)(1)(2.4) + 100mV
(1)(2.4) VOUT = VDIFF (153.6) − 0.2633V
PGA309 Internal Registers
D15 D14 D13 D12 D11 D10 D9
D8
Location '1'
Upper Byte
D7
D6
D5
D4
D3
D2
D1
D0
Location '0'
Lower Byte
External EEPROM
EEPROM Address
D7
D6
D5
D4
D3
D2
D1
D0
00h
D15 D14 D13 D12 D11 D10 D9
D8
01h
Figure A-2. Gain and Offset Scaling for External EEPROM Example
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Table A-2. Final Values for External EEPROM Example
8-Bit EEPROM Load
Location ‘1’
8
PGA309 External EEPROM First Part
(Configuration Data)
External
EEPROM
Address
(Decimal)
PGA309
Internal
Reg
Address
PGA309
Internal
Address
Description
4
2
1
8
Location ‘0’
4
2
1
8
4
2
Upper Byte
1
8
4
2
1
Lower Byte
Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Equiv
1/0
MSB/LSB
Programmed
flag value must
be as shown
0
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
5449
3/2
MSB/LSB
Unused; set to
zero
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000
5/4
MSB/LSB
Unused; set to
zero
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000
RFB
RFB
RFB
RFB
EXS
EXEN
RS
REN
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
OWD
GO2
GO1
GO0
GI3
GI2
GI1
GI0
RFB
RFB
RFB
OS4
OS3
OS2
OS1
OS0
0
0
0
1
0
1
1
0
0
0
0
1
0
0
0
1
RFB
RFB
CLK_
CFG1
CLK_
CFG0
EXTEN
INTEN
EXTPO
L
INTPOL
RFB
OU EN
HL2
HL1
HL0
LL2
LL1
LL0
0
0
0
0
1
0
1
0
0
1
0
0
0
1
1
1
RFB
RFB
ADC2X
ADCS
ISEN
CEN
TEN
AREN
RV1
RV0
M1
M0
G1
G0
R1
R0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
7/6
MSB/LSB
00011
(Register
3)
Reference
Control and
Linearization
00100
(Register
4)
PGA Coarse
Offset and
Gain/Output
Amplifier Gain
00101
(Register
5)
PGA
Configuration
and Over/Under
Scale Limit
00110
(Register
6)
Temperature
ADC
Control
7/6
9/8
MSB/LSB
9/8
11/10
MSB/LSB
11/10
13/12
MSB/LSB
13/12
1
0500
1611
0A47
1603
SUM = 8FA4h
122 External EEPROM Example
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Table A-2. Final Values for External EEPROM Example (continued)
8-Bit EEPROM Load
Location ‘1’
8
PGA309 External EEPROM First Part
(Configuration Data)
External
EEPROM
Address
(Decimal)
PGA309
Internal
Reg
Address
PGA309
Internal
Address
Description
4
2
1
8
Location ‘0’
4
2
1
8
4
2
Upper Byte
1
8
4
2
1
Lower Byte
Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Equiv
Checksum1
1
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
705B
17/16
MSB/LSB
T0
(Temp Index
value for Temp ≤
T0)
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0800
19/18
MSB/LSB
Z0
(Zero DAC value
for Temp ≤ T0)
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0640
21/20
MSB/LSB
G0
(Gain DAC value
for Temp ≤ T0)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FFFF
23/22
MSB/LSB
TEND (end of
Lookup Table)
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7FFF
25/24
MSB/LSB
ZMEND (end of
Lookup Table)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000
15/14
MSB/LSB
FFFF – sum(hex
equiv of each
location – 1/10
through 13/12)
truncated above
16 bits
SUM = 18E3Eh
27/26
MSB/LSB
FFFF – sum(hex
equiv of each
location – 17/16
through 25/24)
truncated above
16 bits
GMEND
(Checksum2)
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
1
71C1
External EEPROM Example 123
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124
External EEPROM Example
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Appendix B
SBOU024B – August 2004 – Revised January 2011
Detailed Block Diagram
Appendix B shows a detailed block diagram of the PGA309.
Topic
B.1
...........................................................................................................................
Detailed Block Diagram
Page
.................................................................................... 126
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Detailed Block Diagram
© 2004–2011, Texas Instruments Incorporated
125
Detailed Block Diagram
B.1
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Detailed Block Diagram
VSA
REFIN/REFOUT
16
Linearization and VEXC
Gain Adjust
PGA309
VFB
x0.83
1
ITEMP
7mA
ITEMP Enable
15
VREF
x0.52
VSA
TEMPIN
VREF Internal Set
(2.5V or 4.096V)
x0.124
S
Internal
Temp Sense
Temp ADC
Internal REF
Bandgap
Reference
VREF
Temp ADC
Ref Mux
VEXC
VSA VREF Internal Set
(2.5V or 4.096V)
TEMPIN
RSET
VREFT
VREF
Temp ADC
Input Mux
VEXC
VSD
POR
7-Bit + Sign
Lin DAC
VEXC
10
VSA
x0.166
VEXC Enable
VEXC
VSD
3
Temp ADC
REF Select
15-Bit + Sign
Temp ADC
xG
Digital Controls
SDA
VOUT
14
Temp ADC, PGA
(x1, x2, x4, x8)
Control Registers
Alarm Register
Temp Select
Source
Temp ADC Input
Mux Select
PGA Gain Select (1 of 8)
Range of 4 to 128
(with PGA Diff Amp Gain = 4)
Input Mux
Control
VREF
Fine
Offset Adjust
4-Bit +
Sign DAC
VREF
Fine Gain Adjust
(16-Bit)
16-Bit
Zero
DAC
PRG
4R
Auto
Zero
5
A2
12
R
Over-Scale
Limit
Front-End
PGA Output
RF
PGA
Diff Amp
RG
VINN
VIN1
4
RF
Auto
Zero
Input Mux
A1
Front-End PGA
Auto
Zero
R
A3
VREF
16-Bit
3-Bit
DAC
VFB VOUT
Gain
DAC
Output
Amplifier
R
Scale
Limiter
VOUT
7
INT/EXT FB Select
Fault Monitor
Circuit
Alarm Register Inputs
RFO
VFB
6
Output Gain Select (1 of 7)
Range of 2 to 9
RGO
TEST
9
SCL
13
Offset TC Adjust and Scan TC Adjust
Look-Up Logic with Interpolation Algorithm
Coarse
Offset Adjust
VINP
VIN2
Interface and
Control Circuitry
VREF
3-Bit
DAC
Test Logic
Under-Scale
Limit
VSJ
8
2
11
GNDA
GNDD
Figure B-1. Detailed Block Diagram
126
Detailed Block Diagram
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Appendix C
SBOU024B – August 2004 – Revised January 2011
Glossary
A
ADC— Analog-to-digital converter
B
BV— Bridge nonlinearity with applied pressure.
BV =
VOUT_MAX - VOUT_MIN
(
(
4 · VREF · KEXC
+ 4 · (VOUT_MAX + VOUT_MIN)
KLIN
BV MAX— Maximum compensable nonlinearity
BV -MAX =
BV –MAX—
BV +MAX =
BV +MAX—
VOUT_MAX - VOUT_MIN
(
(
4 · VREF · KEXC
+ 4 · (VOUT_MAX + VOUT_MIN)
KLIN -MAX
VOUT_MAX - VOUT_MIN
(
(
4 · VREF · KEXC
+ 4 · (VOUT_MAX + VOUT_MIN)
KLIN +MAX
C
CF— External feedback capacitor connected between VSJ and VOUT, for stability.
CMR— Common-mode rejection
D
DAC— Digital-to-analog converter
E
EMI— Electromagnetic interference
F
FSR— Full-scale range of PGA309 output.
FSR = VOUT_MAX - VOUT_MIN
FSS— Full-scale bridge sensitivity for sensor at PMAX (for example, 2mV/V).
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127
Appendix C
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G
GIDEAL— Ideal gain
GIDEAL =
VOUT_MAX - VOUT_MIN
VREF · FSS
GL— Gain of the PGA309 when using the Linearization circuit.
GL =
(VOUT_MAX - VOUT_MIN)
(VREF · KEXC · FSS) + (KLIN · VOUT_MAX · FSS)
GNDA— Analog ground
GNDD— Digital ground
GT— Total gain produced by the PGA309 of VOUT/VIN gain.
GT = (Front-End PGA Gain)(Gain DAC)(Output Amplifier Gain)
I
IVR— Input voltage range of the PGA309.
K
KLIN— PGA linearization coefficient
KLIN =
4 · BV · VREF · KEXC
(VOUT_MAX - VOUT_MIN) - 2 · BV · (VOUT_MAX + VOUT_MIN)
KLIN –MAX— Most negative linearization coefficient. Its value is determined by the selected range of bridge
sensor nonlinearity compensation.
KLIN
— Most positive linearization coefficient. Its value is determined by the selected range of bridge
sensor nonlinearity compensation.
+MAX
KEXC— PGA excitation coefficient. Scale factor on VREF.
KP— Pressure constant. Converts linear input pressure to nonlinear pressure detected by sensor;
referenced to full-scale input pressure.
L
LSB— Least significant bit
M
MSB— Most significant bit
P
P—
Pressure input
PMIN— Minimum sensor input pressure
PMAX— Maximum sensor input pressure
PNL— Nonlinear pressure output of bridge with linear pressure input P.
POR— Power-on reset function
PRG— Single-wire interface program pin
128
Glossary
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Appendix C
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R
RBRG— Bridge resistor value
RFB— External feedback resistor connected to VFB.
RFO— Internal feedback resistor for the Output Amplifier.
RFO EXT— Additional external feedback resistor for the Output Amplifier.
RGO— Internal gain resistor for the Output Amplifier.
RGO
EXT
— Additional external gain resistor for the Output Amplifier.
RISO— External isolation resistor connected to VOUT.
REFIN/REFOUT— Voltage reference input/output pin
RFI— Radio frequency interference
RTO— Referred-to-output
S
SCL— Clock input/output for Two-Wire serial interface
SDA— Data input/output for Two-Wire serial interface
T
TEMPIN— External temperature signal input
TEST— Test/external controller mode pin
V
VBRMAX— Maximum bridge sensor output
VCM— Common-mode voltage applied to the PGA309 input.
VCM =
(V
INP
+ VINN
2
(
VCOS— Coarse offset voltage output of the coarse offset adjust DAC.
VDIFF— Differential voltage applied to the PGA309 inputs.
VDIFF = VINP − VINN
VEXC— Bridge sensor excitation voltage
VEXC = VREF · KEXC + KLIN · VOUT
VEXC
— Maximum bridge sensor excitation voltage
MAX
VEXC MAX = VREF · KEXC + KLIN · VOUT_MAX
VEXC
MIN
— Minimum bridge sensor excitation voltage
VEXC MIN = VREF · KEXC + KLIN · VOUT_MIN
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129
Appendix C
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VFB— VOUT feedback pin
VFRONT— The output of difference amplifier A3, of the Front-End PGA309.
VIN1— Signal input voltage 1
VIN2— Signal input voltage 2
VINN— The positive input of internal auto-zero amplifier A1, of the Front-End PGA.
VINP— The positive input of internal auto-zero amplifier A2, of the Front-End PGA.
VN— Output voltage of one branch of the bridge.
VOA1— Output voltage of internal auto-zero amplifier A1.
( V2 (
DIFF
VOA1 = VCM - G
VOA2— Output voltage of internal auto-zero amplifier A2.
( V2 (
VOA2 = VCM + G
DIFF
VOS— Sensor offset voltage
VOUT— Analog output voltage of conditioned sensor
VOUT ERR FSR— Error in %FSR of VOUT
VOUT
FILT
— Filtered VOUT
VOUT
IDEAL
— Ideal output for a given pressure, P.
VOUT_IDEAL = FSS · GIDEAL
( PP (V
REF
+ VOS
MAX
VOUT
MAX
— VOUT for maximum bridge sensor output
VOUT
MIN
— VOUT for minimum bridge sensor output
VP— Output voltage of one branch of the bridge.
VREF— Reference voltage used by the PGA309 (internal or external).
VREFT— Temperature VREF
VS— Supply voltage
VSA— Analog supply voltage
VSD— Digital supply voltage
VSJ— Output Amplifier summing junction
VTEST— Test signal
VZERO
130
DAC
— Output voltage of the Zero DAC
Glossary
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Revision History
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Revision History
Changes from A Revision (January, 2005) to B Revision .............................................................................................. Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Updated document format to current standards ...................................................................................... 1
Added Table 2-4 .......................................................................................................................... 7
Changed Table 2-5 ....................................................................................................................... 7
Updated Table 6-8 ....................................................................................................................... 8
Added Table 6-9 .......................................................................................................................... 8
Changed times indicated in Power-Up and Normal Operation section .......................................................... 15
Added note to Figure 2-1 .............................................................................................................. 20
Revised Figure 2-3 and added note .................................................................................................. 22
Added PGA Transfer Function section ............................................................................................... 22
Added Table 2-4 ........................................................................................................................ 36
Changed Table 2-5 ..................................................................................................................... 37
Changed time values for power-on reset timeout discussed in Section 2.7.1 .................................................. 42
Corrected time values indicated for wait times ...................................................................................... 60
Revised Figure 3-1 ...................................................................................................................... 61
Changed wait time indicated for Checksum Error event ........................................................................... 70
Revised Figure 4-7 ...................................................................................................................... 79
Changed Figure 4-8 .................................................................................................................... 80
Updated Section 4.9; changed indicated time values, Figure 4-13, and Figure 4-14 .......................................... 86
Revised Section 4.11; added Figure 4-18 through Figure 4-21 .................................................................. 91
Updated Table 6-8 .................................................................................................................... 109
Added Table 6-9 ....................................................................................................................... 110
Corrected typos in Table 6-17 ....................................................................................................... 115
Updated Temp ADC Delay column values and footnote (1) in Table 6-18 .................................................... 116
Corrected VOUT Enable Timeout column values and footnote (1) in Table 6-18 ............................................... 117
Corrected typo in Figure B-1 ......................................................................................................... 126
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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131
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