PGA308 PG A308 PGA3 08 www.ti.com ...................................................................................................................................................................................................... SBOS440 – JULY 2008 Single-Supply, Auto-Zero Sensor Amplifier with Programmable Gain and Offset FEATURES DESCRIPTION 1 • • • • • • • • • • • • 2 Digital Calibration for Bridge Sensors Offset Select: Coarse and Fine Gain Select: Coarse and Fine Bridge Fault Monitor Input Mux for Lead Swap Over/Under Scale Limits DOUT/ VOUT Clamp Function Seven Banks OTP Memory One-Wire Digital UART Interface Operating Voltage: +2.7V to +5.5V Temperature Range: –40°C to +125°C MSOP-10 and 3mm x 4mm DFN-10 Packages The PGA308 is a programmable analog sensor signal conditioner. The analog signal path amplifies the sensor signal and provides digital calibration for offset and gain. Calibration is done via the 1W pin, a digital One-Wire, UART-compatible interface. For three-terminal sensor modules, 1W may be connected to VOUT and the assembly programmed through the VOUT pin. Gain and offset calibration parameters are stored onboard in seven banks of one-time programmable (OTP) memory. The power-on reset (POR) OTP bank may be programmed a total of four times. The all-analog signal path contains a 2x2 input multiplexer (mux) to allow electronic sensor lead swapping, a coarse offset adjust, an auto-zero programmable gain instrumentation amplifier (PGA), a fine gain adjust, a fine offset adjust, and a programmable gain output amplifier. Fault monitor circuitry detects and signals sensor burnout, overload, and system fault conditions. Over/under-scale limits provide additional means for system level diagnostics. The dual-use DOUT/VCLAMP pin can be used as a programmable digital output or as a VOUT over-voltage clamp. APPLICATIONS • • • • Bridge Sensors Remote 4-20mA Transmitters Strain, Load, Weigh Scales Automotive Sensors EVALUATION TOOLS • PGA308EVM (Hardware and Software) – Calibration and Configuration – Sensor Emulation For detailed application information, see the PGA308 User's Guide (SBOU069) available for download at www.ti.com. VS VEXC VREF 4 DOUT/VCLAMP 10 1 PGA308 Digital Interface (One-Wire) Fine Offset VREF OTP (7 Banks) Overscale RAM 3-Bit DAC 16-Bit DAC 7-Bit + Sign DAC Output Gain VREF Ref(1) 8 7 VIN1 Output Gain Select 5 Input Mux Bridge Sensor VIN2 Fault Monitor Auto-Zero PGA 6 1W DOUT Select VREF Coarse Offset 2 16-Bit DAC Output Amplifier Scale Limit 9 VFB VSJ VOUT Ref(1) Fine Gain 3-Bit DAC Front-End Gain Select Underscale 3 GND NOTE: (1) Ref = VREF or VS selectable. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated PGA308 SBOS440 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD MSOP-10 PGA308 (1) (2) 3mm x 4mm DFN-10 (2) PACKAGE DESIGNATOR PACKAGE MARKING DGS P30A DRK P30B For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Available Q1, 2009. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. PARAMETER PGA308 UNIT Supply Voltage, VS +5.5 V DOUT/VCLAMP Output Current Limit ±10 mA –10 to +10 mA GND – 0.3 to VS + 0.3 V Input Current VIN1, VIN2, VREF, 1W, DOUT/VCLAMP, VSJ (2) Pin Protection VFB Terminal Voltage –30 to 30 V VFB Terminal Current –10 to 10 mA –160 to 160 mA Operating Temperature Range –40 to +150 °C Storage Temperature Range –55 to +150 °C Junction Temperature +165 °C ESD Ratings 2000 V VOUT (1) (2) 2 Human Body Model (HBM) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Terminals are diode-clamped to the power-supply rails, VS and GND. Limit current to 10mA or less. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 PGA308 www.ti.com ...................................................................................................................................................................................................... SBOS440 – JULY 2008 ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, VS = +5V, GND = 0V, DOUT/VCLAMP = +5V, and VREF = +5V, unless otherwise noted. PGA308 PARAMETER CONDITIONS MIN VOUT/VIN Differential Signal Gains (1) (Front-End PGA + Output Amplifier) Front-End PGA gains (GF): 4, 6, 8, 12, 16, 32, 64, 100, 200, 400, 480, 600, 800, 960, 1200, 1600 Output Amplifier gains: 2, 2.4, 3, 3.6, 4, 4.5, 6 Fine Gain Adjust = 0.33 to 1 2.67 VOUT/VIN Slew Rate (Front End PGA + Output Amplifier) CMP_SEL [CFG1 register] = 0 0.6 CMP_SEL [CFG1 register] = 1 0.3 V/µs VOUT/VIN differential gain = 8, VOUT = +0.5V to +4.5V step, comp off, no capacitve load 13 µs VOUT/VIN differential gain = 200, VOUT = +0.5V to +4.5V step, comp off, no capacitve load 15 µs VOUT/VIN Settling Time (0.01%FSR) (Front-End PGA + Output Amplifier) External Sensor Output Sensitivity (2) VS = VREF = VCLAMP = +5V TYP MAX UNIT 9600 V/V V/µs 0.08 296 mV/V FRONT-END PGA Auto-Zero Internal Frequency 40 Offset Voltage (RTI) (3) kHz ±5 Coarse Offset Adjust disabled ±0.2 vs Supply Voltage, VS Coarse Offset Adjust disabled 2 + 150/GF 10 + 1000/GF µV/V vs Common-Mode Voltage GF = Front-End PGA gain, Coarse Offset Adjust disabled 1 + 250/GF 10 + 2000/GF µV/V 100 mV vs Temperature Offset Voltage Programming Range (RTI) (3) Coarse Offset Adjust enabled, Coarse Offset Adjust controls offset ±40 µV Coarse Offset Adjust disabled –100 µV/°C Coarse Offset Adjust enabled ±0.2 µV/°C vs Supply Voltage, VS Coarse Offset Adjust enabled 2 + 150/GF µV/V vs Common-Mode Voltage GF = Front End PGA gain, Coarse Offset Adjust enabled 1 + 250/GF µV/V vs Temperature Linear Input Voltage Range (4) 0.2 Input Bias Current ±0.3 vs Temperature VS – 1.4 V ±1.5 nA 10 Input Offset Current pA/°C ±0.1 vs Temperature ±1.5 10 nA pA/°C Input Impedance: Differential 30 6 GΩ pF Input Impedance: Common Mode 50 20 GΩ pF RTI, dc to 10Hz, GF = 100, RS = 0Ω 1.2 µVPP RTI, voltage noise density, f = 1kHz, Coarse Offset Adjust = 0V 50 nV/√Hz RTI, voltage noise density, f = 1kHz, Coarse Offset Adjust = 100mV 80 nV/√Hz Input EMI filter to GND, VIN1 and VIN2 40 MHz Input Voltage Noise Input Voltage Noise Density Input EMI Filter Frequency f3dB PGA Gain (5) Gain Range Steps 4, 6, 8, 12, 16, 32, 64, 100, 200, 400, 480, 600, 800, 960, 1200, 1600 Initial Gain Error 4 GF ≤ 16 ±0.03 ±0.25 % ±0.1 ±0.4 % 600 ≤ GF ≤ 1600 ±0.3 ±1 6 Output Voltage Range (1) (2) (3) (4) (5) V/V 32 ≤ GF ≤ 480 vs Temperature Bandwidth 1600 0.05 % ppm/°C VS – 0.05 V GF = 4 400 kHz GF = 1600 10 kHz PGA308 total differential gain from input (VIN1 – VIN2) to output (VOUT): VOUT / (VIN1 – VIN2) = (PGA gain) x (output amplifier gain) × (fine gain adjust) with output amplifier internal gains used. Based on bridge sensor excitation voltage of +5V and PGA308 output voltage span of 4V. Individual applications must consider noise, small-signal bandwidth, and required system error to assess if the PGA308 will work for a given sensor sensitivity. RTI = Referred-to-input. Linear input range is the allowed min/max voltage on the VIN1 and VIN2 pins for the front-end PGA to continue to operate in a linear region. The allowed common-mode and differential voltage depends on gain and offset settings. Refer to the PGA308 User's Guide (SBOU069), for more information. IREF current load is typically 100µA while in Shutdown mode. Although the output amplifier is disabled in Shutdown mode, RFO and RGO (180kΩ typical total) remain connected in series between VFB and GND while in Shutdown mode. See Figure 37, Detailed Block Diagram, for more information. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 3 PGA308 SBOS440 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, VS = +5V, GND = 0V, DOUT/VCLAMP = +5V, and VREF = +5V, unless otherwise noted. PGA308 PARAMETER CONDITIONS MIN VREF = +5V –100 TYP MAX UNIT +100 mV Coarse Offset Adjust (RTI of Front-End PGA) (6) Range Resolution 7 bit + sign, VREF = +5V PSRR CMRR Drift Coarse Offset Adjust = 100mV 1 mV 2 µV/V 1 µV/V 1.2 µV/°C Fine Offset Adjust (Zero DAC) Programming Range RTO of Front-End PGA Output Voltage Range Resolution –0.5VREF +0.5VREF 0.1 VS – 0.1 65,536 steps, 16-bit DAC, VREF = +5V Integral Nonlinearity V V 76 µV ±6 LSB Differential Nonlinearity ±0.5 LSB Gain Error ±0.5 % ±4 ppm/°C Gain Error Drift Offset ±4 mV Offset Drift ±10 µV/°C PSRR ±200 µV/V Output Amplifier Output Fine Gain Adjust (Gain DAC) Range 0.33 Resolution 65,536 steps, 16-bit DAC Integral Nonlinearity Differential Nonlinearity 1 µV/V ±6 LSB ±0.5 Gain Error LSB ±0.2 Gain Drift V/V 10 3 % ppm/°C Output Amplifier Offset Voltage (RTI of Output Amplifier) (6) vs Temperature vs Supply Voltage, VS ±3 mV ±5 µV/°C µV/V ±100 Common Mode Input Range 0 VS – 1.5 Input Bias Current ±100 V pA Amplifier Internal Gain Gain Range Steps 2, 2.4, 3, 3.6, 4, 4.5, 6 2 6 Initial Gain Error ±0.05 vs Temperature ±1 Output Voltage Range Output Short Circuit Current ISC ±0.25 V/V % ppm/°C IOUT = 0.5mA (7) 0.03 VS – 0.06 IOUT = 4mA (7) 0.1 VS – 0.1 Sourcing/sinking 10 V V mA OpenLoop Gain at 0.1Hz 106 dB Gain-Bandwidth Product 2 MHz Gain = 2, CL = 200pF 45 deg AC small signal, open loop, f = 1MHz, IOUT = 0, see Figure 28 500 Ω Phase Margin Output Resistance (6) (7) 4 RO RTI = Referred-to-input. Unless limited by the over/under-scale setting, or VCLAMP Pin. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 PGA308 www.ti.com ...................................................................................................................................................................................................... SBOS440 – JULY 2008 ELECTRICAL CHARACTERISTICS (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, VS = +5V, GND = 0V, DOUT/VCLAMP = +5V, and VREF = +5V, unless otherwise noted. PGA308 PARAMETER CONDITIONS MIN TYP MAX UNIT Over- and Under-Scale Limits Over-Scale Thresholds VLIM = 4V, register-selectable ratio of VLIM OS0 HL[2:0] (CFG1 register D[5:3]) = 000 0.97 0.9805 0.99 V/V OS1 HL[2:0] (CFG1 register D[5:3]) = 001 0.9588 0.9688 0.9788 V/V OS2 HL[2:0] (CFG1 register D[5:3]) = 010 0.9509 0.9609 0.9709 V/V OS3 HL[2:0] (CFG1 register D[5:3]) = 011 0.9392 0.9492 0.9492 V/V OS4 HL[2:0] (CFG1 register D[5:3]) = 100 0.8416 0.8516 0.8616 V/V OS5 HL[2:0] (CFG1 register D[5:3]) = 101 0.7673 0.7773 0.7873 V/V OS6 HL[2:0] (CFG1 register D[5:3]) = 110 0.6189 0.6289 0.6389 V/V OS7 HL[2:0] (CFG1 register D[5:3]) = 111 0.5603 0.5703 0.5803 Over-Scale Threshold Tempco ±3 V/V ppm/°C Over-Scale Amplifier Offset ±9 mV Over-Scale Amplifier Offset Drift ±10 µV/°C Under-Scale Thresholds VLIM = 5V, register-selectable ratio of VLIM US7 LL[2:0] (CFG1 register D[2:0]) = 111 0.0487 0.0547 0.0607 V/V US6 LL[2:0] (CFG1 register D[2:0]) = 110 0.04478 0.05078 0.05678 V/V US5 LL[2:0] (CFG1 register D[2:0]) = 101 0.04088 0.04688 0.05288 V/V US4 LL[2:0] (CFG1 register D[2:0]) = 100 0.03306 0.03906 0.04506 V/V US3 LL[2:0] (CFG1 register D[2:0]) = 011 0.02916 0.03516 0.04116 V/V US2 LL[2:0] (CFG1 register D[2:0]) = 010 0.02525 0.03125 0.03725 V/V US1 LL[2:0] (CFG1 register D[2:0]) = 001 0.01743 0.02343 0.02943 V/V US0 LL[2:0] (CFG1 register D[2:0]) = 000 0.01353 0.01953 0.02553 Under-Scale Threshold Tempco ±3 V/V ppm/°C Under-Scale Amplifier Offset ±9 mV Under-Scale Amplifier Offset Drift ±10 µV/°C Output Voltage Clamp VCLAMP ≤ VS, VS = +5V Input Voltage Range 1.25 4.95 Input Bias Current ±60 VOUT Clamp Point VCLAMP – 0.05 VCLAMP V nA VCLAMP + 0.05 V Fault Monitor Circuit (External Comparators) INP_HI Comparator Threshold INN_HI Comparator Threshold Fault Detect Mode Select = 0 (bridge fault); see CFG1 register Smaller of (VS – 1.2) or (0.65VFLT) V INP_LO Comparator Threshold INN_LO Comparator Threshold Fault Detect Mode Select = 0 (bridge fault); see CFG1 register Larger of (0.1V) or (0.35VFLT) V Fault Monitor Reference; see CFG1 register, FLT REF bit sets VFLT VS or VREF V INP_HI Comparator Threshold INN_HI Comparator Threshold Fault Detect Mode Select = 1 (common mode fault); see CFG1 register VS – 1.2 V INP_LO Comparator Threshold INN_LO Comparator Threshold Fault Detect Mode Select = 1 (common mode fault); see CFG1 register Fault Monitor Reference VFLT 70 Comparator Hysteresis Comparator Input Offset Voltage 100 130 mV 7 mV ±10 mV Fault Monitor Circuit (Internal Comparators) A1SAT_LO Comparator Threshold A2SAT_LO Comparator Threshold Threshold is amplifier negative saturation voltage 100 mV A1SAT_HI Comparator Threshold A2SAT_HI Comparator Threshold Threshold is amplifier positive saturation voltage VS – 0.12 V A3SAT_LO Comparator Threshold Threshold is amplifier negative saturation voltage 50 mV VIN1, VIN2 Pull-up Current Sources Pull-Up Current Source 30 45 Current Source Matching IPU Register-selectable 15 ±1.5 ±7 Current Source Tempco ±5 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 nA nA pA/°C 5 PGA308 SBOS440 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, VS = +5V, GND = 0V, DOUT/VCLAMP = +5V, and VREF = +5V, unless otherwise noted. PGA308 PARAMETER CONDITIONS MIN TYP MAX UNIT VREF Input Range 1.8 Input Resistance VS 43 V kΩ Digital Interface One-Wire Serial speed baud rate 4.8k 114k bits/s 0.8 V Logic Levels Logic Levels (1W pin) Low High 2.0 Hysteresis V 100 mV Output Low Level (1W pin) Open drain, ISINK = 4mA 0.4 V Output Levels (DOUT/VCLAMP) Low, DOUT mode selected, ISINK = 4mA and VS = +4.5V, or ISINK = 2mA and VS = +2.7V 0.4 V High, DOUT mode selected, ISOURCE = 4mA and VS = +4.5V, or ISOURCE = 2mA and VS = +2.7V VS – 0.4 V POWER SUPPLY Supply Voltage OTP Program Votage Quiescent Current VS 2.7 5.5 VS-PGM 4.5 5.5 V 1.6 mA VS = +5V, does not include IREF 1.3 VS = +5V, does not include IREF (8) 260 µA Power-Up Threshold VS rising 2.1 V Power-Down Threshold VS falling 1.7 V Shutdown Supply Current IQ V ISHDN POWER-ON RESET (POR) TEMPERATURE RANGE Specified Performance Range –40 +125 °C Operational-Degraded Performance Range –40 +150 °C Thermal Resistance MSOP-10, Junction-to-Ambient (8) 6 θJA 150 °C/W IREF current load is typically 100µA while in Shutdown mode. Although the output amplifier is disabled in Shutdown mode, RFO and RGO (180kΩ typical total) remain connected in series between VFB and GND while in Shutdown mode. See Figure 37, Detailed Block Diagram, for more information. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 PGA308 www.ti.com ...................................................................................................................................................................................................... SBOS440 – JULY 2008 TYPICAL THREE-WIRE APPLICATION CIRCUIT Power Supply + - Easy-To-Use Calibration +5V DOUT/ VCLAMP VS VREF Sensor Out 1W Ground PC VCC +5V USB One-Wire GND VOUT RISO 100W VCC CF 10nF PGA308 VIN2 Bridge Sensor ADC RPU VFB VIN1 VSJ CF 47pF PGA308EVM GND Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 7 PGA308 SBOS440 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com PIN CONFIGURATIONS DGS PACKAGE MSOP-10 (TOP VIEW) DRK PACKAGE 3x4 DFN-10 (TOP VIEW) DOUT/VCLAMP 1 10 VREF 1W 2 9 VOUT GND 3 8 VFB VS 4 7 VSJ VIN1 5 6 VIN2 PGA308 DOUT/VCLAMP 1 10 VREF 1W 2 9 VOUT GND 3 8 VFB VS 4 7 VSJ VIN1 5 6 VIN2 PGA308 PIN DESCRIPTIONS PIN # 8 NAME DESCRIPTION 1 DOUT/VCLAMP Dual-use pin: Output voltage clamp limit for VOUT or programmable digital output. The output voltage clamp function is for use in multiple supply systems where the PGA308 may be at VS = +5V and the system analog-to-digital converter (ADC) is powered at +3V. Setting VCLAMP to +3.2V prevents overvoltage and latch-up on the system ADC input. VCLAMP may be set through a resistor divider from VS. If configured for digital output, the DOUT function allows for configuration plus calibration of a sensor module either through the One-Wire interface (1W pin) or as a permanently configured module through the power-on reset (POR) OTP memory setting. 2 1W One-Wire interface program pin. UART interface for digital calibration of the PGA308 over a single wire. Can be connected to VOUT for a three terminal (VS, GND, VOUT) programmable sensor assembly. 3 GND 4 VS 5 VIN1 Signal input voltage 1. Connect to + or – output of the sensor bridge. Internal multiplexer can change connection internally to front-end PGA. 6 VIN2 Signal input voltage 2. Connect to + or – output of the sensor bridge. Internal multiplexer can change connection internally to front-end PGA. 7 VSJ Output amplifier summing junction. Use for output amplifier compensation when driving large capacitive loads (> 200pF) and/or for using external gain setting resistors for the output amplifier. 8 VFB VOUT feedback pin. Voltage feedback sense point for over-/under-scale limit circuitry. If internal gain set resistors for the output amplifier are used, this pin is also the voltage feedback sense point for the output amplifier. VFB in combination with VSJ allows for use of external filter and protection circuits without degrading the PGA308 VOUT accuracy. VFB must always be connected to either VOUT or the point of feedback for VOUT if external filtering is used. 9 VOUT Analog output voltage of conditioned sensor. 10 VREF Reference voltage input pin. VREF is used for coarse offset adjust and Zero DAC. VREF or VS may be individually selected for over-/under-scale threshold reference and fault monitor comparator reference. Ground. +Voltage supply. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 PGA308 www.ti.com ...................................................................................................................................................................................................... SBOS440 – JULY 2008 TYPICAL CHARACTERISTICS At TA = +25°C, VS = VREF = DOUT/VCLAMP = +5V, RL = 10kΩ and CL = 100pF connected to GND, unless otherwise noted. Gain format is presented: G = FE-PGA x Fine Gain x Output Gain. FRONT-END PGA INPUT BIAS CURRENT WITH IPU DISABLED vs TEMPERATURE 40 900 35 800 Input Bias Current (pA) Input Bias Current, Pull-Up Enabled (nA) FRONT-END PGA INPUT BIAS CURRENT WITH IPU ENABLED vs TEMPERATURE 30 25 20 15 10 5 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 0 -50 150 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure 1. Figure 2. COARSE OFFSET ADJUST ERROR vs TEMPERATURE FRONT-END PGA OFFSET VOLTAGE vs TEMPERATURE 150 50 0.6 +51mV to +99mV Offset Adjust 40 Three Typical Units Shown 0.5 30 +11mV Offset Adjust Output Voltage (mV) Error from Ideal Value (%) 700 0.4 0.3 0.2 0.1 -50mV to -100mV Offset Adjust -10mV Offset Adjust 3s 20 Unit 1 10 Unit 2 0 -10 Unit 3 -20 3s -30 0 -50 -25 0 25 50 75 100 125 -40 -50 150 0 25 50 75 100 125 Temperature (°C) Figure 3. Figure 4. 0.1Hz TO 10Hz OUTPUT NOISE (G = 1600) INPUT-REFERRED FRONT-END NOISE vs FREQUENCY 1 RTF Front-End Noise (mV/ÖHz) Coarse Offset = 0V 0V VOUT (500mV/div) -25 Temperature (°C) Coarse Offset = 2.5mV 0V Time (2s/div) Offset = 100mV, G = 4x1x1 Offset = 0V, G = 4x1x1 150 Clock Feedthrough Offset = 100mV, G = 32x1x1 Offset = 40mV, G = 100x1x1 0.1 Offset = 0V, G = 32x1x1 Offset = 0V, G = 100x1x1 0.01 100 Offset = 0V, G = 1600x1x1 1k 10k 100k Frequency (Hz) Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 9 PGA308 SBOS440 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = VREF = DOUT/VCLAMP = +5V, RL = 10kΩ and CL = 100pF connected to GND, unless otherwise noted. Gain format is presented: G = FE-PGA x Fine Gain x Output Gain. OVER-SCALE TOTAL ERROR vs TEMPERATURE (5V Ref) UNDER-SCALE TOTAL ERROR vs TEMPERATURE (4V Ref) 0 14 Eight Programming Levels Shown Eight Programming Levels Shown OS6 -2 OS7 OS5 Under-Scale Total Error (mV) Over-Scale Total Error (mV) -1 -3 -4 -5 OS2 -6 OS0 -7 OS1 OS3, OS4 -8 -9 -10 -50 -25 0 25 50 75 100 125 12 8 US2 4 US5 US6 2 US7 -25 0 25 50 75 100 125 Figure 7. Figure 8. ZERO DAC OFFSET ERROR vs TEMPERATURE COMMON-MODE REJECTION (RTI) vs FREQUENCY 0.2 120 156mV 0 150 Temperature (°C) Temperature (°C) 110 -0.2 G = 600x1x2 -0.4 100 2.344V -0.6 CMR (dB) Offset Error from Ideal Value (mV) US4 US3 6 0 -50 150 US1 US0 10 -0.8 -1.0 -1.2 G = 100x1x2 90 G = 32x1x2 80 70 -1.4 4.844V -1.6 G = 4x1x2 60 -1.8 -2.0 -50 50 -25 0 25 50 75 100 125 10 150 100 1k Temperature (°C) Frequency (Hz) Figure 9. Figure 10. POWER-SUPPLY REJECTION RATIO (RTI) vs FREQUENCY GAIN vs FREQUENCY 120 10k 10000 110 G = 1600x1x6 G = 600x1x2 G = 100x1x2 G = 800x1x2 1000 G = 32x1x2 G = 400x1x2 100 90 Gain PSRR (dB) 100 80 G = 32x1x3 10 G = 4x1x2 70 G = 4x1x2 1 60 50 0.1 10 10 100 1k 10k 1k 10k 100k Frequency (Hz) Frequency (Hz) Figure 11. Figure 12. Submit Documentation Feedback 1M 10M Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 PGA308 www.ti.com ...................................................................................................................................................................................................... SBOS440 – JULY 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = VREF = DOUT/VCLAMP = +5V, RL = 10kΩ and CL = 100pF connected to GND, unless otherwise noted. Gain format is presented: G = FE-PGA x Fine Gain x Output Gain. VOUT WITH VCLAMP LOW (1.25V) vs TEMPERATURE 1.30 4.98 1.29 4.97 1.28 VOUT with VCLAMP Low (V) 4.99 4.96 4.95 4.94 4.93 4.92 4.91 4.90 1.26 1.25 1.24 1.23 1.22 1.21 4.89 -50 -25 0 25 50 75 100 125 150 1.20 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure 13. Figure 14. COMMON-MODE OVERVOLTAGE RECOVERY VCLAMP RESPONSE (No Cap Load, CMP SEL = 1) 125 150 VOUT (1V/div) CMP SEL = 1 (Comp On), 2.5V VCLAMP, RL = 10kW, G = 32x1x2, 300Hz Triangle Wave VIN CM = 5V VIN CM (2V/div) 1.27 VIN CM = 3V 50mV/div VOUT with VCLAMP High (V) VOUT WITH VCLAMP HIGH (4.94V) vs TEMPERATURE RL = 10kW, CMP SEL = 0, CL = 0, CF = 0, Gain = 4x1x2 Time (25ms/div) Time (250ms/div) Figure 15. Figure 16. VCLAMP RESPONSE (No Cap Load, CMP SEL = 0) VCLAMP RESPONSE (CL = 10nF, CMP SEL = 1) CMP SEL = 1 (Comp On), 2.5V VCLAMP, RL = 10kW, G = 32x1x2, 300Hz Triangle Wave 50mV/div 50mV/div CMP SEL = 0 (Comp Off), 2.5V VCLAMP, RL = 10kW, G = 32x1x2, 300Hz Triangle Wave Time (250ms/div) Time (250ms/div) Figure 17. Figure 18. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 11 PGA308 SBOS440 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = VREF = DOUT/VCLAMP = +5V, RL = 10kΩ and CL = 100pF connected to GND, unless otherwise noted. Gain format is presented: G = FE-PGA x Fine Gain x Output Gain. VCLAMP RESPONSE (CL = 10nF, CMP SEL = 0) OUTPUT VOLTAGE vs OUTPUT CURRENT VS CMP SEL = 0 (Comp Off), 2.5V VCLAMP, RL = 10kW, G = 32x1x2, 300Hz Triangle Wave VS - 0.1 50mV/div Output Voltage (V) VS - 0.2 VS - 0.3 VS - 0.4 VS = 2.7V VS = 3V VS = 5V VS = 5.5V GND + 0.4 GND + 0.3 GND + 0.2 GND + 0.1 GND Time (250ms/div) 0 3 6 9 12 15 | Output Current | (mA) Figure 19. Figure 20. QUIESCENT CURRENT vs TEMPERATURE OUTPUT AMPLIFIER OPEN-LOOP GAIN vs FREQUENCY (CMP SEL = 1) 120 Output Amplifier Open-Loop Gain (dB) 1.6 1.4 1.2 IQ (mA) 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 60 40 CL £ 100pF 20 150 CL = 10nF RL = 10kW, CL = 10nF 0 RL = 1kW, CL = 10nF 0.1 1 10 100 1k 10k 100k 1M Temperature (°C) Frequency (Hz) Figure 21. Figure 22. OUTPUT AMPLIFIER OPEN-LOOP GAIN vs FREQUENCY (CMP SEL = 0) OUTPUT AMPLIFIER OPEN-LOOP PHASE vs FREQUENCY (CMP SEL = 1) 10M 180 100 80 60 40 CL £ 100pF 20 CL = 10nF RL = 10kW, CL = 10nF 0 RL = 1kW, CL = 10nF 0.1 1 10 100 1k 10k 100k 1M 10M Output Amplifier Open-Loop Phase (°) Output Amplifier Open-Loop Gain (dB) 12 80 -20 0.01 120 -20 0.01 100 CL £ 100pF 160 140 120 100 80 60 CL = 10nF 40 20 RL = 10kW, CL = 10nF 0 RL = 1kW, CL = 10nF -20 0.01 0.1 1 10 100 1k Frequency (Hz) Frequency (Hz) Figure 23. Figure 24. Submit Documentation Feedback 10k 100k 1M 10M Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 PGA308 www.ti.com ...................................................................................................................................................................................................... SBOS440 – JULY 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = VREF = DOUT/VCLAMP = +5V, RL = 10kΩ and CL = 100pF connected to GND, unless otherwise noted. Gain format is presented: G = FE-PGA x Fine Gain x Output Gain. OUTPUT AMPLIFIER OPEN-LOOP PHASE vs FREQUENCY (CMP SEL = 0) CAPACITIVE LOAD DRIVE CL = 1nF CMP SEL = 0 (Comp Off) G = 4x1x2 VOPP = 100mV RL = 10kW 160 140 CL £ 100pF 120 20mV/div Output Amplifier Open-Loop Phase (°) 180 100 80 60 CL = 10nF 40 20 RL = 10kW, CL = 10nF 0 RL = 1kW, CL = 10nF -20 0.01 0.1 1 10 100 1k 10k 100k 1M Time (5ms/div) 10M Frequency (Hz) Figure 25. Figure 26. CAPACITIVE LOAD DRIVE CL = 10pF OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY 10k 20mV/div Open-Loop Output Impedance (W) CMP SEL = 0 (Comp Off) G = 4x1x2 VOPP = 100mV RL = 10kW CMP SEL = 1 CMP SEL = 0 1k IL = 0 IL = 500mA 100 IL = 5mA 10 Time (5ms/div) 10 100 1k 10k 100k 1M 10M Frequency (Hz) Figure 28. SMALL-SIGNAL STEP RESPONSE CMP SEL = 1 LARGE-SIGNAL STEP RESPONSE CMP SEL = 1 VOUT (1V/div) VOUT (50mV/div) Figure 27. CMP SEL = 1 (Comp On), RL = 10kW, RISO = 100W, CL = 10nF, CF = 47pF, G = 600x1x2, f = 4kHz, VOPP = 100mV CMP SEL = 1 (Comp On), RL = 10kW, RISO = 100W, CL = 10nF, CF = 47pF, G = 600x1x2, f = 4kHz, VOPP = 4V Time (50ms/div) Time (50ms/div) Figure 29. Figure 30. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 13 PGA308 SBOS440 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = VREF = DOUT/VCLAMP = +5V, RL = 10kΩ and CL = 100pF connected to GND, unless otherwise noted. Gain format is presented: G = FE-PGA x Fine Gain x Output Gain. LARGE-SIGNAL STEP RESPONSE CMP SEL = 1 VOUT (1V/div) VOUT (50mV/div) SMALL-SIGNAL STEP RESPONSE CMP SEL = 1 CMP SEL = 1 (Comp On), RL = 10kW, RISO = 100W, CL = 10nF, CF = 47pF, G = 4x1x2, f = 4kHz, VOPP = 100mV CMP SEL = 1 (Comp On), RL = 10kW, RISO = 100W, CL = 10nF, CF = 47pF, G = 4x1x2, f = 4kHz, VOPP = 4V Time (50ms/div) Figure 31. Figure 32. SMALL-SIGNAL STEP RESPONSE CMP SEL = 0 LARGE-SIGNAL STEP RESPONSE CMP SEL = 0 VOUT (1V/div) VOUT (50mV/div) Time (50ms/div) CMP SEL = 0 (Comp Off), RL = 10kW, CL = 0, CF = 0, G = 600x1x2, f = 4kHz, VOPP = 100mV Time (50ms/div) Figure 33. Figure 34. SMALL-SIGNAL STEP RESPONSE CMP SEL = 0 LARGE-SIGNAL STEP RESPONSE CMP SEL = 0 VOUT (1V/div) VOUT (50mV/div) Time (50ms/div) CMP SEL = 0 (Comp Off), RL = 10kW, CL = 0, CF = 0, G = 4x1x2, f = 4kHz, VOPP = 100mV 14 CMP SEL = 0 (Comp Off), RL = 10kW, CL = 0, CF = 0, G = 600x1x2, f = 4kHz, VOPP = 4V CMP SEL = 0 (Comp Off), RL = 10kW, CL = 0, CF = 0, G = 4x1x2, f = 4kHz, VOPP = 4V Time (50ms/div) Time (50ms/div) Figure 35. Figure 36. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 PGA308 www.ti.com ...................................................................................................................................................................................................... SBOS440 – JULY 2008 FUNCTIONAL DESCRIPTION OVERVIEW VOLTAGE REFERENCE The PGA308 is an ideal building block for resistive bridge sensor conditioning and general data acquisition. Digitally-programmable coarse offset, fine offset, and gain may be controlled in real time or permanently programmed into the PGA308. The PGA308 VREF pin provides input from a reference voltage. The reference voltage is used by the Coarse Offset Adjust and Zero DACs. The fault monitor circuitry trip points, as well as the over- and under-scale limits, can be selected to be referenced to either VS or VREF. This flexibility accommodates absolute or ratiometric mode designs. SENSOR ERROR ADJUSTMENT RANGE The PGA308 is designed to readily accommodate the following sensors: Span25°C: 0.08mV/V to 296mV/V Initial Offset: 20mV/V Span and offset are based on a bridge sensor excitation voltage of +5V, a PGA308 output voltage span of 4V (+0.5V to +4.5V), VREF of +5V, and a VOUT/VIN gain up to 9600. For proper PGA308 setup, consider noise, small-signal bandwidth, VOUT/VIN gain, and required system error. AMPLIFICATION SIGNAL PATH The core of the PGA308 is a precision, low drift, and low noise front-end programmable gain amplifier (PGA). This front-end PGA has gain capabilities from x4 to x1600. The output amplifier has a gain range from x2 to x6. A fine gain adjust in front of the output amplifier offers a selectable x0.33 to x1.0 attenuation factor. This architecture yields a VOUT/VIN gain range for the PGA309 of x2.67 to x9600. Many applications use overall gains of x1600 or less. The selection of gains in the front-end PGA and output amplifier, although capable of up to x9600 overall gain, are intended to allow for gain distribution throughout the PGA308; this design enables optimum span and offset scaling from input to output. The polarity of the inputs can be switched through the input mux to accommodate sensors with unknown polarity output. Higher gains reduce bandwidth and require more analog filtering and/or system analog-to-digital converter (ADC) averaging to reject noise. COARSE AND FINE OFFSET ADJUSTMENT The sensor offset adjustment is done in two stages. The input-referred Coarse Offset Adjust DAC has a ±100mV offset adjustment range for a selected VREF of +5V. Any residual input sensor offset is corrected and any desired VOUT offset pedestal for zero-applied sensor strain input is set by a Fine Offset Adjust through the 16-bit Zero DAC that adds to the signal from the output of the front-end PGA. FAULT MONITOR CIRCUIT SENSOR FAULT DETECTION To detect sensor burnout and/or short, a set of four comparators (external fault comparators) are connected to the inputs of the front-end PGA. There are two fault-detect modes of operation for these comparators. Common-Mode Fault If either of the inputs are taken outside of the common-mode range of the amplifier [greater than (VS – 1.2V), or less than 100mV], then the corresponding comparator sets a sensor fault flag that can be programmed to drive the PGA308 VOUT to within 100mV (IOUT < 4mA) of either VS (or VCLAMP if VCLAMP is used) or ground. This level is well above the set over-scale limit level or well below the set under-scale limit level. The state of the fault condition can be read in digital form in the ALRM register. If the over-scale/under-scale limiting is disabled, the PGA308 output voltage is also driven within 100mV (IOUT < 4mA) of either VS (or VCLAMP if VCLAMP is used) or ground, depending on the selected fault polarity (high or low). Bridge Fault To assist in identifying mis-wiring, or open- or short-circuit conditions, the PGA308 provides bridge fault monitoring. For bridge fault detection, either VS or VREF (whichever is used for bridge excitation) can be chosen as VFLT. If either of the inputs are taken to less than the larger of either 100mV or 0.35VFLT, then a fault is signaled. Also, if either of the inputs is taken to greater than the smaller of (VS – 1.2V) or 0.65VFLT, then a fault is signaled. This fault detection allows for operation with bridge differential voltages of up to 30% of the bridge excitation voltage. The corresponding comparator sets a sensor fault flag that can be programmed to drive the PGA308 VOUT to within 100mV (IOUT < 4mA) of either VS (or VCLAMP if VCLAMP is used) or ground. This level is well above the set over-scale limit level or well below the set Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 15 PGA308 SBOS440 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com under-scale limit level. If over-scale/under-scale limiting is disabled, the PGA308 output voltage is driven within 100mV (IOUT < 4mA) of either VS or ground, depending on the selected fault polarity (high or low). Additional Fault Detection There are five additional fault detect comparators (internal fault comparators) that help detect subtle PGA308 front-end violations that could result in linear voltages at VOUT and be interpreted as valid states. These comparators are especially useful during factory calibration and setup. Alarm Register Each of nine fault conditions sets a corresponding bit in the Alarm register. The state of the fault condition can be read digitally from the Alarm register. OVER-SCALE AND UNDER-SCALE LIMITS The over-scale and under-scale limit circuitry provides a programmable upper and lower clip limit for the PGA308 output voltage. When combined with the fault monitor circuitry, system diagnostics can be performed to determine if a conditioned sensor is defective, or if the process being monitored by the sensor is out of range. The selected PGA308 VLIM is divided down by a precision resistor string to form the over- and under-scale trip points. These resistor ratios are extremely accurate and produce no significant initial or temperature errors. An over-scale amplifier driven by the over-scale threshold limits (clips) the maximum PGA308 output, VOUT. Similarly, an under-scale amplifier driven by the under-scale threshold limits (clips) the mimimum PGA308 output, VOUT. The reference for the trip points, VLIM, is register-selectable for either VREF or VS. DOUT/VCLAMP PIN The dual-use DOUT/VCLAMP pin functions either as a VOUT clamp or as a digital push-pull output. The voltage clamp function provides an output voltage clamp, which is external-resistor programmable. In mixed-voltage systems, where the PGA308 may run from +5V with its output scaled for 0.1V to 2.9V, VCLAMP can be set to 3.0V to prevent an overvoltage lock-up/latch-up condition on a 3V system ADC or microcontroller input. When programmed as a digital output this pin can be used for sensor module configuration. The value may be pre-programmed in the one-time programmable (OTP) banks, or controlled through the One-Wire interface (1W pin). 16 DIGITAL INTERFACE: ONE-WIRE PROGRAM PROTOCOL The PGA308 can be configured through a single-wire, UART-compatible interface (1W pin). It is possible to connect this single-wire communication pin to the VOUT pin in true three-terminal modules (VS, ground, and sensor out) and continue to allow for calibration and configuration programming. All communication transactions start with an initialization byte transmitted by the controller. This byte (55h) sets the baud rate used for the communication transaction. The baud rate is sensed during the initialization byte of every transaction, and is used throughout the entire transaction. Each transaction may use a different baud rate, if desired. Baud rates of 4.8k to 114k bits/second are supported. Each communication consists of several bytes of data. Each byte consists of 10-bit periods. The first bit is the start bit and is always '0'. When idle, the 1W pin should always be high. The second through ninth bits are the eight data bits for the byte and are transferred LSB first. The 10th bit is the stop bit and is always '1'. The second byte is a command/address byte. The last bit in this byte indicates either a read or write at the address selected by the address pointer portion of the byte. Additional data transfer occurs after the command/address byte. The number of bytes and direction of data transfer depend on the command byte. For a read sequence, the PGA308 waits for a 2-bit delay (unless programmed otherwise) after the completion of the command/address byte before beginning to transmit. This wait allows time for the controller to ensure that the PGA308 is able to control the One-Wire interface. The first byte transmitted by the PGA308 is the least significant byte of the register and the second byte will be the most significant byte of the register. The recommended circuit implementation is to use a pull-up resistor and/or current source with an open drain (or open collector) output connected to the 1W pin, which is also an open drain output. The single wire can be driven high by the controller during transmit from the controller, but some form of pull-up is required to allow the signal to go high during receive because the PGA308 1W pin can only pull the output low. Timeout on the One-Wire Interface The PGA308 includes a timeout mechanism. If synchronization between the controller and the PGA308 is lost for any reason, the timeout mechanism allows the One-Wire interface to reset communication. The timeout period is set to approximately 28ms (typical). If the timeout period expires between the initialization byte and the Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 PGA308 www.ti.com ...................................................................................................................................................................................................... SBOS440 – JULY 2008 command byte, between the command byte and any data byte, or between any data bytes, the PGA308 resets the One-Wire interface circuitry so that it expects an initialization byte. Every time that a byte is transmitted on the single wire interface, this timeout period restarts. POWER-ON SEQUENCE The PGA308 provides circuitry to detect when the power supply is applied to the PGA308 and resets the internal registers to a known power-on reset (POR) state. This reset also occurs whenever the supply is invalid so that the PGA308 is set to a known state when the supply becomes valid again. The threshold for this circuit is approximately 1.7V to 2.1V. After the power supply becomes valid, the PGA308 waits for approximately 25ms, during which VOUT is disabled, and then attempts to read the data from the last valid OTP memory bank. If the memory bank has the proper checksum, then the PGA308 RAM is loaded with the OTP data and VOUT enabled. If the checksum is invalid, VOUT is set to disabled. Unless disabled by the OWD bit in Configuration Register 2 (CFG2), the One-Wire interface can always communicate to the PGA308 and override the contents of the current RAM in use by setting the appropriate SWL[2:0] bits in the Software Control Register (SFTC). For applications that require instant-on for VOUT, the NOW bit in the CFG2 register can be set to '1', which eliminates the 25ms disable of VOUT on power-up. ONE-WIRE OPERATION WITH 1W CONNECTED TO VOUT In some sensor applications, it is desired to provide the end user of the sensor module with three pins: VS, GND, and Sensor Out. It is also desired in these applications to digitally calibrate the sensor module after its final assembly of sensor and electronics. The PGA308 has a mode that allows the One-Wire interface pin (1W) to be tied directly to the PGA308 output pin (VOUT). To calibrate the PGA308 in Three-Wire configuration, program the internal registers and measure the resulting VOUT. To do this while VOUT is connected to 1W requires the ability to enable and disable VOUT. Thus, the 1W/VOUT line operates in a multiplexed mode where 1W is used as a bidirectional digital interface while VOUT is disabled, and VOUT drives the line as a conditioned sensor output voltage when it is enabled. The PGA308 also provides a mode in which the output amplifier can be enabled for a set time period and then disabled again to allow sharing of the 1W pin with the VOUT connection. This action is accomplished by writing a value to bits OEN[7:0] in the One-Wire Enable Control register (OENC). Any non-zero value enables the output. This non-zero value is decremented every 10ms until it becomes zero. When this value becomes zero, VOUT is disabled and a 1s timeout begins waiting for bus activity on the digital interface (1W pin). As long as there is activity on the 1W pin, the 1s timeout is continually reset. After 1s of no bus activity, the PGA308 checks for a correct checksum. If the checksum is correct, the PGA308 runs with the values that currently exist in RAM. If the checksum is not valid, the PGA308 checks for written bank select registers in OTP in the order of BANK SEL4, BANK SEL3, BANK SEL2 then BANK SEL1. The highest bank select register containing valid programmed data is read. The value read from this register points to one of the seven OTP banks, which is then loaded into RAM. OTP MEMORY BANKS There are four one-time programmable (OTP) bank selection registers: BANK SEL1, BANK SEL2, BANK SEL3, and BANK SEL4. Bank selection may be set four times by programming the BANK SELx registers in order (1, 2, 3, 4). The default OTP bank used on POR is the location stored in the last programmed BANK SELx register. Therefore, if programmed, BANK SEL4 always has priority over lower-numbered bank select registers. The PGA308 contains seven OTP user memory banks. All seven of these banks may be independently programmed. However, the default bank at POR can be set only four times. The seven possible OTP user memory banks allow an end product with a microcontroller interface between the end-user and the PGA308 to select from up to seven factory pre-programmed configurations. It also provides total user flexibility for any other configuration through software communication over the One-Wire interface (1W pin). This flexibility allows no-scrap recovery from miscalibration situations. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 17 PGA308 SBOS440 – JULY 2008................................................................................................................................................................................................................................................................................................... www.ti.com VS VREF VREF VS VS OTP (7 Banks) PGA308 POR Interface and Control Circuitry RAM Control Registers Alarm Register Digital Controls Input Mux Control Bridge Sensor (1) Fine Offset Adjust(1) (16-Bit) VREF Front-End PGA Out 0 < VZDAC < VREF Gain = x4 to x1600 16-Bit DAC Offset Due to Zero DAC -0.5VREF < Offset < +0.5VREF Zero DAC 4R A1 4R R Auto Zero VINN RG RF VS Input Mux Fault Ref Select(1) 7-Bit + Sign DAC Digital Out 2 1 VOUT RISO Clamp VOUT FILT VFB 8R 3 RGO VLIM CF CL 3-Bit DAC Under-Scale Limit(1) Fault Monitor Circuit RCL2 VS Scale Limit RFO INT/EXT FB Select(1) VREF VCLAMP Mode Only 8R VREF Ref Select DOUT/VCLAMP 3-Bit DAC Auto Zero R RCL1 1 Over-Scale Limit(1) VREF A2 (2) (3) Output Amplifier A3 Front-End PGA Gain 1W VLIM Gain DAC PGA Diff Amp Auto Zero VINP Ref Select Fine Gain Adjust (16-Bit)(1) RF VOS VLIM VS VIN1 VIN2 OS/US Ref Select(1) VREF DOUT/VCLAMP(1) PGA Gain Select (1 of 16)(1) Range of 4 to 1600 (w/PGA Diff Amp Gain = 4) VSJ Output Gain Select (1-of-7)(1) Range of 2 to 5 Alarm Register Inputs Coarse Offset Range(1) Coarse Offset Adjust Fault Detect Mode(1) (1) GND NOTES: (1) User-adjustable feature. (2) Optional connection; see the One-Wire Operation with 1W Connected to VOUT section for more information. (3) Optional connection; see the PGA308 User's Guide for more information. Figure 37. Detailed Block Diagram 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA308 PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PGA308AIDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA308AIDGST ACTIVE MSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA308AIDRKR PREVIEW SON DRK 10 3000 TBD Call TI Call TI PGA308AIDRKT PREVIEW SON DRK 10 250 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PGA308AIDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 PGA308AIDGST MSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA308AIDGSR MSOP DGS 10 2500 370.0 355.0 55.0 PGA308AIDGST MSOP DGS 10 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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