PGA309 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 Voltage Output PROGRAMMABLE SENSOR CONDITIONER FEATURES DESCRIPTION D D D D The PGA309 is a programmable analog signal conditioner designed for bridge sensors. The analog signal path amplifies the sensor signal and provides digital calibration for zero, span, zero drift, span drift, and sensor linearization errors with applied stress (pressure, strain, etc.). The calibration is done via a One-Wire digital serial interface or through a Two-Wire industry-standard connection. The calibration parameters are stored in external nonvolatile memory (typically SOT23-5) to eliminate manual trimming and achieve long-term stability. D D D D D D D D D COMPLETE BRIDGE SENSOR CONDITIONER VOLTAGE OUTPUT: Ratiometric or Absolute DIGITAL CAL: No Potentiometers/Sensor Trims SENSOR ERROR COMPENSATION − Span, Offset, and Temperature Drifts LOW ERROR, TIME-STABLE SENSOR LINEARIZATION CIRCUITRY TEMPERATURE SENSE: Internal or External CALIBRATION LOOKUP TABLE LOGIC − Uses External EEPROM (SOT23-5) OVER/UNDER-SCALE LIMITING SENSOR FAULT DETECTION +2.7V TO +5.5V OPERATION −40°C to +125°C OPERATION SMALL TSSOP-16 PACKAGE APPLICATIONS D D D D BRIDGE SENSORS REMOTE 4-20mA TRANSMITTERS STRAIN, LOAD, AND WEIGH SCALES AUTOMOTIVE SENSORS The core of the PGA309 is the precision, low-drift, no 1/f noise Front-End PGA (Programmable Gain Amplifier). The overall gain of the Front-End PGA + Output Amplifier can be adjusted from 2.7V/V to 1152V/V. The polarity of the inputs can be switched through the input mux to accommodate sensors with unknown polarity output. The Fault Monitor circuit detects and signals sensor burnout, overload, and system fault conditions. For detailed application information, see the PGA309 User’s Guide (SBOU024), available for download at www.ti.com. EVALUATION TOOLS D HARDWARE DESIGNER’S KIT (PGA309EVM) − Temperature Eval of PGA309 + Sensor − Full Programming of PGA309 − Sensor Compensation Analysis Tool The all-analog signal path contains a 2x2 input multiplexer (mux), auto-zero programmable-gain instrumentation amplifier, linearization circuit, voltage reference, internal oscillator, control logic, and an output amplifier. Programmable level shifting compensates for sensor DC offsets. VS N onlinear Bridge Linearization Circuit VEXC PGA309 Transducer P 0 psi Ref Lin DAC Analog Sensor Linearization 50 Fault Monitor Auto−Zero PGA Over/Under Scale Limiter Linear VOUT Analog Signal Conditioning +125_C Digital Int Temp Temperature Compensation T −40_C Ext Temp Ext Temp Digital Cal Temp ADC Control Register Interface Circuitry EEPROM (SOT23−5) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2003−2005, Texas Instruments Incorporated ! ! www.ti.com " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE−LEAD PACKAGE DRAWING PGA309 TSSOP-16 PW SPECIFIED TEMPERATURE RANGE PACKAGE MARKING −40°C to +125°C PGA309 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY PGA309AIPWR Tape and Reel, 2500 PGA309AIPWT Tape and Reel, 250 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS(1) Over operating free-air temperature range unless otherwise noted. Supply Voltage, VSD, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input Voltage, VIN1, VIN2(2) . . . . . . . . . . . . . . . . . . . . . −0.3V to VSA +0.3V Input Current, VFB, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±150mA Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Output Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . −60°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C ESD Protection (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less. 2 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER FRONT-END PGA + OUTPUT AMPLIFIER VOUT/VIN Differential Signal Gain Range(1) Input Voltage Noise Density VOUT Slew Rate VOUT Settling Time (0.01%) VOUT Settling Time (0.01%) VOUT Nonlinearity External Sensor Output Sensitivity CONDITIONS MIN Fine Gain Adjust = 1 Front-End PGA Gains: 4, 8, 16, 23.27, 32, 42.67, 64, 128 Output Amplifier Gains: 2, 2.4, 3, 3.6, 4.5, 6, 9 f = 1kHz VOUT/VIN Differential Gain = 8, RL = 5kΩ || 200pF VOUT/VIN Differential Gain = 191, RL = 5kΩ || 200pF VSA = VSD = VEXC = +5V TYP MAX UNITS 8 to 1152 V/V 210 0.5 6 4.1 0.002 1 to 245 nV/√Hz V/µs µs µs %FSR mV/V FRONT-END PGA Auto-Zero Internal Frequency Offset Voltage (RTI)(2) vs Temperature vs Supply Voltage, VSA vs Common-Mode Voltage Linear Input Voltage Range(3) Input Bias Current Input Impedance: Differential Input Impedance: Common-Mode Input Voltage Noise PGA Gain Gain Range Steps Initial Gain Error vs Temperature Output Voltage Range Bandwidth 7 ±3 +0.2 ±2 1500/GF Coarse Offset Adjust Disabled GF = Front-End PGA Gain 0.2 0.1 30 || 6 50 || 20 4 0.1Hz to 10Hz, GF = 128 4, 8, 16, 23.27, 32, 42.67, 64, 128 GF = 4 to 42 GF = 64 GF = 128 ±50 6000/GF VSA−1.5 1.5 4 to 128 0.2 ±1 0.25 ±1.2 0.3 ±1.6 10 0.05 to VSA − 0.1 400 60 Gain = 4 Gain = 128 kHz µV µV/°C µV/V µV/V V nA GΩ || pF GΩ || pF µVPP V/V % % % ppm/°C V kHz kHz COARSE OFFSET ADJUST (RTI OF FRONT-END PGA) Range vs Temperature Resolution ±(14)(VREF)(0.00085) ±56 ±14 steps, 4-Bit + Sign ±59.5 0.004 4 ±64 mV %/°C mV VREF VSA−0.1 73 20 0.5 0.1 10 5 10 V V µV LSB LSB % ppm/°C mV µV/°C 0.33 to 1 10 20 0.5 V/V µV/V LSB LSB FINE OFFSET ADJUST (ZERO DAC) (RTO of the Front-End PGA)(2) Programming Range Output Range Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Gain Error Drift Offset Offset Drift 0 0.1 65,536 steps, 16-Bit DAC OUTPUT FINE GAIN ADJUST (GAIN DAC) Range Resolution Integral Nonlinearity Differential Nonlinearity 65,536 steps, 16-Bit DAC 3 " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS (continued) BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER CONDITIONS MIN TYP MAX UNITS OUTPUT AMPLIFIER Offset Voltage (RTI of Output Amplifier)(2) vs Temperature vs Supply Voltage, VSA Common-Mode Input Range Input Bias Current Amplifier Internal Gain Gain Range Steps Initial Gain Error vs Temperature Output Voltage Range(4) Open Loop Gain Gain-Bandwidth Product Phase Margin Output Resistance OVER- AND UNDER-SCALE LIMITS Over-Scale Thresholds Over-Scale Comparator Offset Over-Scale Comparator Offset Drift Under-Scale Thresholds 3 5 30 0 VSA−1.5 100 2, 2.4, 3, 3.6, 4.5, 6, 9 2, 2.4, 3.6 4.5 6 9 2, 2.4, 3.6 4.5 6 9 RL = 10kΩ 2 to 9 0.25 0.3 0.4 0.6 5 5 15 30 0.1 4.9 115 2 45 675 Gain = 2, CL = 200pF AC Small-Signal, Open-Loop, f = 1MHz, IO = 0 (VREF = 4.096) Ratio of VREF, Register 5—Bits D5, D4, D3 = ‘000’ Ratio of VREF, Register 5—Bits D5, D4, D3 = ‘001’ Ratio of VREF, Register 5—Bits D5, D4, D3 = ‘010’ Ratio of VREF, Register 5—Bits D5, D4, D3 = ‘011’ Ratio of VREF, Register 5—Bits D5, D4, D3 = ‘100’ Ratio of VREF, Register 5—Bits D5, D4, D3 = ‘101’ Ratio of VREF, Register 5—Bits D5, D4, D3 = ‘110’ +6 Ratio of VREF, Register 5—Bits D2, D1, D0 = ‘111’ Ratio of VREF, Register 5—Bits D2, D1, D0 = ‘110’ Ratio of VREF, Register 5—Bits D2, D1, D0 = ‘101’ Ratio of VREF, Register 5—Bits D2, D1, D0 = ‘100’ Ratio of VREF, Register 5—Bits D2, D1, D0 = ‘011’ Ratio of VREF, Register 5—Bits D2, D1, D0 = ‘010’ Ratio of VREF, Register 5—Bits D2, D1, D0 = ‘001’ Ratio of VREF, Register 5—Bits D2, D1, D0 = ‘000’ Under-Scale Comparator Offset Under-Scale Comparator Offset Drift ±1 ±1.2 ±1.5 ±2.0 −7 0.9708 0.9610 0.9394 0.9160 0.9102 0.7324 0.5528 +60 +0.37 0.0605 0.0547 0.0507 0.0449 0.0391 0.0352 0.0293 0.0254 −50 −0.15 mV µV/°C µV/V V pA V/V % % % % ppm/°C ppm/°C ppm/°C ppm/°C V dB MHz Degrees Ω +114 mV mV/°C +93 mV mV/°C FAULT MONITOR CIRCUIT INP_HI, INN_HI Comparator Threshold INP_LO, INN_LO Comparator Threshold A1SAT_HI, A2SAT_HI Comparator Threshold A1SAT_LO, A2SAT_LO Comparator Threshold A3_VCM Comparator Threshold Comparator Hysteresis 4 See Note 5 40 VSA−1.2 or VEXC−0.1 100 VSA−0.12 VSA−0.12 VSA−1.2 20 V mV V V V mV " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS (continued) BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER CONDITIONS MIN TYP MAX UNITS Register 3, Bit D9 = 1 2.46 2.53 Register 3, Bit D9 = 0 4.0 2.5 +10 4.096 +10 100 1 1 V ppm/°C V ppm/°C µA mA mA INTERNAL VOLTAGE REFERENCE VREF1 VREF1 Drift vs Temperature VREF2 VREF2 Drift vs Temperature Input Current REFIN/REFOUT Output Current REFIN/REFOUT Internal VREF Disabled VSA > 2.7V for VREF = 2.5V VSA > 4.3V for VREF = 4.096V 4.14 TEMPERATURE SENSE CIRCUITRY (ADC) Internal Temperature Measurement Accuracy Resolution Temperature Measurement Range Conversion Rate Register 6, Bit D9 = 1 ±2 ±0.0625 12-Bit + Sign, Two’s Complement Data Format −55 R1, R0 = ‘11’, 12-Bit + Sign Resolution +150 24 °C °C °C ms TEMPERATURE ADC External Temperature Mode Gain Range Steps Analog Input Voltage Range Temperature ADC Internal REF (2.048V) Full-Scale Input Voltage Differential Input Impedance Common-Mode Input Impedance Resolution Integral Nonlinearity Offset Error Offset Drift Offset vs VSA Gain Error Gain Error Drift Noise Gain vs VSA Common-Mode Rejection Temp PGA + Temp ADC GPGA = 1, 2, 4, 8 1 to 8 GND−0.2 Register 6, Bit D8 = 1 (+Input) − (−Input) GPGA GPGA GPGA GPGA =1 =2 =4 =8 R1, R0 = ‘00’, ADC2X = ‘0’, Conversion Time = 8ms R1, R0 = ‘01’, ADC2X = ‘0’, Conversion Time = 32ms R1, R0 = ‘10’, ADC2X = ‘0’, Conversion Time = 64ms R1, R0 = ‘11’, ADC2X = ‘0’, Conversion Time = 128ms GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA =1 =2 =4 =8 =1 =2 =4 =8 =1 =2 =4 =8 All Gains At DC and GPGA = 8 At DC and GPGA = 1 VSA+0.2 ±2.048/GPGA 2.8/GPGA 3.5 3.5 1.8 0.9 11 13 14 15 0.004 1.2 0.7 0.5 0.4 1.2 0.6 0.3 0.3 800 400 200 150 0.05 5 <1 80 105 100 0.50 50 V/V V V MΩ MΩ MΩ MΩ MΩ Bits + Sign Bits + Sign Bits + Sign Bits + Sign % mV mV mV mV µV/°C µV/°C µV/°C µV/°C µV/V µV/V µV/V µV/V % ppm/°C LSB ppm/V dB dB 5 " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS (continued) BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER CONDITIONS MIN TYP MAX UNITS TEMPERATURE ADC (CONTINUED) Temp ADC Ext. REF (VREFT = VREF, VEXC, or VSA) Full-Scale Input Voltage Differential Input Impedance Common-Mode Input Impedance Resolution Register 6, Bit D8 = 0 (+Input) − (−Input) GPGA GPGA GPGA GPGA =1 =2 =4 =8 R1, R0 = ‘00’, ADC2X = ‘0’, Conversion Time = 6ms R1, R0 = ‘01’, ADC2X = ‘0’, Conversion Time = 24ms R1, R0 = ‘10’, ADC2X = ‘0’, Conversion Time = 50ms R1, R0 = ‘11’, ADC2X = ‘0’, Conversion Time = 100ms Integral Nonlinearity Offset Error GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA Offset Drift Gain Error Gain Error Drift Gain vs VSA Common-Mode Rejection External Temperature Current Excitation Current Excitation Temperature Drift Voltage Compliance ±VREFT/GPGA 2.4/GPGA 8 8 8 8 11 13 14 15 0.01 2.5 1.25 0.7 0.3 1.5 1.0 0.7 0.6 −0.2 2 80 100 85 =1 =2 =4 =8 =1 =2 =4 =8 At DC and GPGA = 8 At DC and GPGA = 1 Register 6, Bit D11 = 1 ITEMP 5.8 7 5 VSA−1.2 V MΩ MΩ MΩ MΩ MΩ Bits + Sign Bits + Sign Bits + Sign Bits + Sign % mV mV mV mV µV/°C µV/°C µV/°C µV/°C % ppm/°C ppm/V dB dB 8 µA nA/°C V LINEARIZATION ADJUST AND EXCITATION VOLTAGE (VEXC) Range 0 Linearization DAC Range Linearization DAC Resolution VEXC Gain Gain Error Drift Range 1 Linearization DAC Range Linearization DAC Resolution VEXC Gain Gain Error Drift VEXC Range Upper Limit IEXC SHORT Register 3, Bit D11 = 0 With Respect to VFB ±127 Steps, 7-Bit + Sign With Respect to VREF Register 3, Bit D11 = 1 With Respect to VFB ±127 Steps, 7-Bit + Sign With Respect to VREF IEXC = 5mA Short-Circuit VEXC Output Current −0.166 to +0.166 1.307 0.83 25 V/V mV/V V/V ppm/°C −0.124 to +0.124 0.9764 0.52 25 VSA − 0.5 50 V/V mV/V V/V ppm/°C V mA DIGITAL INTERFACE Two-Wire Compatible One-Wire Maximum Lookup Table Size(6) Two-Wire Data Rate Bus Speed Serial Speed Baud Rate 1 4.8K 400 38.4K kHz Bits/s Bits kHz 0.2 • VSD V V V µA µA V 17 x 3 x 16 65 PGA309 to EEPROM (SCL frequency) LOGIC LEVELS Input Levels (SDA, SCL, PRG, TEST) (SDA, SCL, PRG, TEST) (SDA, SCL) Pull-Up Current Source (SDA, SCL) Pull-Down Current Source (TEST) Output LOW Level (SDA, SCL, PRG) 6 Low High Hysteresis 0.7 • VSD 55 15 Open Drain, ISINK = 5mA 0.1 • VSD 85 25 125 40 0.4 " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS (continued) BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER CONDITIONS MIN TYP MAX UNITS VSA = VSD = +5V, without Bridge Load 1.2 5.5 1.6 V mA VSA Rising VSA Falling 2.2 1.7 2.7 V V +125 +150 °C °C POWER SUPPLY VSA, VSD ISA + ISD, Quiescent Current 2.7 POWER-ON RESET Power-Up Threshold Power-Down Threshold TEMPERATURE RANGE Specified Performance Operational − Degraded Performance −40 −55 (1) PGA309 total differential gain from input (VIN1−VIN2) to output (VOUT). VOUT / (VIN1−VIN2) = (Front-End PGA gain) (Output Amplifier gain) (Gain DAC). (2) RTI = referred to input. RTO = referred to output. (3) Linear input range is the allowed min/max voltage on the VIN1 and VIN2 pins for the input PGA to continue to operate in a linear region. The allowed common-mode and differential voltage is dependent upon gain and offset settings. Refer to the Gain Scaling section for more information. (4) Unless limited by over/under-scale setting. (5) When VEXC is enabled, a minimum reference selector circuit becomes the reference for the comparator threshold. This minimum reference selector circuit uses VEXC − 100mV and VSA − 1.2V and compares the VINX pin to the lower of the two references. This ensures accurate fault monitoring in conditions where VEXC might be higher or lower than the input CMR of the PGA input amplifier relative to VSA. (6) Lookup Table allows multislope compensation over temperature. Lookup Table has access to 17 calibration points consisting of 3 adjustment values (Tx, Temperature, ZMx, Zero DAC, GMx, Gain DAC) that are stored in 16-bit data format (17x3x16 = Lookup Table size). 7 " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 PIN CONFIGURATION Top View TSSOP VEXC 1 16 REFIN/REFOUT GNDA 2 15 TEMPIN VSA 3 14 SDA VIN1 4 VIN2 5 12 PRG VFB 6 11 GNDD VOUT 7 10 VSD VSJ 8 9 13 SCL PGA309 TEST PIN DESCRIPTION PIN 8 NAME DESCRIPTION 1 VEXC Bridge sensor excitation. Connect to bridge if linearization and/or internal reference for bridge excitation is to be used. 2 GNDA Analog ground. Connect to analog ground return path for VSA. Should be same as GNDD. 3 VSA Analog voltage supply. Connect to analog voltage supply. To be within 200mV of VSD. 4 VIN1 Signal input voltage 1. Connect to + or – output of sensor bridge. Internal multiplexer can change connection internally to Front-End PGA. 5 VIN2 Signal input voltage 2. Connect to + or – output of sensor bridge. Internal multiplexer can change connection internally to Front-End PGA. 6 VFB VOUT feedback pin. Voltage feedback sense point for over/under-scale limit circuitry. When internal gain set resistors for the output amplifier are used, this is also the voltage feedback sense point for the output amplifier. VFB in combination with VSJ allows for ease of external filter and protection circuits without degrading the PGA309 VOUT accuracy. VFB must always be connected to either VOUT or the point of feedback for VOUT, if external protection is used. 7 VOUT Analog output voltage of conditioned sensor. 8 VSJ Output amplifier summing junction. Use for output amplifier compensation when driving large capacitive loads (> 100pF) and/or for using external gain setting resistors for the output amplifier. 9 TEST Test/External Controller Mode pin. Pull to GNDD in normal mode. 10 VSD Digital voltage supply. Connect to digital voltage supply. To be within 200mV of VSA. 11 GNDD Digital ground. Connect to digital ground return path for VSD. Should be same as GNDA. 12 PRG Single-wire interface program pin. UART-type interface for digital calibration of the PGA309 over a single wire. Can be connected to VOUT for a three-lead (VS, GND, VOUT) digitally-programmable sensor assembly. 13 SCL Clock input/output for Two-Wire, industry-standard compatible interface for reading and writing digital calibration and configuration from external EEPROM. Can also communicate directly to the registers in the PGA309 through the Two-Wire, industry-standard compatible interface. 14 SDA Data input/output for Two-Wire, industry-standard compatible interface for reading and writing digital calibration and configuration from external EEPROM. Can also communicate directly to the registers in the PGA309 through the Two-Wire, industry-standard compatible interface. 15 TEMPIN External temperature signal input. PGA309 can be configured to read a bridge current sense resistor as an indicator of bridge temperature, or an external temperature sensing device such as diode junction, RTD, or thermistor. This input can be internally gained by 1, 2, 4, or 8. In addition, this input can be read differentially with respect to VGNDA, VEXC, or the internal/external VREF. There is also an internal, register-selectable, 7µA current source (ITEMP) that can be connected to TEMPIN as an RTD, thermistor, or diode excitation source. 16 REFIN/REFOUT Reference input/output pin. As an output, the internal reference (selectable as 2.5V or 4.096V) is available for system use on this pin. As an input, the internal reference may be disabled and an external reference can then be applied as the reference for the PGA309. " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. VREF vs TEMPERATURE 4.090 IB CURRENT vs TEMPERATURE 1.0 0.5 4.085 0 IB (nA) VREF (V) 4.080 4.075 Average Average, nA −0.5 −1.0 −1.5 4.070 −2.0 4.065 −2.5 4.060 −55 −35 −15 5 25 45 65 85 −3.0 −55 −35 −15 105 125 145 I TEMP CURRENT vs TEMPERATURE 9 25 65 85 105 125 145 COMMON−MODE REJECTION RATIO vs FREQUENCY RTO of Front−End PGA 60 Average 50 6 40 CMRR (dB) 7 5 4 3 30 20 10 0 2 −10 1 −20 0 −55 −35 −15 5 25 45 65 85 −30 105 125 145 10 100 Temperature (_C) 1k 10k 100k 1M Frequency (Hz) POWER−SUPPLY REJECTION RATIO vs FREQUENCY CLOSED−LOOP GAIN vs FREQUENCY 90 80 80 GOUTAMP = Output Amplifer Gain 70 GOUTAMP = 9V/V GFRONT = 128V/V 60 60 50 Gain (dB) PSRR (dB) 45 70 8 ITEMP (µA) 5 Temperature (_C) Temperature (_C) 40 30 Small−Signal VREF and VEXT Enabled VREF = 2.5V PSRR at VOUT 20 10 0 −10 GOUTAMP = 9V/V GFRONT = 32V/V 40 20 GOUTAMP = 2V/V G FRONT = 32V/V GOUTAMP = 2V/V GFRONT = 8V/V 0 10 100 1k 10k Frequency (Hz) 100k 1M 10 100 1k 10k 100k 1M Frequency (Hz) 9 " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. VOUT SWING TO RAIL vs ILOAD VS 1.6 VS − 0.1 1.4 VS − 0.2 VS = 5V VS = 2.7V VS − 0.3 1.2 IQ (mA) VS − 0.4 VS − 0.5 0.5 1.0 0.8 Ref, Exc, and ADC Disabled VS = 5V 0.3 0.4 VS = 2.7V 0.2 0.2 0.1 0 −55 −35 −15 0 0 5 10 15 20 25 5 25 45 TEMPERATURE ADC ERROR (INTERNAL MODE) 0.2 0.3 0 0.2 Total Error (% of FS) 0.4 −0.2 −0.4 −0.6 −0.8 −1.0 25 45 65 0.1 0 −0.1 −0.2 85 105 125 145 Reg 6 = 0430h VREF = 2.5V Internal 11−Bit + Sign Reg 6 = 0403h VREF = 5V External 15−Bit + Sign −0.4 −100 −80 −60 −40 −20 Actual Die Temperature (_ C) 20 60 80 G = 1152 Coarse Offset = −59mV VIN = +61mV CLK_CFG= 00 (default) 1mV/div 1s/div 40 VOUT NOISE (0.1Hz TO 10Hz PEAK−TO−PEAK NOISE) VREF = 4.096V 50µV/div 0 Input Signal (% FS of VREF) VREF NOISE (0.1Hz TO 10Hz) Measured After Bandpass Filter 0.1Hz Second−Order High−Pass 10Hz Fourth−Order Low−Pass 105 125 145 Reg 6 = 0503h VREF = 2.048V (Temp ADC Internal) 15−Bit + Sign Reg 6 = 0433h VREF = 2.5V Internal 15−Bit + Sign −0.3 5 85 TEMPERATURE ADC ERROR (EXTERNAL MODES) 0.4 −1.2 −55 −35 −15 65 Temperature (_C) ILOAD (mA) Temp ADC Error (_C) All Blocks Enabled 0.6 0.4 10 IQ vs TEMPERATURE Measured After Bandpass Filter 0.1Hz Second−Order High−Pass 10Hz Fourth−Order Low−Pass 1s/div 100 " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. INPUT VOLTAGE NOISE DENSITY INPUT VOLTAGE NOISE DENSITY 1 Coarse Offset Adjust = −59mV VIN = +61mV CLK_CFG = ’00’ (default) eND (µV/√Hz), RTI Coarse Offset Adjust = 0mV CLK_CFG = ’00’ (default) 1 0.1 0.1 0.01 0.01 1 10 100 1k 10k 1 50k 10 100 1k 10k Frequency (Hz) Frequency (Hz) LARGE−SIGNAL STEP RESPONSE LARGE−SIGNAL STEP RESPONSE VOUT (500mV/div) VOUT (500mV/div) 100k Gain = 1152 Gain = 8 Time (10µs/div) Time (10µs/div) SMALL−SIGNAL STEP RESPONSE SMALL−SIGNAL STEP RESPONSE Gain = 256 Gain = 8 VOUT (50mV/div) VOUT (50mV/div) eND (µV/√Hz), RTI 10 Time (10µs/div) Time (10µs/div) 11 " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. CAPACITIVE LOAD DRIVE OVERVOLTAGE RECOVERY 25 VOUT VIN (200mV/div), VOUT (1V/div) 0.5% Settling Time (µs) GOUTAMP = 2V/V 20 15 GOUTAMP = 3.6V/V GOUTAMP = 9V/V 10 5 VIN 0 0 500 1000 1500 2000 2500 Time (100µs/div) CLOAD (pF) OUTPUT AMPLIFIER OPEN−LOOP GAIN/PHASE vs FREQUENCY 120 ZERO DAC TYPICAL ERROR vs CODE CL = 100pF RL = 4.7kΩ 100 20 45 15 0 Unit 2 −45 60 −90 40 −135 20 −180 5 Error (LSB) 80 Phase (_ ) AOL (dB) 10 0 Unit 1 −5 −10 0 0.1 1 10 100 1k 10k 100k 1M −15 −20 −225 10M 0 10000 20000 30000 GAIN DAC TYPICAL ERROR vs CODE 20 15 Error (LSB) 10 5 0 −5 −10 −15 −20 0 10000 20000 30000 40000 Code (LSB) 12 40000 Code (LSB) Frequency (Hz) 50000 60000 70000 50000 60000 70000 " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 FUNCTIONAL DESCRIPTION The PGA309 is a programmable analog signal conditioner designed for resistive bridge sensor applications. It is a complete signal conditioner with bridge excitation, initial span and offset adjustment, temperature adjustment of span and offset, internal/external temperature measurement capability, output over-scale and under-scale limiting, fault detection, and digital calibration. The PGA309, in a calibrated sensor module, can reduce errors to the level approaching the bridge sensor repeatability. Figure 1 shows a block diagram of the PGA309. Following is a brief overview of each major function. SENSOR ERROR ADJUSTMENT RANGE The adjustment capability of the PGA309 summarized in Table 1. FSS (full-scale sensitivity) 1mV/V to 245mV/V Span TC Over ±3300ppmFS/°C(1) Span TC nonlinearity > 10% Zero offset ±200%FS(2) Zero offset TC Over ±3000ppmFS/°C(2) Zero offset TC nonlinearity > 10% Sensor impedance Down to 200Ω(3) is (1) Depends on the temperature sensing scheme (2) Combined coarse and fine offset adjust (3) Lower impedance possible by using a dropping resistor in series with the bridge Table 1. PGA309 Adjustment Capability GAIN SCALING The core of the PGA309 is the precision low-drift and no 1/f noise Front-End PGA. The overall gain of the Front-End PGA + Output Amplifier can be adjusted from 2.7V/V to 1152V/V. The polarity of the inputs can be switched through the 2x2 input mux to accommodate sensors with unknown polarity output. The Front-End PGA provides initial coarse signal gain using a no 1/f noise, auto-zero instrumentation amplifier. The fine gain adjust is accomplished by the 16-bit attenuating Gain Digital-to-Analog Converter (Gain DAC). This Gain DAC is controlled by the data in the Temperature Compensation Lookup Table driven by the Temperature Analog-to-Digital Converter (Temp ADC). In order to compensate for second-order and higher drift nonlinearity, the span drift can be fitted to piecewise linear curves during calibration with the coefficients stored in an external nonvolatile EEPROM lookup table. Following the fine gain adjust stage is the Output Amplifier that provides additional programmable gain. Two key output amplifier connections, VFB and VSJ, are brought out on the PGA309 for application flexibility. These connections allow for an accurate conditioned signal voltage while also providing a means for PGA309 output overvoltage and large capacitive loading for RFI/EMI filtering required in many end applications. OFFSET ADJUSTMENT The sensor offset adjustment is performed in two stages. The input-referred Coarse Offset Adjust DAC has approximately a ±60mV offset adjustment range for a selected VREF of 5V. The fine offset and the offset drift are canceled by the 16-bit Zero DAC that sums the signal with the output of the front-end instrumentation amplifier. Similar to the Gain DAC, the input digital values of the Zero DAC are controlled by the data in the Temperature Compensation Lookup Table, stored in external EEPROM, driven by the Temp ADC. The programming range of the Zero DAC is 0V to VREF with an output range of 0.1V to VSA − 0.1V. VOLTAGE REFERENCE The PGA309 contains a precision low-drift voltage reference (selectable for 2.5V or 4.096V) that can be used for external circuitry through the REFIN/REFOUT pin. This same reference is used for the Coarse Offset Adjust DAC, Zero DAC, Over/Under-Scale Limits and sensor excitation/linearization through the VEXC pin. When the internal reference is disabled, the REFIN/REFOUT pin should be connected to an external reference or to VSA for ratiometric-scaled systems. SENSOR EXCITATION AND LINEARIZATION A dedicated circuit with a 7-bit + sign DAC for sensor voltage excitation and linearization is provided on the PGA309. This block scales the reference voltage and sums it with a portion of the PGA309 output to compensate the positive or negative bow-shaped nonlinearity exhibited by many sensors over their applied pressure range. Sensors not requiring linearization can be connected directly to the supply (VSA) or to the VEXC pin with the Linearization DAC (Lin DAC) set to zero. 13 " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 +5V VSD V SA REFIN /REFOU T PGA309 VREF Power−On Reset KREF VEXC Band−Gap Voltage Reference Σ VO UT KLIN Linearization DAC VFB SDA Interface and Control Circuitry Internal Temp Sense VTE MP TEMPIN Temp ADC Signals Mux +5V SCL Two−Wire EEPROM (SOT23−5) Temperature ADC Temperature ADC Input Select SpanTC and OffsetTC Adjust Lookup Table with interpolation Coarse Offset Adjust PRG Fine Offset Adjust Zero DAC V OS Over/Under− Scale Limits VIN2 Bridge 2x2 Multiplexer VIN1 Front−End PGA Out Front−End PGA (Gain 4 to 128) VOU T Fault Out VOU T F IL T Sensor Fine Gain Adjust Gain DAC V OUT Output Amp R ISO 100Ω CL 10nF RT EMP TEST Fault Conditions Monitoring Circuit Fault Out Int/Ext Feedback VF B V FB Test Logic Output Coarse Gain Adjust (2 to 9) CF 150pF V SJ GND A GNDD Figure 1. Simplified Diagram of the PGA309 in a Typical Configuration. 14 RF B 100Ω " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 ADC FOR TEMPERATURE SENSING The temperature sense circuitry drives the compensation for the sensor span and offset drift. Either internal or external temperature sensing is possible. The temperature can be sensed in one of the following ways: D Bridge impedance change (excitation current sense, in the positive or negative part of the bridge), for sensors with large temperature coefficient of resistance (TCR > 0.1%/°C). D On-chip PGA309 temperature, when the chip is located sufficiently close to the sensor. D External diode, thermistor, or RTD placed on the sensor membrane. An internal 7µA current source may be enabled to excite these types of temperature sensors. The temperature signal is digitized by the onboard Temp ADC. The output of the Temp ADC is used by the control digital circuit to read the data from the Lookup Table in an external EEPROM, and set the output of the Gain DAC and the Zero DAC to the calibrated values as temperature changes. An additional function provided through the Temp ADC is the ability to read the VOUT pin back through the Temp ADC input mux. This provides flexibility for a digital output through either One-Wire or Two-Wire interface, as well as the possibility for an external microcontroller to perform real-time custom calibration of the PGA309. EXTERNAL EEPROM AND TEMPERATURE COEFFICIENTS The PGA309 uses an industry-standard Two-Wire external EEPROM (typically, a SOT23-5 package). A 1k-bit (minimum) EEPROM is needed when using all 17 temperature coefficients. Larger EEPROMs may be used to provide space for a serial number, lot code, or other data. The first part of the external EEPROM contains the configuration data for the PGA309, with settings for: D Register 3—Reference Control and Linearization D Register 4—PGA Coarse Offset and Gain/Output Amplifier Gain D Register 5—PGA Configuration and Over/UnderScale Limit D Register 6—Temp ADC Control This section of the EEPROM contains its own individual checksum (Checksum1). The second part of the external EEPROM contains up to 17 temperature index values and corresponding temperature coefficients for the Zero DAC and Gain DAC adjustments with measured temperature, and also contains its own checksum (Checksum2). The PGA309 lookup logic contains a linear interpolation algorithm for accurate DAC adjustments between stored temperature indexes. This approach allows for a piecewise linear temperature compensation of up to 17 temperature indexes and associated temperature coefficients. If either Checksum1, Checksum2, or both are incorrect, the output of the PGA309 is set to high-impedance. FAULT MONITOR To detect sensor burnout or a short, a set of four comparators are connected to the inputs of the Front-End PGA. If any of the inputs are taken to within 100mV of ground or VEXC, or violate the input CMR of the Front-End PGA, then the corresponding comparator sets a sensor fault flag that causes the PGA309 VOUT to be driven within 100mV of either VSA or ground, depending upon the alarm configuration setting (Register 5—PGA Configuration and Over/Under-Scale Limit). This will be well above the set Over-Scale Limit level or well below the set Under-Scale Limit level. The state of the fault condition can be read in digital form in Register 8—Alarm Status Register. If the Over/Under-Scale Limit is disabled, the PGA309 output voltage will still be driven within 100mV of either VSA or ground, depending upon the alarm configuration setting. There are five other fault detect comparators that help detect subtle PGA309 front-end violations that could otherwise result in linear voltages at VOUT that would be interpreted as valid states. These are especially useful during factory calibration and setup, and are configured through Register 5—PGA Configuration and Over/Under-Scale Limit. Their status can also be read back through Register 8—Alarm Status Register. OVER-SCALE AND UNDER-SCALE LIMITS The over-scale and under-scale limit circuitry combined with the fault monitor circuitry provides a means for system diagnostics. A typical sensor-conditioned output may be scaled for 10% to 90% of the system ADC range for the sensor normal operating range. If the conditioned pressure sensor is below 4%, it is considered under-pressure; if over 96%, it is considered over-pressure. The PGA309 over/under-scale limit circuit can be programmed individually for under-scale and over-scale values that clip or limit the PGA309 output. From a system diagnostic view, 10% to 90% of ADC range is normal operation, < 4% is under-pressure, and > 96% is over-pressure. If the fault detect circuitry is used, a detected fault will cause the PGA309 output to be driven to positive or negative saturation. If this fault 15 " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 flag is programmed for high, then > 97% ADC range will be a fault; if programmed for low, then < 3% ADC range will be a fault. In this configuration, the system software can be used to distinguish between over- or under-pressure condition, which indicates an out-of-control process, or a sensor fault. POWER-UP AND NORMAL OPERATION The PGA309 has circuitry to detect when the power supply is applied to the PGA309, and reset the internal registers and circuitry to an initial state. This reset also occurs when the supply is detected to be invalid, so that the PGA309 is in a known state when the supply becomes valid again. The rising threshold for this circuit is typically 2.2V and the falling threshold is typically 1.7V. After the power supply becomes valid, the PGA309 waits for approximately 25ms and then attempts to read the configuration data from the external EEPROM device. If the EEPROM has the proper flag set in address locations 0 and 1, then the PGA309 continues reading the first part of the EEPROM; otherwise, the PGA309 waits for one second before trying again. If the PGA309 detects no response from the EEPROM, the PGA309 waits for one second and tries again; otherwise, the PGA309 tries to free the bus and waits for 25ms before trying to read the EEPROM again. If a successful read of the first part of the EEPROM is accomplished, (including valid Checksum1 data), the PGA309 triggers the Temp ADC to measure temperature. For 16-bit resolution results, the converter takes approximately 125ms to complete a conversion. Once the conversion is complete, the PGA309 begins reading the Lookup Table information from the EEPROM (second part) to calculate the settings for the Gain DAC and Zero DAC. The PGA309 reads the entire Lookup Table so that it can determine if the checksum for the Lookup Table (Checksum2) is correct. Each entry in the Lookup Table requires approximately 500µs to read from the 16 EEPROM. Once the checksum is determined to be valid, the calculated values for the Gain and Zero DACs are updated into their respective registers, and the output amplifier is enabled. The PGA309 then begins looping through this entire procedure, starting with reading the EEPROM configuration registers from the first part of the EEPROM, then starting a new conversion on the Temp ADC, which then triggers reading the Lookup Table data from the second part of the EEPROM. This loop continues indefinitely. DIGITAL INTERFACE There are two digital interfaces on the PGA309. The PRG pin uses a One-Wire, UART-compatible interface with bit rates from 4.8Kbits/s to 38.4Kbits/s. The SDA and SCL pins together form an industry standard Two-Wire interface at clock rates from 1kHz to 400kHz. The external EEPROM uses the Two-Wire interface. Communication to the PGA309 internal registers, as well as to the external EEPROM, for programming and readback can be conducted through either digital interface. It is also possible to connect the One-Wire communication pin, PRG, to the VOUT pin in true three-wire sensor modules and still allow for programming. In this mode, the PGA309 output amplifier may be enabled for a set time period and then disabled again to allow sharing of the PRG pin with the VOUT connection. This allows for both digital calibration and analog readback during sensor calibration in a three-wire sensor module. The Two-Wire interface has timeout mechanisms to prevent bus lockup from occurring. The Two-Wire master controller in the PGA309 has a mode that attempts to free up a stuck-at-zero SDA line by issuing SCL pulses, even when the bus is not indicated as idle after a timeout period has expired. The timeout will only apply when the master portion of the PGA309 is attempting to initiate a Two-Wire communication. " #$% www.ti.com SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 DETAILED BLOCK DIAGRAM REFIN /REFOUT VSA 16 Linearization and VEXC Gain Adjust PGA309 V EXC Enable VEXC VSD POR x0.83 7−Bit + Sign Lin DAC Σ 1 10 VSA VFB x0 .1 66 VEXC VSD 3 VREF Internal Set (2.5V or 4.096V) x0 .1 24 VREF x0.52 Bandgap Reference VSA ITEMP 7µA VREF ITEMP Enable TEMPIN 15 Internal Temp Sense Temp ADC Internal REF Temp ADC Ref Mux VSA TEMPIN VREF Internal Set (2.5V or 4.096V) RSET VREFT VREF Temp ADC Input Mux VEXC VEXC Temp ADC REF Select 15−Bit + Sign Temp ADC xG Digital Controls SDA VOUT 14 Temp ADC, PGA (x1, x2, x4, x8) Control Registers Alarm Register Temp Select Source Temp ADC Input Mux Select PGA Gain Select (1 of 8) Range of 4 to 128 (with PGA Diff Amp Gain = 4) Input Mux Control VREF Fine Offset Adjust 4−Bit + Sign DAC Fine Gain Adjust (16−Bit) 16−Bit Zero DAC V REF PRG 4R Auto Zero 5 A2 12 R Over−Scale Limit Front−End PGA Output RF PGA Diff Amp RG VINN VIN1 4 RF Auto Zero Input Mux Front End PGA A1 Auto Zero R A3 3−Bit DAC VREF 16−Bit VFB VOUT Gain DAC Output Amplifier R Scale Limiter VOUT 7 INT/EXT FB Select Fault Monitor Circuit Alarm Register Inputs TEST VFB RFO 6 Output Gain Select (1 of 7) Range of 2 to 9 9 SCL 13 Offset TC Adjust and Scan TC Adjust Look−Up Logic with Interpolation Algorithm Coarse Offset Adjust VINP VIN2 Interface and Control Circuitry RGO VREF 3−Bit DAC Test Logic Under−Scale Limit VSJ 8 2 GNDA 11 GNDD Figure 2. Detailed Block Diagram 17 PACKAGE OPTION ADDENDUM www.ti.com 5-Apr-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PGA309AIPWR ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PGA309AIPWRG4 ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PGA309AIPWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PGA309AIPWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PGA309AIPWR TSSOP PW 16 2500 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 PGA309AIPWT TSSOP PW 16 250 180.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA309AIPWR TSSOP PW 16 2500 346.0 346.0 29.0 PGA309AIPWT TSSOP PW 16 250 190.5 212.7 31.8 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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