LP62S161024 Series

LP62S161024 Series
Preliminary
16M BIT (1M x 16 / 2M x 8) LOW VOLTAGE CMOS SRAM
Document Title
16M BIT (1M x 16 / 2M x 8) LOW VOLTAGE CMOS SRAM
Revision History
Rev. No.
0.0
PRELIMINARY
History
Issue Date
Remark
Initial issue
November 20, 2014
Preliminary
(November, 2014, Version 0.0)
AMIC Technology, Corp.
LP62S161024 Series
Preliminary
16M BIT (1M x 16 / 2M x 8) LOW VOLTAGE CMOS SRAM
Features
General Description
„ Operating voltage: 2.7V to 3.6V
„ Access times: 55/70 ns (max.)
„ Current:
Very low power version: Operating: 50mA (max.)
Standby:
20μA (max.)
„ Full static operation, no clock or refreshing required
„ All inputs and outputs are directly TTL-compatible
„ Common I/O using three-state output
„ Data retention voltage: 2.0V (min.)
„ Available in 48-pin TSOP (I) and 48-ball CSP (6 x 8 mm)
packages
„ All Pb-free (Lead-free) products are RoHS2.0 compliant
„ The TSOP (I) package configurable as 1M x 16 or 2M x 8
Static RAM
- BYTE fixed to HIGH, LB controlled I/O0 - I/O7, HB
controlled I/O8 - I/O15
- BYTE fixed to LOW, I/O15 used as address pin, while
I/O8 - I/O14 pins not used
The LP62S161024 is a low operating current 16,777,216bit static random access memory organized as 1,048,576
words by 16 bits and operates on low power voltage from
2.7V to 3.6V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2.0V.
Product Family
Power Dissipation
Product
Family
Operating
Temperature
VCC
Range
Speed
Data Retention
(ICCDR, Typ.)
Standby
(ISB1, Typ.)
Operating
(ICC2, Typ.)
LP62S161024
0°C ~ +70°C
2.7V~3.6V
55ns / 70ns
0.3μA
0.5μA
4mA
LP62S161024(I)
-40°C ~ +85°C
2.7V~3.6V
55ns / 70ns
0.3μA
0.5μA
4mA
Package
Type
48 TSOP (I)
48-ball CSP
48 TSOP (I)
48-ball CSP
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
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AMIC Technology, Corp.
LP62S161024 Series
Pin Configurations
„ TSOP (I)
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CS2
NC
HB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
LP62S161024V
A16
BYTE
GND
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CS1
A0
„ CSP (Chip Size Package)
48-pin Top View
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
CS2
B
I/O8
HB
A3
A4
CS1
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
GND
I/O11
A17
A7
I/O3
VCC
E
VCC
I/O12
NC
A16
I/O4
GND
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
A19
A12
A13
WE
I/O7
H
A18
A8
A9
A10
A11
NC
Note:
The BYTE pin in the 48-pin TSOP (I) package must be tied HIGH to use the device as a 1M x 16 SRAM. The 48-pin TSOP (I)
package can also be used as a 2M x 8 SRAM by tied the BYTE signal LOW. In the 2M x 8 configuration, pin 45 is A20, while
HB , LB and I/O8 to I/O14 pins are not used (NC).
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AMIC Technology, Corp.
LP62S161024 Series
Block Diagram
VCC
A0
GND
1M X 16 / 2M X 8
DECODER
MEMORY ARRAY
A18
A19
I/O0
I/O8
INPUT
COLUMN I/O
INPUT
DATA
CIRCUIT
DATA
CIRCUIT
I/O15/A20
I/O7
LB
CS1
CS2
LB
HB
OE
WE
BYTE
PRELIMINARY
CONTROL
CIRCUIT
(November, 2014, Version 0.0)
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AMIC Technology, Corp.
LP62S161024 Series
Pin Descriptions
Symbol
Description
Symbol
Description
Higher Byte Enable Input
(I/O8 - I/O15)
A0 – A19
Address Inputs
(Word Mode)
HB
A0 – A20
Address Inputs
(Byte Mode)
BYTE
CS1 , CS2
Chip Enable
OE
Output Enable
I/O1 - I/O16
Data Input/Output
VCC
Power Supply
WE
Write Enable Input
GND
Ground
LB
Byte Enable Input
(I/O0 - I/O7)
NC
Byte Enable
No Connection
Recommended DC Operating Conditions
(TA = 0°C to +70°C or -40°C to +85°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.7
3
3.6
V
0
0
0
V
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
2.2
-
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
-
+0.6
V
CL
Output Load
-
-
30
pF
TTL
Output Load
-
-
1
-
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AMIC Technology, Corp.
LP62S161024 Series
Absolute Maximum Ratings*
*Comments
VCC to GND .............................................. -0.5V to +4.0V
IN, IN/OUT Volt to GND................... -0.5V to VCC + 0.5V
Operating Temperature, Topr ...........................................
........................................0°C to +70°C or -40°C to +85°C
Storage Temperature, Tstg.....................-55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended.
Exposure to the absolute
maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics (TA = 0°C to +70°C or -40°C to +85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol
Parameter
LP62S161024-55/70LL(I)
Min.
Max.
Unit
⏐ILI⏐
Input Leakage Current
-
1
μA
⏐ILO⏐
Output Leakage Current
-
1
μA
Conditions
VIN = GND to VCC
CS1 = VIH or CS2 = VIL or
LB = HB = VIH
VI/O = GND to VCC
ICC
Active Power Supply
Current
-
5
mA
CS1 = VIL , CS2 = VIH ,
LB = VIL or HB = VIL , II/O = 0mA
Min. Cycle, Duty = 100%, CS1 = VIL ,
ICC1
-
50
mA
CS2 = VIH , LB = VIL or HB = VIL
II/O = 0mA
Dynamic Operating
Current
CS1 ≤ 0.2V , CS2 ≥ VCC-0.2V ,
ICC2
-
8
mA
LB ≤ 0.2V or HB ≤ 0.2V
f = 1MHz , II/O = 0mA
CS1 = VIH or CS2 = VIL or
ISB
-
1
mA
-
20
μA
Standby Current
LB = HB = VIH
CS1 ≥ VCC - 0.2V or CS2 ≤ 0.2V or
ISB1
LB = HB ≥ VCC-0.2V
VIN ≥ VCC-0.2V or VIN ≤ 0.2V
VOL
Output Low Voltage
-
0.4
V
IOL = 2.1 mA
VOH
Output High Voltage
2.2
-
V
IOH = -1.0 mA
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AMIC Technology, Corp.
LP62S161024 Series
Truth Table
I/O0 to I/O7 Mode
I/O8 to I/O15 Mode
VCC Current
CS1
CS2
OE
WE
LB
HB
H
X
X
X
X
X
High - Z
High - Z
ISB1, ISB
X
L
X
X
X
X
High - Z
High - Z
ISB1, ISB
X
X
X
X
H
H
High - Z
High - Z
ISB1, ISB
L
L
Read
Read
ICC1, ICC2, ICC
L
H
Read
High - Z
ICC1, ICC2, ICC
H
L
High - Z
Read
ICC1, ICC2, ICC
L
L
Write
Write
ICC1, ICC2, ICC
L
H
Write
High - Z
ICC1, ICC2, ICC
H
L
High - Z
Write
ICC1, ICC2, ICC
L
H
L
H
L
X
H
L
L
H
H
H
L
X
High - Z
High - Z
ICC1, ICC2, ICC
L
H
H
H
X
L
High - Z
High - Z
ICC1, ICC2, ICC
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CIN*
Input Capacitance
6
pF
VIN = 0V
CI/O*
Input/Output Capacitance
8
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
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AMIC Technology, Corp.
LP62S161024 Series
AC Characteristics (TA = 0°C to +70°C or -40°C to +85°C, VCC = 2.7V to 3.6V)
Symbol
Parameter
LP62S161024-55LL(I)
LP62S161024-70LL(I)
Unit
Max.
Min.
Min.
Max.
55
-
70
-
ns
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
-
55
-
70
ns
tAcs1 , tAcs2
Chip Enable Access Time
-
55
-
70
ns
tBE
Byte Enable Access Time
-
55
-
70
ns
tOE
Output Enable to Output Valid
-
25
-
35
ns
tCLZ1 , tCLZ2
Chip Enable to Output in Low Z
10
-
10
-
ns
tBLZ
Byte Enable to Output in Low Z
10
-
10
-
ns
tOLZ
Output Enable to Output in Low Z
5
-
5
-
ns
tCHZ1 , tCHZ2
Chip Disable to Output in High Z
-
20
-
25
ns
tBHZ
Byte Disable to Output in High Z
-
20
-
25
ns
tOHZ
Output Disable to Output in High Z
-
20
-
25
ns
tOH
Output Hold from Address Change
5
-
5
-
ns
Write Cycle Time
55
-
70
-
ns
tCW1 , tCW2
Chip Enable to End of Write
50
-
60
-
ns
tBW
Byte Enable to End of Write
50
-
60
-
ns
tAS
Address Setup Time
0
-
0
-
ns
tAW
Address Valid to End of Write
50
-
60
-
ns
tWP
Write Pulse Width
40
-
50
-
ns
tWR
Write Recovery Time
0
-
0
-
ns
tWHZ
Write to Output in High Z
-
25
-
25
ns
tDW
Data to Write Time Overlap
25
-
30
-
ns
tDH
Data Hold from Write Time
0
-
0
-
ns
tOW
Output Active from End of Write
5
-
5
-
ns
Write Cycle
tWC
Note: tCLZ1 , tCLZ2 , tBLZ , tOLZ , tCHZ1, tCHZ2 , tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open
circuit condition and are not referred to output voltage levels.
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AMIC Technology, Corp.
LP62S161024 Series
Timing Waveforms
Read Cycle 1(1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 2(1, 2, 3)
tRC
Address
tAA
CS1
CS2
tACS1 , tACS2
tCHZ1 , tCHZ2
tCLZ1 , tCLZ2
tBE
HB, LB
tBLZ5
tBHZ5
OE
tOHZ5
tOE
tOLZ5
DOUT
Notes:
1. WE is high for Read Cycle.
2. Device is continuously enabled CS1 = VIL, or CS2 = VIH , HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CS1 and ( HB and, or LB ) transition low or CS2 transition High.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
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AMIC Technology, Corp.
LP62S161024 Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
tWC
Address
tWR3
tAW
tCW
CS1
CS2
tBW
HB, LB
tAS1
tWP2
WE
tDW
tDH
DATA IN
tWHZ4
tOW
DATA OUT
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AMIC Technology, Corp.
LP62S161024 Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
tAW
tAS1
tWR3
tCW1 , tCW2
CS1
CS2
tBW
HB, LB
tWP
WE
tDW
tDH
DATA IN
tWHZ4
tOW
DATA OUT
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AMIC Technology, Corp.
LP62S161024 Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
tWC
Address
tAW
tCW1 , tCW2
CS1
tAS1
tWR3
tBW2
CS2
HB, LB
tWP
WE
tDW
tDH
DATA IN
tWHZ4
tOW
DATA OUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CS1 , WE and ( HB and , or LB ) or a high CS2.
3. tWR is measured from the earliest of CS1 or WE or ( HB and , or LB ) going high or CS2 going Low to the end of the
Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
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AMIC Technology, Corp.
LP62S161024 Series
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
Input Rise And Fall Time
5 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 1 and 2
TTL
TTL
CL
CL
5pF
30pF
* Including scope and jig.
* Including scope and jig.
Figure 2. Output Load for tCLZ1, tCLZ2 , tBHZ , tBLZ ,
tOLZ, tCHZ1, tCHZ2 , tOHZ, tWHZ, and tOW
Figure 1. Output Load
Data Retention Characteristics (TA = 0°C to +70°C or -40°C to 85°C)
Symbol
VDR
Parameter
VCC for Data Retention
Min.
Max.
Unit
2.0
3.6
V
Conditions
CS1 ≥ VCC - 0.2V or
CS2 ≤ 0.2V or
LB = HB ≥ VCC-0.2V
VCC = 2.0V,
ICCDR
Data Retention Current
-
6*
μA
tCDR
Chip Disable to Data Retention Time
0
-
ns
tRC
-
ns
5
-
ms
tR
Operation Recovery Time
tVR
VCC Rising Time from Data Retention
Voltage to Operating Voltage
* LP62S161024-55/70LL(I)
PRELIMINARY
ICCDR: max.
CS1 ≥ VCC - 0.2V or
CS2 ≤ 0.2V or
LB = HB ≥ VCC-0.2V
VIN ≥ VCC-0.2V or VIN ≤ 0.2V
See Retention Waveform
1μA at TA = 25°C
(3μA at TA = 0°C to +40°C )
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AMIC Technology, Corp.
LP62S161024 Series
Low VCC Data Retention Waveform (1) ( CS1 Controlled)
DATA RETENTION MODE
VCC
2.7V
2.7V
tCDR
tR
VDR ≥ 2.0V
tVR
VIH
CS1
VIH
CS1 ≥ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CS2 Controlled)
DATA RETENTION MODE
VCC
2.7V
2.7V
tCDR
tR
VDR ≥ 2.0V
tVR
CS2
VIL
VIL
CS2 ≤ 0.2V
Ordering Information
Part No.
Access Time(ns)
Operating Current
Max.(mA)
Standby Current
Max.(uA)
55
50
20
LP62S161024V-55LL(I)F
48L Pb-Free TSOP (I)
LP62S161024U-55LL(I)F
48L Pb-Free CSP
LP62S161024V-70LL(I)F
48L Pb-Free TSOP (I)
70
50
LP62S161024U-70LL(I)F
PRELIMINARY
Package
(November, 2014, Version 0.0)
20
48L Pb-Free CSP
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AMIC Technology, Corp.
LP62S161024 Series
Package Information
TSOP 48L (Type I) Outline Dimensions
unit: inches/mm
1
48
24
25
y
D1
A1
A2 A
D
0.25
c
S
e
E
b
D
Detail "A"
L
θ
Detail "A"
Symbol
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.042
0.94
1.00
1.06
b
0.007
0.009
0.011
0.18
0.22
0.27
c
0.004
-
0.008
0.12
-
0.20
D
0.779
0.787
0.795
19.80
20.00
20.20
D1
0.720
0.724
0.728
18.30
18.40
18.50
E
-
0.472
0.476
-
12.00
12.10
e
L
0.020 BASIC
0.020
S
0.024
0.50 BASIC
0.0275
0.50
0.011 Typ.
0.60
0.70
0.28 Typ.
y
-
-
0.004
-
-
0.10
θ
0°
-
8°
0°
-
8°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
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AMIC Technology, Corp.
LP62S161024 Series
Package Information
48LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
(48TFBGA)
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
0.10 S C
0.25 S C A B
Ball*A1 CORNER
b (48X)
6 5 4 3 2 1
1 2 3 4 5 6
A
B
C
D
E
E1
e
A
B
C
D
E
F
G
E
F
G
H
H
B
A
0.10 C
SIDE VIEW
D
0.20(4X)
Symbol
A
A1
D
E
D1
E1
e
b
A
SEATING PLANE
A1
C
e
D1
Dimensions in mm
MIN.
NOM.
MAX.
--0.20
5.90
7.90
------0.30
--0.25
6.00
8.00
3.75
5.25
0.75
0.35
1.20
0.30
6.10
8.10
------0.40
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS
OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE
SOLDER BALL AND THE BODY EDGE.
4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD)
PRELIMINARY
(November, 2014, Version 0.0)
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AMIC Technology, Corp.