HD32/42 ADP SRAM I o 5 Volt x8 Asynchronous Dual-Port Static RAM Memory Configuration Mode Device 2K x 8 Master HD32L 2K x 8 Slave HD42L Key Features: • • • • • • • • • • • Industry leading asynchronous Dual-Port Static RAM (up to 15ns) Simultaneous memory access through two ports TTL compatible; 5V power supply Supports Interrupt arbitration schemes Bus Width can easily expand to over 16 bits by using both MASTER and SLAVE HD32 with on-chip port arbitration logic BUSY output flag on HD32; BUSY input flag on HD42 Available packages: 52 – pin Plastic Lead Chip Carrier (PLCC) (0°C to 70°C) Commercial operating temperature available for access time of 15ns and above (-40°C to 85°C) Industrial operating temperature available for access time of 25ns Pin-to-pin compatible with conventional dual-port devices including IDT 7132, 7142 and Cypress CY7C136 CY7C146 Product Description: HBA’s Asynchronous Dual-Port (ADP I) Static RAM offers industry leading 0.25um process technology and 2K x 8 memory configuration. Both devices support two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access to any location in memory. System designer has full flexibility of implementing deeper and wider memory using the depth and width expansion features. The HD32 is a stand alone 16K-bit Dual-Port Static RAM or as a “MASTER” Dual-Port Static RAM with HD42 as a “SLAVE” Dual-Port Static RAM in 16-bit-or-more bus width application. No additional discrete logic is required when using the MASTER/SLAVE configuration to provide bus width expansion. These devices have low power consumption, hence minimizing system power requirements. They are ideal for applications such as data communication, telecommunication, multiprocessing, test equipment, network switching, etc. 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 1 of 14 HD32/42 ADP SRAM I Block Diagram of Asynchronous D ual Port Static R AM 2K X 8 OE L OE R CE L CE R R /W L R /W R I/O 0-7 L I/O Control I/O 0-7 R I/O Control (1,2) BUSY L A1 0 L A0 L BUSY R Address Decoder OE L CE L R /W L Address Decoder SRAM Arbitration and Interrupt Logic (1,2) A 10 R A0 R OE R CE R R / WR NOTES: 1. 2. __________ __________ HD32 MASTER mode: BUSY is open drain. HD42 SLAVE mode: BUSY is input Open drain output: requires pull-up resistor of 270Ω Figure 1. Device Architecture 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 2 of 14 HD32/42 7 A1L A2L A3L A4L 8 6 5 4 3 2 52 51 50 49 NC A10R BUSYR VCC CER R/WR BUSYL R/WL CEL Index OEL A10L NC A0L ADP SRAM I 48 47 1 46 9 45 10 44 11 43 A5L A6L A7L 12 42 13 41 14 40 A8L A9L I/O0L I/O1L 15 39 16 38 17 37 18 36 I/O2L I/O3L 19 35 20 34 25 26 27 28 29 30 31 32 A3R A4R A5R A6R A7R A8R A9R NC I/O7R 33 I/O4R I/O5R I/O6R 24 I/O1R I/O2R I/O3R 23 NC GND I/O0R I/O4L 22 I/O5L I/O6L I/O7L 21 OER A0R A1R A2R PLCC – 52 (Drw No: J-02A; Order code: J) Top View Figure 2. Device Pin-Out 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 3 of 14 HD32/42 ADP SRAM I Left Port Right Port _____ Name _____ CEL CER Chip Enable R/WL R/WR Read / Write Enable ____ ____ __________ __________ BUSYL BUSYR Busy Flag OEL OER Output Enable A0L-10L A0R-10R Address I/O0L-7R I/O0R –7R Data Inputs/Outputs _____ _____ Vcc Power GND Ground Symbol Rating Com & Ind Unit VTERM Terminal Voltage with respect to GND -0.5 to + 7.0 V TBIAS Temperature Under Bias -55 to +125 ° C TSTG Storage Temperature -65 to +150 ° C IOUT DC Output Current 50 mA NOTES: Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions. Table 1. Pin Descriptions Table 2. Absolute Maximum Ratings Symbol Parameter Commercial Temperature Industrial Temperature Min. Typ. Max. Min. Typ. Max. 4.5 5.0 5.5 4.5 5.0 5.5 V 0 0 0 0 0 0 V - 6.0 2.2 - 6.0 V Unit Recommended Operating Conditions VCC Supply Voltage Com’l/Ind’l GND Supply Voltage VIH VIL TA Input High Voltage Com’l/Ind’l 2.2 Input Low Voltage Com’l/Ind’l -0.5 - 0.8 -0.5 - 0.8 V 0 - 70 -40 - 85 ° - - 10 - - 10 µA Operating Temperature C DC Electrical Characteristics ILI(1) ILO VOH VOL Input Leakage Current (any input) - - 10 - - 10 µA Output Logic “1” Voltage, IOH=-4mA 2.4 - - 2.4 - - V Output Logic “0” Voltage, IOL = 4mA - - 0.4 - - 0.4 V Output Leakage Current Capacitance at 1.0MHz Ambient Temperature (25°C) Symbol Parameter Input Capacitance CIN(2) (2) Output Capacitance COUT Conditions(3) VIN= 3dV VOUT= 3dV Max. 11 11 Unit pF pF NOTES: 1. At Vcc < 2.0V, input leakage is undefined. 2. This parameter is determined by device characterization but is not production tested. 3. 3dV represents the interpolated capacitance when input and output signals switch from 0V to 3V or from 3V to 0V. 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 4 of 14 HD32/42 ADP SRAM I Power Consumption Symbol Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports – TTL Level Inputs) ICC ISB1 Conditions _____ CE = VIL, Outputs Disabled, f=fMAX _____ _____ CEL = CER = VIH, f=fMAX _____ Temp HD32L15 HD42L15 HD32L25 HD42L25 Typ. Max. Typ. Max. C 110 190 110 170 I - - C 30 45 30 45 I - - C 65 135 65 115 I - - C 0.2 5 0.2 5 I - - C 60 125 I - - Unit mA mA _____ ISB2 Standby Current (One Port – TTL Level Inputs) CEA = VIL and CEB = VIH Active Port Outputs Disabled, f=fMAX ISB3 Full Standby Current (Both Ports – All CMOS Level Inputs) Both Ports CEL and CER > Vcc – 0.2V, VIN > Vcc – 0.2V or VIN < 0.2V, f = 0 ISB4 Standby Current (One Port – All CMOS Level Inputs) _____ _____ _____ mA mA _____ CEA < 0.2V and CEB > Vcc – 0.2V, Active Port Outputs Disabled, f=fMAX 60 105 mA Power Consumption Symbol Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports – TTL Level Inputs) ICC ISB1 Conditions _____ CE = VIL, Outputs Disabled, f=fMAX _____ _____ CEL = CER = VIH, f=fMAX _____ HD32L35 HD42L35 HD32L55 HD42L55 Typ. Max. Typ. Max. C 80 120 65 90 I - - - - C 25 45 20 35 I - - - - C 50 90 40 75 I - - - - C 0.2 4 0.2 4 I - - - - C 45 85 40 70 I - - - - Unit mA mA _____ ISB2 Standby Current (One Port – TTL Level Inputs) CEA = VIL and CEB = VIH Active Port Outputs Disabled, f=fMAX ISB3 Full Standby Current (Both Ports – All CMOS Level Inputs) Both Ports CEL and CER > Vcc – 0.2V, VIN > Vcc – 0.2V or VIN < 0.2V, f = 0 ISB4 Standby Current (One Port – All CMOS Level Inputs) _____ _____ Temp _____ mA mA _____ CEA < 0.2V and CEB > Vcc – 0.2V, Active Port Outputs Disabled, f=fMAX mA NOTES: 1. 2. 3. 4. At f=fMAX, address and control lines, except Output Enable, are cycling at the maximum frequency read cycle of 1/trc, and using AC Test Conditions of input level of GND to 3V. f = 0 means no address or control lines change. Vcc = 5V, tA = +25C for Typ and is not production tested. Vcc dc = 100mA (Typ) Port A and B can be either left or right port. If Port A is left port, Port B is right port. If Port A is right port, Port B is left port. 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 5 of 14 HD32/42 ADP SRAM I HD32L15 HD42L15 Symbol Parameter Commercial & Industrial HD32L25 HD32L35 HD42L25 HD42L35 HD32L55 HD42L55 Min. Max. Min. Max. Min. Max. Min. Max. Unit 15 - 25 - 35 - 55 - ns Read Cycle tRC Read Cycle Time tAA Address Access Time - 15 - 25 - 35 - 55 ns tACE Chip Enable Access Time - 15 - 25 - 35 - 55 ns tABE Byte Enable Access Time - 15 - 25 - 35 - 55 ns tAOE Output Enable Access Time - 10 - 12 - 20 - 25 ns tOH Output Hold from Address Change 3 - 3 - 3 - 3 - ns 0 - 0 - 0 - 5 - ns - 10 - 10 - 15 - 25 ns 0 - 0 - 0 - 0 - ns - 15 - 25 - 35 - 50 ns tLZ tHZ tPU Output Low-Z Time (1,2) Output High-Z Time (1,2) Chip Enable to Power Up Time tPD (2) Chip Disable to Power Down Time (2) Write Cycle tWC Write Cycle Time 15 - 25 - 35 - 55 - ns tEW Chip Enable to End-of-Write 12 - 20 - 30 - 40 - ns tAW Address Valid to End-of-Write 12 - 20 - 30 - 40 - ns tAS Address Set-up Time 0 - 0 - 0 - 0 - ns tWP Write Pulse Width (4) 12 - 15 - 25 - 30 - ns tWR Write Recovery Time 0 - 0 - 0 - 0 - ns tDW Data Valid to End-of-Write 10 - 12 - 15 - 20 - ns tHZ Output High-Z Time (1,2,3) - 10 - 10 - 15 - 25 ns tDH Data Hold Time tWZ tOW 0 - 0 - 0 - 0 - ns Write Enable to Output in High-Z (1,3) - 10 - 10 - 15 - 30 ns Output Active from End-of-Write (1,2,3) 0 - 0 - 0 - 0 - ns NOTES: 1. 2. 3. Transition is measured 500mV from Low or High-impedance voltage Output Test Load This parameter is guaranteed by device characterization, but is not production tested. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA. 4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be ______ ____ ______ ____ placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Table 3. AC Electrical Characteristics 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 6 of 14 HD32/42 ADP SRAM I HD32L15 HD42L15 Symbol Parameter Commercial & Industrial HD32L25 HD32L35 HD42L25 HD42L35 HD32L55 HD42L55 Min Max. Min Max. Min. Max. Min. Max. Unit ___________ BUSY Timing (for MASTER) tBAA BUSY Access Time from Address __________ - 15 - 20 - 20 - 30 ns tBDA BUSY Disable Time from Address __________ - 15 - 20 - 20 - 30 ns tBAC __________ BUSY Access Time from Chip Enable - 15 - 20 - 20 - 30 ns tBDC __________ BUSY Disable Time from Chip Enable - 15 - 20 - 20 - 30 ns tWH Write Hold after BUSY 12 - 15 - 20 - 20 - ns tWDD Write Pulse to Data Delay - 30 - 50 - 60 - 80 ns tDOD Write Data Valid to Read Data Delay - 25 - 35 - 35 - 55 ns tAPS Arbitration Priority Set-up Time 5 - 5 - 5 - 5 - ns tBDD __________ - 15 - 25 - 35 - 50 ns 0 - 0 - 0 - 0 - ns 12 - 15 - 20 - 20 - ns __________ BUSY Disable to Valid Data ___________ BUSY Timing (for SLAVE) __________ tWB BUSY Input to Write __________ tWH Write Hold after BUSY tWDD Write Pulse to Data Delay - 30 - 50 - 60 - 80 ns tDDD Write Data Valid to Read Data Delay - 25 - 35 - 45 - 55 ns Table 3. AC Electrical Characteristics (Continued) Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Test Load Refer to Figure 3, 4, and 5 NOTES: 1. Include jig and scope capacitances Table 4. AC Test Condition 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 7 of 14 HD32/42 ADP SRAM I 5V 5V 5V 1250 Ω 1250Ω D.U.T. 1250Ω D.U.T. 30pF 775Ω BUSY 5pF* 775Ω Figure 3. AC Output Test Load *100pF for 55ns versions 30pF* Figure 4. Output Test Load for tLZ, tHZ, tWZ, tOW *Includes jig and scope capacitances. Figure 5. BUSY AC Output Test Load Left or Right Port ____ Mode ______ ______ OE X D0-7 Z Port Disabled and in Power-Down Mode, ISB2 or ISB4 X H X Z CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3 L L X Data In Data on Port Written Intro Memory (2) H L L Data Out Data in Memory Output on Port (3) X L H Z High Impedance Outputs R/W X CE H NOTES: 1. 2. 3. 4. A0L-15L ≠ A0R-15R. ___________ If BUSY = L, data is not written ___________ If BUSY = L, data may not be valid, see tWDD and tDDD timing H = VIH, L = VIL, X = Don’t Care, Z = High Impedance Table 5. Truth Table – Non-Contention Read/Write Control Inputs ______ CE L X 2. 3. Outputs __________ A10-0 __________ Function No Match BUSY L(1) H BUSY R(1) H X Match H H Normal H Match H H Normal L Match (2) (2) Write Inhibit(3) CE R X H X L NOTES: 1. ______ __________ Normal __________ __________ When part is configured as master, BUSYL and BUSYR are both outputs. When configured as slave, both are inputs and internally inhibits writes. BUSY outputs are push-pull, not open drain. If inputs to opposite port were stable prior to address and enable inputs of this port, then “L.” If inputs to the opposite port became stable after the address the enable inputs __________ __________ __________ __________ of port, then “H.” If tAPS is not met, then either BUSYL or BUSYR = LOW. BUSYL and BUSYR cannot be LOW simultaneously __________ Writes to one port are internally ignored when its BUSY outputs are LOW regardless of actual logic level on the pin. __________ Table 6. Truth Table – Address BUSY Arbitration 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 8 of 14 HD32/42 ADP SRAM I Timing Diagrams tRC ADDR t AA t ACE (4) CE t AOE (4) OE R/W t OH t LZ (1) Data Out Valid Data (4) t HZ (2) BUSYOut t BDD (3,4) NOTES: ______ ______ 1. tLZ timing is based on which signal is asserted last, C E______ ,OE______ ,. 2. tHZ timing is based on which signal is de-asserted first, C E ,OE . _________ 3. tBDD is needed only where the opposite port is completing a write operation to the same address. BUSY has no effect on valid output data. 4. Valid data starts from the last of tAOE, tACE, tAA or tBDD. Diagram 1. Read Cycles 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 9 of 14 HD32/42 ADP SRAM I tWC ADD R t HZ ( 7 ) OE t HZ t AW (7 ) CE t A S (6 ) tWP t W R (3 ) (2 ) R/W tWZ D ata Out t OW (4) (4) t DH t DW D ata In ____ Diagram 2. Write Cycle No. 1, R/W Controlled Timing tWC AD DR tAW CE t AS(6) t W R(3) t EW (2) R /W t DW t DH D ata In NOTES: ____ ______ 1. R/W or C E must be ______ HIGH during all ____ address transitions. R/W = ____ VIL for memory write cycle. 2. A write occurs when C E = VIL and ______ 3. tWR timing is from the earlier of C E or R/W going HIGH to the end of write cycle. 4. The ______ I/O pins are in the output state and input signals must not be applied during DATA out period. ____ with or after the R/W = VIL transition, the outputs remain in the high-impedance state. 5. For C E =VIL transition simultaneously ______ ____ 6. tAS timing is based on latter of C E or R/W . is measured 0mV from steady state with the Output Test Load. 7. tHZ transition _____ ____ =VIL during R/W write cycle, the write pulse width is the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required 8. For OE _____ ____ tDW. If OE = VIH during an R/W controlled writing cycle, the write pulse is specified as tWP. _____ Diagram 3. Write Cycle No. 2, CE Controlled Timing 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 10 of 14 HD32/42 ADP SRAM I tWC AD DR A M atch tWP R /W A t DW tDH Data In A Valid t AP S(1 ) M atch AD D R B t BAA t BDA BUSY B t W DD Valid D ata OutB t D DD NOTES: t BD D (3) ___ 1. _____ tAPS is_____ ignored for SLAVE part (M/S = VIL) L =CER = VIH. 2. CE _____ port. ___________ 3. OE = VIL for the reading ___ 4. For SLAVE mode (M/S = VIL), BUSY is an input. 5. Timing for both ports is the same. Port B is opposite of port A. ___________ __ Diagram 4. Write with Port-to-Port Read and BUSY (M/S = VIH) tWP R/WA t W B (2 ) t W H (2 ) BUSYB R/WB NOTES: ___________ (2) ___________ 1. ___________ SLAVE (BUSY input) and MASTER (BUSY output) must meet tWH. ____ ___________ 2. BUSY is sent to port B blocking R/W B till BUSYB=VIH. 3. tWB is for SLAVE mode. ___________ __ Diagram 5. Write with BUSY (M/S = VIL) 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 11 of 14 HD32/42 ADP SRAM I ADDRA and ADDRB Addresses Match CE A t APS CE B t BAC t BDC BUSYB ___________ _____ __ Diagram 6. BUSY Arbitration Controlled by CE Timing (M/S = VIH) ADDRA Addresses N t APS (1) ADDRB Matching Addresses N t BAA t BDA BUSYB NOTES: ___________ 1. If tAPS is not satisfied, the BUSY signal will be asserted randomly on one side or the other. ___________ __ Diagram 7. BUSY Arbitration Controlled by Address Match Timing (M/S = VIH) 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 12 of 14 HD32/42 ADP SRAM I Functional Description HD32/42 supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access to any location in memory. Busy Logic When both ports attempt to access the same memory location at the same time, data corruption can potentially occur. In the case of HD32, the on-chip Busy Logic arbitrates simultaneous accesses to the same memory location, and determines the __________ “winner” between the two ports. If Busy Logic considers the right port lost in the arbitration, then the right port B U S Y pin is set active (LOW) to signal the system that this memory location is “busy” being accessed by the other port. Furthermore, the Busy __________ Logic prevents the right port from writing to the same memory location for as long as the right port B U S Y signal stays active (LOW). Once the left port finishes access to this memory location, the dual-port SRAM signals the system by setting the right __________ port B U S Y pin back to inactive (HIGH), so that the system can resume its normal access from the right port. Note that only the write operation from the losing port is inhibited; the read operation is nondestructive and can thus continue regardless of the arbitration result. __________ The B U S Y pins are output pins for HD32, but become input pins instead for HD42. There is no on-chip arbitration __________ logic for HD42, and the device relies on the input B__________ U S Y signals for the results of arbitration when simultaneous access to the same memory location occurs. Specifically, when a B U S Y pin is set to HIGH, normal operation can be performed from this port, ___________ but when a B U S Y pin is set to LOW, write operations will be inhibited from this port. If width expansion with multiple HBA __________ HD32/42 devices is used, it is recommended that only one of them be HD32,__________ and the rest of them HD42. The B U S Y (output) signal from the master device (HD32) should be connected to the respective B U S Y (input) pins of the slave devices (HD42). This means that only one device (the master) is performing the Busy Logic arbitration, and all the other devices (the slaves) will follow this arbitration accordingly. This can prevent the conflicts caused by the potential inconsistent arbitration results from different dual-port SRAM devices. The Busy arbitration logic is triggered whenever the two ports simultaneously attempt to access the same memory location, where____ data accesses are determined by the timings and values of the Address and Chip Enable signals only, not by the value of the R/ W signal. This means that both read and write operations can trigger the Busy Logic, even though only the write operation is inhibited from the losing port. Note that in a master/slave configuration, an additional timing constraint concerning ____ the R/ W signal needs to be met in order to prevent data corruption in the__________ slave device: the write operation in the slave device __________ cannot start before the B U S Y signal –____ which originates from the output B U S Y pin – is received by the slave device to ensure write inhibition. In other words, the R/ W signal needs to stay high from the time__________ the Busy Logic on the master device is triggered (through the changing of the Address and Chip Enable signals) till the B U S Y signal is received by the slave device. 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 13 of 14 HD32/42 ADP SRAM I Order Information: HBA Device Family Device Type Power Speed (ns)* Package** Temperature Range XX HD XXX 32 (2K x 8) X Low XX 15 XX J X Blank – Commercial (0°C to 70°C) 42 (2K x 8) 25 I – Industrial (-40° to 85°C) † 35 55 *Speed – Slower speeds available upon request. **Package –52 pin Plastic Lead Chip Carrier (PLCC) † Temperature – Industrial only offered in 25ns Example: HD32L15J (2K x 8, 15ns, Commercial temp) USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA Tel: 408.453.8885 Fax: 408.453.8886 www.hba.com Taiwan No. 81, Suite 8F-9, Shui-Lee Rd. Hsinchu, Taiwan, R.O.C. Tel: 886.3.516.9118 Fax: 886.3.516.9181 www.hba.com Europe CDE Technology B.V. Nijverheidslaan 28 1382 L J Weesp, The Netherlands Tel: 31.294.280.914 Fax: 31.294.280.919 www.hba.com 5HD086 A © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 14 of 14