HDV24VL ADP II o 2.8 Volt x16 Very Low Power Dual-Port Static RAM Memory Device 4K x 16 HDV24VL Key Features: • • • • • • • • Very low power true Dual-Port Static RAM with high speed access Simultaneous memory access through two ports LVTTL compatible; 2.8V power supply Bus Width can easily expand to over 16 bits by using both MASTER and SLAVE select function Interrupt, Semaphore, and Busy Logic Supports Interrupt and Semaphore arbitration schemes Available packages: 108 ball 8mmx8mm 0.5mm pitch BGA and 84 ball 7mmx7mm 0.5mm pitch BGA (-40°C to 85°C) Industrial operating temperature available for access time of 55ns Product Description: The HDV24VL Dual-Port Static RAM offers industry leading CMOS process technology and 4K x 16 memory configuration. The device supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access to any location in memory. System designer has full flexibility of implementing deeper and wider memory using the depth and width expansion features. The HDV24VL is a stand alone 4K x 16 Asynchronous Dual-Port SRAM. For 32 bits or more bus width, the MASTER/SLAVE pin offers bus width expansion without additional discrete logic. Bus width expansion can easily be done without external logic. The device has low power consumption, hence minimizing system power requirements. It is ideal for applications such as data communication, telecommunication, multiprocessing, test equipment, network switching, etc. 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 1 of 1 HDV24VL ADP II Block Diagram of Dual Port Static RAM 4K x 16 R/ W L R/ W R UB L UBR LB L CE L LBR OER OE L CE R I/O 8-15 L I/O 8-15 R I/O Control I/O Control I/O 0-7 L I/O 0-7 R (1) (1) BUSYL A 11L A0 L BUSYR Address Decoder CEL OEL SRAM Arbitration Interrupt Semaphore Logic R/ WL SEM Address Decoder A0R CE R OER R/W R SEM L INTF L A11 R (1) M/S R INTFR Figure 2. Device Architecture 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 2 of 2 HDV24VL ADP II 1 2 3 4 5 6 7 A I/O8R I/O7R NC I/O6R I/O4R I/O2R I/O1R B I/O9R C I/O11R GND VCC D VCC I/O10R E I/O13R VCC NC F I/O15R I/O14R I/O12R G R/WR OER GND 8 9 10 11 VCC I/O13L GND I/O10L 12 13 14 NC I/O 9L GND I/O7L I/O5R H GND GND SEMR J CE R UB R LB R K NC A11R A7R L A10R A9R M A8R NC N A6R P A5R A4R A2R I/O3R I/O0R I/O15L I/O12L NC VCC I/O8L I/O6L I/O5L I/O4L GND GND I/O14L I/O11L VCC GND VCC I/O3L I/O2L I/O1L OEL GND I/O0L VCC SEML R/WL LB L CEL VCC NC A11L UBL A9L NC A7L A10L HDV24VL BZ108 Top View A0R M/S GND BUSYR GND VCC A0L INTFL A2L A4L A8L NC A3R A1R INTFR NC GND NC BUSYL A1L A3L NC A5L A6L Top View Figure 3.108-Ball 0.5mm Pitch BGA (Order code: BZ) 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 3 of 3 HDV24VL ADP II NOTES: All VCC connect to power supply and all GND connect to ground supply. 84-Ball 0.5mm Pitch BGA( Order code: BY) Figure 4. Device Pin-O u t 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 4 of 4 HDV24VL ADP II Left Port Right Port _____ Name Symbol Rating Com & Ind Unit Chip Enable V TERM Terminal Voltage with respect to GND -0.5 to + 4.6 V TBIAS Temperature Under Bias -55 to +125 ° ° _____ CE L CE R ____ ____ R/W L R/WR _____ Read/Write Enable _____ OEL OER Output Enable A0L-11L A 0R-11R Address I/O 0-15L I/O 0-15R Data Inputs/ Output TSTG Storage Temperature -65 to +150 __________ __________ SEML S E MR Semaphore Enable IOUT DC Output Current -50 to +50 ______ ______ U BL U BR _____ C C mA Upper Byte Select _____ LBL LBR ________ Lower Byte Select NOTES: 1. Absolute Max Ratings are for reference only. Permanent damage to the device may occur if ________ INTFL INTFR __________ Interrupt Flag __________ BUSY L BUSYR extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions . Busy Flag ___ M /S Master or Slave Select VCC Power GND Ground 2. VTERM must not exceed VCC +0.3V for more than 25% of the cycle time or 10ns maximum , and is limited to <+ 20Ma for the period over VTERM =VDD+ 0.3V. Table 2. Absolute Maximum Ratings Table 1. Pin Descriptions Symbol Parameter Min. Typ. Max. Unit 2.6 2.8 3.0 V Recommended Operating Conditions VCC Supply Voltage GND Ground Voltage 0 0 0 V VIH VIL Input High Voltage 2.0 - Vcc+0.3 V Input Low Voltage -0.3 - 0.8 V TA(1) Operating Temperature Industrial -40 - 85 ° - - 10 µA - - 10 µA 2.0 - - V - - 0.4 V C DC Electrical Characteristics ILI(1) Input Leakage Current (VCC =2.8V, VIN=0V to VCC ) _____ ILO VOH VOL Output Leakage Current (CE =VIH, VOUT =0V to VCC ) Output Logic “1” Voltage, IOH=-4mA Output Logic “0” Voltage, IOL = 4mA Capacitance at 1.0MHz Ambient Temperature (25°C) Symbol Parameter CIN (2) COUT(2) Input Capacitance Output Capacitance Conditions Max. Unit VIN = 3dV 9 pF VOUT= 3dV 10 pF NOTES: 1. T A is the “instant on” case temperature. 2. CIN and COUT are determined by device characterization , not production tested. Table 3. Operating conditions 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 5 of 5 HDV24VL ADP II Power Consumption (Continued) Symbol ICC ISB1 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports – TTL Level Inputs) ISB2 Standby Current (One Port – TTL Level Inputs) ISB3 Full Standby Current (Both Ports – All CMOS Level Inputs) ISB4 Standby Current (One Port – All CMOS Level Inputs) Conditions Version HDV24VL55 Typ. Max. _____ CE = VIL ,________ Outputs Disabled, SEM = VIH , f=f MAX _____ Industrial VL 20 25 mA Industrial VL 5 10 mA Industrial VL 15 20 mA Industrial VL 0.2 0.3 mA Industrial VL 12 _____ CE L = CER = V IH , ________ ________ SEM R = SEM L = VIH , f=f MAX _____ _____ CEA = V IL and CEB = VIH Active Port Outputs Disabled, f=FMAX, ________ ________ SEM R = SEM L = VIH _____ Both Ports CEL and _____ CER > Vcc – 0.2V, VIN > Vcc – 0.2V or V IN < 0.2V, f = 0, ________ ________ SEM R = SEM L > Vcc – 0.2V _____ _____ CEA < 0.2V and CEB ________ > Vcc – 0.2V, SEM R ________ = SEM L > Vcc – 0.2V, Active Port Outputs Disabled, f=fMAX 15 mA 2.8 V Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels Unit 590Ω DATAOUT BUSY INTF 1.5V 2.8 V 590Ω DATAOUT 30pF* 435Ω Output Reference Levels 1.5V Output Load, clock = 15 ns Output Load (1), clock = 15ns, 20ns, 25ns, 30ns Refer to Figure 4 Refer to Figure 5 Figure 4. AC Test Load (for t LZ, tHZ, tWZ, tOW) 30pF* 435Ω Figure 5. Output Load (for t LZ, tHZ, tWZ, tOW) *Includes jig and scope capacitances. NOTES: 1. Include jig and scope capacitances Table 4. AC Test Conditions 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 6 of 6 HDV24VL ADP II 70V24VL55I Symbol Parameter Min. Max. Unit Read Cycle t RC Read Cycle Time 55 - MHz t AA Address Access Time - 55 ns t ACE Chip Enable Access Time - 55 ns t ABE Byte Enable Access Time - 55 ns t AOE Output Enable Access Time - 30 ns t OH Output Hold from A ddress Change 3 - ns t LZ Output Low-Z Time 3 - ns t HZ Output High-Z Time - 25 ns t PU Chip Enable to Power Up Time 0 - ns t PD Chip Disable to Power Down Time - 50 ns t SOP Semaphore Flag Update Pulse 15 - ns t SAA Semaphore Address Access Time - 55 ns Write Cycle t WC Write Cycle Time 55 - ns t EW Chip Enable to End-of-Write 45 - ns t AW Address Valid to End-of-Write 45 - ns t AS Address Set-up Time 0 - ns t WP Write Pulse Width 40 - ns t WR Write Recovery Time 0 - ns t DW Data Valid to End-of-Write 30 - ns t HZ Output High-Z Time - 25 ns t DH Data Hold Time 0 - ns tWZ Write Enable to Output in High-Z - 25 ns t OW Output Active from End-of-Write 0 - ns 5 - ns 5 - ns ns t SWRD t SPS ________ SEM Flag Write to Read T ime ________ SEM Flag Contention Window Interrupt Timing t AS Address Set-up Time 0 - t WR Write Recover Time 0 - t INS Interrupt Set Time - 40 ns t INR Interrupt Reset Time - 40 ns Table 5. AC Electrical Characteristics 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 7 of 7 HDV24VL ADP II Symbol Parameter Min Max. Unit - 45 MHz - 40 ns - 40 ns ___________ BUSY Timing (MASTER) t BAA __________ BUSY Access Time form Address Match __________ t BDA BUSY Disable Time from Address Not Matched __________ t BAC BUSY Access Time from Chip Enable Low __________ t BDC BUSY Access Time from Chip Enable High - 35 ns t APS Arbitration Priority Set-up Time 5 - ns - 40 ns 25 - ns 0 - ns 25 - ns t BDD t WH __________ BUSY Disable to Valid Data __________ Write Hold after BUSY ___________ BUSY Timing (SLAVE) t WB t WH __________ BUSY Input to Write __________ Write Hold after BUSY Port-to-Port Delay Timing t WDD Write Cycle Time - 80 ns t DOD Chip Enable to End-of-Write - 65 ns Table 4. AC Electrical Characteristics (Continued) 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 8 of 8 HDV24VL ADP II Inputs Outputs ______ ____ ______ ______ _____ _________ CE H R/W X OE X UB X LB X X X X H L L X L L L L L H L H L X Mode SEM H I/O 8-15 I/O 0-7 High-Z High-Z Deselected: Power-Down H H High-Z High-Z Both Bytes Deselected L H H DATA IN High-Z Write to Upper Byte Only X H L H High-Z DATA IN Write to Lower Byte Only X L L H DATA IN DATA IN Write to Both Bytes L L H H DATA OUT High-Z Read Upper Byte Only L H L H High-Z DATA OUT Read Lower Byte Only H L L L H DATA OUT DATA OUT Read Both Bytes X H X X X High-Z High-Z Outputs Disabled Table 6. Truth Table – Non-Contention Read/Write Control Inputs Outputs ______ ____ ______ ______ _____ _________ CE H R/W H OE L UB X LB X Mode SEM L I/O 8-15 I/O 0-7 DATA OUT DATA OUT Read Data in Semaphore Flag X H L H H L DATA OUT DATA OUT Read Data in Semaphore Flag H ↑ X X X L DATA IN DATA IN Write I/O into Semaphore Flag X ↑ X H H L DATA IN DATA IN Write I/O into Semaphore Flag L X X L X L - - Not Allowed L X X X L L - - Not Allowed NOTES: 1. Eight semaphore flags are addressed by A0-A2. Table 7. Truth Table – Semaphore Read/Write Control Left Port Right Port ____ ______ ______ R/W L CE L OE X A11-0 _______ FFF X X X X Mode ____ ______ ______ CE X OE X A11-0 X R/W X _______ X L Set Right INTF Flag X X L L FFF H Reset Right INTF Flag INTF INTF _______ _______ _______ X X X X L L L X FFE X Set Left INTF Flag X L L FFE H X X X X X Reset Left INTF Flag _______ NOTES: __________ 1. Assuming BUSY = VIH. __________ 2. If_______ BUSY = VIL, then no change. 3. INTF must be initialized at power-up. Table 8. Truth Table – Interrupt Flag 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 9 of 9 HDV24VL ADP II Inputs Outputs __________ Function ______ ______ CE L X CE R X No Match H X Match X H Match H H Normal L L Match (2) (2) Write Inhibit (3) A11-0 NOTES: BUSYL H (1) __________ BUSY R(1) H Normal H Normal H __________ __________ __________ 1. When part is configured as master, BUSY L and BUSY R are both outputs. When configured as slave, both are inputs and internally inhibits writes. BUSY outputs are pushpull, not open drain. 2. If inputs to opposite port were stable prior to address and enable inputs of this port, then “L.” If inputs to the opposite port became stable after the address the enable inputs of __________ __________ ________ _ _ __________ port, then “H.” If tAPS is not met, then either BUSY L or BUSY R = LOW. BUSY L and BUSY R cannot be LOW simultaneously __________ 3. Writes to one port are internally ignored when its BUSY outputs are LOW regardless of actual logic level on the pin. __________ Table 9. Truth Table – Address BUSY Arbitration Functions Left D 0-15 Right D0-15 Status No Action 1 1 Semaphore free Left port writes “0” to semaphore 0 1 Left port has semaphore token Right port writes “0” to semaphore 0 1 No change. Right port has no write access to semaphore Left port writes “1” to semaphore 1 0 Right port obtains semaphore token Left port writes “0” to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes “1” to semaphore 0 1 Left port obtains semaphore token Left port writes “1” to semaphore 1 1 Semaphore free Right port writes “0” to semaphore 1 0 Right port has semaphore token Right port writes “1” to semaphore 1 1 Semaphore free Left port writes “0” to semaphore 0 1 Left port has semaphore token Left port writes “1” to semaphore 1 1 Semaphore free NOTES: 1. Table shows sequence of events for one of the eight semaphores. 2. There are eight semaphore flags (A0-2) written via I/O 0 and read from I/O0-15. _____ ________ 3. CE = VIH, S E M = VIL to access semaphores. 4. Refer to Table 6. Table 10. Truth Table – Semaphore Procurement Sequence Example 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 10 of 10 HDV24VL ADP II Timing Diagrams tRC ADDR t AA (4) t ACE (4) CE t AOE (4) OE t ABE (4) UB, LB R/W tO H t LZ (1) DATAOUT Valid Data(4) t HZ (2) BUSY OUT t BDD NOTES: ______ ______ _____ (3,4) ______ 1. tLZ timing is bases on which signal is asserted last, C E______ ,O E______ , LB _____ or U B______ . 2. tHZ timing is bases on which signal is de-asserted first, C E ,O E , LB or U B. _________ 3. tBDD is needed only where the opposite port is completing a write operation to the same address. BUSY has no effect on valid output data. 4. Valid data starts from the last of t AOE , t ACE, tAA or t BDD. ________ 5. S E M=VIH. Diagram 1. Read Cycles CE (1) t t PU PD I CC I SB 50% 50% Diagram 2. Power-Up Power-Down 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 11 of 11 HDV24VL ADP II tWC ADDR tHZ (7) OE tAW CE or SEM (9,10) UB or LB (9) t AS (6) t WR (3) t WP (2) R/W tWZ DATA OUT tOW (4) (4) tDW t DH DATAIN ____ Diagram 3. Write Cycle No. 1, R/ W Controlled Timing t WC ADDR tAW CE or SEM (9,10) t AS (6) t EW(2) t WR (3) UB or LB(9) R/W t DW t DH DATA IN _____ _____ _____ Diagram 4. Write Cycle No. 2, C E, UB, LB, Controlled Timing NOTES: ____ ______ ______ _____ 1. R/W or CE or U B and LB must be HIGH during all address transitions. ______ ____ 2. A write occurs when C E = VIL and a R/W ____ = VIL for memory____ write cycle. ______ ________ 3. tWR timing is from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. The______ I/O pins are in the output state and input signals must not be applied during DATA out period. ________ ____ 5. For C E or SEM =VIL transition ______ simultaneously with or after the R/W = VIL transition, the outputs remain in the high-impedance state. ____ 6. tAS timing is based on latter of C E or R/W. 7. tHZ transition is measured 0mV from steady state with the Output Test Load. _____ ____ 8. For OE =VIL during R/W write cycle, the write pulse width is the larger of t WP or (t W Z + t DW ) to allow the I/O drivers to turn off and data to be placed on the bus for the required _____ ____ t DW. If______ OE = VIH during an R/W controlled writing cycle, the write pulse is specified as t WP . ________ ______ ________ 9. Set C E =VIL and SEM = VIH to access memory. Set CE = VIH and SEM = VIL to access semaphore. t EW must be met for either condition. 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 12 of 12 HDV24VL ADP II t SAA A0-A2 Valid Address t AW Valid Address t WR t ACE t EW SEM t SOP tD W I/O t OH DATAOUT Valid (2) DATAIN Valid t AS tWP t DH R/W tSWRD tAOE OE Write Cycle NOTES: _____ ______ Read Cycle ______ 1. CE = VIH or U B and L B = VIH for the duration of the above timing (both write and read cycle) . 2. “DATA OUT VALID” represents all I/O’s (I/O0-15) equal to the semaphore value. Diagram 5. Semaphore Read after Write Timing, Either Side A0 A-A2A SIDE A Match R/WA SEMA t SPS A0B -A2B SIDE B Match R/WB SEM B NOTES: _____ _____ ______ ______ 1. DOR = DOL = VIL, CE L = CE R =VIH or both U B and L B =VIH. 2. Timing for both ports is the same. ____ Port B ________ is opposite of port____A. ________ 3. This parameter is measured from R/W A or SEM A =VIH to R/WB or SEM B = VIH. 4. The semaphore will be sent to either side if tSPS is not met. It cannot be guaranteed which side receives semaphore. . Diagram 6. Semaphore Write Contention 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 13 of 13 HDV24VL ADP II t WC ADDR A Match t WP R/WA t DW DATA INA t DH Valid t APS ADDR B tBAA t BDA BUSYB t BDD t WDD Valid DATA OUTB t DDD NOTES: ___ 1. t_____ APS is ignored fo r SLAVE part (M/ S = VIL) _____ 2. _____ CE L =CER = VIH. 3. OE = VIL for the reading port. ___________ ___ 4. For SLAVE mode (M/ S = V IL), BUSY is an input. 5. Timing for both ports is the same. Port B is opposite of port A. ___________ __ Diagram 7. Write with Port-to-Port Read and BUSY (M/S = VIH ) t WP R/W A t WB t WH BUSY B R/W B NOTES: ___________ ___________ 1. SLAVE (BUSY input) and MASTER (BUSY___________ output) must meet t WH. ___________ ____ 2. BUSY is sent to port B blocking R/ W B till BUSY B =VIH. 3. tWB is for SLAVE mode. ___________ __ Diagram 8. Write with BUSY (M/S = V IL ) ADDRA and ADDRB CE Addresses Match A t APS CE B t BAC tBDC BUSY B ___________ _____ __ Diagram 9. BUSY Arbitration Controlled by C E Timing (M/S = VIH ) 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 14 of 14 HDV24VL ADP II ADDR A Addresses N t APS Matching Addresses N ADDRB t BAA t BDA BUSYB ___________ __ Diagram 10. BUSY Arbitration Controlled by Address Match Timing (M/S = VIH ) t WC ADDRA Interrupt Set Address t t AS WR CE A R/W A t INS INTF B t RC Interrupt Clear Address ADDR B t AS CE B OEB tINR INTF B Diagram 11. Interrupt Timing 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 15 of 15 HDV24VL ADP II Functional Description HDV24VL supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access to any location in memory. Interrupts A special memory location is associated with each port when the interrupt function is used. These special memory locations are best considered as mailboxes between the two ports and the corresponding interrupt signals as the flags of the _______ mailboxes. When the right port writes a data word to the special location FFE (HEX), the left port interrupt flag (INTFL) becomes _____ ____ _______ active or LOW (a data write is defined as CE R = R/ W R = VIL). The left port_____ can clear INTFL (HIGH) through either read or write _____ ____ access of the same memory location FFE (a data access is defined as CE L = OE L = VIL, and the value of R/W is irrelevant in the _______ case). Similarly, when the left port writes to the memory location FFF (HEX), the right_______ port interrupt flag (I N TR) becomes asserted (LOW). The right port must access the memory location FFF in order to clear INTFR (HIGH). The exact value of the data word at address FFE or FFF is user defined, and is irrelevant as far as the interrupt logic is concerned. If the user chooses not to use the interrupt function, the two special memory locations (FFE and FFF) are treated as part of the regular dual-port memory, and the interrupt flags can simply be ignored. Busy Logic When both ports attempt to access the same memory location at the same time, data corruption can potentially occur. In ___ the single-device or MASTER configuration (i.e. when the M /S pin is tied HIGH), the on-chip Busy Logic arbitrates simultaneous accesses to the same memory location, and determines the “winner” between the two ports. If Busy Logic considers __________ the right port lost in the arbitration, then the right port B U S Y pin is set active (LOW) to signal the system that this memory location is “busy ” being accessed by the other port. Furthermore, the Busy Logic prevents the right port from writing to the same __________ memory location for as long as the right port B U S Y signal stays active (LOW). Once the left port finishes access to this memory __________ location, the dual-port SRAM signals the system by setting the right port B U S Y pin back to inactive (HIGH), so that the system can resume its normal access from the right port. Note that only the write operation from the losing port is inhibited; the read operation is nondestructive and can thus continue regardless of the arbitration result. __________ The B U S Y pins are output pins in the single-device or MASTER mode, but become input pins instead when the ___ device is configured in SLAVE mode (this is accomplished by tying M/ S pin LOW). In SLAVE mode the on-chip arbitration __________ logic is disabled, and the device relies on the input BUSY signals for the results of arbitration when simultaneous access to the __________ same memory location occurs. Specifically, when a B U S Y pin is set to HIGH, normal operation can be performed from this port , ___________ but when a B U S Y pin is set to LOW, write operations will be inhibited from this port. If width expansion with multiple HBA HDV24VL devices is used, it is recommended that only one of them be configured in MASTER mode, and the rest of them in __________ __________ SLAVE mode. The B U S Y (output) signal from the master device should be connected to the respective B U S Y (input) pins of the slave devices. This means that only one device (the master) is performing the Busy Logic arbitration, and all the other devices (the slaves) will follow this arbitration accordingly. This can prevent the conflicts caused by the potential inconsistent arbitration results from different dual-port SRAM devices. Note that if the user does not wish the write operation to be inhibited by the Busy __________ Logic, the user can disable this feature by configuring the device in SLAVE mode and tying the B U S Y input pins to HIGH. The Busy arbitration logic is triggered whenever the two ports simultaneously attempt to access the same memory location, where____ data accesses are determined by the timings and values of the Address and Chip Enable signals only, not by the value of the R/ W signal. This means that both read and write operations can trigger the Busy Logic, even though only the write operation is inhibited from the losing port. Note that in a master/slave configuration, an additional timing constraint concerning ____ the R/ W signal needs to be met in order to prevent data corruption in the slave device: the write operation in the slave device __________ __________ cannot start before the BUSY signal –____ which originates from the output B U S Y pin – is received by the slave device to ensure write inhibition. In other words, the R/ W signal needs to stay high from the time the Busy Logic on the master device is __________ triggered (through the changing of the Address and Chip Enable signals ) till the B U S Y signal is received by the slave device. 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 16 of 16 HDV24VL ADP II Semaphores A semaphore can be considered as a special one-bit dual-port memory cell that can be “owned” by (or granted to) only one port at any given time. Typically a semaphore is used as an arbiter for the exclusive ownership (or access privilege) of any shared resource in a system. A semaphore ownership can be requested by writing a zero “0” to the semaphore; a semaphore ownership can be relinquished by writing a one “1” to the semaphore; and a semaphore ownership can be tested by reading from the semaphore – a readout of zero “0” means that the semaphore is owned by this port, while a readout of one “1” means that either the semaphore is owned by the other port, or there is no owner at all. A token-passing system can be used to conceptualize the semaphore mechanism: requesting for the semaphore ownership is equivalent to requesting for the token, and relinquishing the semaphore ownership is equivalent to releasing the token. HBA HDV24VL device provides eight addressable semaphores in addition to the regular 4Kx16 dual-port memory space. A typical sequence of accessing a semaphore is as follows: first a port attempts to request for the token by writing a zero “0” to the semaphore. The result of the request is then tested by reading from the semaphore: if the readout is zero “0”, then the token request has succeeded; but if the readout is one “1”, then the token request has failed. The requester should then try to repeatedly read from the semaphore until the readout becomes zero “0”, upon which time the requester becomes the new possessor of the token, and can be granted exclusive access privilege to the shared resource the semaphore represents. In the case when both ports request for the token at the same time, the semaphore logic ensures that only one port is granted the token. In other words, at most one of the two semaphore readout ports can assume the value of zero “0”. When the token is not owned by any port, the semaphore will appear to contain the value one “1” to both ports. Note that a failed token request becomes an outstanding token request, and will remain valid until either the other port releases the token (which means the requester now becomes the new possessor of the token), or when the outstanding request is withdrawn by writing a one “1” to the semaphore before the other port releases the token. ________ Semaphore accesses are distinguished from the regular memory access through the use of the semaphore select (S E M ) ________ signal: S E M should remain HIGH when the regular dual-port_____ memory is____ being accessed, but should be tied LOW when semaphores are being accessed. Other control signals such as CE , and R/ W behave identically in both cases. Address pins A0 to A2 are used to address the eight semaphore flags (the values of the other address pins are irrelevant to semaphores). Only data pin D0 is used when writing to a semaphore. However, when reading from a semaphore, the one-bit semaphore value will be duplicated on all data pins (I/O 0-I/OD 15). Note that the semaphore logic is not automatically initialized during power up. The system has to handle the initialization of the semaphores during power up by writing ones from both sides to all semaphores ensure their availabilities for future use. As discussed previously, semaphores are typically used to resolve contentions of shared resources in a system. These shared resources can be a common data bus, a bi-directional shared buffer, or even a segment of the dual-port SRAM on an HBA HDV24VL device. Before any component in the system attempts to gain exclusive access to a shared resource, the semaphore can be used to ensure that no resource contention or data corruption will occur. One advantage in using hardware-supported semaphores is performance improvement by eliminating the processor wait states. HBA HDV24VL semaphores also provide system designers with higher flexibility because the resource sharing can be managed much more easily. With proper system software support, semaphores can even replace the Busy arbitration logic in certain cases, albeit with a coarser data granularity. 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. October 2003 Page 17 of 17 HDV24VL ADP II Order Information: HBA Device Family Device Type Power Speed (ns)* Package** Temperature Range XX XXX XX V24 (4K x 16) XX BZ BY X HD XX Very Low 55 I – Industrial (-40° to 85°C) * Speed – Ohter speeds available upon request. **Package – BZ: 108 Ball 8mm x8mm 0.5mm-pitch BGA BY: 84 Ball 7mm x7mm 0.5mm-pitch BGA Example: HDV24VL55BZI (4K x 16, 55ns, 108 ball BGA, Industrial temperature) USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA www.hba.com Tel: 408.453.8885 Fax: 408.453.8886 Taiwan No. 81, Suite 8F-9, ShuiLee Rd. Hsinchu, Taiwan, R.O.C. www.hba.com 3HD166B © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Tel: 886.3.516.9118 Fax: 886.3.516.9181 October 2003 Page 18 of 18