Clock Generator for Cavium Processors
ICS8430S10I-03
DATA SHEET
General Description
Features
The ICS8430S10I-03 is a PLL-based clock generator specifically
designed for Cavium Networks SoC processors. This high
performance device is optimized to generate the processor core
reference clock, the DDR reference clocks, the PCI/PCI-X bus
clocks, and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers low-jitter, low-skew clock outputs, and
edge rates that easily meet the input requirements for the
CN30XX/CN31XX/CN38XX/CN58XX processors. The output
frequencies are generated from a 25MHz external input source or an
external 25MHz parallel resonant crystal. The extended temperature
range of the ICS8430S10I-03 supports telecommunication,
networking, and storage requirements.
•
One selectable differential output pair for DDR 533/400/667,
LVPECL, LVDS interface levels
•
•
•
Nine LVCMOS/ LVTTL outputs, 23Ω typical output impedance
•
Differential input pair (PCLK, nPCLK) accepts LVPECL, LVDS,
CML, SSTL input levels
•
Internal resistor bias on nPCLK pin allows the user to drive PCLK
input with external single-ended (LVCMOS/ LVTTL) input levels
•
Power supply modes:
CORE / OUTPUT
3.3V / 3.3V LVDS, LVPECL, LVCMOS
3.3V / 2.5V LVCMOS
•
•
-40°C to 85°C ambient operating temperature
Applications
Systems using Cavium Processors
CPE Gateway Design
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Available in lead-free (RoHS 6) package
Pin Assignment
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
VDD
nOE_D
GND
nPLL_ SEL
XTAL_IN
XTAL _ OUT
nXTAL _ SEL
PCLK
nPCLK
nOE_C
VDD
nOE_B
GND
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
ICS8430S10I-03
33
48-Pin
TQFP,
E- Pad 32
48 TQFP,
E-Pad
5
x x7mm
1mm 31
x 7mm
1mmxpackage
6 7mm7mm
body
7
package body 30
Y Package
8
29
Y
Package
Top View
9
28
Top View
10
27
26
11
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
1
VDDO_CD
QC
QD0
QD1
CORE_SEL
GND
GND
nOE_REF
VDDO_B
QB0
QB1
VDDO_B
SPI_SEL0
PCI_SEL1
PCI_SEL0
DDR_SEL 1
DDR_SEL0
nQA
QA
VDD
VDDA
Soho SME Gateway
VDDO_E
VDDO_REF
nOE_E
Soho Secure Gateway
GND
QREF0
QREF1
802.11n AP or Gateway
QREF2
GND
VDDO_REF
nLVDS_SEL
GND
QE
Home Media Servers
nOE_A
SPI_SEL1
•
•
•
•
•
•
•
•
•
Selectable external crystal or differential input source
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Block Diagram
Pulldown
Pulldown
Pulldown
Pullup/Pulldown
Pulldown
2
Pulldown
nLVDS_SEL
Pulldown
2
Pulldown
2
Pulldown
Pulldown
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
2
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Table 1. Pin Descriptions
Number
Name
1, 13, 23
VDD
Power
Type
Description
2
nOE_D
Input
3, 12, 30, 31,
39, 42, 46
GND
Power
4
nPLL_SEL
Input
5,
6
XTAL_IN,
XTAL_OUT
Input
7
nXTAL_SEL
Input
Pulldown
Selects XTAL input when LOW. Selects differential clock (PCLK, nPCLK) input
when HIGH. LVCMOS/LVTTL interface levels.
8
PCLK
Input
Pulldown
Non-inverting differential clock input.
9
nPCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VDD/2.
10
nOE_C
Input
Pulldown
Active LOW output enable for Bank C output. When logic HIGH, the output is high
impedance (HI-Z). When logic LOW, QC output is enabled. LVCMOS/LVTTL
interface levels.
11
nOE_B
Input
Pulldown
Active LOW output enable for Bank B outputs. When logic HIGH, the outputs are
high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
14
nOE_A
Input
Pulldown
Active LOW output enable for Bank A outputs. LVCMOS/LVTTL interface levels.
15,
16
SPI_SEL1,
SPI_SEL0
Input
Pulldown
Selects the SPI PLL clock reference frequency. See Table 3D.
17,
18
PCI_SEL1,
PCI_SEL0
Input
Pulldown
Selects the PCI, PCI-X reference clock output frequency. See Table 3C.
LVCMOS/LVTTL interface levels.
19,
20
DDR_SEL1,
DDR_SEL0
Input
Pulldown
Selects the DDR reference clock output frequency. See Table 3B.
LVCMOS/LVTTL interface levels.
21, 22
nQA, QA
Output
Differential output pair. Selectable between LVPECL and LVDS interface levels.
24
VDDA
Power
Analog supply pin.
25, 28
VDDO_B
Power
Bank B output supply pins. 3.3 V or 2.5V supply.
26, 27
QB1, QB0
Output
Single-ended Bank B outputs. LVCMOS/LVTTL interface levels.
29
nOE_REF
Input
Pulldown
Active LOW output enabled. When logic HIGH, the QREF[2:0] outputs are high
impedance (HI-Z). When logic LOW, the QREF[2:0] outputs are enabled.
LVCMOS/ LVTTL interface levels.
32
CORE_SEL
Input
Pulldown
Selects the processor core clock output frequency. The output frequency is 50MHz
when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL
interface levels.
33, 34
QD1, QD0
Output
Single-end Bank D outputs. LVCMOS/LVTTL interface levels.
35
QC
Output
Single-end Bank C output. LVCMOS/LVTTL interface levels.
36
VDDO_CD
Power
Bank C and Bank D output supply pin. 3.3 V or 2.5V supply.
Core supply pins.
Pulldown
Active LOW output enable for Bank D outputs. When logic HIGH, the outputs are
high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
Power supply ground.
Pulldown
PLL bypass. When LOW, PLL is enabled. When HIGH, PLL is bypassed.
LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
Pin descriptions continue on the next page.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
3
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Number
Name
Type
37
VDDO_E
Power
38
QE
Output
Description
Bank E output supply pin. 3.3 V or 2.5V supply.
Single-end Bank E output. LVCMOS/LVTTL interface levels.
Pulldown
Selects between LVDS and LVPECL interface levels on differential output pair QA
and nQA. When LOW, LVDS levels are selected. When HIGH, LVPECL levels are
selected. See Table 3E.
40
nLVDS_SEL
Input
41, 48
VDDO_REF
Power
Bank QREF output supply pins. 3.3 V or 2.5V supply.
43,
44,
45
QREF2,
QREF1,
QREF0
Output
Single-ended reference clock outputs. LVCMOS/LVTTL interface levels.
47
nOE_E
Input
Pulldown
Active LOW output enable for Bank E output. When logic HIGH, the output is high
impedance (HI-Z). When logic LOW, the output is enabled. LVCMOS/LVTTL
interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
RPULLDOWN
ROUT
Test Conditions
Minimum
Typical
Maximum
Units
2
pF
VDD, VDDO_X = 3.465V
10
pF
VDD = 3.465V, VDDO_X = 2.625V
10
pF
Input Pullup Resistor
51
kΩ
Input Pulldown Resistor
51
kΩ
Output Impedance
QB[0:1], QC,
QD[0:1], QE
QREF[0:2]
VDDO_X = 3.465V
23
Ω
QB[0:1], QC,
QD[0:1], QE
QREF[0:2]
VDDO_X = 2.625V
26
Ω
NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Function Tables
Table 3A. Control Input Function Table
Input
Output Frequency
CORE_SEL
QB[0:1]
0
50MHz (default)
1
33.333MHz
Table 3B. Control Input Function Table
Inputs
Output Frequency
DDR_SEL1
DDR_SEL0
QA, nQA
0
0
133.333MHz (default)
0
1
100.000MHz
1
0
83.333MHz
1
1
125.000MHz
Table 3C. Control Input Function Table
Inputs
Output Frequency
PCI_SEL1
PCI_SEL0
QC
0
0
133.333MHz (default)
0
1
100.000MHz
1
0
66.6667MHz
1
1
33.333MHz
Table 3D. Control Input Function Table
Inputs
Output Frequency
SPI_SEL1
SPI_SEL0
QD[0:1]
0
0
100.000MHz (default)
0
1
125.000MHz
1
0
80.000MHz
Table 3E. Control Input Function Table
Input
Output Levels
nLVDS_SEL
QA, nQA
0
LVDS (default)
1
LVPECL
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, VO (LVCMOS)
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
33.1°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVCMOS Power Supply DC Characteristics, VDD = VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.20
3.3
VDD
V
VDDO_X
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
150
mA
IDDA
Analog Supply Current
20
mA
IDDO_X
Output Supply Current
39
mA
No Load, nLVDS_SEL = 0
NOTE: VDDO_X denotes VDDO_B, VDDO_CD and VDDO_REF.
Table 4B. LVCMOS Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.20
3.3
VDD
V
VDDO_X
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
150
mA
IDDA
Analog Supply Current
20
mA
IDDO_X
Output Supply Current
27
mA
No Load, nLVDS_SEL = 0
NOTE: VDDO_X denotes VDDO_B, VDDO_CD and VDDO_REF.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Table 4C. LVPECL Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
IGND
Power Supply Current
IDDA
Analog Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD – 0.20
3.3
VDD
V
186
mA
20
mA
nLVDS_SEL = 1
Table 4D. LVDS Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
IDD
Power Supply Current
IDDA
Analog Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD – 0.20
3.3
VDD
V
150
mA
20
mA
nLVDS_SEL = 0
Table 4E. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
VOH
VOL
Test Conditions
Minimum
Typical
Maximum
Units
2.2
VDD + 0.3
V
-0.3
0.8
V
150
µA
Input
High Current
DDR_SEL[0:1],
nPLL_SEL, nLVDS_SEL,
PCI_SEL[0:1], nOE_REF,
SPI_SEL[0:1], nOE_[A:E],
nXTAL_SEL, CORE_SEL
VDD = VIN = 3.465V
Input
Low Current
DDR_SEL[0:1],
nPLL_SEL, nLVDS_SEL,
PCI_SEL[0:1], nOE_REF,
SPI_SEL[0:1], nOE_[A:E],
nXTAL_SEL, CORE_SEL
VDD = 3.465V, VIN = 0V
-10
µA
VDDO_X = 3.465V,
IOH = -12mA
2.6
V
VDDO_X = 2.625V,
IOH = -12mA
1.8
V
Output High Voltage
Output Low Voltage
VDDO_X = 3.465V,
IOL = 12mA
0.65
V
VDDO_X = 2.625V,
IOL = 12mA
0.55
V
NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Table 4F. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Voltage
VCMR
Test Conditions
PCLK, nPCLK
Minimum
Typical
VDD = VIN = 3.465V
Maximum
Units
150
µA
PCLK
VDD = 3.465V, VIN = 0V
-10
µA
nPCLK
VDD = 3.465V, VIN = 0V
-150
µA
0.3
1.0
V
Common Mode Input Voltage; NOTE 1
GND + 1.5
VDD
V
VOH
Output High Voltage; NOTE 2
VDD – 1.4
VDD – 0.9
V
VOL
Output Low Voltage; NOTE 2
VDD – 2.0
VDD – 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: Outputs terminated with 50Ω to VDD – 2V.
Table 4G. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
∆VOD
VOD Magnitude Change
VOS
Offset Voltage
∆VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
300
1.04
1.14
Maximum
Units
600
mV
50
mV
1.24
V
50
mV
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
fOUT
Parameter
Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
QA, nQA
DDR_SEL[1:0] = 00
133.333
MHz
QA, nQA
DDR_SEL[1:0] = 01
100
MHz
QA, nQA
DDR_SEL[1:0] = 10
83.333
MHz
QA, nQA
DDR_SEL[1:0] = 11
125
MHz
QBx
CORE_SEL = 0
50
MHz
QBx
CORE_SEL = 1
33.333
MHz
QC
PCI_SEL[1:0] = 00
133.333
MHz
QC
PCI_SEL[1:0] = 01
100
MHz
QC
PCI_SEL[1:0] = 10
66.667
MHz
QC
PCI_SEL[1:0] = 11
33.333
MHz
QDx
SPI_SEL[1:0] = 00
100
MHz
QDx
SPI_SEL[1:0] = 01
125
MHz
QDx
SPI_SEL[1:0] = 10
80
MHz
QE
125
MHz
QREFx
25
MHz
tsk(b)
Bank Skew; NOTE 1, 2
QREFx
Using PCLK, nPCLK
25
ps
tsk(pp)
Part-to-Part Skew;
NOTE 2, 3
QREFx
Using PCLK, nPCLK
350
ps
tjit(Ø)
RMS Phase Jitter,
(Random); NOTE 5
QREFx
25MHz (10kHz to 5MHz)
0.637
ps
125MHz (1.875MHz to 20MHz)
0.557
ps
QE
QA, nQA
QBx
tjit(per)
Period Jitter (pk-pk);
NOTE 4, 11
QC
QDx
QE
133.33MHz; NOTE 6
115
ps
100MHz; NOTE 7
115
ps
133.33MHz; NOTE 8
115
ps
100MHz; NOTE 9
115
ps
83.33MHz; NOTE 10
115
ps
50MHz; NOTE 6
95
ps
50MHz; NOTE 7
95
ps
50MHz; NOTE 8
95
ps
50MHz; NOTE 9
95
ps
50MHz; NOTE 10
95
ps
133.33MHz; NOTE 6
90
ps
133.33MHz; NOTE 9
90
ps
100MHz; NOTE 7
95
ps
125MHz; NOTE 8
95
ps
125MHz; NOTE 10
95
ps
125MHz; NOTE 6
90
ps
125MHz; NOTE 8
90
ps
125MHz; NOTE 9
90
ps
125MHz; NOTE 10
90
ps
9
©2011 Integrated Device Technology, Inc.
Continued on next page.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
ICS8430S10I-03 Data Sheet
Symbol
tjit(hper)
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Parameter
RMS Half-Period Jitter;
NOTE 2, 4
Test Conditions
QA, nQA
Minimum
odc
Output Duty Cycle
tLOCK
Lock Time
Units
30
ps
100MHz; NOTE 7
30
ps
133.33MHz; NOTE 8
30
ps
100MHz; NOTE 9
30
ps
83.33MHz; NOTE 10
Output Rise/Fall Time
Maximum
133.33MHz; NOTE 6
30
ps
150
350
ps
200
900
ps
QA, nQA
48
52
%
QBx, QC,
QE, QREFx
48
52
%
QDx
48
52
%
55
ms
QA, nQA
tR / tF
Typical
QBx, QC,
QDx, QE,
QREFx
10% to 90%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at maximum fOUT, unless noted otherwise.
NOTE: All parameters are characterized using crystal input, unless noted otherwise.
NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF.
NOTE 1: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO_REF/2.
NOTE 4: This parameter is measured at the crosspoint for differential and VDDO_X /2 single-ended signals.
NOTE 5: Refer to the phase noise plot.
NOTE 6: DDR_SEL[1:0] = 00: QA, nQA = 133.33MHz, QBx = 50MHz, QC = 133.33MHz, QDx = OFF, QE = 125MHz and QREFx = 25MHz.
NOTE 7: DDR_SEL[1:0] = 01: QA, nQA = 100MHz, QBx = 50MHz, QC = OFF, QDx = 100MHz, QE = OFF and QREFx = 25MHz.
NOTE 8: DDR_SEL[1:0] = 00: QA, nQA = 133.33MHz, QBx = 50MHz, QC = OFF, QDx = 125MHz, QE = 125MHz and QREFx = 25MHz.
NOTE 9: DDR_SEL[1:0] = 01: QA, nQA = 100MHz, QBx = 50MHz, QC = 133.33MHz, QDx = OFF, QE = 125MHz and QREFx = 25MHz.
NOTE 10: DDR_SEL[1:0] = 10: QA, nQA = 83.33MHz, QBx = 50MHz, QC = OFF, QDx = 125MHz, QE = 125MHz and QREFx = 25MHz.
NOTE 11: This parameter is measured at 10K cycles.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Noise Power
dBc
Hz
Typical Phase Noise at 125MHz (QE output)
Offset Frequency (Hz)
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Noise Power
dBc
Hz
Typical Phase Noise at 25MHz (QREF output)
Offset Frequency (Hz)
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Parameter Measurement Information
2.05V±5%
1.65V±5%
1.25V±5%
1.65V±5%
2.05V±5%
SCOPE
VDD,
SCOPE
VDD
VDDO_X
VDDA
VDDO_X
Qx
Qx
VDDA
GND
GND
-
-1.65V±5%
-1.25V±5%
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
2V
2V
VDD
Qx
SCOPE
SCOPE
3.3V±5%
POWER SUPPLY
+ Float GND –
VDDA
Qx
VDD
VDDA
LVPECL
nQx
nQx
GND
-1.3V±0.165V
3.3V Core/3.3V LVPECL Output Load AC Test Circuit
3.3V Core/3.3V LVDS Output Load AC Test Circuit
VDD
Part 1
V
DDO_X
QREFx
nPCLK
V
PP
Cross Points
V
2
Part 2
CMR
V
PCLK
DDO_X
QREFy
2
tsk(pp)
GND
Differential Input Level
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
LVCMOS Part-to-Part Skew
13
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Parameter Measurement Information, continued
VOH
nQA
VREF
QA
➤
➤
t jit (pk-pk)
(Trigger Edge)
t half period
n+1
1
fo
➤
➤
t jit(hper) = t half period n — 1
Histogram
Reference Point
➤
t half period n
➤
VOL
2*fo
Mean Period
(First edge after trigger)
10,000 cycles
Period Jitter, Peak-to-Peak
Half Period Jitter
V
QBx, QC,
QDx, QE,
QREFx
nQA
QA
DDO_X
2
t PW
t PW
t
odc =
t
PERIOD
t PW
x 100%
odc =
t PERIOD
PERIOD
t PW
x 100%
t PERIOD
Differential Output Duty Cycle/Pulse Width/Period
LVCMOS Output Duty Cycle/Pulse Width/Period
Noise Power
Phase Noise Plot
QREF{0:2]
VDDO_X
2
VDDO_X
2
QREF{0:2]
f1
Offset Frequency
tsk(b)
f2
RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers
RMS Phase Jitter
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
LVCMOS Bank Skew
14
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Parameter Measurement Information, continued
nQA
nQA
90%
90%
90%
90%
VSW I N G
VOD
QA
LVDS Output Rise/Fall Time
QBx, QC,
QDx, QE,
QREFx
tF
tR
tF
tR
10%
10%
10%
10%
QA
LVPECL Output Rise/Fall Time
90%
90%
tR
tF
10%
10%
LVCMOS Output Rise/Fall Time
Lock Time
VDD
VDD
out
LVDS
➤
out
DC Input
➤
LVDS
100
VOS/∆ VOS
➤
VOD/∆ VOD
out
➤
DC Input
➤
out
➤
Offset Voltage Setup
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
Differential Output Voltage Setup
15
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
PCLK/nPCLK Inputs
LVPECL Outputs
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
The unused LVPECL output pair can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs
Crystal Inputs
The unused LVDS output pair can be either left floating or terminated
with 100Ω across. If they are left floating, there should be no trace
attached.
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VDD/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
16
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
3.3V LVPECL Differential Clock Input Interface
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. The differential signals must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the PCLK/ nPCLK input driven by the most common driver types.
3.3V
3.3V
3.3V
3.3V
3.3V
R3
84
Zo = 50Ω
3.3V LVPECL
3.3V
R3
125Ω
R4
84
R4
125Ω
Zo = 50Ω
C1
PCLK
PCLK
Zo = 50Ω
C2
Zo = 50Ω
nPCLK
R5
100 - 200
R6
100 - 200
R1
125
nPCLK
LVPECL
Input
R2
125
LVPECL
Input
LVPECL
R1
84Ω
Figure 2A. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
R2
84Ω
Figure 2B. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
2.5V
3.3V
3.3V
3.3V
Zo = 50Ω
2.5V
R3
120Ω
C1
PCLK
R5
100Ω
R4
120Ω
Zo = 60Ω
VBB
C2
PCLK
nPCLK
Zo = 50Ω
LVPECL
Input
LVDS
R1
1k
Zo = 60Ω
R2
1k
nPCLK
SSTL
R1
120Ω
R2
120Ω
LVPECL
Input
C3
0.1µF
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
Figure 2D. PCLK/nPCLK Input Driven by a
3.3V SSTL Driver
3.3V
3.3V
3.3V
R1
50Ω
R2
50Ω
Zo = 50Ω
PCLK
Zo = 50Ω
nPCLK
CML
LVPECL
Input
Figure 2E. PCLK/nPCLK Input Driven by a CML Driver
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
17
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
VCC
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
applications, R1 and R2 can be 100Ω. This can also be
accomplished by removing R1 and making R2 50Ω. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
18
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
The differential output pair is low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
R3
125Ω
3.3V
3.3V
Zo = 50Ω
3.3V
R4
125Ω
3.3V
3.3V
+
Zo = 50Ω
+
_
LVPECL
Input
Zo = 50Ω
R1
50Ω
_
LVPECL
R2
50Ω
R1
84Ω
VCC - 2V
RTT =
1
* Zo
((VOH + VOL) / (VCC – 2)) – 2
Input
Zo = 50Ω
R2
84Ω
RTT
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
LVDS Driver Termination
A general LVDS interface is shown in Figure 5. Standard termination
for LVDS type output structure requires both a 100Ω parallel resistor
at the receiver and a 100Ω differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100Ω
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 5 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the amplitude and common mode input
range of the input receivers should be verified for compatibility with
the output.
+
LVDS Driver
LVDS
Receiver
100Ω
–
100Ω Differential Transmission Line
Figure 5. Typical LVDS Driver Termination
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
19
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 6. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
PIN
PIN PAD
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
20
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Application Schematic
Figure 7 shows an example of ICS8430S10I-03 application
schematic. In this example, the device is operated at VDD = VDDA =
VDDO_B = VDDO_CD = VDDO_E = VDDO_REF = 3.3V. An 18pF parallel
resonant 25MHz crystal is used. The load capacitance C1 = 18pF
and C2 = 18pF are recommended for frequency accuracy.
Depending on the parasitics of the printed circuit board layout, these
values might require a slight adjustment to optimize the frequency
accuracy. Crystals with other load capacitance specifications can be
used. This will require adjusting C1 and C2. For this device, the
crystal load capacitors are required for proper operation.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS8430S10I-03 provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
QREF0
Logic Control Input Examples
Set Logic
Input to
'0'
VDDO_REF
RU2
Not Install
To Logic
Input
pins
QE
RD2
1K
F
p
8
1
1
2
3
4
5
6
7
8
9
10
11
12
nOE_D
18pF
nPLL_SEL
XTAL_IN
XTAL_OUT
nXTAL_SEL
VDD
nOE_C
nOE_B
R4
125
VDD
nOE_D
GND
nPLL_SEL
XTAL_IN
XTAL_OUT
nXTAL_SEL
PCLK
nPCLK
nOE_C
nOE_B
GND
CLK
Zo = 50
VDDO_CD
QC
QD0
QD1
CORE_SEL
GND
GND
nOE_REF
VDDO_B
QB0
QB1
VDDO_B
VD D
nOE_A
SPI_SEL1
SPI_SEL0
PC I_SEL1
PC I_SEL0
D DR _SEL1
D DR _SEL0
nQA
QA
VD D
VD D A
R3
125
13
14
15
16
17
18
19
20
21
22
23
24
nCLK
Zo = 50
R7
84
Receiv er
36
35
34
33
32
31
30
29
28
27
26
25
VDD= VDDO_B = 3.3V
VDDO_CD = VDDO_E= VDDO_REF = 3.3V
CORE_SEL
nOE_REF
3.3V
R5
133
PAD
X1
C2
R6
133
Zo = 50 Ohm
QA0
+
nQA0
R8
84
Zo = 50 Ohm
nOE_A
SPI_SEL1
SPI_SEL0
PCI_SEL1
PCI_SEL0
DDR_SEL1
DDR_SEL0
3.3V
Zo = 50
27
49
VDD
25MHz
R2
VDD O_REF
nOE_E
GN D
QR EF0
QR EF1
QR EF2
GN D
VDD O_REF
LVD S_SEL
GN D
QE
VD D O_E
U1
LVPECL Driv er
VDDO
To Logic
Input
pins
RD1
Not Install
C1
18pF
LVDS_SEL
RU1
1K
Receiv er
nOE_E
VDD
Zo = 50
27
48
47
46
45
44
43
42
41
40
39
38
37
Set Logic
Input to
'1'
VDD
R1
VDDA
C3
0.01u
R9
10
-
VDD
R10
82.5
R11
82.5
LVPECL
Termination
C4
10u
BLM18BB221SN1
1
C5
0.1uF
3.3V
2 VDDO_REF (U1:41)
Ferrite Bead C6
VDDO_REF
(U1:48)
C7
C8
10uF 0.1uF
0.1uF
QA0
nQA0
BLM18BB221SN2
1
C9
0.1uF
3.3V
2
Ferrite Bead C10
(U1:1)
(U1:13) (U1:23) VDD
C11
C12
10uF 0.1uF
0.1uF
+
C13
nQA0
0.1uF
1
2 VDDO
Ferrite Bead C15
Zo = 50 Ohm
R12
100
-
LVDS
Termination
BLM18BB221SN3
C14
0.1uF
Zo = 50 Ohm
QA0
VDD
(U1:25)
C16
10uF 0.1uF
(U1:28)
(U1:36) (U1:37)
C17
C18
0.1uF
0.1uF
VDDO
C19
0.1uF
Figure 7. ICS8430S10I-03 Schematic Example
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
21
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Power Considerations (LVCMOS/LVDS Outputs)
This section provides information on power dissipation and junction temperature for the ICS8430S10I-03.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8430S10I-03 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Core and LVDS Output Power Dissipation
•
Power (core, LVDS) = VDD_MAX * (IDD + IDDA) = 3.465V * (150mA + 20mA) = 589.05mW
LVCMOS Output Power Dissipation
•
Dynamic Power Dissipation at 133.33MHz
Power (133.33MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133.33MHz * (3.465V)2 = 16mW per output
Total Power (133.33MHz) = 16mW * 1 = 16mW
•
Power(125MHz) = 10pF * 125MHz * (3.465V)2 = 15mW per output
Total Power (125MHz) = 15mW * 3 = 45mW
•
Dynamic Power Dissipation at 25MHz
Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465V)2 = 3mW per output
Total Power (25MHz) = 3mW * 3 = 9mW
Power (50MHz) = CPD * Frequency * (VDDO)2 = 10pF * 50MHz * (3.465V)2 = 6mW per output
Total Power (50MHz) = 6mW * 2 = 12mW
Total Power Dissipation
•
Total Power
= Power (core, LVDS) + Total Power (133.33MHz) + Total Power (125MHz) + Total Power (25MHz) + Total Power (50MHz)
= 589.05mW + 16mW + 45mW + 9mW + 12mW
= 671.05mW
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
22
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.671W * 33.1°C/W = 107.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board.
Table 7A. Thermal Resistance θJA for 48 Lead TQFP, EPAD Forced Convection
θJA Vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
0
1
2.5
33.1°C/W
27.2°C/W
25.7°C/W
23
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Power Considerations (LVCMOS/LVPECL Outputs)
This section provides information on power dissipation and junction temperature for the ICS8430S10I-03.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8430S10I-03 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Core and LVPECL Output Power Dissipation
•
Power (core)_MAX = VDD_MAX * IEE_MAX = 3.465V * 186mA = 644.49mW
•
Power (output)_MAX = 30mW/Loaded Output Pair
LVCMOS Output Power Dissipation
•
Dynamic Power Dissipation at 133.33MHz
Power (133.33MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133.33MHz * (3.465V)2 = 16mW per output
Total Power (133.33MHz) = 16mW * 1 = 16mW
•
Power(125MHz) = 10pF * 125MHz * (3.465V)2 = 15mW per output
Total Power (125MHz) = 15mW * 3 = 45mW
•
Dynamic Power Dissipation at 25MHz
Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465V)2 = 3mW per output
Total Power (25MHz) = 3mW * 3 = 9mW
Power (50MHz) = CPD * Frequency * (VDDO)2 = 10pF * 50MHz * (3.465V)2 = 6mW per output
Total Power (50MHz) = 6mW * 2 = 12mW
Total Power Dissipation
•
Total Power
= Power (core, LVPECL) + Total Power (133.33MHz) + Total Power (125MHz) + Total Power (25MHz) + Total Power (50MHz)
= 644.49mW + 16mW + 45mW + 9mW + 12mW
= 726.49mW
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
24
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 7B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.727W * 33.1°C/W = 109.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board.
Table 7B. Thermal Resistance θJA for 48 Lead TQFP, EPAD Forced Convection
θJA Vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
0
1
2.5
33.1°C/W
27.2°C/W
25.7°C/W
25
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
The LVPECL output driver circuit and termination are shown in Figure 8.
VDD
Q1
VOUT
RL
50Ω
VDD - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VDD – 2V.
•
For logic high, VOUT = VOH_MAX = VDD_MAX – 0.9V
(VDD_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VDD_MAX – 1.7V
(VDD_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOH_MAX) = [(2V – (VDD_MAX – VOH_MAX))/RL] * (VDD_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOL_MAX) = [(2V – (VDD_MAX – VOL_MAX))/RL] * (VDD_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Reliability Information
Table 8. θJA vs. Air Flow Table for a 48 Lead TQFP, EPAD
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
33.1°C/W
27.2°C/W
25.7°C/W
Transistor Count
The transistor count for ICS8430S10I-03 is: 9,291
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ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Package Outline and Package Dimensions
Package Outline - Y Suffix for 48 Lead TQFP, EPAD
-HD VERSION
EXPOSED PAD DOWN
0.20 TAB
-TAB, EXPOSED PART OF CONNECTION BAR OR TIE BAR
Table 9. Package Dimensions 48L TQFP, EPAD
Symbol
N
A
A1
A2
b
c
D&E
D1 & E1
D2 & E2
D3 & E3
e
L
θ
ccc
JEDEC Variation: ABC - HD
All Dimensions in Millimeters
Minimum
Nominal
Maximum
48
1.20
0.05
0.10
0.15
0.95
1.00
1.05
0.17
0.22
0.27
0.09
0.20
9.00 Basic
7.00 Basic
5.50 Ref.
3.5
0.5 Basic
0.45
0.60
0.75
0°
7°
0.08
Reference Document: JEDEC Publication 95, MS-026
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©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Ordering Information
Table 10. Ordering Information
Part/Order Number
8430S10BYI-03LF
8430S10BYI-03LFT
Marking
ICS0S10BI03L
ICS0S10BI03L
Package
“Lead-Free” 48 TQFP, EPAD
“Lead-Free” 48 TQFP, EPAD
Shipping Packaging
Tray
1000 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Revision History Sheet
Rev
A
Table
Page
T6
9
14
Description of Change
Date
AC Characteristics Table - deleted Cycle-to-Cycle Jitter specs.
Parameter Measurement Information, deleted Cycle-to-Cycle Jitter diagrams.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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2/22/11
©2011 Integrated Device Technology, Inc.
ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
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