AWT6652 High Efficiency ProEficientTM UMTS 1900, 2100 (Band 1, 2) LTE/WCDMA/CDMA Linear PAM DATA SHEET - Rev 2.0 FEATURES • CDMA/EVDO, WCDMA/HSPA and LTE Compliant • High Efficiency (R99 waveform): • 46% @ POUT = +28.5 dBm • 20% @ POUT = +17 dBm in LPM, without DC/DC Converter AWT6652 • Simple Calibration with only 2 Bias Modes • Optimized for SMPS Supply • Low Leakage Current in Shutdown Mode: <4 µA • Internal Voltage Regulator • Integrated “daisy chainable” directional coupler with CPLIN and CPLOUT Ports • Optimized for a 50 Ω System 10 Pin 3 mm x 3 mm x 0.9 mm Surface Mount Module • Internal DC blocks on IN/OUT RF ports • 1.8 V Control Logic • RoHS Compliant Package, 260 oC MSL-3 APPLICATIONS • Wireless Handsets and Data Devices for: • WCDMA/HSPA/LTE PCS Band 2 • WCDMA Band 1 • CDMA/EVDO Bandclass 1 & 14 • Band 25 LTE Devices GND at Slug (pad) VBATT PRODUCT DESCRIPTION The AWT6652 PA is designed to provide highly linear RFIN output for WCDMA, CDMA and LTE handsets and data devices with high efficiency at both high and low power modes. This ProEficientTM PA can be used with an external switch mode power supply (SMPS) to VMODE2 (N/C) improve its efficiency and reduce current consumption further at medium and low output powers. The device is manufactured on an advanced InGaP HBT VMODE1 MMIC technology offering state-of-the-art reliability, temperature stability, and ruggedness. There are two selectable bias modes that optimize efficiency for VEN different output power levels, and a shutdown mode with low leakage current, which increases handset talk and standby time. The self-contained 3 mm x 3 mm x 0.9 mm surface mount package incorporates matching networks optimized for output power, efficiency, and linearity in a 50 Ω system. 08/2014 1 10 2 VCC 9 RFOUT 8 CPLIN 4 7 GND 5 6 CPLOUT 3 CPL Bias Control Voltage Regulation Figure 1: Block Diagram AWT6652 VBATT 1 10 RFIN 2 9 RFOUT N/C 3 8 CPLIN VMODE1 4 7 GND VEN 5 6 CPLOUT Figure 2: Pinout (X-ray Top View) Table 1: Pin Description 2 PIN NAME DESCRIPTION 1 VBATT Battery Voltage 2 RFIN RF Input 3 N/C No Connection 4 VMODE1 5 VEN 6 CPLOUT 7 GND Ground 8 CPLIN Coupler Input 9 RFOUT RF Output 10 VCC Mode Control Voltage 1 PA Enable Voltage Coupler Output Supply Voltage DATA SHEET - Rev 2.0 08/2014 VCC AWT6652 ELECTRICAL CHARACTERISTICS Table 2: Absolute Minimum and Maximum Ratings PARAMETER MIN TYP MAX UNIT RF Input (PIN) - 0 10 dBm VCC 0 3.4 5 V VBATT 0 3.4 6 V Control Voltage (VENABLE, VMODE) 0 1.8 3.5 V Storage Temperature (TSTORAGE) -40 25 150 °C Functional operation to the specified performance is not implied under these conditions. Operation of any single parameter in excess of the absolute ratings may cause permanent damage. No damage occurs if one parameter is set at the limit while all other parameters are set within normal operating ranges. Table 3: Operating Ranges PARAMETER MIN TYP MAX UNIT COMMENTS Operating Frequency (f) 1850 - 1915 MHz UMTS Band 2, CDMA BC1 & 14 Supply Voltage (VCC) +0.6 +3.4 +4.4 V POUT < +28.5 dBm Battery Voltage (VBATT) +3.1 +3.4 +4.4 V POUT < +28.5 dBm Enable Voltage (VENABLE) +1.35 0 +1.8 0 +3.1 +0.5 V PA “on” PA “shut down” Mode Control Voltage (VMODE1) +1.35 0 +1.8 0 +3.1 +0.5 V Low Bias Mode High Bias Mode RF Output Power (POUT) (1) R99 WCDMA, HPM HSPA (MPR = 0), HPM LTE, HPM R99 WCDMA, LPM HSPA (MPR = 0), LPM LTE, LPM 27.7 26.6 26.4 16.2 15.2 15.2 28.5 27.4 27.2 17 16 16 - dBm CDMA Output Power (1) HPM LPM 27.2 15.2 28 16 - dBm Case Temperature (TC) -30 - +90 °C 3GPP TS 34.121-1, Rel 8 Table C.11.1.3, for WCDMA Subtest 1 TS 36.101 Rel 8 for LTE CDMA2000, RC-1 The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. Notes: (1) For operation at Vcc = +3.1 V, Pout is derated by 0.8 dB. 3 DATA SHEET - Rev 2.0 08/2014 AWT6652 Table 4: B 2 (1850 - 1910 MHz) Electrical Specifications - WCDMA Operation (R99 waveform) (TC = +25 °C, VCC = VBATT = +3.4 V, VEN = +1.8 V, 50 Ω system, unless otherwise specified) PARAMETER MIN TYP MAX Gain 24.5 20 12 27 24.5 14.5 30 28 18 ACLR1 at 5 MHz offset (1) - -40 -53 -45 ACLR2 at 10 MHz offset (1) - Power-Added Efficiency (1) UNIT COMMENTS POUT VCC VMODE1 dB +28.5 dBm +17 dBm +17 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V -36 -36 -36 dBc +28.5 dBm +17 dBm +17 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V -54 -65 -55 -48 -48 -48 dBc +28.5 dBm +17 dBm +17 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V 40 - 46 26 20 - % +28.5 dBm +17 dBm +17 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V Quiescent Current (Icq) Low Bias Mode - 18 - mA VMODE1 = +1.8 V Mode Control Current - 0.16 - mA through VMODE pin, VMODE1 = 1.8 V Enable Current - 0.02 - mA through VENABLE pin BATT Current - 2.8 - mA through VBATT pin, VMODE1 = +1.8 V Leakage Current - 3 10 µA VBATT = +4.4 V, VCC = +4.4 V VENABLE = 0 V, VMODE1 = 0 V Noise in Receive Band (2) - -133 -143 - dBm/Hz Harmonics 2fO 3fO, 4fO - -43 -55 -30 -35 dBc Input Impedance - - 2:1 VSWR Coupling Factor 17 20 23 dB Directivity - 20 - dB Coupler IN-OUT Daisy Chain Insertion Loss - <0.25 - dB 698 to 2620 MHz Pin 8 to 6 Shutdown Mode POUT < +28.5 dBm In-band load VSWR < 5:1 Out-of-band load VSWR < 10:1 Applies over all operating conditions Spurious Output Level (all suprious outputs) Load mismatch stress with no permanent degradation or failure Phase Delta (HPM-LPM) - - -70 dBc 8:1 - - VSWR - 10 - Deg Notes: (1) ACLR and Efficiency measured at 1880 MHz. (2) Noise measured at 1930 MHz to 1990 MHz. 4 DATA SHEET - Rev 2.0 08/2014 POUT < +28.5 dBm, VMODE1 = 0 V POUT < 17 dBm, VMODE1 = +1.8 V POUT < +28.5 dBm Applies over full operating range AWT6652 Table 5: B 2 (1850 - 1910 MHz) Electrical Specifications - LTE Operation (RB = 12, START = 0, QPSK) (TC = +25 °C, VCC = VBATT = +3.4 V, VEN = +1.8 V, 50 Ω system, unless otherwise specified) PARAMETER MIN TYP MAX UNIT Gain 24.5 - 27 24.5 14.5 30 - ACLR E-UTRA (1) at ± 10 MHz offset - -38 -52 -40 ACLR1 UTRA (1) at ± 7.5 MHz offset - ACLR2 UTRA (1) at ± 12.5 MHz offset COMMENTS POUT VCC VMODE1 dB +27.2 dBm +16 dBm +16 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V -34 -34 -34 dBc +27.2 dBm +16 dBm +16 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V -38 -52 -40 -36 -36 -36 dBc +27.2 dBm +16 dBm +16 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V - -62 -67 -64 -40 -40 -40 dBc +27.2 dBm +16 dBm +16 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V Power-Added Efficiency (1) - 42 23.5 19.5 - % +27.2 dBm +16 dBm +16 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V Noise emissions B34 - -38 - LTE NS_05 PHS emissions - -48 - Spurious Output Level (all spurious outputs) Load mismatch stress with no permanent degradation or failure 2010 - 2025 MHz, 100 RB QPSK dBm/MHz LTE signal centered at 1970 MHz at LTE max power dBm/ 300 kHz - - <-70 dBc 8:1 - - VSWR Notes: (1) ACLR and Efficiency measured at 1880 MHz. 5 DATA SHEET - Rev 2.0 08/2014 1884.5 - 1919.6 MHz POUT < +27.2 dBm In-band load VSWR < 5:1 Out-of-band load VSWR < 10:1 Applies over all operating conditions Applies over full operating range AWT6652 Table 6: B 2 (1850 - 1910 MHz) Electrical Specifications - CDMA Operation (CDMA2000, RC-1) (TC = +25 °C, VCC = VBATT = +3.4 V, VEN = +1.8 V, 50 Ω system, unless otherwise specified) PARAMETER MIN TYP MAX UNIT Gain 24.5 - 27 24.5 15.5 30 - Adjacent Channel Power (1) at +1.25 MHz offset Primary Channel BW = 1.23 MHz Adjacent Channel BW = 30 kHz - -50 -66 -59 Adjacent Channel Power (1) at +1.98 MHz offset Primary Channel BW = 1.23 MHz Adjacent Channel BW = 30 kHz - Power-Added Efficiency (1) - Spurious Output Level (all spurious outputs) Load mismatch stress with no permanent degradation or failure POUT VCC VMODE1 dB +28 dBm +16 dBm +16 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V -46 -46 -46 dBc +28 dBm +16 dBm +16 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V -55 -74 -61 -53 -53 -53 dBc +28 dBm +16 dBm +16 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V 45 23 19.5 - % +28 dBm +16 dBm +16 dBm 3.4 V 1.5 V 3.4 V 0V 0V 1.8 V - - <-70 dBc 8:1 - - VSWR Notes: (1) ACLR and Efficiency measured at 1880 MHz. 6 COMMENTS DATA SHEET - Rev 2.0 08/2014 POUT < +28 dBm In-band load VSWR < 5:1 Out-of-band load VSWR < 10:1 Applies over all operating conditions Applies over full operating range AWT6652 Table 7: B 1 (1920 - 1980 MHz) Electrical Specifications - WCDMA Operation (R99 waveform) (TC = +25 °C, VCC = VBATT = +3.4 V, VEN = +1.8 V, 50 Ω system, unless otherwise specified) PARAMETER MIN TYP MAX UNIT 24 12 26 15 29 17.5 ACLR1 at 5 MHz offset (1) - -40 -42 ACLR2 at 10 MHz offset (1) - Power-Added Efficiency (1) COMMENTS POUT VCC VMODE1 dB +27.3 dBm +17 dBm 3.4 V 3.4 V 0V 1.8 V -36 -36 dBc +27.3 dBm +17 dBm 3.4 V 3.4 V 0V 1.8 V -52 -55 -47 -47 dBc +27.3 dBm +17 dBm 3.4 V 3.4 V 0V 1.8 V 35 17 40 23 - % +27.3 dBm +17 dBm 3.4 V 3.4 V 0V 1.8 V Quiescent Current (Icq) Low Bias Mode - 18 - mA through VCC pin, VMODE1 = +1.8 V Mode Control Current - 0.16 - mA through VMODE pin, VMODE1 = 1.8 V Enable Current - 0.02 - mA through VENABLE pin BATT Current - 2.8 - mA through VBATT pin, VMODE1 = +1.8 V Leakage Current - 3 10 µA VBATT = +4.4 V, VCC = +4.4 V VENABLE = 0 V, VMODE1 = 0 V Noise in Receive Band (2) - -135 -140 - dBm/Hz Harmonics 2fO 3fO, 4fO - -43 -55 - dBc Input Impedance - - 2:1 VSWR Coupling Factor Gain POUT < +27.3 dBm, VMODE1 = 0 V POUT < 17 dBm, VMODE1 = +1.8 V POUT < +27.3 dBm 17 20 23 dB Directivity - 20 - dB Coupler IN-OUT Daisy Chain Insertion Loss - <0.25 - dB 698 to 2620 MHz Pin 8 to 6 Shutdown Mode POUT < +27.3 dBm In-band load VSWR < 5:1 Out-of-band load VSWR < 10:1 Applies over all operating conditions Spurious Output Level (all suprious outputs) Load mismatch stress with no permanent degradation or failure Phase Delta (HPM-LPM) - - -70 dBc 8:1 - - VSWR - 10 - Deg Notes: (1) ACLR and Efficiency measured at 1950 MHz. (2) Noise measured at 2110 MHz to 2170 MHz. 7 DATA SHEET - Rev 2.0 08/2014 Applies over full operating range AWT6652 APPLICATION INFORMATION To ensure proper performance, refer to all related Application Notes on the ANADIGICS web site: http://www.anadigics.com Shutdown Mode The power amplifier may be placed in a shutdown mode by applying logic low levels (see Operating Ranges table) to the VENABLE and VMODE1 voltages. Bias Modes The power amplifier may be placed in either a Low Bias mode or a High Bias mode by applying the appropriate logic level (see Operating Ranges table) to VMODE1. The Bias Control table lists the recommended modes of operation for various applications. VMODE2 is not necessary for this PA. Two operating modes are available to optimize current consumption. High Bias/High Power operating mode is for POUT levels > 16 dBm. At around 17 dBm output power, the PA should be “Mode Switched” to Low power mode for lowest quiescent current consumption. Vcontrols Venable/Vmode(s) On Sequence Start T_0N = 0µ Rise/Fall Max 1µS Defined at 10% to 90% of Min/Max Voltage Off Sequence Start T_0FF = 0µ ON Sequence OFF Sequence RFIN notes 1,2 VEN VCC note 1 T_0N+1µS T_0N+3µS Referenced After 90% of Rise Time T_0FF+2µS T_0FF+3µS Referenced Before10% of Fall Time Figure 3: Recommended ON/OFF Timing Sequence Notes: (1) Level might be changed after RF is ON. (2) RF OFF defined as PIN ≤ -30 dBm. (3) Switching simultaneously between VMODE and VEN is not recommended. 8 DATA SHEET - Rev 2.0 08/2014 AWT6652 Table 8: Bias Control POUT LEVELS BIAS MODE VENABLE VMODE1 VCC VBATT High power (High Bias Mode) > +16 dBm High +1.8 V 0V 1.5 - 4.4 V > 3.1 V Med/low power (Low Bias Mode) ≤ +17 dBm Low +1.8 V +1.8 V 0.6 - 4.4 V > 3.1 V - Shutdown 0V 0V 0.6 - 4.4 V > 3.1 V APPLICATION Shutdown 9 DATA SHEET - Rev 2.0 08/2014 AWT6652 VBATT VCC C2 2.2 µF C1 33pF GND at slug 1 2 RFIN 3 VMODE2 VMODE1 VEN 10 VBATT VCC RFIN RFOUT N/C 4 VMODE1 5 VEN CPLIN 8 GND 7 VMODE1 VEN GND GND VMODE2 VCC GND GND C1 RFOUT C4 C3 CPLOUT VBATT Figure 4: Evaluation Board Schematic RFIN CPLIN Figure 5: Evaluation Board Layout 10 DATA SHEET - Rev 2.0 08/2014 C4 2.2µF ceramic 9 CPLOUT 6 C2 C3 0.1µF RFOUT CPLIN CPLOUT AWT6652 ProEficientTM The AWT6652 power amplifier module is based on ANADIGICS proprietary ProEficient™ technology. The PA is designed to operate up to 17 dBm in the low power mode, thus eliminating the need for three gain states, while still maintaining low quiescent current and high efficiency in low and medium power levels. Average weighted efficiency can be increased by using an external switch mode power supply (SMPS) or DC/DC converter to reduce VCC. The directional “daisy chainable” coupler is integrated within the PA module, therefore there is no need for external couplers. voltage source. The PA is turn on/off is controlled by VEN pin. A single VMODE control logic (VMODE1) is needed to operate this device. AWT6652 requires only two calibration sweeps for system calibration, thus saving calibration time. Figure 6 shows one application example on mobile board. C1 and C2 are RF bypass caps and should be placed nearby pin 1 and pin 10. Bypass caps C3 and C4 may not be needed. Also a “T” matching topology is recommended at PA RFIN and RFOUT ports to provide matching between input TX Filter and Duplexer / Isolator. The AWT6652 has an integrated voltage regulator, which eliminates the need for an external constant SMPS VBATT C2 GND RFIN TX filter C1 C3 GND at slug GND VBATT VCC RFIN RFOUT N/C CPL IN VMODE1 VEN GND GND RFOUT 50Ω GND To Detector PA_R0 PA_ON Figure 6: Typical Application Circuit 11 DATA SHEET - Rev 2.0 08/2014 GND Duplexer CPLOUT BB C4 AWT6652 PACKAGE OUTLINE Figure 7: Package Outline - 10 Pin 3 mm x 3 mm x 0.9 mm Surface Mount Module Pin 1 Identifier Date Code YY=Year; WW=Work week 6652 Part Number LLLLNN YYWWCC Lot Number Country Code (CC) Figure 8: Branding Specification 12 DATA SHEET - Rev 2.0 08/2014 AWT6652 PCB AND STENCIL DESIGN GUIDELINE Figure 9: Recommended PCB Layout Information 13 DATA SHEET - Rev 2.0 08/2014 AWT6652 COMPONENT PACKAGING Pin 1 Figure 10: Carrier Tape Figure 11: Reel 14 DATA SHEET - Rev 2.0 08/2014 AWT6652 ORDERING INFORMATION ORDER NUMBER TEMPERATURE RANGE PACKAGE DESCRIPTION COMPONENT PACKAGING AWT6652Q7 -30 oC to +90 oC RoHS Compliant 10 Pin 3 mm x 3 mm x 0.9 mm Surface Mount Module Tape and Reel, 2500 pieces per Reel AWT6652P9 -30 oC to +90 oC RoHS Compliant 10 Pin 3 mm x 3 mm x 0.9 mm Partial Tape and Reel Surface Mount Module ANADIGICS, Inc. 141 Mount Bethel Road Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. WARNING ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. 15 DATA SHEET - Rev 2.0 08/2014