EN25QH256 EN25QH256 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector FEATURES • Single power supply operation - Full voltage range: 2.7-3.6 volt • Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 • 256 M-bit Serial Flash - 256 M-bit/32,768 K-byte/131,072 pages - 256 bytes per programmable page • - Standard, Dual or Quad SPI Standard SPI: CLK, CS#, DI, DO, WP#, HOLD# Dual SPI: CLK, CS#, DQ0, DQ1, WP#, HOLD# Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3 • - High performance 80MHz clock rate for Standard SPI 80MHz clock rate for two data bits 50MHz clock rate for four data bits • Low power consumption - 12 mA typical active current - 1 μA typical power down current • - Uniform Sector Architecture: 8192 sectors of 4-Kbyte 512 blocks of 64-Kbyte Any sector or block can be erased individually • Software and Hardware Write Protection: - Write Protect all or portion of memory via software - Enable/Disable protection with WP# pin • - High performance program/erase speed Page program time: 0.8ms typical Sector erase time: 50ms typical Block erase time 400ms typical Chip erase time: 100 seconds typical • Lockable 512 byte OTP security sector • Support Serial Flash Discoverable Parameters (SFDP) signature • Read Unique ID Number • Support High Bank Latch Mode • Minimum 100K endurance cycle • Package Options - 8 contact VDFN (6x8mm) - 16 pins SOP 300mil body width - 24 balls BGA (6x8mm) - All Pb-free packages are RoHS compliant • Industrial temperature Range GENERAL DESCRIPTION The EN25QH256 is a 256 Megabit (32,768 K-byte) Serial Flash memory, with enhanced write protection mechanisms. The EN25QH256 supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ0(DI), DQ1(DO), DQ2(WP#) and DQ3(HOLD#). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz (80MHz x 2) for Dual Output when using the Dual Output Fast Read instructions, and SPI clock frequencies of up to 50MHz are supported allowing equivalent clock rates of 200MHz (50MHz x 4) for Quad Output when using the Quad Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The EN25QH256 is designed to allow either single Sector/Block at a time or full chip erase operation. The EN25QH256 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector or block. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 1 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure.1 CONNECTION DIAGRAMS CS# 1 8 VCC DO (DQ1) 2 7 HOLD# (DQ3) WP# (DQ2) 3 6 CLK 4 5 DI (DQ0) VSS 8 - LEAD VDFN 16 - LEAD SOP This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 2 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Top View, Balls Facing Down 24 - Ball BGA This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 3 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 2. BLOCK DIAGRAM Note: 1. DQ0 and DQ1 are used for Dual and Quad instructions. 2. DQ0 ~ DQ3 are used for Quad instructions. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 4 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 1. Pin Names Symbol Pin Name CLK Serial Clock Input DI (DQ0) Serial Data Input (Data Input Output 0) DO (DQ1) Serial Data Output (Data Input Output 1) CS# Chip Select WP# (DQ2) Write Protect (Data Input Output 2) HOLD# (DQ3) HOLD# pin (Data Input Output 3) Vcc Supply Voltage (2.7-3.6V) Vss Ground NC No Connect *1 *1 *2 *2 Note: 1. DQ0 and DQ1 are used for Dual and Quad instructions. 2. DQ2 ~ DQ3 are used for Quad instructions. SIGNAL DESCRIPTION Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3) The EN25QH256 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Mode") Chip Select (CS#) The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When CS# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. Hold (HOLD#) The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial Data IO (DQ3) for Quad I/O operation. Write Protect (WP#) The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial Data IO (DQ2) for Quad I/O operation. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 5 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 MEMORY ORGANIZATION The memory is organized as: z 33,554,432 bytes z Uniform Sector Architecture 512 blocks of 64-Kbyte 8,192 sectors of 4-Kbyte 131,072 pages (256 bytes each) Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block or Chip Erasable but not Page Erasable. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 6 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 2. Uniform Block Sector Architecture ( 1/8 ) 7424 1D00000h 1D00FFFh 449 448 …. …. …. …. …. …. …. …. …. …. 1E10FFFh 1E0FFFFh …. …. …. 1E10000h 1E0F000h …. 7696 7695 …. …. …. 1E20FFFh 1E1FFFFh …. 1E20000h 1E1F000h 7680 1E00000h 1E00FFFh 1CF0000h 1CEF000h 1CF0FFFh 1CEFFFFh 1CE0000h 1CDF000h 1CE0FFFh 1CDFFFFh …. 7392 7391 …. …. 7408 7407 …. …. Address range 1CFF000h 1CFFFFFh …. Sector 7423 7376 1CD0000h 1CD0FFFh 1C2FFFFh …. 1C2F000h …. 7215 7200 7199 1C20000h 1C1F000h 1C20FFFh 1C1FFFFh …. 1D10FFFh 1D0FFFFh 7712 7711 7184 7183 1C10000h 1C0F000h 1C10FFFh 1C0FFFFh …. 1D10000h 1D0F000h …. 7440 7439 …. …. 1D20FFFh 1D1FFFFh …. 1D20000h 1D1F000h 1E2FFFFh …. 7456 7455 450 1E2F000h …. 1D2FFFFh 7727 …. 1D2F000h 461 …. 7471 462 1ED0FFFh …. 1DD0FFFh …. 1DD0000h …. 7632 463 1ED0000h …. 1DE0FFFh 1DDFFFFh …. 1DE0000h 1DDF000h …. 7648 7647 Block 7888 …. …. 1DF0FFFh 1DEFFFFh …. 1DF0000h 1DEF000h …. 7664 7663 …. …. Address range 1DFF000h 1DFFFFFh …. Sector 7679 480 1EE0FFFh 1EDFFFFh …. 1F00FFFh 1EE0000h 1EDF000h …. 1F00000h 481 7904 7903 …. 7936 482 1EF0FFFh 1EEFFFFh …. …. 1F10FFFh 1F0FFFFh …. 1F10000h 1F0F000h …. 7952 7951 493 1EF0000h 1EEF000h …. …. 1F20FFFh 1F1FFFFh …. …. …. …. …. 1F20000h 1F1F000h …. …. …. …. …. …. …. …. 7968 7967 …. 1F2FFFFh …. 464 1F2F000h …. 465 7983 …. …. 466 1FD0FFFh 7920 7919 …. 477 1FD0000h 494 Address range 1EFF000h 1EFFFFFh …. 478 8144 495 Sector 7935 …. 479 1FE0FFFh 1FDFFFFh Block …. Block 1FE0000h 1FDF000h …. 496 8160 8159 …. 497 1FF0FFFh 1FEFFFFh …. …. 498 1FF0000h 1FEF000h …. 509 8176 8175 …. 510 Address range 1FFF000h 1FFFFFFh …. 511 Sector 8191 …. Block 7168 1C00000h 1C00FFFh This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 7 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 2. Uniform Block Sector Architecture ( 2/8 ) 6400 1900000h 1900FFFh 385 384 …. …. …. …. …. …. …. …. …. …. 1A10FFFh 1A0FFFFh …. …. …. 1A10000h 1A0F000h …. 6672 6671 …. …. …. 1A20FFFh 1A1FFFFh …. 1A20000h 1A1F000h 6656 1A00000h 1A00FFFh 18F0000h 18EF000h 18F0FFFh 18EFFFFh 18E0000h 18DF000h 18E0FFFh 18DFFFFh …. 6368 6367 …. …. 6384 6383 …. …. Address range 18FF000h 18FFFFFh …. Sector 6399 6352 18D0000h 18D0FFFh 182FFFFh …. 182F000h …. 6191 6176 6175 1820000h 181F000h 1820FFFh 181FFFFh …. 1910FFFh 190FFFFh 6688 6687 6160 6159 1810000h 180F000h 1810FFFh 180FFFFh …. 1910000h 190F000h …. 6416 6415 …. …. 1920FFFh 191FFFFh …. 1920000h 191F000h 1A2FFFFh …. 6432 6431 386 1A2F000h …. 192FFFFh 6703 …. 192F000h 397 …. 6447 398 1AD0FFFh …. 19D0FFFh …. 19D0000h …. 6608 399 1AD0000h …. 19E0FFFh 19DFFFFh …. 19E0000h 19DF000h …. 6624 6623 Block 6864 …. …. 19F0FFFh 19EFFFFh …. 19F0000h 19EF000h …. 6640 6639 …. …. Address range 19FF000h 19FFFFFh …. Sector 6655 416 1AE0FFFh 1ADFFFFh …. 1B00FFFh 1AE0000h 1ADF000h …. 1B00000h 417 6880 6879 …. 6912 418 1AF0FFFh 1AEFFFFh …. …. 1B10FFFh 1B0FFFFh …. 1B10000h 1B0F000h …. 6928 6927 429 1AF0000h 1AEF000h …. …. 1B20FFFh 1B1FFFFh …. …. …. …. …. 1B20000h 1B1F000h …. …. …. …. …. …. …. …. 6944 6943 …. 1B2FFFFh …. 400 1B2F000h …. 401 6959 …. …. 402 1BD0FFFh 6896 6895 …. 413 1BD0000h 430 Address range 1AFF000h 1AFFFFFh …. 414 7120 431 Sector 6911 …. 415 1BE0FFFh 1BDFFFFh Block …. Block 1BE0000h 1BDF000h …. 432 7136 7135 …. 433 1BF0FFFh 1BEFFFFh …. …. 434 1BF0000h 1BEF000h …. 445 7152 7151 …. 446 Address range 1BFF000h 1BFFFFFh …. 447 Sector 7167 …. Block 6144 1800000h 1800FFFh This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 8 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 2. Uniform Block Sector Architecture ( 3/8 ) 5376 1500000h 1500FFFh 321 320 …. …. …. …. …. …. …. …. …. …. …. …. 1620FFFh 161FFFFh …. …. 1620000h 161F000h …. 5664 5663 5648 5647 …. 5632 1610000h 160F000h …. 1600000h 1610FFFh 160FFFFh …. 1600FFFh …. 14F0000h 14EF000h 14F0FFFh 14EFFFFh 14E0000h 14DF000h 14E0FFFh 14DFFFFh …. 5344 5343 …. …. 5360 5359 …. …. Address range 14FF000h 14FFFFFh …. Sector 5375 5328 14D0000h 14D0FFFh 142FFFFh …. 142F000h …. 5167 5152 5151 1420000h 141F000h 1420FFFh 141FFFFh …. 1510FFFh 150FFFFh 162FFFFh 5136 5135 1410000h 140F000h 1410FFFh 140FFFFh …. 1510000h 150F000h …. 5392 5391 …. …. 1520FFFh 151FFFFh …. 1520000h 151F000h 162F000h …. 5408 5407 322 5679 …. 152FFFFh 333 16D0FFFh …. 152F000h 334 …. 5423 335 16D0000h …. 15D0FFFh …. 15D0000h …. 5584 Block 5840 …. 15E0FFFh 15DFFFFh …. 15E0000h 15DF000h …. 5600 5599 352 16E0FFFh 16DFFFFh …. …. 15F0FFFh 15EFFFFh …. 15F0000h 15EF000h …. 5616 5615 …. …. Address range 15FF000h 15FFFFFh …. Sector 5631 353 16E0000h 16DF000h …. 1710FFFh 170FFFFh …. 1700FFFh 5856 5855 …. 1710000h 170F000h …. 1700000h 354 16F0FFFh 16EFFFFh …. 5904 5903 …. 5888 365 16F0000h 16EF000h …. …. 1720FFFh 171FFFFh …. …. …. …. …. 1720000h 171F000h …. …. …. …. …. …. …. …. 5920 5919 …. 172FFFFh …. 336 172F000h …. 337 5935 …. …. 338 17D0FFFh 5872 5871 …. 349 17D0000h 366 Address range 16FF000h 16FFFFFh …. 350 6096 367 Sector 5887 …. 351 17E0FFFh 17DFFFFh Block …. Block 17E0000h 17DF000h …. 368 6112 6111 …. 369 17F0FFFh 17EFFFFh …. …. 370 17F0000h 17EF000h …. 381 6128 6127 …. 382 Address range 17FF000h 17FFFFFh …. 383 Sector 6143 …. Block 5120 1400000h 1400FFFh This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 9 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 2. Uniform Block Sector Architecture ( 4/8 ) 4353 1100000h 1100FFFh 257 256 …. …. …. …. …. …. …. …. …. …. 1210FFFh 120FFFFh …. …. …. 1210000h 120F000h …. 4624 4623 …. …. …. 1220FFFh 121FFFFh …. 1220000h 121F000h 4608 1200000h 1200FFFh 10F0000h 10EF000h 10F0FFFh 10EFFFFh 10E0000h 10DF000h 10E0FFFh 10DFFFFh …. 4320 4319 …. …. 4336 4335 …. …. Address range 10FF000h 10FFFFFh …. Sector 4351 4304 10D0000h 10D0FFFh 102FFFFh …. 102F000h …. 4143 4128 4127 1020000h 101F000h 1020FFFh 101FFFFh …. 1110FFFh 110FFFFh 4640 4639 4112 4111 1010000h 100F000h 1010FFFh 100FFFFh …. 1110000h 110F000h …. 4368 4367 …. …. 1120FFFh 111FFFFh …. 1120000h 111F000h 122FFFFh …. 4384 4383 258 122F000h …. 112FFFFh 4655 …. 112F000h 269 …. 4399 270 12D0FFFh …. 11D0FFFh …. 11D0000h …. 4560 271 12D0000h …. 11E0FFFh 11DFFFFh …. 11E0000h 11DF000h …. 4576 4575 Block 4816 …. …. 11F0FFFh 11EFFFFh …. 11F0000h 11EF000h …. 4592 4591 …. …. Address range 11FF000h 11FFFFFh …. Sector 4606 288 12E0FFFh 12DFFFFh …. 1300FFFh 12E0000h 12DF000h …. 1300000h 289 4831 4831 …. 4864 290 12F0FFFh 12EFFFFh …. …. 1310FFFh 130FFFFh …. 1310000h 130F000h …. 4880 4879 301 12F0000h 12EF000h …. …. 1320FFFh 131FFFFh …. …. …. …. …. 1320000h 131F000h …. …. …. …. …. …. …. …. 4896 4895 …. 132FFFFh …. 272 132F000h …. 273 4911 …. …. 274 13D0FFFh 4848 4847 …. 285 13D0000h 302 Address range 12FF000h 12FFFFFh …. 286 5072 303 Sector 4863 …. 287 13E0FFFh 13DFFFFh Block …. Block 13E0000h 13DF000h …. 304 5088 5087 …. 305 13F0FFFh 13EFFFFh …. …. 306 13F0000h 13EF000h …. 317 5104 5103 …. 318 Address range 13FF000h 13FFFFFh …. 319 Sector 5119 …. Block 4096 1000000h 1000FFFh This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 10 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 2. Uniform Block Sector Architecture ( 5/8 ) 3328 0D00000h 0D00FFFh 193 192 …. …. …. …. …. …. …. …. …. …. 0E10FFFh 0E0FFFFh …. …. …. 0E10000h 0E0F000h …. 3600 3599 …. …. …. 0E20FFFh 0E1FFFFh …. 0E20000h 0E1F000h 3584 0E00000h 0E00FFFh 0CF0000h 0CEF000h 0CF0FFFh 0CEFFFFh 0CE0000h 0CDF000h 0CE0FFFh 0CDFFFFh …. 3296 3295 …. …. 3312 3311 …. …. Address range 0CFF000h 0CFFFFFh …. Sector 3327 3280 0CD0000h 0CD0FFFh 0C2FFFFh …. 0C2F000h …. 3119 3014 3103 0C20000h 0C1F000h 0C20FFFh 0C1FFFFh …. 0D10FFFh 0D0FFFFh 3616 3615 3088 3087 0C10000h 0C0F000h 0C10FFFh 0C0FFFFh …. 0D10000h 0D0F000h …. 3344 3343 …. …. 0D20FFFh 0D1FFFFh …. 0D20000h 0D1F000h 0E2FFFFh …. 3360 3359 194 0E2F000h …. 0D2FFFFh 3631 …. 0D2F000h 205 …. 3375 206 0ED0FFFh …. 0DD0FFFh …. 0DD0000h …. 3536 207 0ED0000h …. 0DE0FFFh 0DDFFFFh …. 0DE0000h 0DDF000h …. 3552 3551 Block 3792 …. …. 0DF0FFFh 0DEFFFFh …. 0DF0000h 0DEF000h …. 3568 3567 …. …. Address range 0DFF000h 0DFFFFFh …. Sector 3583 224 0EE0FFFh 0EDFFFFh …. 0F00FFFh 0EE0000h 0EDF000h …. 0F00000h 225 3808 3807 …. 3840 226 0EF0FFFh 0EEFFFFh …. …. 0F10FFFh 0F0FFFFh …. 0F10000h 0F0F000h …. 3856 3855 237 0EF0000h 0EEF000h …. …. 0F20FFFh 0F1FFFFh …. …. …. …. …. 0F20000h 0F1F000h …. …. …. …. …. …. …. …. 3872 3871 …. 0F2FFFFh …. 208 0F2F000h …. 209 3887 …. …. 210 0FD0FFFh 3824 3823 …. 221 0FD0000h 238 Address range 0EFF000h 0EFFFFFh …. 222 4048 239 Sector 3839 …. 223 0FE0FFFh 0FDFFFFh Block …. Block 0FE0000h 0FDF000h …. 240 4064 4063 …. 241 0FF0FFFh 0FEFFFFh …. …. 242 0FF0000h 0FEF000h …. 253 4080 4079 …. 254 Address range 0FFF000h 0FFFFFFh …. 255 Sector 4095 …. Block 3072 0C00000h 0C00FFFh This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 11 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 2. Uniform Block Sector Architecture ( 6/8) 2304 0900000h 0900FFFh 129 128 …. …. …. …. …. …. …. …. …. …. 0A10FFFh 0A0FFFFh …. …. …. 0A10000h 0A0F000h …. 2576 2575 …. …. …. 0A20FFFh 0A1FFFFh …. 0A20000h 0A1F000h 2560 0A00000h 0A00FFFh 08F0000h 08EF000h 08F0FFFh 08EFFFFh 08E0000h 08DF000h 08E0FFFh 08DFFFFh …. 2272 2271 …. …. 2288 2287 …. …. Address range 08FF000h 08FFFFFh …. Sector 2303 2256 08D0000h 08D0FFFh 082FFFFh …. 082F000h …. 2095 2080 2079 0820000h 081F000h 0820FFFh 081FFFFh …. 0910FFFh 090FFFFh 2592 2591 2064 2063 0810000h 080F000h 0810FFFh 080FFFFh …. 0910000h 090F000h …. 2320 2319 …. …. 0920FFFh 091FFFFh …. 0920000h 091F000h 0A2FFFFh …. 2336 2335 130 0A2F000h …. 092FFFFh 2607 …. 092F000h 141 …. 2351 142 0AD0FFFh …. 09D0FFFh …. 09D0000h …. 2512 143 0AD0000h …. 09E0FFFh 09DFFFFh …. 09E0000h 09DF000h …. 2528 2527 Block 2768 …. …. 09F0FFFh 09EFFFFh …. 09F0000h 09EF000h …. 2544 2543 …. …. Address range 09FF000h 09FFFFFh …. Sector 2559 160 0AE0FFFh 0ADFFFFh …. 0B00FFFh 0AE0000h 0ADF000h …. 0B00000h 161 2784 2783 …. 2816 162 0AF0FFFh 0AEFFFFh …. …. 0B10FFFh 0B0FFFFh …. 0B10000h 0B0F000h …. 2832 2831 173 0AF0000h 0AEF000h …. …. 0B20FFFh 0B1FFFFh …. …. …. …. …. 0B20000h 0B1F000h …. …. …. …. …. …. …. …. 2848 2847 …. 0B2FFFFh …. 144 0B2F000h …. 145 2863 …. …. 146 0BD0FFFh 2800 2799 …. 157 0BD0000h 174 Address range 0AFF000h 0AFFFFFh …. 158 3024 175 Sector 2815 …. 159 0BE0FFFh 0BDFFFFh Block …. Block 0BE0000h 0BDF000h …. 176 3040 3039 …. 177 0BF0FFFh 0BEFFFFh …. …. 178 0BF0000h 0BEF000h …. 189 3056 3055 …. 190 Address range 0BFF000h 0BFFFFFh …. 191 Sector 3071 …. Block 2048 0800000h 0800FFFh This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 12 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 2. Uniform Block Sector Architecture ( 7/8 ) 1280 0500000h 0500FFFh 65 64 …. …. …. …. …. …. …. …. …. …. 0610FFFh 060FFFFh …. …. …. 0610000h 060F000h …. 1552 1551 …. …. …. 0620FFFh 061FFFFh …. 0620000h 061F000h 1536 0600000h 0600FFFh 04F0000h 04EF000h 04F0FFFh 04EFFFFh 04E0000h 04DF000h 04E0FFFh 04DFFFFh …. 1248 1247 …. …. 1264 1263 …. …. Address range 04FF000h 04FFFFFh …. Sector 1279 1232 04D0000h 04D0FFFh 042FFFFh …. 042F000h …. 1071 1056 1055 0420000h 041F000h 0420FFFh 041FFFFh …. 0510FFFh 050FFFFh 1568 1567 1040 1039 0410000h 040F000h 0410FFFh 040FFFFh …. 0510000h 050F000h …. 1296 1295 …. …. 0520FFFh 051FFFFh …. 0520000h 051F000h 062FFFFh …. 1312 1311 66 062F000h …. 052FFFFh 1583 …. 052F000h 77 …. 1327 78 06D0FFFh …. 05D0FFFh …. 05D0000h …. 1488 79 06D0000h …. 05E0FFFh 05DFFFFh …. 05E0000h 05DF000h …. 1504 1503 Block 1744 …. …. 05F0FFFh 05EFFFFh …. 05F0000h 05EF000h …. 1520 1519 …. …. Address range 05FF000h 05FFFFFh …. Sector 1535 96 06E0FFFh 06DFFFFh …. 0700FFFh 06E0000h 06DF000h …. 0700000h 97 1760 1759 …. 1972 98 06F0FFFh 06EFFFFh …. …. 0710FFFh 070FFFFh …. 0710000h 070F000h …. 1808 1807 109 06F0000h 06EF000h …. …. 0720FFFh 071FFFFh …. …. …. …. …. 0720000h 071F000h …. …. …. …. …. …. …. …. 1824 1823 …. 072FFFFh …. 80 072F000h …. 81 1839 …. …. 82 07D0FFFh 1776 1775 …. 93 07D0000h 110 Address range 06FF000h 06FFFFFh …. 94 2000 111 Sector 1791 …. 95 07E0FFFh 07DFFFFh Block …. Block 07E0000h 07DF000h …. 112 2016 2015 …. 113 07F0FFFh 07EFFFFh …. …. 114 07F0000h 07EF000h …. 125 2032 2031 …. 126 Address range 07FF000h 07FFFFFh …. 127 Sector 2047 …. Block 1024 0400000h 0400FFFh This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 13 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 2. Uniform Block Sector Architecture ( 8/8 ) 256 0100000h 0100FFFh 1 0 …. …. …. …. …. …. …. …. …. …. 0210FFFh 020FFFFh …. …. …. 0210000h 020F000h …. 528 527 …. …. …. 0220FFFh 021FFFFh …. 0220000h 021F000h 512 0200000h 0200FFFh 00F0000h 00EF000h 00F0FFFh 00EFFFFh 00E0000h 00DF000h 00E0FFFh 00DFFFFh …. 224 223 …. …. 240 239 …. …. Address range 00FF000h 00FFFFFh …. Sector 255 208 00D0000h 00D0FFFh 002FFFFh …. 002F000h …. 47 32 31 0020000h 001F000h 0020FFFh 001FFFFh …. 0110FFFh 010FFFFh 544 543 16 15 0010000h 000F000h 0010FFFh 000FFFFh …. 0110000h 010F000h …. 272 271 …. …. 0120FFFh 011FFFFh …. 0120000h 011F000h 022FFFFh …. 288 287 2 022F000h …. 012FFFFh 559 …. 012F000h 13 …. 303 14 02D0FFFh …. 01D0FFFh …. 01D0000h …. 464 15 02D0000h …. 01E0FFFh 01DFFFFh …. 01E0000h 01DF000h …. 480 479 Block 720 …. …. 01F0FFFh 01EFFFFh …. 01F0000h 01EF000h …. 496 495 …. …. Address range 01FF000h 01FFFFFh …. Sector 511 32 02E0FFFh 02DFFFFh …. 0300FFFh 02E0000h 02DF000h …. 0300000h 736 735 …. 768 33 02F0FFFh 02EFFFFh …. …. 0310FFFh 030FFFFh …. 0310000h 030F000h …. 784 783 34 02F0000h 02EF000h …. …. …. 0320FFFh 031FFFFh …. …. …. …. …. 0320000h 031F000h …. …. …. …. …. …. …. 800 799 …. 032FFFFh …. 16 032F000h …. 17 815 …. …. 18 03D0FFFh 45 752 751 …. 29 03D0000h 46 Address range 02FF000h 02FFFFFh …. 30 976 47 Sector 767 …. 31 03E0FFFh 03DFFFFh Block …. Block 03E0000h 03DF000h …. 48 992 991 …. 49 03F0FFFh 03EFFFFh …. …. 50 03F0000h 03EF000h …. 61 1008 1007 …. 62 Address range 03FF000h 03FFFFFh …. 63 Sector 1023 …. Block 4 3 2 1 0 0004000h 0003000h 0002000h 0001000h 0000000h 0004FFFh 0003FFFh 0002FFFh 0001FFFh 0000FFFh This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 14 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 OPERATING FEATURES Standard SPI Modes The EN25QH256 is accessed through a SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK. Figure 3. SPI Modes Dual SPI Instruction The EN25QH256 supports Dual SPI operation when using the “Dual Output Fast Read and Dual I/O Fast Read “ (3Bh and BBh) instructions. These instructions allow data to be transferred to or from the Serial Flash memory at two to three times the rate possible with the standard SPI. The Dual Read instructions are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing) or for application that cache code-segments to RAM for execution. The Dual output feature simply allows the SPI input pin to also serve as an output during this instruction. When using Dual SPI instructions the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1. All other operations use the standard SPI interface with single output signal. Quad SPI Instruction The EN25QH256 supports Quad output operation when using the Quad I/O Fast Read (EBh).This instruction allows data to be transferred to or from the Serial Flash memory at four to six times the rate possible with the standard SPI. The Quad Read instruction offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or for application that cache code-segments to RAM for execution. The EN25QH256 also supports full Quad Mode function while using the Enable Quad Peripheral Interface mode (EQPI) (38h). When using Quad SPI instruction the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1, and the WP# and HOLD# pins become DQ2 and DQ3 respectively. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 15 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 4. Quad SPI Modes Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0) provided that they lie in consecutive addresses on the same page of memory. Sector Erase, Block Erase and Chip Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time, using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration tSE tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Polling During a Write, Program or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or CE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, and Write Status Register). The device then goes into the Stand-by Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI) instruction) is executed. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 16 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. Status Register and Information Register The Status Register and Information Register contain a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. QE bit. The Quad Enable (QE) bit, non-volatile bit, enable bit only for Quad Input/Output FAST_READ (EBh) in SPI command. When it is “0” (factory default), it disables Quad Input/Output FAST_READ (EBh) in SPI command and WP#, HOLD# are enabled. While QE is “1”, it enables Quad Input/Output FAST_READ (EBh) in SPI command and WP#, HOLD# are disabled. In other words, in SPI mode, the QE bit needs to be assigned through WRSR to enable or disable SPI command Quad Input/Output FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI), this QE bit becomes no affection since WP# and HOLD# function will be disabled by EQPI mode and Quad Input/Output FAST_READ (EBh) will be always available in EQPI mode. SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRP, BP3, BP2, BP1, BP0) become read-only bits. In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be programmed once. Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1, user must clear the protect bits before entering OTP mode and program the OTP code, then execute WRSR command to lock the OTP sector before leaving OTP mode. 4 BYTE Indicator bit. By writing EN4B instruction, the 4 BYTE bit may be set to “1” to access the address length of 32-bit for higher density (larger than 128Mb) memory area. The default state is “0”, which means the mode of 24-bit address. The 4 BYTE bit may be clear by power off or writing EX4B instruction to reset the state to be “0” Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can indicate whether one or more of program operations fail, and can be reset by Program (PP) or Erase (SE, BE or CE) instructions. Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate whether one or more of erase operations fail, and can be reset by Program (PP) or Erase (SE, BE or CE) instructions. Note : For Program and Erase Flag bits, 1. The flag bits can be reset by power-on or that embedded mode was executed like WRSR, Erase or Program command. 2. If the system is trying to erase a locked block and then program a locked block. The erase fail or program fail flag bit will be high due to no successful Program, Erase or WRSE command. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 17 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the EN25QH256 provides the following data protection mechanisms: z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. z Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: – Power-up – Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction completion z The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode (SPM). z The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM). z In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction). Table 3. Protected Area Sizes Sector Organization Status Register Content BP3 Bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 Bit 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 Bit 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 Bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Memory Content Protect Areas Addresses None Block 511 Block 510 to 511 Block 508 to 511 Block 504 to 511 Block 496 to 511 Block 480 to 511 All None Block 0 Block 0 to 1 Block 0 to 3 Block 0 to 7 Block 0 to 15 Block 0 to 31 All None 1FF0000h-1FFFFFFh 1FE0000h-1FFFFFFh 1FC0000h-1FFFFFFh 1F80000h-1FFFFFFh 1F00000h-1FFFFFFh 1E00000h-1FFFFFFh 0000000h-1FFFFFFh None 0000000h-000FFFFh 0000000h-001FFFFh 0000000h-003FFFFh 0000000h-007FFFFh 0000000h-00FFFFFh 0000000h-01FFFFFh 0000000h-1FFFFFFh Density(KB) None 64KB 128KB 256KB 512KB 1024KB 2048KB 32768KB None 64KB 128KB 256KB 512KB 1024KB 2048KB 32768KB This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 18 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 Portion None Upper 1/512 Upper 2/512 Upper 4/512 Upper 8/512 Upper 16/512 Upper 32/512 All None Lower 1/512 Lower 2/512 Lower 4/512 Lower 8/512 Lower 16/512 Lower 32/512 All www.eonssi.com EN25QH256 INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output FAST_READ (EBh), Read Status Register (RDSR), Read Information Register (RDIFR) or Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down (RES ) minimum number of bytes specified has to be given, without which, the command will be ignored. In the case of Page Program, if the number of byte after the command is less than 4 (at least 1 data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any less or more will cause the command to be ignored. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 19 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 4A. Instruction Set Instruction Name Byte 1 Code EQPI 38h RSTQIO(2) FFh RSTEN 66h RST(1) 99h Write Enable Write Disable / Exit OTP mode Read Status Register Read Information Register Write Status Register Enter 4-byte mode 06h Exit 4-byte mode Enter High Bank Latch Mode Exit High Bank Latch Mode Page Program Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes 04h 05h (S7-S0)(3) continuous(4) 2Bh (S7-S0)(3) continuous(4) 01h S7-S0 B7h E9h 67h 98h 02h (8) A23-A16 A15-A8 A7-A0 Sector Erase 20h (8) A23-A16 A15-A8 A7-A0 Block Erase D8h (8) A23-A16 A15-A8 A7-A0 Chip Erase C7h/ 60h Deep Power-down Release from Deep Power-down, and read Device ID Release from Deep Power-down Manufacturer/ Device ID B9h D7-D0 Next byte continuous (5) dummy dummy dummy (ID7-ID0) 90h dummy dummy 00h 01h Read Identification 9Fh (M7-M0) (ID15-ID8) (ID7-ID0) (7) Enter OTP mode Read SFDP mode and Unique ID Number 3Ah A23-A16 A15-A8 A7-A0 dummy ABh 5Ah (8) (M7-M0) (ID7-ID0) (ID7-ID0) (M7-M0) (D7-D0) (6) (Next Byte) continuous Notes: 1. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset. 2. Device accepts eight-clocks command in Standard SPI mode, or two-clocks command in Quad SPI mode 3. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the device on the DO pin 4. The Status Register contents will repeat continuously until CS# terminate the instruction 5. The Device ID will repeat continuously until CS# terminates the instruction 6. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction. 00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID 7. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity 8. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 20 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 4B. Instruction Set (Read Instruction) Instruction Name Byte 1 Code Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Read Data 03h (6) A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) Fast Read 0Bh (6) A23-A16 A15-A8 A7-A0 dummy (D7-D0) Dual Output Fast Read 3Bh (6) A23-A16 A15-A8 A7-A0 dummy (D7-D0, …) (1) Dual I/O Fast Read BBh (6) A23-A8(2) A7-A0, dummy (2) (D7-D0, …) (1) Quad I/O Fast Read EBh (6) A23-A0, (dummy, dummy (4) D7-D0 ) (5) (D7-D0, …) (3) n-Bytes continuous (Next Byte) continuous (one byte per 4 clocks, continuous) (one byte per 4 clocks, continuous) (one byte per 2 clocks, continuous) Notes: 1. Dual Output data DQ0 = (D6, D4, D2, D0) DQ1 = (D7, D5, D3, D1) 2. Dual Input Address DQ0 = A22, A20, A18, A16, A14, A12, A10, A8 ; A6, A4, A2, A0, dummy 6, dummy 4, dummy 2, dummy 0 DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 ; A7, A5, A3, A1, dummy 7, dummy 5, dummy 3, dummy 1 3. Quad Data DQ0 = (D4, D0, …… ) DQ1 = (D5, D1, …… ) DQ2 = (D6, D2, …... ) DQ3 = (D7, D3, …... ) 4. Quad Input Address DQ0 = A20, A16, A12, A8, A4, A0, dummy 4, dummy 0 DQ1 = A21, A17, A13, A9, A5, A1, dummy 5, dummy 1 DQ2 = A22, A18, A14, A10, A6, A2, dummy 6, dummy 2 DQ3 = A23, A19, A15, A11, A7, A3, dummy 7, dummy 3 5. Quad I/O Fast Read Data DQ0 = ( dummy 12, dummy 8, dummy 4, dummy 0, D4, D0 ) DQ1 = ( dummy 13, dummy 9, dummy 5, dummy 1, D5, D1 ) DQ2 = ( dummy 14, dummy 10, dummy 6, dummy 2, D6, D2 ) DQ3 = ( dummy 15, dummy 11, dummy 7, dummy 3, D7, D3 ) 6. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 21 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 5. Manufacturer and Device Identification OP Code (M7-M0) (ID15-ID0) ABh (ID7-ID0) 18h 90h 1Ch 9Fh 1Ch 18h 7019h Enable Quad Peripheral Interface mode (EQPI) (38h) The Enable Quad Peripheral Interface mode (EQPI) instruction will enable the flash device for Quad SPI bus operation. Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power cycle or “ Reset Quad I/O instruction “ instruction, as shown in Figure 5. The device did not support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh) and Dual Input/Output FAST_READ (BBh) modes while the Enable Quad Peripheral Interface mode (EQPI) (38h) turns on. Figure 5. Enable Quad Peripheral Interface mode Sequence Diagram Reset Quad I/O (RSTQIO) (FFh) The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then, drives CS# high. This command can’t be used in Standard SPI mode. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 22 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) The Reset operation is used as a system (software) reset that puts the device in normal operating Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). To reset the EN25QH256 the host drives CS# low, sends the Reset-Enable command (66h), and drives CS# high. Next, the host drives CS# low again, sends the Reset command (99h), and drives CS# high. The Reset operation requires the Reset-Enable command followed by the Reset command. Any command other than the Reset command after the Reset-Enable command will disable the ResetEnable. A successful command execution will reset the Status register and the Information register to data = 00h, see Figure 6 for SPI Mode and Figure 6.1 for EQPI Mode. A device reset during an active Program or Erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. Depending on the prior operation, the reset timing may vary. Recovery from a Write operation requires more software latency time (tSR) than recovery from other operations. Figure 6. Reset-Enable and Reset Sequence Diagram Figure 6.1 Reset-Enable and Reset Sequence Diagram under EQPI Mode This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 23 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Software Reset Flow Initial Command = 66h ? No Yes Reset enable Command = 99h ? No Yes Reset start No WIP = 0 ? Embedded Reset Cycle Yes Reset done Note: 1. Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) commands need to match standard SPI or EQPI (Quad) mode. 2. Continue (Enhance) EB mode need to use quad Reset-Enable (RSTEN) (66h) and quad Reset (RST) (99h) commands. 3. If user is not sure it is in SPI or Quad mode, we suggest to execute sequence as follows: Quad Reset-Enable (RSTEN) (66h) -> Quad Reset (RST) (99h) -> SPI Reset-Enable (RSTEN) (66h) -> SPI Reset (RST) (99h) to reset. 4. The reset command could be executed during embedded program and erase process, EQPI mode and Continue EB mode to back to SPI mode. 5. This flow cannot release the device from Deep power down mode. 6. The Status Register Bit and Information register Bit will reset to default value after reset done. 7. If user reset device during erase, the embedded reset cycle software reset latency will take about 28us in worst case. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 24 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Write Enable (WREN) (06h) The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High. The instruction sequence is shown in Figure 8.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 7. Write Enable Instruction Sequence Diagram Write Disable (WRDI) (04h) The Write Disable instruction (Figure 8) resets the Write Enable Latch (WEL) bit in the Status Register to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#) high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase (BE) and Chip Erase instructions. The instruction sequence is shown in Figure 8.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 8. Write Disable Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 25 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 8.1 Write Enable/Disable Instruction Sequence under EQPI Mode Read Status Register (RDSR) (05h) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 9. The instruction sequence is shown in Figure 9.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 9. Read Status Register Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 26 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 9.1 Read Status Register Instruction Sequence under EQPI Mode Table 6. Status Register Bit Locations S7 S6 S5 SRP OTP_LOCK Status Register Protect bit (note 1) 1 = status register write disable 1 = OTP sector is protected Non-volatile bit QE (Quad Enable) 1 = Quad enable 0 = not Quad enable BP3 S4 S3 S2 S1 BP2 BP1 BP0 WEL (Block (Block (Block (Block (Write Enable Protected bits) Protected bits) Protected bits) Protected bits) Latch) (note 2) (note 2) (note 2) (note 2) S0 WIP (Write In Progress bit) (Note 3) 1 = write enable 0 = not write enable 1 = write operation 0 = not in write operation volatile bit volatile bit Non-volatile bit Non-volatile bit. Non-volatile bit Non-volatile bit Non-volatile bit Note 1. In OTP mode, SRP bit is served as OTP_LOCK bit. 2. See the table “Protected Area Sizes Sector Organization”. 3. When executed the (RDSR) (05h) command, the OTP_LOCK bit (S7 / in OTP mode) value is the same as OTP_LOCK bit (S1) in table 7. The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3, BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 27 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 (BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1, BP0) bits are 0. QE bit. The Quad Enable (QE) bit, non-volatile bit, enable bit only for Quad Input/Output FAST_READ (EBh) in SPI command. When it is “0” (factory default), it disables Quad Input/Output FAST_READ (EBh) in SPI command and WP#, HOLD# are enabled. While QE is “1”, it enables Quad Input/Output FAST_READ (EBh) in SPI command and WP#, HOLD# are disabled. In other words, in SPI mode, the QE bit needs to be assigned through WRSR to enable or disable SPI command Quad Input/Output FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI), this QE bit becomes no affection since WP# and HOLD# function will be disabled by EQPI mode and Quad Input/Output FAST_READ (EBh) will be always available in EQPI mode. SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be programmed once. Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1, user must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR command to lock the OTP sector before leaving OTP mode. Read Information Register (RDIFR) (2Bh) The Read Information Register (RDIFR) instruction is for reading the value of Information Register. The Read Information Register can be read at any time (even in program/erase/write status register condition) and continuously, as shown in Figure 10. The sequence of issuing RDIFR instruction is: CS# goes low -> sending RDIFR instruction -> Information Register data out on DO -> CS# goes high. The instruction sequence is shown in Figure 10.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 10. Read Information register Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 28 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 10.1 Read Information register Instruction Sequence under EQPI Mode Table 7. Information Register Bit Locations S7 HBL (High Bank Latch bit) 1 = access larger than 128Mb 0 = access smaller than 128Mb S6 S5 Erase Fail Flag Program Fail Flag S4 1 = indicate 1 = indicate Reserved Erase failed Program failed bit 0 = normal 0 = normal Erase succeed Program succeed (default = 0) (default = 0) S3 Reserved bit S2 S1 S0 4 BYTE OTP_LOCK bit 1 = 4-byte address mode 0 = 3-byte address mode (default = 0) 1 = OTP sector is protected (default = 0) volatile bit volatile bit volatile bit volatile bit non-volatile bit Read Only Read Only Read Only Read Only Read Only Reserved bit Note: 1. When executed the (RDIFR) (2Bh) command, the OTP_LOCK bit (S1) value is the same as OTP_LOCK bit (S7 / in OTP mode) in table 6. 2. Default at Power-up is “0” This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 29 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 The status and control bits of the Secured Register are as follows: Reserved bit. Information register bit locations 0, 3 and 4 are reserved for future use. Current devices will read 0 for these bit locations. It is recommended to mask out the reserved bit when testing the Suspend Status Register. Doing this will ensure compatibility with future devices. OTP_LOCK bit. The OTP_LOCK bit, user can read/program/erase OTP sector as normal sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be programmed once. 4 BYTE Indicator bit. By writing EN4B instruction, the 4 BYTE bit may be set to “1” to access the address length of 32-bit for higher density (large than 128Mb) memory area. The default state is “0”, which means the mode of 24-bit address. The 4 BYTE bit may be clear by power off or writing EX4B instruction to reset the state to be “0” Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can indicate whether one or more of program operations fail, and can be reset by Program (PP) or Erase (SE, BE or CE) instructions. Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate whether one or more of erase operations fail, and can be reset by Program (PP) or Erase (SE, BE or CE) instructions. Note : For Program and Erase Flag bits, 1. The flag bits can be reset by power-on or that embedded mode was executed like WRSR, Erase or Program command. 2. If the system is trying to erase a locked block and then program a locked block. The erase fail or program fail flag bit will be high due to no successful Program, Erase or WRSE command. HBL bit. The High Bank Latch (HBL) bit indicates the status of the internal High Bank Latch. By writing ENHB instruction, the HBL bit may be set to “1” to access the memory area of higher bank (larger than 128M). The default state is “0”, which mean if execute read / program / erase command, then the first byte addresses will be accessed at the memory area of lower density (smaller than 128M). The HBL bit may be clear by power off or writing EXHBL instruction to reset the state to be “0” Write Status Register (WRSR) (01h) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code and the data byte on Serial Data Input (DI). The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 30 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 The instruction sequence is shown in Figure 11.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1. Figure 11. Write Status Register Instruction Sequence Diagram Figure 11.1 Write Status Register Instruction Sequence under EQPI Mode This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 31 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Enter 4-byte mode (EN4B) (B7h) The EN4B instruction enables accessing the address length of 32-bit for the memory area of higher density (larger than 128Mb). The device default is in 24-bit address mode; after sending out the EN4B instruction, the bit 2 (4 BYTE bit) of Information register will be automatically set to “1” to indicate the 4byte address mode has been enabled. Once the 4-byte address mode is enable, the address length becomes 32-bit instead of the default 24-bit. There are two methods to exit the 4-byte mode: power-off or writing exit 4-byte mode (EX4B) instruction. All instructions are accepted normally, and just the address bit is changed form 24-bit to 32-bit. The sequence of issuing EN4B instruction is: CS# goes low -> sending EN4B instruction to enter 4-byte mode (automatically set 4 BYTE bit as “1”) -> CS# goes high, as shown in Figure 12. The instruction sequence is shown in Figure 13.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 12. Enter 4-byte mode Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 32 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Exit 4-byte mode (EX4B) (E9h) The EX4B instruction is executed to exit the 4-byte address mode and return to the default 3-bytes address mode. After sending out the EX4B instruction, the bit 2 (4 BYTE bit) of Information register will be cleared to be ”0” to indicate the exit of the 4-byte address mode. Once exiting the 4-byte address mode, the address length will return to 24-bit. The sequence of issuing EX4B instruction is: CS# goes low -> sending EX4B instruction to exit 4-byte mode (automatically clear the 4 BYTE bit to be “0”) -> CS# goes high, as shown in Figure 13. The instruction sequence is shown in Figure 13.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 13. Exit 4-byte mode Instruction Sequence Diagram Figure 13.1 Enter / Exit 4-byte mode Instruction Sequence under EQPI Mode This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 33 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Enter High Bank Latch mode (ENHBL) (67h) The High Bank Latch mode (ENHBL) instruction enables the first byte addresses was accessed at the memory area of higher bank (larger than 128Mb) while execute the read / program / erase command, that means the address 24-bit was asserted high after entering this mode. In other words, for read / program / erase command the Host system can also access the addresses from 1000000h to 1FFFFFF even if without inputting 4 byte address. The device default is in the memory area of lower bank (smaller than 128M); after sending out the ENHBL instruction, the bit 7 (HBL bit) of Information register will be automatically set to “1” to indicate the High Bank Latch has been enabled. Once the High Bank Latch mode is enable, if execute read / program / erase command, then the first byte addresses will be accessed at memory area of the higher bank (larger than 128Mb) instead of the default the memory area lower bank (smaller than 128M). There are some methods that can exit the High Bank Latch mode: power-off, or by writing Reset Quad I/O (RSTQIO), Enter 4-byte mode (EN4B) and Exit High Bank Latch mode (EXHBL) instructions. The sequence of issuing ENHBL instruction is: CS# goes low -> sending ENHBL instruction to enter High Bank Latch mode (automatically set HBL bit as “1”) -> CS# goes high, as shown in Figure 14. The instruction sequence is shown in Figure 15.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 14. Enter High Bank Latch mode Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 34 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Exit High Bank Latch mode (EXHBL) (98h) The Exit High Bank Latch Mode (EXHBL) instruction is executed to exit the High Bank Latch mode and then return to the default state: the first byte addresses was accessed at memory area of lower bank (smaller than 128M) while execute the read / program / erase command. After sending out the EXHBL instruction, the bit 7 (HBL bit) of Information register will be cleared to be ”0” to indicate the exit of the High Bank Latch mode. Once the exit the High Bank Latch mode is enable, if executed the read / program / erase command then the first byte addresses will be accessed at memory area of lower bank (smaller than 128M). The sequence of issuing EXHBL instruction is: CS# goes low -> sending EXHBL instruction to Exit High Bank Latch mode (automatically clear the HBL bit to be “0”) -> CS# goes high, as shown in Figure 15. The instruction sequence is shown in Figure 15.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 15. Exit High Bank Latch mode Instruction Sequence Diagram Figure 15.1 Enter / Exit High Bank Latch mode Instruction Sequence under EQPI Mode This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 35 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Read Data Bytes (READ) (03h) The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte or 4-byte address (depending on mode state), each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (CLK). The instruction sequence is shown in Figure 16. The first byte addresses can be at any location. To access higher address (larger than 128Mb), there are two methods. One is the Enter 4-byte mode (B7h) command and the other is the Enter High Bank Latch Mode (67h) command. For these methods, the address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 16. Read Data Instruction Sequence Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 36 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Read Data Bytes at Higher Speed (FAST_READ) (0Bh) The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte or 4-byte address (depending on mode state) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum frequency FR, during the falling edge of Serial Clock (CLK). The instruction sequence is shown in Figure 17. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. The instruction sequence is shown in Figure 17.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 17. Fast Read Instruction Sequence Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 37 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 17.1 Fast Read Instruction Sequence under EQPI Mode Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Dual Output Fast Read (3Bh) The Dual Output Fast Read (3Bh) is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins, DQ0 and DQ1, instead of just DQ0. This allows data to be transferred from the EN25QH256 at twice the rate of standard SPI devices. The Dual Output Fast Read instruction is ideal for quickly downloading code from to RAM upon power-up or for applications that cache codesegments to RAM for execution. Similar to the Fast Read instruction, the Dual Output Fast Read instruction can operation at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy clocks after the 3-byte or 4-byte address (depending on mode state) as shown in Figure 18. The dummy clocks allow the device’s internal circuits additional time for setting up the initial address. The input data during the dummy clock is “don’t care”. However, the DI pin should be high-impedance prior to the falling edge of the first data out clock. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 38 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 18. Dual Output Fast Read Instruction Sequence Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Dual Input / Output FAST_READ (BBh) The Dual I/O Fast Read (BBh) instruction allows for improved random access while maintaining two IO pins, DQ0 and DQ1. It is similar to the Dual Output Fast Read (3Bh) instruction but with the capability to input the Address bits (3-byte or 4-byte, depending on mode state) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. The Dual I/O Fast Read instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of CLK, and data of every two bits (interleave 2 I/O pins) shift out on the falling edge of CLK at a maximum frequency. The first address can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single Dual I/O Fast Read instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing Dual I/O Fast Read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in Figure 19. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 39 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 19. Dual Input / Output Fast Read Instruction Sequence Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 40 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Quad Input / Output FAST_READ (EBh) The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh) instruction except that address (3-byte or 4-byte, depending on mode state) and data bits are input and output through four pins, DQ0, DQ1, DQ2 and DQ3 and six dummy clocks are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read mode. In SPI mode, the QE bit needs to be assigned through WRSR to set to “1” before sending the SPI instruction Quad Input/Output FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI), this QE bit becomes no affection since WP# and HOLD# function will be disabled by EQPI mode and Quad Input/Output FAST_READ (EBh) will be always available in EQPI mode. The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of CLK at a maximum frequency FR. The first address can be any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single Quad Input/Output FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing Quad Input/Output FAST_READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit or 32-bit address (depending on mode state ) interleave on DQ3, DQ2, DQ1 and DQ0 -> 6 dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 -> to end Quad Input/Output FAST_READ (EBh) operation can use CS# to high at any time during data out, as shown in Figure 20. The instruction sequence is shown in Figure 20.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 20. Quad Input / Output Fast Read Instruction Sequence Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 41 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 20.1. Quad Input / Output Fast Read Instruction Sequence under EQPI Mode Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24bit address interleave on DQ3, DQ2, DQ1 and DQ0 -> performance enhance toggling bit P[7:0] -> 4 dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 till CS# goes high -> CS# goes low (reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit or 32-bit random access address (depending on mode state), as shown in Figure 21. In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh) instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. And afterwards CS# is raised, the system then will escape from performance enhance mode and return to normal operation. While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh) instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle. The instruction sequence is shown in Figure 21.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 42 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 21. Quad Input/Output Fast Read Enhance Performance Mode Sequence Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 43 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 21.1 Quad Input/Output Fast Read Enhance Performance Mode Sequence under EQPI Mode Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 44 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Page Program (PP) (02h) The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three or four address bytes (depending on mode state) and at least one data byte on Serial Data Input (DI). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 22. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3, BP2, BP1, BP0) bits (see Table 3) is not executed. The instruction sequence is shown in Figure 22.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 22. Page Program Instruction Sequence Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 45 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 22.1 Program Instruction Sequence under EQPI Mode Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Sector Erase (SE) (20h) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three or four address bytes (depending on mode state) on Serial Data Input (DI). Any address inside the Sector (see Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The instruction sequence is shown in Figure 23. Chip Select (CS#) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP3, BP2, BP1, BP0) bits (see Table 3) is not executed. The instruction sequence is shown in Figure 24.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 46 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 23. Sector Erase Instruction Sequence Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Block Erase (BE) (D8h) The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Block Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three or four address bytes (depending on mode state) on Serial Data Input (DI). Any address inside the Block (see Table 2) is a valid address for the Block Erase (BE) instruction. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The instruction sequence is shown in Figure 24. Chip Select (CS#) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Block Erase (BE) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Block Erase (BE) instruction applied to a block which is protected by the Block Protect (BP3, BP2, BP1, BP0) bits (see Table 3) is not executed. The instruction sequence is shown in Figure 24.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 47 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 24. Block Erase Instruction Sequence Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Figure 24.1 Block/Sector Erase Instruction Sequence under EQPI Mode Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 48 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Chip Erase (CE) (C7h/60h) The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 25. Chip Select (CS#) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0. The Chip Erase (CE) instruction is ignored if one, or more blocks are protected. The instruction sequence is shown in Figure 25.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 25. Chip Erase Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 49 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 25.1 Chip Erase Sequence under EQPI Mode Deep Power-down (DP) (B9h) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified in Table 13.) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Device ID (RDI) instruction. This releases the device from this mode. The Release from Deep Power-down and Read Device ID (RDI) instruction also allows the Device ID of the device to be output on Serial Data Output (DO). The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 26. Chip Select (CS#) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (CS#) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 50 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 26. Deep Power-down Instruction Sequence Diagram Release from Deep Power-down and Read Device ID (RDI) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes the device out of the Deep Power-down mode. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for reasons of backward compatibility, only, and should not be used for new designs. New designs should, instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction. When used only to release the device from the power-down state, the instruction is issued by driving the CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 27. After the time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other instructions will be accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 28. The Device ID value for the EN25QH256 are listed in Table 5. The Device ID can be read continuously. The instruction is completed by driving CS# high. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2 (max), as specified in Table 15. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the device, and can be applied even if the Deep Power-down mode has not been entered. Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 51 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 27. Release Power-down Instruction Sequence Diagram Figure 28. Release Power-down / Device ID Instruction Sequence Diagram Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code “90h” followed by a 24-bit or 32-bit address (depending on mode state) of 000000h. After which, the Manufacturer ID for Eon (1Ch) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 29. The Device ID values for the EN25QH256 are listed in Table 5. If the 24-bit or 32-bit address (depending on mode state) is initially set to 000001h the Device ID will be read first The instruction sequence is shown in Figure 29.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 52 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 29. Read Manufacturer / Device ID Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Figure 29.1. Read Manufacturer / Device ID Diagram under EQPI Mode Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 53 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Read Identification (RDID) (9Fh) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte , and the memory capacity of the device in the second byte . Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction should not be issued while the device is in Deep Power down mode. The device is first selected by driving Chip Select Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The instruction sequence is shown in Figure 30. The Read Identification (RDID) instruction is terminated by driving Chip Select High at any time during data output. When Chip Select is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The instruction sequence is shown in Figure 30.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Figure 30. Read Identification (RDID) This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 54 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 30.1. Read Identification (RDID) under EQPI Mode Enter OTP Mode (3Ah) This Flash has an extra 512 bytes OTP sector, user must issue ENTER OTP MODE command to read, program or erase OTP sector. After entering OTP mode, SRP bit becomes OTP_LOCK bit and can be read with RDSR command. Program / Erase command will be disabled when OTP_LOCK bit is ‘1’ WRSR command will ignore the input data and program OTP_LOCK bit to 1. User must clear the protect bits before enter OTP mode. OTP sector can only be program and erase before OTP_LOCK bit is set to ‘1’ and BP [3:0] = ‘0000’. While in OTP mode, array access is not allowed. User can use WRDI (04h) command to exit OTP mode. While in OTP mode, user can use Sector Erase (20h) command only to erase OTP data. The instruction sequence is shown in Figure 31.1 while using the Enable Quad Peripheral Interface mode (EQPI) (38h) command. Table 8. OTP Sector Address Sector Size Address Range 512 byte xxx000h – xxx1FFh This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 55 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 31. Enter OTP Mode Sequence Figure 31.1 Enter OTP Mode Sequence under EQPI Mode This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 56 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Read SFDP Mode and Unique ID Number (5Ah) Read SFDP Mode EN25QH256 features Serial Flash Discoverable Parameters (SFDP) mode. Host system can retrieve the operating characteristics, structure and vendor specified information such as identifying information, memory size, operating voltage and timing information of this device by SFDP mode. The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read SFDP Mode is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum frequency FR, during the falling edge of Serial Clock (CLK). The instruction sequence is shown in Figure 32. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Serial Flash Discoverable Parameters (SFDP) instruction. When the highest address is reached, the address counter rolls over to 0x00h, allowing the read sequence to be continued indefinitely. The Serial Flash Discoverable Parameters (SFDP) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes at Serial Flash Discoverable Parameters (SFDP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 32. Read SFDP Mode Instruction Sequence Diagram Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 57 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 9. Serial Flash Discoverable Parameters (SFDP) Signature and Parameter Identification Data Value (Advanced Information) Description SFDP Signature SFDP Minor Revision Number SFDP Major Revision Number Number of Parameter Headers (NPH) Unused ID Number Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in DW) Parameter Table Pointer (PTP) Unused Address (h) Address (Bit) (Byte Mode) Data Comment 00h 01h 02h 03h 04h 05h 06h 07h 08h 07 : 00 15 : 08 23 : 16 31 : 24 07 : 00 15 : 08 23 : 16 31 : 24 07 : 00 53h 46h 44h 50h 00h 01h 00h FFh 00h Star from 0x00 Star from 0x01 1 parameter header Reserved JEDEC ID 09h 15 : 08 00h Star from 0x00 0Ah 23 : 16 01h Star from 0x01 0Bh 0Ch 0Dh 0Eh 0Fh 31 : 24 07 : 00 15 : 08 23 : 16 31 : 24 09h 30h 00h 00h FFh 9 DWORDs This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 58 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 Signature [31:0]: Hex: 50444653 000030h Reserved www.eonssi.com EN25QH256 Table 10. Parameter ID (0) (Advanced Information) 1/9 Description Address (h) (Byte Mode) Address (Bit) Block / Sector Erase sizes Identifies the erase granularity for all Flash Components 00 Write Granularity Write Enable Instruction Required for Writing to Volatile Status Register Write Enable Opcode Select for Writing to Volatile Status Register 02 30h 01b 1b 0 = No, 1 = Yes 00b 00 = N/A 01 = use 50h opcode 11 = use 06h opcode 03 04 31h Supports (1-1-2) Fast Read Device supports single input opcode & address and quad output data Fast Read 05 06 07 08 09 10 11 12 13 14 15 111b 4 KB Erase Support (FFh = not supported) 1b 0 = not supported 1 = supported 01b 00 = 3-Byte 01 = 3- or 4-Byte (e.g. defaults to 3-Byte mode; enters 4-Byte mode on command) 10 = 4-Byte 11 = reserved 19 0b 0 = not supported 1 = supported 20 1b 0 = not supported 1 = supported 21 1b 0 = not supported 1 = supported 22 0b 0 = not supported 1 = supported 23 24 1b Reserved FFh Reserved 17 Supports Double Transfer Rate (DTR) Clocking Indicates the device supports some type of double transfer rate clocking. Supports (1-2-2) Fast Read Device supports single input opcode, dual input address, and quad output data Fast Read Supports (1-4-4) Fast Read Device supports single input opcode, quad input address, and quad output data Fast Read Supports (1-1-4) Fast Read Device supports single input opcode & address and quad output data Fast Read Unused 18 32h Reserved 20h 16 Address Byte Number of bytes used in addressing for flash arra write and erase. Comment 00 = reserved 01 = 4KB erase 10 = reserved 11 = 64KB erase 01 Unused 4 Kilo-Byte Erase Opcode Data 25 26 Unused 33h 27 28 29 30 31 This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 59 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 10. Parameter ID (0) (Advanced Information) 2/9 Description Flash Memory Density Address (h) (Byte Mode) 37h : 34h Address (Bit) 31 : 00 Data Comment 0FFFFFFFh 256 Mbits Data Comment 00100b 4 dummy clocks 010b 8 mode bits Table 10. Parameter ID (0) (Advanced Information) 3/9 Description (1-4-4) Fast Read Number of Wait states (dummy clocks) needed before valid output Address (h) (Byte Mode) 38h Quad Input Address Quad Output (1-44) Fast Read Number of Mode Bits (1-4-4) Fast Read Opcode Opcode for single input opcode, quad input address, and quad output data Fast Read. (1-1-4) Fast Read Number of Wait states (dummy clocks) needed before valid output 39h 3Ah (1-1-4) Fast Read Number of Mode Bits (1-1-4) Fast Read Opcode Opcode for single input opcode & address and quad output data Fast Read. 3Bh Address (Bit) 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 31 : 24 EBh 00000b Not Supported 000b Not Supported FFh Not Supported This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 60 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 10. Parameter ID (0) (Advanced Information) 4/9 Description (1-1-2) Fast Read Number of Wait states (dummy clocks) needed before valid output Address (h) (Byte Mode) 3Ch (1-1-2) Fast Read Number of Mode Bits (1-1-2) Fast Read Opcode Opcode for single input opcode & address and dual output data Fast Read. (1-2-2) Fast Read Number of Wait states (dummy clocks) needed before valid output 3Dh 15 : 08 3Eh 16 17 18 19 20 21 22 23 (1-2-2) Fast Read Number of Mode Bits (1-2-2) Fast Read Opcode Opcode for single input opcode, dual input address, and dual output data Fast Read. Address (Bit) 00 01 02 03 04 05 06 07 3Fh Data Comment 01000b 8 dummy clocks 000b Not Supported 3Bh 00100b 4 dummy clocks 000b Not Supported 31 : 24 BBh Address (Bit) Data Supports (4-4-4) Fast Read Device supports Quad input opcode & address and quad output data Fast Read. 00 0b Reserved. These bits default to all 1’s 01 02 03 111b 04 1b Table 10. Parameter ID (0) (Advanced Information) 5/9 Description Supports (2-2-2) Fast Read Device supports dual input opcode & address and dual output data Fast Read. Address (h) (Byte Mode) 40h Reserved. These bits default to all 1’s Reserved. These bits default to all 1’s 43h : 41h 05 06 07 31 : 08 Comment 0 = not supported 1 = supported Reserved 0 = not supported 1 = supported (EQPI Mode) 111b Reserved FFh Reserved This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 61 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 10. Parameter ID (0) (Advanced Information) 6/9 Description Reserved. These bits default to all 1’s Address (h) (Byte Mode) 45h : 44h (2-2-2) Fast Read Number of Wait states (dummy clocks) needed before valid output 46h (2-2-2) Fast Read Number of Mode Bits (2-2-2) Fast Read Opcode Opcode for dual input opcode & address and dual output data Fast Read. 47h Address (Bit) 15 : 00 16 17 18 19 20 21 22 23 31 : 24 Data Comment FFh Reserved 00000b Not Supported 000b Not Supported FFh Not Supported Data Comment Table 10. Parameter ID (0) (Advanced Information) 7/9 Description Reserved. These bits default to all 1’s Address (h) (Byte Mode) 49h : 48h (4-4-4) Fast Read Number of Wait states (dummy clocks) needed before valid output 4Ah (4-4-4) Fast Read Number of Mode Bits (4-4-4) Fast Read Opcode Opcode for quad input opcode/address, quad output data Fast Read. 4Bh Address (Bit) 15 : 00 16 17 18 19 20 21 22 23 FFh Reserved 00100b 4 dummy clocks 010b 8 mode bits 31 : 24 EBh Must Enter EQPI Mode Firstly Table 10. Parameter ID (0) (Advanced Information) 8/9 Description Sector Type 1 Size Sector Type 1 Opcode Sector Type 2 Size Sector Type 2 Opcode Address (h) (Byte Mode) 4Ch 4Dh 4Eh 4Fh Address (Bit) 07 : 00 15 : 08 23 : 16 31 : 24 Data Comment 0Ch 20h 00h FFh 4 KB Not Supported Not Supported Data Comment 10h D8h 00h FFh 64 KB Table 10. Parameter ID (0) (Advanced Information) 9/9 Description Sector Type 3 Size Sector Type 3 Opcode Sector Type 4 Size Sector Type 4 Opcode Address (h) (Byte Mode) 50h 51h 52h 53h Address (Bit) 07 : 00 15 : 08 23 : 16 31 : 24 This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 62 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 Not Supported Not Supported www.eonssi.com EN25QH256 Read Unique ID Number The Read Unique ID Number instruction accesses a factory-set read-only 96-bit number that is unique to each EN25QH256 device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the CS# pin low and shifting the instruction code “5Ah” followed by a three bytes of addresses, 0x80h, and one byte of dummy clocks. After which, the 96-bit ID is shifted out on the falling edge of CLK as shown in figure 32. Table 11. Unique ID Number Description Address (h) (Byte Mode) Address (Bit) Data Unique ID Number 80h : 8Bh 95 : 00 By die Comment Power-up Timing Figure 33. Power-up Timing Table 12. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min. Max. Unit tVSL(1) VCC(min) to CS# low 10 tPUW(1) Time delay to Write instruction 1 10 ms Write Inhibit Voltage 1 2.5 V VWI(1) µs Note: 1.The parameters are characterized only. 2. VCC (max.) is 3.6V and VCC (min.) is 2.7V INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 63 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 13. DC Characteristics (Ta = - 40°C to 85°C; VCC = 2.7-3.6V) Symbol ILI Parameter Test Conditions Min. Max. Unit - ±2 µA - ±2 µA - 20 µA - 20 µA - 20 mA Input Leakage Current ILO Output Leakage Current ICC1 Standby Current ICC2 Deep Power-down Current ICC3 Operating Current (READ) ICC4 Operating Current (PP) ICC5 Operating Current (WRSR) ICC6 ICC7 CS# = VCC, VIN = VSS or VCC CS# = VCC, VIN = VSS or VCC CLK = 0.1 VCC / 0.9 VCC at 80MHz, DQ = open CS# = VCC - 28 mA - 18 mA Operating Current (SE) CS# = VCC CS# = VCC - 25 mA Operating Current (BE) CS# = VCC - VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage IOL = 1.6 mA VOH Output High Voltage IOH = –100 µA 25 mA – 0.5 0.2 VCC V 0.7VCC VCC+0.4 V - 0.4 V VCC-0.2 - V Table 14. AC Measurement Conditions Symbol CL Parameter Min. Max. Unit Load Capacitance 20 pF Input Rise and Fall Times 5 ns Input Pulse Voltages 0.2VCC to 0.8VCC V Input Timing Reference Voltages 0.3VCC to 0.7VCC V VCC / 2 V Output Timing Reference Voltages Figure 34. AC Measurement I/O Waveform This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 64 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 15. AC Characteristics (Ta = - 40°C to 85°C; VCC = 2.7-3.6V) Symbol FR Alt fC Parameter Serial Clock Frequency for: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, WRSR tCH tCL1 tCLCH tCHCL 2 Unit 80 MHz D.C. - 80 MHz D.C. - 50 MHz 5 - - ns 5 - - ns Serial Clock Rise Time (Slew Rate) 0.1 - - V / ns Serial Clock Fall Time (Slew Rate) Serial Clock Low Time 2 Max - Serial Clock Frequency for READ, Quad I/O Fast Read, RDSR, RDID, Serial Clock High Time 1 Typ D.C. Serial Clock Frequency for: Dual Output Fast Read fR Min 0.1 - - V / ns CS# Active Setup Time (Relative to CLK) 5 - - ns tCHSH CS# Active Hold Time (Relative to CLK) 5 - - ns tSHCH CS# Not Active Setup Time (Relative to CLK) 5 - - ns tCHSL 5 15 50 - - - - - tSLCH tCSS tSHQZ 2 tDIS CS# Not Active Hold Time (Relative to CLK) CS# High Time for read CS# High Time for program/erase Output Disable Time - 6 ns ns ns ns tCLQX tHO Output Hold Time 0 - - ns tDVCH tDSU Data In Setup Time 2 - - ns tCHDX tDH - - ns tSHSL tCSH Data In Hold Time 5 tHLCH HOLD# Low Setup Time ( relative to CLK ) 5 ns tHHCH HOLD# High Setup Time ( relative to CLK ) 5 ns tCHHH HOLD# Low Hold Time ( relative to CLK ) 5 ns HOLD# High Hold Time ( relative to CLK ) 5 ns tCHHL tHLQZ 2 tHZ HOLD# Low to High-Z Output 6 ns tHHQX 2 tLZ HOLD# High to Low-Z Output 6 ns tV Output Valid from CLK tCLQV - - 10 ns tWHSL3 Write Protect Setup Time before CS# Low 20 - - ns tSHWL3 Write Protect Hold Time after CS# High 100 - - ns - - 3 µs - - 3 µs - - 1.8 µs - 10 50 ms tDP 2 tW CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature read CS# High to Standby Mode with Electronic Signature read Write Status Register Cycle Time tPP Page Programming Time - 0.8 5 ms tSE Sector Erase Time - 50 300 ms tBE Block Erase Time - 0.4 2 s tCE Chip Erase Time - 100 280 s tSR Software Reset Latency WIP = write operation - - 28 µs WIP = not in write operation - - 0 µs tRES1 2 tRES2 2 Note: 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 65 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 35. Serial Output Timing Figure 36. Input Timing Figure 37. Hold Timing This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 66 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 ABSOLUTE MAXIMUM RATINGS Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. Parameter Value Unit Storage Temperature -65 to +150 C Plastic Packages -65 to +125 C Output Short Circuit Current1 200 mA Input and Output Voltage (with respect to ground) 2 -0.5 to +4.0 V Vcc -0.5 to +4.0 V Notes: 1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below. RECOMMENDED OPERATING RANGES 1 Parameter Value Ambient Operating Temperature Industrial Devices -40 to 85 Operating Supply Voltage Vcc Full: 2.7 to 3.6 Unit C V Notes: 1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed. Vcc +1.5V Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 67 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Table 16. DATA RETENTION and ENDURANCE Parameter Description Test Conditions Min Unit 150°C 10 Years 125°C 20 Years -40 to 85 °C 100k cycles Data Retention Time Erase/Program Endurance Table 17. CAPACITANCE ( VCC = 2.7-3.6V) Parameter Symbol Parameter Description Test Setup Max Unit CIN Input Capacitance VIN = 0 6 pF COUT Output Capacitance VOUT = 0 8 pF Note : Sampled only, not 100% tested, at TA = 25°C and a frequency of 20MHz. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 68 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 PACKAGE MECHANICAL Figure 38. VDFN 8 ( 6x8 mm ) Notice: This package can’t contact to metal trace or pad on board due to expose metal pad underneath the package. DIMENSION IN MM MIN. NOR A 0.70 0.75 A1 0.00 0.02 A2 --0.20 D 7.90 8.00 E 5.90 6.00 D1 4.65 4.70 E1 4.55 4.60 e --1.27 b 0.35 0.40 L 0.4 0.50 Note : 1. Coplanarity: 0.1 mm SYMBOL MAX 0.80 0.05 --8.10 6.10 4.75 4.65 --0.48 0.60 This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 69 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 39. 16 LEAD SOP 300 mil SYMBOL MIN. --0.10 2.25 0.20 10.10 10.00 7.40 --0.31 0.4 DIMENSION IN MM NOR MAX --2.65 0.20 0.30 --2.40 0.25 0.30 10.30 10.50 --10.65 7.50 7.60 1.27 ----0.51 --1.27 A A1 A2 C D E E1 e b L θ 00 50 Note : 1. Coplanarity: 0.1 mm 80 This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 70 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Figure 40. 24-ball Ball Grid Array (6 x 8 mm) Package SYMBOL DIMENSIONIN MM A MIN. - -- NOR - -- MAX 1.20 A1 0.27 - -- 0.37 0.21 REF 0.54 REF A2 A3 D E 6 BSC 8 BSC D1 - -- 3.00 - -- E1 e - -- -- 5.00 1.00 - -- -- b - -- 0.40 - -- This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 71 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Purpose Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the Ics. Eon is still keeping the promise of quality for all the products with the same as that of Eon delivered before. Please be advised with the change and appreciate your kindly cooperation and fully support Eon’s product family. Eon products’ Top Marking cFeon Top Marking Example: cFeon Part Number: XXXX-XXX Lot Number: XXXXX Date Code: XXXXX For More Information Please contact your local sales office for additional information about Eon memory solutions. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 72 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 ORDERING INFORMATION EN25QH256 - 80 F I P PACKAGING CONTENT P = RoHS compliant TEMPERATURE RANGE I = Industrial (-40°C to +85°C) PACKAGE Y = 8-pin VDFN (6x8mm) F = 16-pin 300mil SOP BB = 24-ball Ball Grid Array (6 x 8 mm) SPEED 80 = 80 MHz BASE PART NUMBER EN = Eon Silicon Solution Inc. 25QH = 3V Serial Flash with 4KB Uniform-Sector, Dual and Quad I/O 256 = 256 Megabit (32768K x 8) This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 73 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 www.eonssi.com EN25QH256 Revisions List Revision No Description Date A 2011/01/10 B C D E Initial Release 1. Add the note “5. This flow cannot release the device from Deep power down mode.” on page 24. 2. Correct the typo of 6 dummy clocks for EBh command on page 41. 3. Update Read SFDP Mode and add Unique ID Number (5Ah) description on page 57. 1. Update Standard SPI speed from 104MHz to 80MHz. 2. Update Table 16. DC Characteristics on page 63. 3. Update Table 18. AC Characteristics on page 64. 4. Update ORDERING INFORMATION on page 72. 1. Update Figure 2. BLOCK DIAGRAM on page 4. 2. Update the Serial Flash Discoverable Parameters (SFDP) table on page 58, 59, 60, 61 and 62. Update Unique ID Number from 64 bits to 96 bits on page 63. This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., 74 or modifications due to changes in technical specifications. Rev. E, Issue Date: 2012/01/30 2011/06/07 2011/09/01 2011/11/28 2012/01/30 www.eonssi.com