Model 635 Low Jitter LVPECL or LVDS Clock Oscillator FEATURES • • • • • • • • • • • Standard 7.0mm x 5.0mm, 6-Pad Surface Mount Package Low Phase Jitter, 0.7ps RMS Maximum LVPECL or LVDS Output Fundamental and 3rd Overtone Crystal Designs Frequency Range 10 – 320 MHz Frequency Stability ±50 ppm Standard Operating Voltages +2.5Vdc or +3.3Vdc Operating Temperature to -40°C to +85°C Output Enable Standard Tape & Reel Packaging Standard, EIA-418 RoHS/Green Compliant [6/6] APPLICATIONS Model 635 is ideal for applications such as broadband access, SerDes, Ethernet/Gigabit Ethernet, SONET/SDH and optical networking. ORDERING INFORMATION 635 M OUTPUT TYPE P = LVPECL - Pin 1 Enable [std] L = LVDS - Pin 1 Enable [std] E = LVPECL - Pin 2 Enable [opt] V = LVDS - Pin 2 Enable [opt] FREQUENCY IN MHz M - indicates MHz and decimal point. SUPPLY VOLTAGE 2 = 2.5 Vdc 3 = 3.3 Vdc FREQUENCY STABILITY 6 5 3 2 = = = = ± ± ± ± 2 20 ppm 1 25 ppm 50 ppm 100 ppm OPERATING TEMPERATURE RANGE A = -10°C to +60°C C = -20°C to +70°C I = -40°C to +85°C 2 1] Consult factory for availability of 6I Stability/Temperature combination. 2] Frequency is recorded with 3 significant digits before the ‘M’ and 4 significant digits after the ‘M’ (including zeros). See Table I for part number frequency codes that exceed 4 significant digits. [Ex. XXXMXXXX (008M0000), XXXMXXXX (049M1520), XXXMXXXX (122M8800)] Not all performance combinations and frequencies may be available. Contact your local CTS Representative or CTS Customer Service for availability. PACKAGING INFORMATION [reference] Device quantity is 1k pcs. maximum per 180mm reel. Document No. 008-0284-0 Table I NOMINAL FREQUENCY [MHz] 025.000625 101.575694 125.009375 148.351648 153.600770 156.253906 178.018970 Page 1- 3 www.ctscorp.com CTS PART NUMBER FREQUENCY CODE 025M0006 101M5756 125M0093 148M351A 153M6007 156M2539 178M0189 Rev. E Model 635 7.0mm x 5.0mm Low Jitter LVPECL or LVDS Clock ELECTRICAL CHARACTERISTICS SYMBOL CONDITIONS MIN TYP MAX Maximum Supply Voltage PARAMETER VCC - -0.5 - 5.0 UNIT V Storage Temperature TSTG - -40 - +100 °C fO - 10.00 - 320 MHz 80.00 - 320 Frequency Range LVPECL LVDS Frequency Stability Δf/fO All Inclusive, see Note 1. - - 20, 25, 50, 100 1st year aging - - 3 ± ppm Operating Temperature Commercial Industrial Supply Voltage TA - -20 25 -40 VCC ±5% ICC Maximum Load +70 °C +85 2.38 2.5 2.63 3.14 3.3 3.47 - - 88 - - 65 V Supply Current LVPECL LVDS ELECTRICAL PARAMETERS Start Up Time TS Phase Jitter tjrms Period Jitter RMS pjrms Application of VCC - 2 5 Bandwidth 12 kHz - 20 MHz - 0.3 0.7 - - 2.6 - - - 25 - Period Jitter Pk-Pk Enable Function mA ms ps Standby V Enable Input Voltage VIH Pin 1 or 2 Logic '1', Output Enabled 0.7*VCC - - Disable Input Voltage VIL Pin 1 or 2 Logic '0', Output Disabled - - 0.3*VCC Disable Time TPLZ Pin 1 or 2 Logic '0' , Output Disabled - - 200 ns Enable Time TPLZ Pin 1 or 2 Logic '1', Output Enabled - - 2 ms LVPECL WAVEFORM Output Load RL Terminated to VCC - 2.0V - 50 - Ohms 45 - 55 % PECL Load, -20°C to +70°C VCC - 1.025 - VCC - 0.880 PECL Load, -20°C to +70°C VCC - 1.810 - VCC - 1.620 VOH PECL Load, -40°C to +85°C VCC - 1.085 - VCC - 0.880 VOL PECL Load, -40°C to +85°C VCC - 1.830 - VCC - 1.555 - 0.3 0.7 ns Ohms SYM @ VCC - 1.3V Logic '1' Level VOH Logic '0' Level VOL Logic '1' Level Logic '0' Level Output Duty Cycle Output Voltage Levels Rise and Fall Time TR, TF @ 20% - 80% Levels V V LVDS WAVEFORM RL - 100 - Output Duty Cycle SYM @ 1.25V 45 - 55 % Differential Output Voltage VOD RL = 100 Ohms 247 350 454 mV Offset Voltage VOS LVDS Load 1.125 1.25 1.375 V Logic '1' Level VOH LVDS Load - 1.43 1.60 V Logic '0' Level VOL LVDS Load 0.90 1.10 - - 0.4 0.7 Output Load Between Outputs Output Voltage Levels Rise and Fall Time TR, TF @ 20% - 80% Levels ns Notes: 1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging. LVPECL/LVDS OUTPUT WAVEFORM Document No. 008-0284-0 ENABLE TRUTH TABLE PIN 1 or Pin 2 Logic ‘1’ PIN 4 & 5 Output Open Output Logic ‘0’ High Z Page 2 - 3 Rev. E Model 635 7.0mm x 5.0mm Low Jitter LVPECL or LVDS Clock TEST CIRCUIT, LVPECL LOAD TEST CIRCUIT, LVDS LOAD MECHANICAL SPECIFICATIONS MARKING INFORMATION 1. ** - Manufacturing Site Code. 2. YYWW – Date code, YY – year, WW – week. 3. O – Output Type. P or E = LVPECL, L or V = LVDS. 4. ST – Frequency stability/temperature code. PACKAGE DRAWING [Refer to Ordering Information.] CTS**YYWW 635OSTV ● XXXMXXXXXX 5. V – Voltage code. 3 = 3.3V, 2 = 2.5V 6. XXXMXXXXXX – Frequency is marked with only leading significant digits before the ‘M’ and 4 – 6 digits after the ‘M’ (including zeros). Ex. XXMXXXX [19M4400] XXXMXXXXX [153M60077] XXXMXXXXXX [148M351648] NOTES 1. Complete CTS part number, frequency value and date code information must appear on reel and carton labels. 2. Termination pads [e4]. Barrier-plating is nickel [Ni] with gold [Au] flash plate. 3. Reflow conditions per JEDEC J-STD-020; 260°C maximum, 20 seconds. 4. MSL = 1. SUGGESTED SOLDER PAD GEOMETRY CBYPASS should be ≥ 0.01 uF. D.U.T. PIN ASSIGNMENTS PIN SYMBOL Document No. 008-0284-0 Page 3 - 3 DESCRIPTION 1 EOH or N.C. Enable [std] or No Connect 2 N.C. or EOH No Connect or Enable [opt] 3 GND Circuit & Package Ground 4 Output RF Output 5 Output Complimentary RF Output 6 VCC Supply Voltage Rev. E