Model 653 - CTS Corp.

Model 653
LVPECL or LVDS Clock Oscillator
FEATURES
•
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•
•
•
•
•
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Standard 5.0mm x 3.2mm 6-Pad Surface Mount Package
Low Phase Jitter, 0.7ps RMS Maximum
LVPECL or LVDS Output
Fundamental and 3rd Overtone Crystal Designs
Frequency Range 25 – 320 MHz
Frequency Stability ±50 ppm Standard
Operating Voltages +2.5Vdc or +3.3Vdc
Operating Temperature to -40°C to +85°C
Output Enable Standard
Tape & Reel Packaging Standard, EIA-418
RoHS/Green Compliant [6/6]
APPLICATIONS
Model 653 is ideal for applications such as broadband access, Ethernet/Gigabit Ethernet, SONET/SDH and
optical networking.
ORDERING INFORMATION
653
OUTPUT TYPE
P = LVPECL - Pin 1 Enable [std]
L = LVDS - Pin 1 Enable [std]
E = LVPECL - Pin 2 Enable [opt]
V = LVDS - Pin 2 Enable [opt]
PACKAGING
T - 1k pcs./reel
SUPPLY VOLTAGE
2 = 2.5 Vdc
3 = 3.3 Vdc
FREQUENCY
Product Frequency Code
1
OPERATING TEMPERATURE RANGE
A = -10°C to +60°C
C = -20°C to +70°C
2
I = -40°C to +85°C
FREQUENCY STABILITY
6 = ± 20 ppm
5 = ± 25 ppm
3 = ± 50 ppm
2
1] Refer to document 016-1454-0, Frequency Code Tables.
3-digits required for frequencies below 100MHz and 4-digits for frequencies 100MHz or greater.
2] Consult factory for availability of 6I Stability/Temperature combination.
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
PACKAGING INFORMATION [reference]
Device quantity is 1k pcs. maximum per 180mm reel.
Document No. 008-0367-0
Page 1- 3
www.ctscorp.com
Rev. A
Model 653
5.0mm x 3.2mm Low Jitter
LVPECL or LVDS Clock Oscillator
ELECTRICAL CHARACTERISTICS
SYMBOL
CONDITIONS
MIN
TYP
MAX
Maximum Supply Voltage
PARAMETER
VCC
-
-0.5
-
5.0
UNIT
V
Storage Temperature
TSTG
-
-40
-
+100
°C
fO
-
25
-
320
MHz
80
-
320
Frequency Range
LVPECL
LVDS
Frequency Stability
Δf/fO
All Inclusive, see Note 1.
-
-
20, 25, 50
1st year aging
-
-
3
± ppm
Operating Temperature
Commercial
Industrial
Supply Voltage
TA
-
-20
25
-40
VCC
±5%
ICC
Maximum Load
+70
°C
+85
2.38
2.5
2.63
3.14
3.3
3.47
-
-
88
-
-
65
V
Supply Current
LVPECL
LVDS
ELECTRICAL PARAMETERS
Start Up Time
TS
Phase Jitter
tjrms
Period Jitter RMS
pjrms
Application of VCC
-
2
5
Bandwidth 12 kHz - 20 MHz
-
0.3
0.7
-
-
2.6
-
-
-
25
-
Period Jitter Pk-Pk
Enable Function
mA
ms
ps
Standby
V
Enable Input Voltage
VIH
Pin 1 or 2 Logic '1', Output Enabled
0.7*VCC
-
-
Disable Input Voltage
VIL
Pin 1 or 2 Logic '0', Output Disabled
-
-
0.3*VCC
Disable Time
TPLZ
Pin 1 or 2 Logic '0' , Output Disabled
-
-
200
ns
Enable Time
TPLZ
Pin 1 or 2 Logic '1', Output Enabled
-
-
2
ms
LVPECL WAVEFORM
Output Load
RL
Terminated to VCC - 2.0V
-
50
-
Ohms
45
-
55
%
PECL Load, -20°C to +70°C
VCC - 1.025
-
VCC - 0.880
PECL Load, -20°C to +70°C
VCC - 1.810
-
VCC - 1.620
VOH
PECL Load, -40°C to +85°C
VCC - 1.085
-
VCC - 0.880
VOL
PECL Load, -40°C to +85°C
VCC - 1.830
-
VCC - 1.555
-
0.6
1.0
ns
Ohms
SYM
@ VCC - 1.3V
Logic '1' Level
VOH
Logic '0' Level
VOL
Logic '1' Level
Logic '0' Level
Output Duty Cycle
Output Voltage Levels
Rise and Fall Time
TR, TF
@ 20% - 80% Levels
V
V
LVDS WAVEFORM
RL
-
100
-
Output Duty Cycle
SYM
@ 1.25V
45
-
55
%
Differential Output Voltage
VOD
RL = 100 Ohms
247
350
454
mV
Offset Voltage
VOS
LVDS Load
1.125
1.25
1.375
V
Logic '1' Level
VOH
LVDS Load
-
1.43
1.6
V
Logic '0' Level
VOL
LVDS Load
0.9
1.1
-
-
0.4
0.7
Output Load
Between Outputs
Output Voltage Levels
Rise and Fall Time
TR, TF
@ 20% - 80% Levels
ns
Notes:
1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
LVPECL/LVDS OUTPUT WAVEFORM
ENABLE TRUTH TABLE
PIN 1 or Pin 2
Logic ‘1’
Open
Logic ‘0’
Document No. 008-0367-0
Page 2 - 3
PIN 4 & 5
Output
Output
High Imp.
Rev. A
Model 653
5.0mm x 3.2mm Low Jitter
LVPECL or LVDS Clock Oscillator
TEST CIRCUIT, LVDS LOAD
TEST CIRCUIT, LVPECL LOAD
MECHANICAL SPECIFICATIONS
MARKING INFORMATION
1. ** - Manufacturing Site Code.
2. D – Date Code. See Table I for codes.
3. O – Output Type. P or E = LVPECL, L or V = LVDS.
PACKAGE DRAWING
[Refer to Ordering Information.]
4. ST – Frequency stability/temperature code.
CTS**D
653OSTV
● xxxx
[Refer to Ordering Information.]
5. V – Voltage code. 3 = 3.3V, 2 = 2.5V
6. xxxx – Frequency Code.
3-digits, frequencies below 100MHz
4-digits, frequencies 100MHz or greater.
Refer to document 016-1454-0, Frequency Code Tables.
NOTES
1. Complete CTS part number, frequency value and
date code information must appear on reel and
carton labels.
2. Termination pads [e4]. Barrier-plating is nickel [Ni]
with gold [Au] flash plate.
3. Reflow conditions per JEDEC J-STD-020; 260°C
maximum, 20 seconds.
4. MSL = 1.
SUGGESTED SOLDER PAD GEOMETRY
CBYPASS should be ≥ 0.01 uF.
D.U.T. PIN ASSIGNMENTS
PIN
SYMBOL
1
EOH or N.C.
DESCRIPTION
Enable [std] or No Connect
2
N.C. or EOH
No Connect or Enable [opt]
3
GND
Circuit & Package Ground
4
Output
RF Output
5
Output
Complimentary RF Output
6
VCC
Supply Voltage
TABLE I – DATE CODE
MONTH
JAN
YEAR
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
NOV
DEC
M
2001
2005
2009
2013
2017
A
B
C
D
E
F
G
H
J
K
L
2002
2006
2010
2014
2018
N
P
Q
R
S
T
U
V
W
X
Y
Z
2003
2007
2011
2015
2019
a
b
c
d
e
f
g
h
j
k
l
m
2004
2008
2012
2016
2020
n
p
q
r
s
t
u
v
w
x
y
z
Document No. 008-0367-0
Page 3 - 3
Rev. A