240-Pin ECC U-DIMM 8GB (1024M x 72-bits)

SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
ADATA Technology Corp.
Memory Module Data Sheet
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB
(1024M x 72-bits)
Version 0.0
Document Number : R11-0837
1
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Revision History
Version
0.0
Changes
Initial release
Page
Date
-
2012/01/13
2
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Table of Contents
1. General Description .................................................................................... 4
2. Features ..................................................................................................... 4
3. Pin Assignment...................................................................................….5~6
4. Pin Description ....................................................................................... 7~8
5. Block Diagram............................................................................................. 9
6. Absolute Maximum Ratings..................................................................... 10
7. DC Operating Condition..........................................................……………10
8. Input DC & AC Logic Level for single-ended signals…………………..…11
9. Input AC Logic Level for single-ended signals…………………………….11
10. IDD Specification……………………………………………………………….12
11.Speed Bins and CL,tRCD,tRP,tRC and tRAS for
Corresponding Bin …………………………………………………………….12
12. Timing Parameters …………..……………………………………………13~14
13. Package Dimensions……………………..……………………………………15
14. Ordering Information…………..……………...…….…………………………16
3
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
General Description:
:
The ADATA’s module is a 1024Mx72 bits 8GB(8192MB) DDR3-1600(CL11)-11-11-28
SDRAM memory module. The SPD is programmed to JEDEC standard latency 1600Mbps
timing of 11-11-11-28 at 1.35V. The module is composed of eight-teen 512Mx8 bits CMOS
DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin
glass–epoxy printed circuit board.
The module is a Dual In-line Memory Module and intended for mounting onto 240-pins
edge connector sockets. Synchronous design allows precise cycle control with the use of
system clock. Data I/O transactions are possible on both edges of DQS. Range of operating
frequencies, programmable latencies and burst lengths allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Features:
:
• Power supply (Normal): VDD & VDDQ = 1.35V (1.283V to 1.45V)
• Backward-compatible to VDD=+1.5V+-0.075V
• MRS Cycle with address key programs
- CAS Latency (5,6,7,8,9,10,11)
- Burst Length (BL):8 and 4 with Burst Chop(BC)
• Bi-directional, differential data strobe (DQS and /DQS)
• Differential clock input (CK, /CK) operation
• DLL aligns DQ and DQS transition with CK transition
• Double-data-rate architecture; two data transfers per clock cycle
• 8 independent internal bank
• Internal (self) calibration: Internal self calibration through ZQ pin (RZQ:240 ohm±1%)
• Auto refresh and self refresh
• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
• 8-bit pre-fetch.
• On Die Termination using ODT pin.
• On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM.
• EEPROM software write protect.
• Lead-free products are RoHS Compliant
4
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Pin Assignment:
:
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
VREFDQ
41
VSS
81
DQ32
121
VSS
161
NC,DM8
201
DQ37
2
VSS
42
NC
82
DQ33
122
DQ4
162
NC
202
VSS
3
DQ0
43
NC
83
VSS
123
DQ5
163
VSS
203
DM4
4
DQ1
44
VSS
84
/DQS4
124
VSS
164
NC,CB6
204
NC
5
VSS
45
NC,CB2
85
DQS4
125
DM0
165
NC,CB7
205
VSS
6
/DQS0
46
NC,CB3
86
VSS
126
NC
166
VSS
206
DQ38
7
DQS0
47
VSS
87
DQ34
127
VSS
167
NC
207
DQ39
8
VSS
48
NC
88
DQ35
128
DQ6
168
/RESET
208
VSS
9
DQ2
49
NC
89
VSS
129
DQ7
169
CKE1,NC
209
DQ44
10
DQ3
50
CKE0
90
DQ40
130
VSS
170
VDD
210
DQ45
11
VSS
51
VDD
91
DQ41
131
DQ12
171
A15
211
VSS
12
DQ8
52
BA2
92
VSS
132
DQ13
172
A14
212
DM5
13
DQ9
53
NC
93
/DQS5
133
VSS
173
VDD
213
NC
14
VSS
54
VDD
94
DQS5
134
DM1
174
A12
214
VSS
15
/DQS1
55
A11
95
VSS
135
NC
175
A9
215
DQ46
16
DQS1
56
A7
96
DQ42
136
VSS
176
VDD
216
DQ47
17
VSS
57
VDD
97
DQ43
137
DQ14
177
A8
217
VSS
18
DQ10
58
A5
98
VSS
138
DQ15
178
A6
218
DQ52
19
DQ11
59
A4
99
DQ48
139
VSS
179
VDD
219
DQ53
20
VSS
60
VDD
100
DQ49
140
DQ20
180
A3
220
VSS
21
DQ16
61
A2
101
VSS
141
DQ21
181
A1
221
DM6
22
DQ17
62
VDD
102
/DQS6
142
VSS
182
VDD
222
NC
23
VSS
63
CK1,NC
103
DQS6
143
DM2
183
VDD
223
VSS
24
/DQS2
64
/CK1,NC
104
VSS
144
NC
184
CK0
224
DQ54
25
DQS2
65
VDD
105
DQ50
145
VSS
185
/CK0
225
DQ55
26
VSS
66
VDD
106
DQ51
146
DQ22
186
VDD
226
VSS
27
DQ18
67
VREFCA
107
VSS
147
DQ23
187
NC,/EVENT
227
DQ60
28
DQ19
68
NC
108
DQ56
148
VSS
188
A0
228
DQ61
29
VSS
69
VDD
109
DQ57
149
DQ28
189
VDD
229
VSS
30
DQ24
70
A10/AP
110
VSS
150
DQ29
190
BA1
230
DM7
31
DQ25
71
BA0
111
/DQS7
151
VSS
191
VDD
231
NC
32
VSS
72
VDD
112
DQS7
152
DM3
192
/RAS
232
VSS
33
/DQS3
73
/WE
113
VSS
153
NC
193
/S0
233
DQ62
5
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
34
DQS3
74
/CAS
114
DQ58
154
VSS
194
VDD
234
DQ63
35
VSS
75
VDD
115
DQ59
155
DQ30
195
ODT0
235
VSS
36
DQ26
76
/S1,NC
116
VSS
156
DQ31
196
A13
236
VDDSPD
37
DQ27
77
ODT1,NC
117
SA0
157
VSS
197
VDD
237
SA1
38
VSS
78
VDD
118
SCL
158
NC,CB4
198
NC
238
SDA
39
NC,CB0
79
NC
119
SA2
159
NC,CB5
199
VSS
239
VSS
40
NC,CB1
80
VSS
120
VTT
160
VSS
200
DQ36
240
VTT
6
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Pin Description:
:
PIN
NAME
FUNCTION
CK0~CK1,
System Clock
Active on the positive and negative edge to sample all inputs.
/CK0~/CK1
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at
CKE0~CKE1
Clock Enable
least on cycle prior new command. Disable input buffers for power down in standby
Disables or Enables device operation by masking or enabling all input except CK, CKE and
/S0~/S1
Chip Select
L(U)DQM
Row / Column address are multiplexed on the same pins.
A0~A14
Address
(Row Address: A0~A14 , Column Address: A0~A9 , Auto precharge: A10/AP)
Selects bank to be activated during row address latch time.
BA0~BA2
Banks Select
Selects bank for read / write during column address latch time.
DQ0~DQ63
Data
Data and check bit inputs / outputs are multiplexed on the same pins.
CB0~CB7
DQS0~DQS8,
Data Strobe
Bi-directional Data Strobe
DM0~DM8
Data Mask
Mask input data when DM is high.
/RAS
Row Address Strobe
/DQS0~/DQS8
/CAS
Latches row addresses on the positive edge of the CK with /RAS low
Column Address Strobe Latches Column addresses on the positive edge of the CK with /CAS low
/WE
Write Enable
VDD / VSS
Power Supply/Ground
Enables write operation and row recharge.
Power and Ground for the input buffers and the core logic.
VREFDQ
Power Supply reference Power Supply for reference.DQ,DM.VDD/2
VREFCA
Power Supply reference Power Supply for reference. Command , address, & control.VDD/2
VDDQ
Power Supply
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity
SDA
Serial data I/O
EEPROM serial data I/O
7
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
SCL
Serial clock
SA0~SA2
Address in EEPROM
ODT0~ODT1
On Die Termination
EEPROM clock input
EEPROM address input
When high, termination resistance is enabled for all DQ, /DQ and DM pins, assuming the
function is enabled in the Extended Mode Register Set.
NC
No Connection
This pin is recommended to be left No Connection on the device.
8
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Block Diagram:
:
9
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Absolute Maximum Ratings:
:
Parameter
Symbol
Value
Unit
VDD
-0.4 ~ 1.975
V
VDDQ
-0.4 ~1.975
V
VIN, Vout
-0.4 ~ 1.975
V
TStg
-55 ~ +100
℃
Voltage on VDD supply relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on any pin relative to Vss
Storage temperature
Note: DDR3 SDRAM component specification.
Operation Temperature Condition
Parameter
Symbol
Value
Normal Operating Temperature Range
TC
0~+85
Extended Temperature Range (Optional)
TC
+85~+95
Note: (1) If the DRAM case temperature is above 85
Unit
℃
℃
Note
1
1
℃, the Auto-Refresh command interval has to be reduced to tREFI=3.9us.
DC Operating Condition:
:
Voltage referenced to Vss = 0V, VDD&VDDQ=1.5V±0.075V, Tc = 0 to 85
Parameter
℃
Symbol
Min
Max
Unit
Note
VDD
1.283
1.45
V
1,2
VDDSPD
3
3.6
V
VDDQ
1.283
1.45
V
1,2
I/O Reference Voltage(CMD/ADD)
VREFCA, (DC)
0.49 x VDDQ
0.51 x VDDQ
V
3,4
I/O Reference Voltage(DQ)
VREFDQ, (DC)
0.49 x VDDQ
0.51 x VDDQ
V
3,4
VTT
0.49 x VDDQ-20mV
0.51 x VDDQ+20mV
V
Supply Voltage
Supply Voltage for Output
Termination Voltage
Note: (1) Under all conditions VDDQ must be less than or equal to VDD.
(2) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
(3) The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ±1% VDD
(for reference: approx. ±15mV)
(4) For reference: approx. VDD/2 ±15mV
10
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Input DC & AC Logic Level for single-ended signals:
:
Parameter
Symbol
Min
Max
Unit
Note
DC Input logic high voltage
VIH (DC)
VREF+100
VDD
mV
1
DC Input logic low voltage
VIL (DC)
VSS
VREF-100
mV
1
AC input logic high
VIH(AC)
VREF + 175
-
mV
1,2
AC input logic low
VIL(AC)
-
VREF – 175
mV
1,2
Note: 1. For DQ and DM, VREF = VREFDQ . For input only pins except RESET, or VREF = VREFCA.
2. See "Overshoot and Undershoot specifications" on component datasheet
Input AC Logic Level for single-ended signals:
:
Parameter
Symbol
Min
Max
Unit
Note
Differential input high
VIHdiff
+0.2
Note 3
V
1
Differential input low
VILdiff
Note 3
-0.2
V
1
Differential input high AC
VIHdiff(AC)
2 (VIH(ac)-Vref)
Note 3
V
2
Differential input low AC
VILdiff (AC)
Note 3
2 x (Vref - VIL(ac))
V
2
Notes: 1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(ac) of DQs
and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, /CK, DQS, /DQS, DQSL, /DQSL, DQSU, /DQSU need to be
within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot
on Component Datasheet.
11
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
IDD Specification:
:
Symbol
Condition
Typical
Unit
IDD0
Operating One Bank Active-Precharge Current
1188
mA
IDD1
Operating One Bank Active-Read-Precharge Current
1368
mA
IDD2P0
Precharge Power-Down Current Slow Exit
216
mA
IDD2P1
Precharge Power-Down Current Fast Exit
810
mA
IDD2Q
Precharge Quiet Standby Current
1206
mA
IDD2N
Precharge Standby Current
1260
mA
IDD3P
Active Power-Down Current
810
mA
IDD3N
Active Standby Current
1206
mA
IDD4W
Operating Burst Write Current
2358
mA
IDD4R
Operating Burst Read Current
2358
mA
IDD5B
Burst Refresh Current
4680
mA
IDD6
Self Refresh Current: Normal Temperature Range
108
mA
IDD7
Operating Bank Interleave Read Current
5508
mA
Note: IDD current measure method and detail patterns are described on DDR3 component datasheet. Only for reference.
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin:
:
Speed
DDR3-1600
Bin(CL-tRCD-tRP)
11-11-11
Parameter
min
CL
11
tCK
tRCD
13.125
ns
tRC
48.125
ns
tRRD
6
ns
tCK
1.25
ns
tRAS
35
ns
tRP
13.125
ns
tRFC
300
ns
Units
12
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Timing Parameters:
Symbol
AC Characteristics Parameter
tCK(DLL_OFF) Minimum Clock Cycle Time (DLL off mode)
Min
Max
Unit
8
-
ns
tCH(avg)
Average high pulse width
0.47
0.53
tCK(avg)
tCL(avg)
Average low pulse width
0.47
0.53
tCK(avg)
tDQSQ
DQS, DQS# to DQ skew, per group, per access
-
125
ps
0.38
-
tCK(avg)
30
-
ps
65
-
ps
tQH
DQ output hold time from DQS, DQS#
Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac)
tDS(base)
levels
Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc)
tDH(base)
levels
tDIPW
DQ and DM Input pulse width for each input
400
-
ps
tRPRE
DQS,DQS# differential READ Preamble
0.9
-
tCK(avg)
tRPST
DQS, DQS# differential READ Postamble
0.3
-
tCK(avg)
tQSH
DQS, DQS# differential output high time
0.40
-
tCK(avg)
tQSL
DQS, DQS# differential output low time
0.40
-
tCK(avg)
tWPRE
DQS, DQS# differential WRITE Preamble
0.9
-
tCK(avg)
tWPST
DQS, DQS# differential WRITE Postamble
0.3
-
tCK(avg)
-255
255
ps
DQS, DQS# rising edge output access time from rising CK,
tDQSCK
CK#
tLZ
DQ, DQS and DQS# low-impedance time
-500
250
ps
tHZ
DQ, DQS and DQS# high-impedance time
-
250
ps
tDQSL
DQS, DQS# differential input low pulse width
0.45
0.55
tCK(avg)
tDQSH
DQS, DQS# differential input high pulse width
0.45
0.55
tCK(avg)
tDQSS
DQS, DQS# rising edge to CK, CK# rising edge
-0.25
0.25
tCK(avg)
tDSS
DQS, DQS# falling edge setup time to CK, CK# rising edge
0.2
-
tCK(avg)
tDSH
DQS, DQS# falling edge hold time from CK, CK# rising edge
0.2
-
tCK(avg)
tRTP
Internal READ Command to PRECHARGE Command delay
max(4nCK,7.5ns)
-
-
max(4nCK,7.5ns)
-
-
Delay from start of internal write transaction to internal read
tWTR
command
tWR
WRITE recovery time
15
-
ns
tMRD
Mode Register Set command cycle time
4
-
nCK
Command and Address setup time to CK, CK# referenced to
65
-
ps
tIS(base)
13
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Vih(ac) / Vil(ac) levels
Command and Address hold time from CK, CK# referenced to
tIH(base)
140
-
ps
max(3nCK,6ns)
-
-
max(3nCK,5.625ns)
-
-
Vih(dc) / Vil(dc) levels
Exit Power Down with DLL on to any valid command; Exit
tXP
Precharge Power Down with DLL frozen to commands not
requiring a locked DLL
tCKE
CKE minimum pulse width
tREFI
Average Periodic Refresh interval
℃
℃ 0℃<TCASE <85℃
85 <TCASE <95
/3.9
us
/7.8
14
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Package Dimensions:
:
15
SUDE1600W8G11
DDR3L-1600(CL11) 240-Pin ECC U-DIMM
8GB(1024M x 72-bits)
Ordering Information:
:
S U D E 1 6 0 0 W 8G 11 X X X
1-2
34
1-2. Product Prefix
SU: ADATA
3. Generation
5-8
9 10-11 12
9. Component Config Code
W: 512MX8
10-11. Capacity
3: DDR3
4G: 4GB
D:DDR3L
8G: 8GB
4. DRAM Type
E: ECC U-DIMM
13-15
12. CAS Latency
9: CL9
11: CL11
5-8. Speed MHz
1600: 1600MHz
13-15. Reserved
16